Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Patchwork <patchwork@emeril.freedesktop.org>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✓ Fi.CI.BAT: success for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)
Date: Wed, 28 Nov 2018 23:15:43 -0000	[thread overview]
Message-ID: <20181128231543.30718.83679@emeril.freedesktop.org> (raw)
In-Reply-To: <20181128202628.20238-1-manasi.d.navare@intel.com>

== Series Details ==

Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)
URL   : https://patchwork.freedesktop.org/series/53184/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10939
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/53184/revisions/2/mbox/

Known issues
------------

  Here are the changes found in Patchwork_10939 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_contexts:
    - fi-bsw-kefka:       PASS -> DMESG-FAIL [fdo#108626] / [fdo#108656]

  * igt@kms_frontbuffer_tracking@basic:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#108626]: https://bugs.freedesktop.org/show_bug.cgi?id=108626
  [fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656


Participating hosts (49 -> 42)
------------------------------

  Missing    (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


Build changes
-------------

    * Linux: CI_DRM_5217 -> Patchwork_10939

  CI_DRM_5217: 3b8acd938b1edc326fb69d377cbceca8791df177 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10939: c878df13f9c00451f7281d105e0f2246cd65748c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c878df13f9c0 drm/i915/fec: Disable FEC state.
303f000edcd4 i915/dp/fec: Configure the Forward Error Correction bits.
2cb9fde528c3 drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
9211bdb6b64b i915/dp/fec: Add fec_enable to the crtc state.
2f4fb87c9b59 drm/i915/dsc: Enable and disable appropriate power wells for VDSC
1cfac339f7ea drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
ca153c0dbe0a drm/i915/dp: Configure Display stream splitter registers during DSC enable
ad3fbff47ade drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
909a40d71447 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
f078f264482d drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
0541a790e095 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
5a207b28b067 drm/i915/dp: Enable/Disable DSC in DP Sink
f0efd1a5bded drm/i915/dsc: Compute Rate Control parameters for DSC
682f70ba2e90 drm/i915/dsc: Define & Compute VESA DSC params
7e99dcca72b9 drm/i915/dp: Do not enable PSR2 if DSC is enabled
3251c57ea8f7 drm/i915/dp: Compute DSC pipe config in atomic check
6cc046b0e53f drm/i915/dp: Add DSC params and DSC config to intel_crtc_state

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10939/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2018-11-28 23:15 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-28 20:26 [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-28 20:26 ` [CI v13 02/17] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-28 21:36   ` [PATCH v14 " Manasi Navare
2018-11-28 20:26 ` [CI v13 03/17] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-28 20:26 ` [CI v13 04/17] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-29 19:38   ` [CI v15 " Manasi Navare
2018-11-28 20:26 ` [CI v13 05/17] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-28 20:26 ` [CI v13 06/17] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-28 20:26 ` [CI v13 07/17] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-28 20:26 ` [CI v13 08/17] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-28 20:26 ` [CI v13 09/17] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-28 20:26 ` [CI v13 10/17] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-28 20:26 ` [CI v13 11/17] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-28 20:26 ` [CI v13 12/17] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-28 20:26 ` [CI v13 13/17] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-28 20:26 ` [CI v13 14/17] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-28 20:26 ` [CI v13 15/17] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-28 20:26 ` [CI v13 16/17] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-28 20:26 ` [CI v13 17/17] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-28 21:01 ` ✗ Fi.CI.BAT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Patchwork
2018-11-28 22:59 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2) Patchwork
2018-11-28 23:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-28 23:15 ` Patchwork [this message]
2018-11-29 10:29 ` ✓ Fi.CI.IGT: success " Patchwork
2018-11-29 19:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) Patchwork
2018-11-29 19:56 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-29 20:08 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-29 20:52 ` [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-30 12:52 ` ✗ Fi.CI.IGT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181128231543.30718.83679@emeril.freedesktop.org \
    --to=patchwork@emeril.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=manasi.d.navare@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox