✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)

From: Patchwork <patchwork@emeril.freedesktop.org>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)
Date: Wed, 28 Nov 2018 22:59:42 -0000	[thread overview]
Message-ID: <20181128225942.30717.66818@emeril.freedesktop.org> (raw)
In-Reply-To: <20181128202628.20238-1-manasi.d.navare@intel.com>

== Series Details ==

Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2)
URL   : https://patchwork.freedesktop.org/series/53184/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
6cc046b0e53f drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#49: FILE: drivers/gpu/drm/i915/intel_drv.h:948:
+		bool compression_enable;

-:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#50: FILE: drivers/gpu/drm/i915/intel_drv.h:949:
+		bool dsc_split;

total: 0 errors, 0 warnings, 2 checks, 22 lines checked
3251c57ea8f7 drm/i915/dp: Compute DSC pipe config in atomic check
7e99dcca72b9 drm/i915/dp: Do not enable PSR2 if DSC is enabled
682f70ba2e90 drm/i915/dsc: Define & Compute VESA DSC params
-:68: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#68: 
Co-developed-by: Manasi Navare <manasi.d.navare@intel.com>

-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#119: 
new file mode 100644

total: 0 errors, 2 warnings, 0 checks, 497 lines checked
f0efd1a5bded drm/i915/dsc: Compute Rate Control parameters for DSC
5a207b28b067 drm/i915/dp: Enable/Disable DSC in DP Sink
0541a790e095 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
f078f264482d drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
-:391: WARNING:LONG_LINE: line over 100 characters
#391: FILE: drivers/gpu/drm/i915/intel_vdsc.c:897:
+		rc_range_params_dword[i / 2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<

total: 0 errors, 1 warnings, 0 checks, 426 lines checked
909a40d71447 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
ad3fbff47ade drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
ca153c0dbe0a drm/i915/dp: Configure Display stream splitter registers during DSC enable
1cfac339f7ea drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
2f4fb87c9b59 drm/i915/dsc: Enable and disable appropriate power wells for VDSC
9211bdb6b64b i915/dp/fec: Add fec_enable to the crtc state.
-:126: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#126: FILE: drivers/gpu/drm/i915/intel_drv.h:956:
+	bool fec_enable;

total: 0 errors, 0 warnings, 1 checks, 65 lines checked
2cb9fde528c3 drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
303f000edcd4 i915/dp/fec: Configure the Forward Error Correction bits.
c878df13f9c0 drm/i915/fec: Disable FEC state.

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