From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [CI v13 07/17] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
Date: Wed, 28 Nov 2018 12:26:18 -0800 [thread overview]
Message-ID: <20181128202628.20238-7-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20181128202628.20238-1-manasi.d.navare@intel.com>
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.h | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 5e253f741d29..b41b06dc8347 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -242,6 +242,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
+ POWER_DOMAIN_TRANSCODER_EDP_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1c2de9b69a19..4350a5270423 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -76,6 +76,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
+ case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
+ return "TRANSCODER_EDP_VDSC";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2028,9 +2030,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
- * - eDP/DSI VDSC
* - KVMR (HW control)
*/
#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
--
2.19.1
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next prev parent reply other threads:[~2018-11-28 20:23 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-28 20:26 [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-28 20:26 ` [CI v13 02/17] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-28 21:36 ` [PATCH v14 " Manasi Navare
2018-11-28 20:26 ` [CI v13 03/17] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-28 20:26 ` [CI v13 04/17] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-29 19:38 ` [CI v15 " Manasi Navare
2018-11-28 20:26 ` [CI v13 05/17] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-28 20:26 ` [CI v13 06/17] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-28 20:26 ` Manasi Navare [this message]
2018-11-28 20:26 ` [CI v13 08/17] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-28 20:26 ` [CI v13 09/17] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-28 20:26 ` [CI v13 10/17] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-28 20:26 ` [CI v13 11/17] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-28 20:26 ` [CI v13 12/17] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-28 20:26 ` [CI v13 13/17] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-28 20:26 ` [CI v13 14/17] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-28 20:26 ` [CI v13 15/17] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-28 20:26 ` [CI v13 16/17] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-28 20:26 ` [CI v13 17/17] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-28 21:01 ` ✗ Fi.CI.BAT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Patchwork
2018-11-28 22:59 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2) Patchwork
2018-11-28 23:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-28 23:15 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-29 10:29 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-29 19:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) Patchwork
2018-11-29 19:56 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-29 20:08 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-29 20:52 ` [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-30 12:52 ` ✗ Fi.CI.IGT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) Patchwork
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