From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3 15/48] drm/i915/xelpd: Provide port/phy mapping for vbt
Date: Fri, 7 May 2021 19:27:47 -0700 [thread overview]
Message-ID: <20210508022820.780227-16-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210508022820.780227-1-matthew.d.roper@intel.com>
From: José Roberto de Souza <jose.souza@intel.com>
This will allow proper DDI initialization based on vbt information.
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 027cc738a168..bf7f76e5241b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1743,8 +1743,24 @@ static enum port dvo_port_to_port(struct drm_i915_private *i915,
[PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
[PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
};
+ static const int xelpd_port_mapping[][3] = {
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+ [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+ [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+ [PORT_D_XELPD] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_E_XELPD] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
+ [PORT_TC1] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
+ [PORT_TC2] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
+ [PORT_TC3] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 },
+ [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
+ };
- if (IS_ALDERLAKE_S(i915))
+ if (DISPLAY_VER(i915) == 13)
+ return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping),
+ ARRAY_SIZE(xelpd_port_mapping[0]),
+ xelpd_port_mapping,
+ dvo_port);
+ else if (IS_ALDERLAKE_S(i915))
return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
ARRAY_SIZE(adls_port_mapping[0]),
adls_port_mapping,
--
2.25.4
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next prev parent reply other threads:[~2021-05-08 2:29 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-08 2:27 [Intel-gfx] [PATCH v3 00/48] Alder Lake-P Support Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 01/48] drm/i915/xelpd: Handle proper AUX interrupt bits Matt Roper
2021-05-12 21:37 ` Lucas De Marchi
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 02/48] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 03/48] drm/i915/xelpd: Define plane capabilities Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 04/48] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
2021-05-14 13:52 ` Imre Deak
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 05/48] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 06/48] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
2021-05-12 17:56 ` Srivatsa, Anusha
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 07/48] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 08/48] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 09/48] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-05-12 18:11 ` Srivatsa, Anusha
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 10/48] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-05-13 19:18 ` Navare, Manasi
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 11/48] drm/i915: Get slice height before computing rc params Matt Roper
2021-05-13 19:20 ` Navare, Manasi
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 12/48] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 13/48] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-05-08 2:52 ` [Intel-gfx] [PATCH v3.1 " Matt Roper
2021-05-12 22:28 ` Lucas De Marchi
2021-05-08 9:10 ` [Intel-gfx] [PATCH v3 " kernel test robot
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 14/48] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-05-08 2:27 ` Matt Roper [this message]
2021-05-12 19:21 ` [Intel-gfx] [PATCH v3 15/48] drm/i915/xelpd: Provide port/phy mapping for vbt Srivatsa, Anusha
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 16/48] drm/i915/adl_p: Add PCH support Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 17/48] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 18/48] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 19/48] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 20/48] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
2021-05-14 9:06 ` Kahola, Mika
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 21/48] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 22/48] drm/i915/adl_p: Handle TC cold Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 23/48] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 24/48] drm/i915/adl_p: Enable modular fia Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 25/48] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 26/48] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 27/48] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 28/48] drm/i915: Move intel_modeset_all_pipes() Matt Roper
2021-05-12 17:03 ` Srivatsa, Anusha
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 29/48] drm/i915/adl_p: MBUS programming Matt Roper
2021-05-14 10:09 ` Lisovskiy, Stanislav
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 30/48] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 31/48] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 32/48] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 33/48] drm/i915/display: Add PSR interrupt error check function Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 34/48] drm/i915/display: Introduce new intel_psr_pause/resume function Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 35/48] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-05-12 19:49 ` Srivatsa, Anusha
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 36/48] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
2021-05-12 23:07 ` Srivatsa, Anusha
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 37/48] drm/i915/adl_p: Add PLL Support Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 38/48] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 39/48] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
2021-05-12 22:11 ` Srivatsa, Anusha
2021-05-13 19:09 ` Navare, Manasi
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 40/48] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
2021-05-13 19:12 ` Navare, Manasi
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 41/48] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
2021-05-13 19:17 ` Navare, Manasi
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 42/48] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 43/48] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 44/48] drm/i915/adl_p: Add IPs stepping mapping Matt Roper
2021-05-12 22:35 ` Srivatsa, Anusha
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 45/48] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
2021-05-14 9:35 ` Kahola, Mika
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 46/48] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
2021-05-14 11:11 ` Kahola, Mika
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 47/48] drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057) Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 48/48] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
2021-05-08 2:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Alder Lake-P Support Patchwork
2021-05-08 3:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev2) Patchwork
2021-05-08 3:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-08 3:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-08 5:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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