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From: "Navare, Manasi" <manasi.d.navare@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 41/48] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
Date: Thu, 13 May 2021 12:17:42 -0700	[thread overview]
Message-ID: <20210513191742.GD23292@labuser-Z97X-UD5H> (raw)
In-Reply-To: <20210508022820.780227-42-matthew.d.roper@intel.com>

On Fri, May 07, 2021 at 07:28:13PM -0700, Matt Roper wrote:
> From: Animesh Manna <animesh.manna@intel.com>
> 
> Respective bit for master or slave to be set for uncompressed
> bigjoiner in dss_ctl1 register.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Looks good to me :

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  6 +++
>  drivers/gpu/drm/i915/display/intel_vdsc.c    | 40 +++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_vdsc.h    |  2 +
>  drivers/gpu/drm/i915/i915_reg.h              |  2 +
>  4 files changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7ae1e3a53dc9..44aabb3ec2b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
>  					 const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(master->base.dev);
>  	struct intel_crtc_state *master_crtc_state;
>  	struct drm_connector_state *conn_state;
>  	struct drm_connector *conn;
> @@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
>  		/* and DSC on slave */
>  		intel_dsc_enable(NULL, crtc_state);
>  	}
> +
> +	if (DISPLAY_VER(dev_priv) >= 13)
> +		intel_uncompressed_joiner_enable(crtc_state);
>  }
>  
>  static void hsw_crtc_enable(struct intel_atomic_state *state,
> @@ -6252,6 +6256,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>  	}
>  
>  	intel_dsc_get_config(pipe_config);
> +	if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)
> +		intel_uncompressed_joiner_get_config(pipe_config);
>  
>  	if (!active) {
>  		/* bigjoiner slave doesn't enable transcoder */
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index afaf6187e255..19cd9531c115 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -1106,6 +1106,22 @@ static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
>  	return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
>  }
>  
> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	u32 dss_ctl1_val = 0;
> +
> +	if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
> +		if (crtc_state->bigjoiner_slave)
> +			dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
> +		else
> +			dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
> +
> +		intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
> +	}
> +}
> +
>  void intel_dsc_enable(struct intel_encoder *encoder,
>  		      const struct intel_crtc_state *crtc_state)
>  {
> @@ -1145,13 +1161,35 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	if (!old_crtc_state->dsc.compression_enable)
> +	if (!(old_crtc_state->dsc.compression_enable &&
> +	      old_crtc_state->bigjoiner))
>  		return;
>  
>  	intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
>  	intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
>  }
>  
> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	u32 dss_ctl1;
> +
> +	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
> +	if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
> +		crtc_state->bigjoiner = true;
> +		if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
> +			crtc_state->bigjoiner_linked_crtc =
> +				intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
> +	} else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
> +		crtc_state->bigjoiner = true;
> +		crtc_state->bigjoiner_slave = true;
> +		if (!WARN_ON(crtc->pipe == PIPE_A))
> +			crtc_state->bigjoiner_linked_crtc =
> +				intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
> +	}
> +}
> +
>  void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 65d301c23580..fe4d45561253 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -12,11 +12,13 @@ struct intel_encoder;
>  struct intel_crtc_state;
>  
>  bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
>  void intel_dsc_enable(struct intel_encoder *encoder,
>  		      const struct intel_crtc_state *crtc_state);
>  void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
>  int intel_dsc_compute_params(struct intel_encoder *encoder,
>  			     struct intel_crtc_state *pipe_config);
> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state);
>  void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
>  enum intel_display_power_domain
>  intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f7cf3ab8db65..00505b011339 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11570,6 +11570,8 @@ enum skl_power_gate {
>  #define  SPLITTER_CONFIGURATION_MASK		REG_GENMASK(26, 25)
>  #define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>  #define  SPLITTER_CONFIGURATION_4_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> +#define  UNCOMPRESSED_JOINER_MASTER		(1 << 21)
> +#define  UNCOMPRESSED_JOINER_SLAVE		(1 << 20)
>  
>  #define _ICL_PIPE_DSS_CTL2_PB			0x78204
>  #define _ICL_PIPE_DSS_CTL2_PC			0x78404
> -- 
> 2.25.4
> 
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  reply	other threads:[~2021-05-13 19:09 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-08  2:27 [Intel-gfx] [PATCH v3 00/48] Alder Lake-P Support Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 01/48] drm/i915/xelpd: Handle proper AUX interrupt bits Matt Roper
2021-05-12 21:37   ` Lucas De Marchi
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 02/48] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 03/48] drm/i915/xelpd: Define plane capabilities Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 04/48] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
2021-05-14 13:52   ` Imre Deak
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 05/48] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 06/48] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
2021-05-12 17:56   ` Srivatsa, Anusha
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 07/48] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 08/48] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 09/48] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-05-12 18:11   ` Srivatsa, Anusha
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 10/48] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-05-13 19:18   ` Navare, Manasi
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 11/48] drm/i915: Get slice height before computing rc params Matt Roper
2021-05-13 19:20   ` Navare, Manasi
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 12/48] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 13/48] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-05-08  2:52   ` [Intel-gfx] [PATCH v3.1 " Matt Roper
2021-05-12 22:28     ` Lucas De Marchi
2021-05-08  9:10   ` [Intel-gfx] [PATCH v3 " kernel test robot
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 14/48] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 15/48] drm/i915/xelpd: Provide port/phy mapping for vbt Matt Roper
2021-05-12 19:21   ` Srivatsa, Anusha
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 16/48] drm/i915/adl_p: Add PCH support Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 17/48] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 18/48] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 19/48] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 20/48] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
2021-05-14  9:06   ` Kahola, Mika
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 21/48] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 22/48] drm/i915/adl_p: Handle TC cold Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 23/48] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 24/48] drm/i915/adl_p: Enable modular fia Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 25/48] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 26/48] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-05-08  2:27 ` [Intel-gfx] [PATCH v3 27/48] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 28/48] drm/i915: Move intel_modeset_all_pipes() Matt Roper
2021-05-12 17:03   ` Srivatsa, Anusha
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 29/48] drm/i915/adl_p: MBUS programming Matt Roper
2021-05-14 10:09   ` Lisovskiy, Stanislav
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 30/48] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 31/48] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 32/48] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 33/48] drm/i915/display: Add PSR interrupt error check function Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 34/48] drm/i915/display: Introduce new intel_psr_pause/resume function Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 35/48] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-05-12 19:49   ` Srivatsa, Anusha
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 36/48] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
2021-05-12 23:07   ` Srivatsa, Anusha
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 37/48] drm/i915/adl_p: Add PLL Support Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 38/48] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 39/48] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
2021-05-12 22:11   ` Srivatsa, Anusha
2021-05-13 19:09   ` Navare, Manasi
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 40/48] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
2021-05-13 19:12   ` Navare, Manasi
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 41/48] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
2021-05-13 19:17   ` Navare, Manasi [this message]
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 42/48] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 43/48] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 44/48] drm/i915/adl_p: Add IPs stepping mapping Matt Roper
2021-05-12 22:35   ` Srivatsa, Anusha
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 45/48] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
2021-05-14  9:35   ` Kahola, Mika
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 46/48] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
2021-05-14 11:11   ` Kahola, Mika
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 47/48] drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057) Matt Roper
2021-05-08  2:28 ` [Intel-gfx] [PATCH v3 48/48] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
2021-05-08  2:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Alder Lake-P Support Patchwork
2021-05-08  3:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev2) Patchwork
2021-05-08  3:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-08  3:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-08  5:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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