From: Imre Deak <imre.deak@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 04/48] drm/i915/xelpd: Handle new location of outputs D and E
Date: Fri, 14 May 2021 16:52:41 +0300 [thread overview]
Message-ID: <20210514135241.GA1296833@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <20210508022820.780227-5-matthew.d.roper@intel.com>
On Fri, May 07, 2021 at 07:27:36PM -0700, Matt Roper wrote:
> The DDI naming template for display version 12 went A-C, TC1-TC6. With
> XE_LPD, that naming scheme for DDI's has now changed to A-E, TC1-TC4.
>
> The XE_LPD design keeps the register offsets and bitfields relating to
> the TC outputs in the same location they were previously. The new "D"
> and "E" outputs now take the locations that were previously used by TC5
> and TC6 outputs, or what we would have considered to be outputs "H" and
> "I" under the legacy lettering scheme.
>
> For the most part everything will just work as long as we initialize the
> output with the proper 'enum port' value. However we do need to take
> care to pick the correct AUX channel when parsing the VBT (e.g., a
> reference to 'AUX D' is actually asking us to use the 8th aux channel,
> not the fourth). We should also make sure that our encoders and aux
> channels are named appropriately so that it's easier to correlate driver
> debug messages with the bspec instructions.
>
> v2:
> - Update handling of TGL_TRANS_CLK_SEL_PORT. (Jose)
>
> v3:
> - Add hpd_pin to handle outputs D and E (Jose)
> - Fixed conversion of BIOS port to aux ch for TC ports (Jose)
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 28 +++++++++++---
> drivers/gpu/drm/i915/display/intel_ddi.c | 40 +++++++++++++++-----
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++-
> drivers/gpu/drm/i915/display/intel_display.h | 8 ++++
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 14 ++++---
> 5 files changed, 74 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index befab891a6b9..027cc738a168 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2853,7 +2853,9 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
> aux_ch = AUX_CH_C;
> break;
> case DP_AUX_D:
> - if (IS_ALDERLAKE_S(i915))
> + if (DISPLAY_VER(i915) == 13)
> + aux_ch = AUX_CH_D_XELPD;
> + else if (IS_ALDERLAKE_S(i915))
> aux_ch = AUX_CH_USBC3;
> else if (IS_DG1(i915) || IS_ROCKETLAKE(i915))
> aux_ch = AUX_CH_USBC2;
> @@ -2861,22 +2863,36 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
> aux_ch = AUX_CH_D;
> break;
> case DP_AUX_E:
> - if (IS_ALDERLAKE_S(i915))
> + if (DISPLAY_VER(i915) == 13)
> + aux_ch = AUX_CH_E_XELPD;
> + else if (IS_ALDERLAKE_S(i915))
> aux_ch = AUX_CH_USBC4;
> else
> aux_ch = AUX_CH_E;
> break;
> case DP_AUX_F:
> - aux_ch = AUX_CH_F;
> + if (DISPLAY_VER(i915) == 13)
> + aux_ch = AUX_CH_USBC1;
> + else
> + aux_ch = AUX_CH_F;
> break;
> case DP_AUX_G:
> - aux_ch = AUX_CH_G;
> + if (DISPLAY_VER(i915) == 13)
> + aux_ch = AUX_CH_USBC2;
> + else
> + aux_ch = AUX_CH_G;
> break;
> case DP_AUX_H:
> - aux_ch = AUX_CH_H;
> + if (DISPLAY_VER(i915) == 13)
> + aux_ch = AUX_CH_USBC3;
> + else
> + aux_ch = AUX_CH_H;
> break;
> case DP_AUX_I:
> - aux_ch = AUX_CH_I;
> + if (DISPLAY_VER(i915) == 13)
> + aux_ch = AUX_CH_USBC4;
> + else
> + aux_ch = AUX_CH_I;
> break;
> default:
> MISSING_CASE(info->alternate_aux_channel);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 0b382e40d594..d37b01b889c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -854,18 +854,19 @@ void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum port port = encoder->port;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> + u32 val;
>
> if (cpu_transcoder != TRANSCODER_EDP) {
> - if (DISPLAY_VER(dev_priv) >= 12)
> - intel_de_write(dev_priv,
> - TRANS_CLK_SEL(cpu_transcoder),
> - TGL_TRANS_CLK_SEL_PORT(port));
> + if (DISPLAY_VER(dev_priv) >= 13)
> + val = TGL_TRANS_CLK_SEL_PORT(phy);
> + else if (DISPLAY_VER(dev_priv) >= 12)
> + val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
> else
> - intel_de_write(dev_priv,
> - TRANS_CLK_SEL(cpu_transcoder),
> - TRANS_CLK_SEL_PORT(port));
> + val = TRANS_CLK_SEL_PORT(encoder->port);
> +
> + intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
> }
> }
>
> @@ -4354,6 +4355,17 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
> i915->hti_state & HDPORT_DDI_USED(phy);
> }
>
> +static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
> + enum port port)
> +{
> + if (port >= PORT_D_XELPD)
> + return HPD_PORT_D + port - PORT_D_XELPD;
> + else if (port >= PORT_TC1)
> + return HPD_PORT_TC1 + port - PORT_TC1;
> + else
> + return HPD_PORT_A + port - PORT_A;
> +}
> +
> static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
> enum port port)
> {
> @@ -4493,7 +4505,13 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder = &dig_port->base;
> encoder->devdata = devdata;
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
> + drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
> + DRM_MODE_ENCODER_TMDS,
> + "DDI %c/PHY %c",
> + port_name(port - PORT_D_XELPD + PORT_D),
> + phy_name(phy));
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>
> drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
> @@ -4604,7 +4622,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->get_config = hsw_ddi_get_config;
> }
>
> - if (IS_DG1(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 13)
> + encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
> + else if (IS_DG1(dev_priv))
> encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
> else if (IS_ROCKETLAKE(dev_priv))
> encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e117fb312216..4aad98913d62 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3681,7 +3681,11 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>
> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> {
> - if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
> + if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
> + return PHY_D + port - PORT_D_XELPD;
> + else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
> + return PHY_F + port - PORT_TC1;
> + else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
> return PHY_B + port - PORT_TC1;
> else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
> return PHY_C + port - PORT_TC1;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index e7764e746c6a..bd69affc791c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -217,6 +217,10 @@ enum port {
> PORT_TC5,
> PORT_TC6,
>
> + /* XE_LPD repositions D/E offsets and bitfields */
> + PORT_D_XELPD = PORT_TC5,
> + PORT_E_XELPD,
> +
> I915_MAX_PORTS
> };
>
> @@ -300,6 +304,10 @@ enum aux_ch {
> AUX_CH_USBC4,
> AUX_CH_USBC5,
> AUX_CH_USBC6,
> +
> + /* XE_LPD repositions D/E offsets and bitfields */
> + AUX_CH_D_XELPD = AUX_CH_USBC5,
> + AUX_CH_E_XELPD,
> };
>
> #define aux_ch_name(a) ((a) + 'A')
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 350b12f0beb8..7c048d2ecf43 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -602,8 +602,8 @@ static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
> case AUX_CH_USBC2:
> case AUX_CH_USBC3:
> case AUX_CH_USBC4:
> - case AUX_CH_USBC5:
> - case AUX_CH_USBC6:
> + case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
> + case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
> return DP_AUX_CH_CTL(aux_ch);
> default:
> MISSING_CASE(aux_ch);
> @@ -625,8 +625,8 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
> case AUX_CH_USBC2:
> case AUX_CH_USBC3:
> case AUX_CH_USBC4:
> - case AUX_CH_USBC5:
> - case AUX_CH_USBC6:
> + case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
> + case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
> return DP_AUX_CH_DATA(aux_ch, index);
> default:
> MISSING_CASE(aux_ch);
> @@ -681,7 +681,11 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
> drm_dp_aux_init(&intel_dp->aux);
>
> /* Failure to allocate our preferred name is not critical */
> - if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
> + if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD)
> + intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
> + aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D),
> + encoder->base.name);
> + else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
> intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
> aux_ch - AUX_CH_USBC1 + '1',
> encoder->base.name);
> --
> 2.25.4
>
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next prev parent reply other threads:[~2021-05-14 13:52 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-08 2:27 [Intel-gfx] [PATCH v3 00/48] Alder Lake-P Support Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 01/48] drm/i915/xelpd: Handle proper AUX interrupt bits Matt Roper
2021-05-12 21:37 ` Lucas De Marchi
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 02/48] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 03/48] drm/i915/xelpd: Define plane capabilities Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 04/48] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
2021-05-14 13:52 ` Imre Deak [this message]
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 05/48] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 06/48] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
2021-05-12 17:56 ` Srivatsa, Anusha
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 07/48] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 08/48] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 09/48] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-05-12 18:11 ` Srivatsa, Anusha
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 10/48] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-05-13 19:18 ` Navare, Manasi
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 11/48] drm/i915: Get slice height before computing rc params Matt Roper
2021-05-13 19:20 ` Navare, Manasi
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 12/48] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 13/48] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-05-08 2:52 ` [Intel-gfx] [PATCH v3.1 " Matt Roper
2021-05-12 22:28 ` Lucas De Marchi
2021-05-08 9:10 ` [Intel-gfx] [PATCH v3 " kernel test robot
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 14/48] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 15/48] drm/i915/xelpd: Provide port/phy mapping for vbt Matt Roper
2021-05-12 19:21 ` Srivatsa, Anusha
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 16/48] drm/i915/adl_p: Add PCH support Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 17/48] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 18/48] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 19/48] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 20/48] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
2021-05-14 9:06 ` Kahola, Mika
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 21/48] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 22/48] drm/i915/adl_p: Handle TC cold Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 23/48] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 24/48] drm/i915/adl_p: Enable modular fia Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 25/48] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 26/48] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-05-08 2:27 ` [Intel-gfx] [PATCH v3 27/48] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 28/48] drm/i915: Move intel_modeset_all_pipes() Matt Roper
2021-05-12 17:03 ` Srivatsa, Anusha
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 29/48] drm/i915/adl_p: MBUS programming Matt Roper
2021-05-14 10:09 ` Lisovskiy, Stanislav
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 30/48] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 31/48] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 32/48] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 33/48] drm/i915/display: Add PSR interrupt error check function Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 34/48] drm/i915/display: Introduce new intel_psr_pause/resume function Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 35/48] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-05-12 19:49 ` Srivatsa, Anusha
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 36/48] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
2021-05-12 23:07 ` Srivatsa, Anusha
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 37/48] drm/i915/adl_p: Add PLL Support Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 38/48] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 39/48] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
2021-05-12 22:11 ` Srivatsa, Anusha
2021-05-13 19:09 ` Navare, Manasi
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 40/48] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
2021-05-13 19:12 ` Navare, Manasi
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 41/48] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
2021-05-13 19:17 ` Navare, Manasi
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 42/48] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 43/48] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 44/48] drm/i915/adl_p: Add IPs stepping mapping Matt Roper
2021-05-12 22:35 ` Srivatsa, Anusha
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 45/48] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
2021-05-14 9:35 ` Kahola, Mika
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 46/48] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
2021-05-14 11:11 ` Kahola, Mika
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 47/48] drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057) Matt Roper
2021-05-08 2:28 ` [Intel-gfx] [PATCH v3 48/48] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
2021-05-08 2:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Alder Lake-P Support Patchwork
2021-05-08 3:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev2) Patchwork
2021-05-08 3:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-08 3:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-08 5:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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