From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 15/15] drm/i915: Define more PS_CTRL bits
Date: Tue, 18 Apr 2023 20:55:28 +0300 [thread overview]
Message-ID: <20230418175528.13117-16-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230418175528.13117-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
To avoid annoying spec lookups let's define more PS_CTRL
bits in the header.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a6343d2e0fa..5baaf6df6951 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4050,6 +4050,9 @@
#define _PS_2B_CTRL 0x68A80
#define _PS_1C_CTRL 0x69180
#define PS_SCALER_EN REG_BIT(31)
+#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
+#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
+#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
@@ -4057,6 +4060,7 @@
#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
+#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
#define PS_BINDING_MASK REG_GENMASK(27, 25)
#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
@@ -4065,8 +4069,15 @@
#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
+#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
+#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
+#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
+#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
+#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
+#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
+#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
#define PS_PWRUP_PROGRESS REG_BIT(17)
#define PS_V_FILTER_BYPASS REG_BIT(8)
#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
--
2.39.2
next prev parent reply other threads:[~2023-04-18 17:56 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
2023-04-18 17:55 ` [Intel-gfx] [PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers Ville Syrjala
2023-04-19 15:11 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 02/15] drm/i915: Relocate VBLANK_EVASION_TIME_US Ville Syrjala
2023-04-19 15:13 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 03/15] drm/i915: Relocate intel_atomic_setup_scalers() Ville Syrjala
2023-04-19 15:16 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 04/15] drm/i915: Relocate skl_get_pfit_config() Ville Syrjala
2023-04-19 15:17 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 05/15] drm/i915: Use REG_BIT() & co for the pre-ilk pfit registers Ville Syrjala
2023-04-19 15:28 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 06/15] drm/i915: Namespace pfit registers properly Ville Syrjala
2023-04-19 15:28 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 07/15] drm/i915: Use REG_BIT() & co. for ilk+ pfit registers Ville Syrjala
2023-04-19 15:29 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 08/15] drm/i915: Drop a useless forward declararion Ville Syrjala
2023-04-19 15:30 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 09/15] drm/i915: Define bitmasks for ilk pfit window pos/size Ville Syrjala
2023-04-19 15:34 ` Jani Nikula
2023-04-20 12:09 ` Ville Syrjälä
2023-04-25 10:49 ` Ville Syrjälä
2023-04-18 17:55 ` [Intel-gfx] [PATCH 10/15] drm/i915: Remove dead scaler register defines Ville Syrjala
2023-04-19 15:35 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits Ville Syrjala
2023-04-18 19:36 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-04-19 15:38 ` Jani Nikula
2023-04-18 22:06 ` [Intel-gfx] [PATCH " kernel test robot
2023-04-19 15:38 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 12/15] drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/ Ville Syrjala
2023-04-19 15:38 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 13/15] drm/i915: Define bitmasks for sik+ scaler window pos/size Ville Syrjala
2023-04-19 15:41 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 14/15] drm/i915: Use REG_BIT() & co. for pipe scaler registers Ville Syrjala
2023-04-19 15:48 ` Jani Nikula
2023-04-18 17:55 ` Ville Syrjala [this message]
2023-04-18 18:31 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Scaler/pfit stuff Patchwork
2023-04-18 22:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scaler/pfit stuff (rev2) Patchwork
2023-04-18 22:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-18 22:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-19 4:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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