From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Ross Zwisler <zwisler@google.com>, stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers
Date: Wed, 19 Apr 2023 18:11:16 +0300 [thread overview]
Message-ID: <87ildrzz3f.fsf@intel.com> (raw)
In-Reply-To: <20230418175528.13117-2-ville.syrjala@linux.intel.com>
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The skl+ scalers only sample 12 bits of PIPESRC so we can't
> do any plane scaling at all when the pipe source size is >4k.
>
> Make sure the pipe source size is also below the scaler's src
> size limits. Might not be 100% accurate, but should at least be
> safe. We can refine the limits later if we discover that recent
> hw is less restricted.
>
> Cc: stable@vger.kernel.org
> Tested-by: Ross Zwisler <zwisler@google.com>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8357
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 473d53610b92..0e7e014fcc71 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -111,6 +111,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> const struct drm_display_mode *adjusted_mode =
> &crtc_state->hw.adjusted_mode;
> + int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
> + int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
> int min_src_w, min_src_h, min_dst_w, min_dst_h;
> int max_src_w, max_src_h, max_dst_w, max_dst_h;
>
> @@ -207,6 +209,21 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> return -EINVAL;
> }
>
> + /*
> + * The pipe scaler does not use all the bits of PIPESRC, at least
> + * on the earlier platforms. So even when we're scaling a plane
> + * the *pipe* source size must not be too large. For simplicity
> + * we assume the limits match the scaler source size limits. Might
> + * not be 100% accurate on all platforms, but good enough for now.
> + */
> + if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) {
> + drm_dbg_kms(&dev_priv->drm,
> + "scaler_user index %u.%u: pipe src size %ux%u "
> + "is out of scaler range\n",
> + crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);
> + return -EINVAL;
> + }
> +
> /* mark this plane as a scaler user in crtc_state */
> scaler_state->scaler_users |= (1 << scaler_user);
> drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2023-04-19 15:11 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
2023-04-18 17:55 ` [Intel-gfx] [PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers Ville Syrjala
2023-04-19 15:11 ` Jani Nikula [this message]
2023-04-18 17:55 ` [Intel-gfx] [PATCH 02/15] drm/i915: Relocate VBLANK_EVASION_TIME_US Ville Syrjala
2023-04-19 15:13 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 03/15] drm/i915: Relocate intel_atomic_setup_scalers() Ville Syrjala
2023-04-19 15:16 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 04/15] drm/i915: Relocate skl_get_pfit_config() Ville Syrjala
2023-04-19 15:17 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 05/15] drm/i915: Use REG_BIT() & co for the pre-ilk pfit registers Ville Syrjala
2023-04-19 15:28 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 06/15] drm/i915: Namespace pfit registers properly Ville Syrjala
2023-04-19 15:28 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 07/15] drm/i915: Use REG_BIT() & co. for ilk+ pfit registers Ville Syrjala
2023-04-19 15:29 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 08/15] drm/i915: Drop a useless forward declararion Ville Syrjala
2023-04-19 15:30 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 09/15] drm/i915: Define bitmasks for ilk pfit window pos/size Ville Syrjala
2023-04-19 15:34 ` Jani Nikula
2023-04-20 12:09 ` Ville Syrjälä
2023-04-25 10:49 ` Ville Syrjälä
2023-04-18 17:55 ` [Intel-gfx] [PATCH 10/15] drm/i915: Remove dead scaler register defines Ville Syrjala
2023-04-19 15:35 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits Ville Syrjala
2023-04-18 19:36 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-04-19 15:38 ` Jani Nikula
2023-04-18 22:06 ` [Intel-gfx] [PATCH " kernel test robot
2023-04-19 15:38 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 12/15] drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/ Ville Syrjala
2023-04-19 15:38 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 13/15] drm/i915: Define bitmasks for sik+ scaler window pos/size Ville Syrjala
2023-04-19 15:41 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 14/15] drm/i915: Use REG_BIT() & co. for pipe scaler registers Ville Syrjala
2023-04-19 15:48 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 15/15] drm/i915: Define more PS_CTRL bits Ville Syrjala
2023-04-18 18:31 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Scaler/pfit stuff Patchwork
2023-04-18 22:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scaler/pfit stuff (rev2) Patchwork
2023-04-18 22:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-18 22:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-19 4:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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