From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 03/19] drm/i915/dsb: Dump the DSB command buffer when DSB fails
Date: Tue, 6 Jun 2023 22:14:48 +0300 [thread overview]
Message-ID: <20230606191504.18099-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230606191504.18099-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Dump the full DSB command buffers and head/tail pointers if the
the DSB hasn't completed its job in time.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 33 +++++++++++++++++++++---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 97e593d9f100..42911abcd3ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -93,6 +93,22 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb)
crtc->base.base.id, crtc->base.name, dsb->id);
}
+static void intel_dsb_dump(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ const u32 *buf = dsb->cmd_buf;
+ int i;
+
+ drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] DSB %d commands {\n",
+ crtc->base.base.id, crtc->base.name, dsb->id);
+ for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
+ drm_dbg_kms(&i915->drm,
+ " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
+ drm_dbg_kms(&i915->drm, "}\n");
+}
+
static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
enum dsb_id id)
{
@@ -258,10 +274,21 @@ void intel_dsb_wait(struct intel_dsb *dsb)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
+ if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
+ u32 offset = i915_ggtt_offset(dsb->vma);
+
+ intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
+ DSB_ENABLE | DSB_HALT);
+
drm_err(&dev_priv->drm,
- "[CRTC:%d:%s] DSB %d timed out waiting for idle\n",
- crtc->base.base.id, crtc->base.name, dsb->id);
+ "[CRTC:%d:%s] DSB %d timed out waiting for idle (current head=0x%x, head=0x%x, tail=0x%x)\n",
+ crtc->base.base.id, crtc->base.name, dsb->id,
+ intel_de_read_fw(dev_priv, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset,
+ intel_de_read_fw(dev_priv, DSB_HEAD(pipe, dsb->id)) - offset,
+ intel_de_read_fw(dev_priv, DSB_TAIL(pipe, dsb->id)) - offset);
+
+ intel_dsb_dump(dsb);
+ }
/* Attempt to reset it */
dsb->free_pos = 0;
--
2.39.3
next prev parent reply other threads:[~2023-06-06 19:15 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-06 19:14 [Intel-gfx] [PATCH v2 00/19] drm/i915: Load LUTs with DSB Ville Syrjala
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 01/19] drm/i915: Constify LUT entries in checker Ville Syrjala
2023-07-05 9:43 ` Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 02/19] drm/i915/dsb: Use non-locked register access Ville Syrjala
2023-06-08 11:46 ` Jani Nikula
2023-09-11 20:22 ` Shankar, Uma
2023-09-12 7:37 ` Jani Nikula
2023-09-12 7:49 ` Shankar, Uma
2023-06-06 19:14 ` Ville Syrjala [this message]
2023-07-11 4:55 ` [Intel-gfx] [PATCH v2 03/19] drm/i915/dsb: Dump the DSB command buffer when DSB fails Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 04/19] drm/i915/dsb: Define more DSB bits Ville Syrjala
2023-09-11 20:32 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 05/19] drm/i915/dsb: Define the contents of some intstructions bit better Ville Syrjala
2023-09-11 20:50 ` Shankar, Uma
2023-09-27 15:38 ` Ville Syrjälä
2023-09-27 16:16 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 06/19] drm/i915/dsb: Avoid corrupting the first register write Ville Syrjala
2023-07-05 9:39 ` Manna, Animesh
2023-07-05 9:46 ` Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 07/19] drm/i915/dsb: Don't use indexed writes when byte enables are not all set Ville Syrjala
2023-07-11 5:00 ` Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 08/19] drm/i915/dsb: Introduce intel_dsb_noop() Ville Syrjala
2023-09-11 20:52 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 09/19] drm/i915/dsb: Introduce intel_dsb_reg_write_masked() Ville Syrjala
2023-09-11 20:55 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 10/19] drm/i915/dsb: Add support for non-posted DSB registers writes Ville Syrjala
2023-07-11 5:43 ` Manna, Animesh
2023-09-11 21:04 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 11/19] drm/i915/dsb: Don't use DSB to load the LUTs during full modeset Ville Syrjala
2023-09-11 21:09 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 12/19] drm/i915/dsb: Load LUTs using the DSB during vblank Ville Syrjala
2023-09-13 16:24 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 13/19] drm/i915/dsb: Use non-posted register writes for legacy LUT Ville Syrjala
2023-09-13 17:02 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 14/19] drm/i915/dsb: Evade transcoder undelayed vblank when using DSB Ville Syrjala
2023-09-13 17:13 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 15/19] drm/i915: Introduce skl_watermark_max_latency() Ville Syrjala
2023-09-13 17:25 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 16/19] drm/i915: Introudce intel_crtc_scanline_to_hw() Ville Syrjala
2023-09-13 17:37 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 17/19] drm/i915/dsb: Use DEwake to combat PkgC latency Ville Syrjala
2023-09-13 18:08 ` Shankar, Uma
2023-09-27 15:51 ` Ville Syrjälä
2023-09-27 16:11 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 18/19] drm/i915/dsb: Re-instate DSB for LUT updates Ville Syrjala
2023-09-13 18:09 ` Shankar, Uma
2025-01-13 19:26 ` Ed Maste
2025-01-17 14:51 ` Ville Syrjälä
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 19/19] drm/i915: Do state check for color management changes Ville Syrjala
2023-06-06 22:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Load LUTs with DSB (rev2) Patchwork
2023-06-06 22:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-06-06 22:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-07 14:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-27 16:05 ` [Intel-gfx] [PATCH v2 00/19] drm/i915: Load LUTs with DSB Ville Syrjälä
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