From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 04/19] drm/i915/dsb: Define more DSB bits
Date: Tue, 6 Jun 2023 22:14:49 +0300 [thread overview]
Message-ID: <20230606191504.18099-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230606191504.18099-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Define all the DSB register bits so I don't have to look through
bspec to find them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb_regs.h | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h
index 12535d478775..210e2665441d 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h
@@ -37,6 +37,19 @@
#define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)
#define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
#define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)
+#define DSB_HP_IDLE_STATUS REG_BIT(31)
+#define DSB_DEWAKE_STATUS REG_BIT(30)
+#define DSB_REQARB_SM_STATE_MASK REG_GENMASK(29, 27)
+#define DSB_SAFE_WINDOW_LIVE REG_BIT(26)
+#define DSB_VTDFAULT_ARB_SM_STATE_MASK REG_GENMASK(25, 23)
+#define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20)
+#define DSB_SAFE_WINDOW REG_BIT(19)
+#define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17)
+#define DSB_BUSY_ON_DELAYED_VBLANK REG_BIT(16)
+#define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13)
+#define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7)
+#define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4)
+#define DSB_RUN_SM_STATE_MASK REG_GENMASK(2, 0)
#define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
#define DSB_ATS_FAULT_INT_EN REG_BIT(20)
#define DSB_GTT_FAULT_INT_EN REG_BIT(19)
@@ -58,10 +71,28 @@
#define DSB_RM_READY_TIMEOUT_VALUE(x) REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */
#define DSB_RMTIMEOUTREG_CAPTURE(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34)
#define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)
+#define DSB_ENABLE_DEWAKE REG_BIT(31)
+#define DSB_SCANLINE_FOR_DEWAKE_MASK REG_GENMASK(30, 0)
+#define DSB_SCANLINE_FOR_DEWAKE(x) REG_FIELD_PREP(DSB_SCANLINE_FOR_DEWAKE_MASK, (x))
#define DSB_PMCTRL_2(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c)
+#define DSB_MMIOGEN_DEWAKE_DIS REG_BIT(31)
+#define DSB_FORCE_DEWAKE REG_BIT(23)
+#define DSB_BLOCK_DEWAKE_EXTENSION REG_BIT(15)
+#define DSB_OVERRIDE_DC5_DC6_OK REG_BIT(7)
#define DSB_PF_LN_LOWER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x40)
#define DSB_PF_LN_UPPER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x44)
#define DSB_BUFRPT_CNT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x48)
#define DSB_CHICKEN(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0)
+#define DSB_FORCE_DMA_SYNC_RESET REG_BIT(31)
+#define DSB_FORCE_VTD_ENGIE_RESET REG_BIT(30)
+#define DSB_DISABLE_IPC_DEMOTE REG_BIT(29)
+#define DSB_SKIP_WAITS_EN REG_BIT(23)
+#define DSB_EXTEND_HP_IDLE REG_BIT(16)
+#define DSB_CTRL_WAIT_SAFE_WINDOW REG_BIT(15)
+#define DSB_CTRL_NO_WAIT_VBLANK REG_BIT(14)
+#define DSB_INST_WAIT_SAFE_WINDOW REG_BIT(7)
+#define DSB_INST_NO_WAIT_VBLANK REG_BIT(6)
+#define DSB_MMIOGEN_DEWAKE_DIS_CHICKEN REG_BIT(2)
+#define DSB_DISABLE_MMIO_COUNT_FOR_INDEXED REG_BIT(0)
#endif /* __INTEL_DSB_REGS_H__ */
--
2.39.3
next prev parent reply other threads:[~2023-06-06 19:15 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-06 19:14 [Intel-gfx] [PATCH v2 00/19] drm/i915: Load LUTs with DSB Ville Syrjala
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 01/19] drm/i915: Constify LUT entries in checker Ville Syrjala
2023-07-05 9:43 ` Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 02/19] drm/i915/dsb: Use non-locked register access Ville Syrjala
2023-06-08 11:46 ` Jani Nikula
2023-09-11 20:22 ` Shankar, Uma
2023-09-12 7:37 ` Jani Nikula
2023-09-12 7:49 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 03/19] drm/i915/dsb: Dump the DSB command buffer when DSB fails Ville Syrjala
2023-07-11 4:55 ` Manna, Animesh
2023-06-06 19:14 ` Ville Syrjala [this message]
2023-09-11 20:32 ` [Intel-gfx] [PATCH v2 04/19] drm/i915/dsb: Define more DSB bits Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 05/19] drm/i915/dsb: Define the contents of some intstructions bit better Ville Syrjala
2023-09-11 20:50 ` Shankar, Uma
2023-09-27 15:38 ` Ville Syrjälä
2023-09-27 16:16 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 06/19] drm/i915/dsb: Avoid corrupting the first register write Ville Syrjala
2023-07-05 9:39 ` Manna, Animesh
2023-07-05 9:46 ` Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 07/19] drm/i915/dsb: Don't use indexed writes when byte enables are not all set Ville Syrjala
2023-07-11 5:00 ` Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 08/19] drm/i915/dsb: Introduce intel_dsb_noop() Ville Syrjala
2023-09-11 20:52 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 09/19] drm/i915/dsb: Introduce intel_dsb_reg_write_masked() Ville Syrjala
2023-09-11 20:55 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 10/19] drm/i915/dsb: Add support for non-posted DSB registers writes Ville Syrjala
2023-07-11 5:43 ` Manna, Animesh
2023-09-11 21:04 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 11/19] drm/i915/dsb: Don't use DSB to load the LUTs during full modeset Ville Syrjala
2023-09-11 21:09 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 12/19] drm/i915/dsb: Load LUTs using the DSB during vblank Ville Syrjala
2023-09-13 16:24 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 13/19] drm/i915/dsb: Use non-posted register writes for legacy LUT Ville Syrjala
2023-09-13 17:02 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 14/19] drm/i915/dsb: Evade transcoder undelayed vblank when using DSB Ville Syrjala
2023-09-13 17:13 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 15/19] drm/i915: Introduce skl_watermark_max_latency() Ville Syrjala
2023-09-13 17:25 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 16/19] drm/i915: Introudce intel_crtc_scanline_to_hw() Ville Syrjala
2023-09-13 17:37 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 17/19] drm/i915/dsb: Use DEwake to combat PkgC latency Ville Syrjala
2023-09-13 18:08 ` Shankar, Uma
2023-09-27 15:51 ` Ville Syrjälä
2023-09-27 16:11 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 18/19] drm/i915/dsb: Re-instate DSB for LUT updates Ville Syrjala
2023-09-13 18:09 ` Shankar, Uma
2025-01-13 19:26 ` Ed Maste
2025-01-17 14:51 ` Ville Syrjälä
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 19/19] drm/i915: Do state check for color management changes Ville Syrjala
2023-06-06 22:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Load LUTs with DSB (rev2) Patchwork
2023-06-06 22:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-06-06 22:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-07 14:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-27 16:05 ` [Intel-gfx] [PATCH v2 00/19] drm/i915: Load LUTs with DSB Ville Syrjälä
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