From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Shankar, Uma" <uma.shankar@intel.com>,
Ville Syrjala <ville.syrjala@linux.intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v2 02/19] drm/i915/dsb: Use non-locked register access
Date: Tue, 12 Sep 2023 10:37:56 +0300 [thread overview]
Message-ID: <87cyynet9n.fsf@intel.com> (raw)
In-Reply-To: <DM4PR11MB6360F00A1944B8F6D83FC19DF4F2A@DM4PR11MB6360.namprd11.prod.outlook.com>
On Mon, 11 Sep 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Thursday, June 8, 2023 5:16 PM
>> To: Ville Syrjala <ville.syrjala@linux.intel.com>; intel-gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH v2 02/19] drm/i915/dsb: Use non-locked register
>> access
>>
>> On Tue, 06 Jun 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Avoid the locking overhead for DSB registers. We don't need the locks
>> > and intel_dsb_commit() in particular needs to be called from the
>> > vblank evade critical section and thus needs to be fast.
>>
>> Mmmh, I always find it slightly puzzling to encounter _fw calls in code, wondering
>> what the rationale was, and why we can use the _fw variants.
>>
>> Should we start adding comments explaining why?
>
> I believe it’s a light weight write without any locks and forcewake.
That part is clear; the why isn't. :)
> Maybe a comment to explain the rationale would be good.
>
> With that added, this is:
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>
>> BR,
>> Jani.
>>
>>
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_dsb.c | 18 +++++++++---------
>> > 1 file changed, 9 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
>> > b/drivers/gpu/drm/i915/display/intel_dsb.c
>> > index bed058d2c3ac..97e593d9f100 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> > @@ -96,7 +96,7 @@ static bool assert_dsb_has_room(struct intel_dsb
>> > *dsb) static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
>> > enum dsb_id id)
>> > {
>> > - return intel_de_read(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY;
>> > + return intel_de_read_fw(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY;
>> > }
>> >
>> > static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
>> > @@ -243,13 +243,13 @@ void intel_dsb_commit(struct intel_dsb *dsb, bool
>> wait_for_vblank)
>> > return;
>> > }
>> >
>> > - intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
>> > - (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) |
>> > - DSB_ENABLE);
>> > - intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
>> > - i915_ggtt_offset(dsb->vma));
>> > - intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
>> > - i915_ggtt_offset(dsb->vma) + tail);
>> > + intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
>> > + (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) |
>> > + DSB_ENABLE);
>> > + intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id),
>> > + i915_ggtt_offset(dsb->vma));
>> > + intel_de_write_fw(dev_priv, DSB_TAIL(pipe, dsb->id),
>> > + i915_ggtt_offset(dsb->vma) + tail);
>> > }
>> >
>> > void intel_dsb_wait(struct intel_dsb *dsb) @@ -266,7 +266,7 @@ void
>> > intel_dsb_wait(struct intel_dsb *dsb)
>> > /* Attempt to reset it */
>> > dsb->free_pos = 0;
>> > dsb->ins_start_offset = 0;
>> > - intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
>> > + intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
>> > }
>> >
>> > /**
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel
next prev parent reply other threads:[~2023-09-12 7:38 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-06 19:14 [Intel-gfx] [PATCH v2 00/19] drm/i915: Load LUTs with DSB Ville Syrjala
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 01/19] drm/i915: Constify LUT entries in checker Ville Syrjala
2023-07-05 9:43 ` Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 02/19] drm/i915/dsb: Use non-locked register access Ville Syrjala
2023-06-08 11:46 ` Jani Nikula
2023-09-11 20:22 ` Shankar, Uma
2023-09-12 7:37 ` Jani Nikula [this message]
2023-09-12 7:49 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 03/19] drm/i915/dsb: Dump the DSB command buffer when DSB fails Ville Syrjala
2023-07-11 4:55 ` Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 04/19] drm/i915/dsb: Define more DSB bits Ville Syrjala
2023-09-11 20:32 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 05/19] drm/i915/dsb: Define the contents of some intstructions bit better Ville Syrjala
2023-09-11 20:50 ` Shankar, Uma
2023-09-27 15:38 ` Ville Syrjälä
2023-09-27 16:16 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 06/19] drm/i915/dsb: Avoid corrupting the first register write Ville Syrjala
2023-07-05 9:39 ` Manna, Animesh
2023-07-05 9:46 ` Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 07/19] drm/i915/dsb: Don't use indexed writes when byte enables are not all set Ville Syrjala
2023-07-11 5:00 ` Manna, Animesh
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 08/19] drm/i915/dsb: Introduce intel_dsb_noop() Ville Syrjala
2023-09-11 20:52 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 09/19] drm/i915/dsb: Introduce intel_dsb_reg_write_masked() Ville Syrjala
2023-09-11 20:55 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 10/19] drm/i915/dsb: Add support for non-posted DSB registers writes Ville Syrjala
2023-07-11 5:43 ` Manna, Animesh
2023-09-11 21:04 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 11/19] drm/i915/dsb: Don't use DSB to load the LUTs during full modeset Ville Syrjala
2023-09-11 21:09 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 12/19] drm/i915/dsb: Load LUTs using the DSB during vblank Ville Syrjala
2023-09-13 16:24 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 13/19] drm/i915/dsb: Use non-posted register writes for legacy LUT Ville Syrjala
2023-09-13 17:02 ` Shankar, Uma
2023-06-06 19:14 ` [Intel-gfx] [PATCH v2 14/19] drm/i915/dsb: Evade transcoder undelayed vblank when using DSB Ville Syrjala
2023-09-13 17:13 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 15/19] drm/i915: Introduce skl_watermark_max_latency() Ville Syrjala
2023-09-13 17:25 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 16/19] drm/i915: Introudce intel_crtc_scanline_to_hw() Ville Syrjala
2023-09-13 17:37 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 17/19] drm/i915/dsb: Use DEwake to combat PkgC latency Ville Syrjala
2023-09-13 18:08 ` Shankar, Uma
2023-09-27 15:51 ` Ville Syrjälä
2023-09-27 16:11 ` Shankar, Uma
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 18/19] drm/i915/dsb: Re-instate DSB for LUT updates Ville Syrjala
2023-09-13 18:09 ` Shankar, Uma
2025-01-13 19:26 ` Ed Maste
2025-01-17 14:51 ` Ville Syrjälä
2023-06-06 19:15 ` [Intel-gfx] [PATCH v2 19/19] drm/i915: Do state check for color management changes Ville Syrjala
2023-06-06 22:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Load LUTs with DSB (rev2) Patchwork
2023-06-06 22:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-06-06 22:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-07 14:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-27 16:05 ` [Intel-gfx] [PATCH v2 00/19] drm/i915: Load LUTs with DSB Ville Syrjälä
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