* [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB
@ 2025-06-24 7:49 Mitul Golani
2025-06-24 7:49 ` [PATCH v7 01/18] drm/i915/vrr: Refactor vmin/vmax stuff Mitul Golani
` (19 more replies)
0 siblings, 20 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Control DC Balance Adjustment bit to accomodate changes along
with VRR DSB implementation.
Mitul Golani (10):
drm/i915/display: Add source param for dc balance
drm/i915/display: Add VRR DC balance registers
drm/i915/vrr: Add DC Balance params to crtc_state
drm/i915/vrr: Add state dump for DC Balance params
drm/i915/vrr: Add compute config for DC Balance params
drm/i915/vrr: Write DC balance params to hw registers
drm/i915/vrr: Add function to check if DC Balance Possible
drm/i915/display: Add function to configure PIPEDMC_EVT_CTL
drm/i915/vrr: Enable Adaptive sync counter bit
drm/i915/vrr: Enable DC Balance
Ville Syrjälä (8):
drm/i915/vrr: Refactor vmin/vmax stuff
drm/i915/display: Add pipe dmc registers and bits for DC Balance
drm/i915/vrr: Add functions to read out vmin/vmax stuff
drm/i915: Extract vrr_vblank_start()
drm/i915/vrr: Implement vblank evasion with DC balancing
drm/i915/dsb: Add pipedmc dc balance enable/disable
drm/i915/vrr: Restructure VRR enablement bit
drm/i915/vrr: Pause DC Balancing for DSB commits
.../drm/i915/display/intel_crtc_state_dump.c | 8 +
drivers/gpu/drm/i915/display/intel_display.c | 26 ++
.../drm/i915/display/intel_display_device.h | 1 +
.../drm/i915/display/intel_display_types.h | 7 +
drivers/gpu/drm/i915/display/intel_dmc.c | 35 +++
drivers/gpu/drm/i915/display/intel_dmc.h | 7 +
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 51 ++++
drivers/gpu/drm/i915/display/intel_dsb.c | 31 ++-
drivers/gpu/drm/i915/display/intel_vblank.c | 33 ++-
drivers/gpu/drm/i915/display/intel_vrr.c | 240 +++++++++++++++---
drivers/gpu/drm/i915/display/intel_vrr.h | 5 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 45 ++++
12 files changed, 449 insertions(+), 40 deletions(-)
--
2.48.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v7 01/18] drm/i915/vrr: Refactor vmin/vmax stuff
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 02/18] drm/i915/display: Add source param for dc balance Mitul Golani
` (18 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Refactor vmin/vmax functions for better computation.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 41 +++++++++++-------------
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 3eed37f271b0..dd8fe4b49690 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -146,37 +146,41 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
}
-int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
+static int intel_vrr_vtotal(const struct intel_crtc_state *crtc_state, int vmin_vmax)
{
struct intel_display *display = to_intel_display(crtc_state);
- /* Min vblank actually determined by flipline */
if (DISPLAY_VER(display) >= 13)
- return intel_vrr_vmin_flipline(crtc_state);
+ return vmin_vmax;
else
- return intel_vrr_vmin_flipline(crtc_state) +
- intel_vrr_real_vblank_delay(crtc_state);
+ return vmin_vmax + intel_vrr_real_vblank_delay(crtc_state);
}
-int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
+static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
+ int vmin_vmax)
{
- struct intel_display *display = to_intel_display(crtc_state);
+ return intel_vrr_vtotal(crtc_state, vmin_vmax) -
+ intel_vrr_vblank_exit_length(crtc_state);
+}
- if (DISPLAY_VER(display) >= 13)
- return crtc_state->vrr.vmax;
- else
- return crtc_state->vrr.vmax +
- intel_vrr_real_vblank_delay(crtc_state);
+int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
+{
+ return intel_vrr_vtotal(crtc_state, intel_vrr_vmin_flipline(crtc_state));
+}
+
+int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
+{
+ return intel_vrr_vtotal(crtc_state, crtc_state->vrr.vmax);
}
int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
{
- return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
+ return intel_vrr_vblank_start(crtc_state, intel_vrr_vmin_flipline(crtc_state));
}
int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
{
- return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
+ return intel_vrr_vblank_start(crtc_state, crtc_state->vrr.vmax);
}
static bool
@@ -257,14 +261,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
static
int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
- int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
-
- if (DISPLAY_VER(display) >= 13)
- return crtc_vtotal;
- else
- return crtc_vtotal -
- intel_vrr_real_vblank_delay(crtc_state);
+ return intel_vrr_vtotal(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);
}
static
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 02/18] drm/i915/display: Add source param for dc balance
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-06-24 7:49 ` [PATCH v7 01/18] drm/i915/vrr: Refactor vmin/vmax stuff Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 03/18] drm/i915/display: Add pipe dmc registers and bits for DC Balance Mitul Golani
` (17 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Add source param for dc balance enablement further.
--v2:
- Arrange in alphabetic order. (Ankit)
- Update name. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 0ac5484c0043..201a22d71bf0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -196,6 +196,7 @@ struct intel_display_platforms {
((__display)->platform.dgfx && DISPLAY_VER(__display) == 14)) && \
HAS_DSC(__display))
#define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11)
+#define HAS_VRR_DC_BALANCE(__display) (DISPLAY_VER(__display) >= 30)
#define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
#define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical)
#define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv)
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 03/18] drm/i915/display: Add pipe dmc registers and bits for DC Balance
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-06-24 7:49 ` [PATCH v7 01/18] drm/i915/vrr: Refactor vmin/vmax stuff Mitul Golani
2025-06-24 7:49 ` [PATCH v7 02/18] drm/i915/display: Add source param for dc balance Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 04/18] drm/i915/display: Add VRR DC balance registers Mitul Golani
` (16 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add pipe dmc registers and access bits for DC Balance params
configuration and enablement.
--v2:
- Separate register definitions for transcoder and
pipe dmc. (Ankit)
- Use MMIO pipe macros instead of transcoder ones. (Ankit)
- Remove dev_priv use. (Jani, Nikula)
--v3:
- Add all register address, from capital alphabet to small. (Ankit)
- Add EVT CTL registers.
- Add co-author tag.
- Add event flag for Triggering DC Balance.
Co-authored-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 6f406315dd65..66cc92cc3f50 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -394,4 +394,55 @@ enum pipedmc_event_id {
#define DMC_WAKELOCK_CTL_REQ REG_BIT(31)
#define DMC_WAKELOCK_CTL_ACK REG_BIT(15)
+#define _PIPEDMC_DCB_CTL_A 0x5f1a0
+#define _PIPEDMC_DCB_CTL_B 0x5f5a0
+#define PIPEDMC_DCB_CTL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A,\
+ _PIPEDMC_DCB_CTL_B)
+#define PIPEDMC_ADAPTIVE_DCB_ENABLE REG_BIT(31)
+
+#define _PIPEDMC_DCB_VBLANK_A 0x5f1bc
+#define _PIPEDMC_DCB_VBLANK_B 0x5f5bc
+#define PIPEDMC_DCB_VBLANK(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A,\
+ _PIPEDMC_DCB_VBLANK_B)
+
+#define _PIPEDMC_DCB_SLOPE_A 0x5f1b8
+#define _PIPEDMC_DCB_SLOPE_B 0x5f5b8
+#define PIPEDMC_DCB_SLOPE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A,\
+ _PIPEDMC_DCB_SLOPE_B)
+
+#define _PIPEDMC_DCB_GUARDBAND_A 0x5f1b4
+#define _PIPEDMC_DCB_GUARDBAND_B 0x5f5b4
+#define PIPEDMC_DCB_GUARDBAND(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A,\
+ _PIPEDMC_DCB_GUARDBAND_B)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A 0x5f1ac
+#define _PIPEDMC_DCB_MAX_INCREASE_B 0x5f5ac
+#define PIPEDMC_DCB_MAX_INCREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A,\
+ _PIPEDMC_DCB_MAX_INCREASE_B)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A 0x5f1b0
+#define _PIPEDMC_DCB_MAX_DECREASE_B 0x5f5b0
+#define PIPEDMC_DCB_MAX_DECREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A,\
+ _PIPEDMC_DCB_MAX_DECREASE_B)
+
+#define _PIPEDMC_DCB_VMIN_A 0x5f1a4
+#define _PIPEDMC_DCB_VMIN_B 0x5f5a4
+#define PIPEDMC_DCB_VMIN(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A,\
+ _PIPEDMC_DCB_VMIN_B)
+
+#define _PIPEDMC_DCB_VMAX_A 0x5f1a8
+#define _PIPEDMC_DCB_VMAX_B 0x5f5a8
+#define PIPEDMC_DCB_VMAX(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A,\
+ _PIPEDMC_DCB_VMAX_B)
+
+#define _PIPEDMC_DCB_DEBUG_A 0x5f1c0
+#define _PIPEDMC_DCB_DEBUG_B 0x5f5c0
+#define PIPEDMC_DCB_DEBUG(pipe) _MMIO_PIPE(pipe, _PIPEDMC_DCB_DEBUG_A,\
+ _PIPEDMC_DCB_DEBUG_B)
+
+#define _PIPEDMC_EVT_CTL_3_A 0x5f040
+#define _PIPEDMC_EVT_CTL_3_B 0x5f440
+#define PIPEDMC_EVT_CTL_3(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_3_A,\
+ _PIPEDMC_EVT_CTL_3_B)
+
#endif /* __INTEL_DMC_REGS_H__ */
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 04/18] drm/i915/display: Add VRR DC balance registers
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (2 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 03/18] drm/i915/display: Add pipe dmc registers and bits for DC Balance Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 8:13 ` Jani Nikula
2025-06-24 7:49 ` [PATCH v7 05/18] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
` (15 subsequent siblings)
19 siblings, 1 reply; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Add VRR register offsets and bits to access DC Balance configuration.
--v2:
- Separate register definitions. (Ankit)
- Remove usage of dev_priv. (Jani, Nikula)
--v3:
- Convert register address offset, from capital to small. (Ankit)
- Move mask bits near to register offsets. (Ankit)
--v4:
- Use _MMIO_TRANS wherever possible. (Jani)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index ba9b9215dc11..c5cba5879f40 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -8,6 +8,50 @@
#include "intel_display_reg_defs.h"
+/* VRR registers */
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604d4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614d4
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
+ _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
+#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0)
+#define VRR_DCB_ADJ_FLIPLINE(flipline) REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \
+ (flipline))
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604d8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614d8
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
+ _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
+#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0)
+#define VRR_DCB_ADJ_VMAX(vmax) REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax))
+
+#define _TRANS_VRR_DCB_FLIPLINE_A 0x60418
+#define _TRANS_VRR_DCB_FLIPLINE_B 0x61418
+#define TRANS_VRR_DCB_FLIPLINE(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_FLIPLINE_A, \
+ _TRANS_VRR_DCB_FLIPLINE_B)
+#define VRR_DCB_FLIPLINE_MASK REG_GENMASK(19, 0)
+#define VRR_DCB_FLIPLINE(flipline) REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \
+ (flipline))
+
+#define _TRANS_VRR_DCB_VMAX_A 0x60414
+#define _TRANS_VRR_DCB_VMAX_B 0x61414
+#define TRANS_VRR_DCB_VMAX(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_VMAX_A, \
+ _TRANS_VRR_DCB_VMAX_B)
+#define VRR_DCB_VMAX_MASK REG_GENMASK(19, 0)
+#define VRR_DCB_VMAX(vmax) REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax))
+
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604c0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614c0
+#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans) _MMIO_TRANS(trans, \
+ _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
+ _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
+#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31)
+
#define _TRANS_VRR_CTL_A 0x60420
#define _TRANS_VRR_CTL_B 0x61420
#define _TRANS_VRR_CTL_C 0x62420
@@ -20,6 +64,7 @@
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
+#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28)
#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 05/18] drm/i915/vrr: Add functions to read out vmin/vmax stuff
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (3 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 04/18] drm/i915/display: Add VRR DC balance registers Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 06/18] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
` (14 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.
--v2:
- Correct Author details.
--v3:
- Separate register details from this patch.
--v4:
- Add mask macros.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 50 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 5 +++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index dd8fe4b49690..d7bc35b07bab 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -769,3 +769,53 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
if (crtc_state->vrr.enable)
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
+
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 tmp = 0;
+
+ tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder));
+
+ if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
+ return -1;
+
+ return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 tmp = 0;
+
+ tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder));
+
+ if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
+ return -1;
+
+ return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 tmp = 0;
+
+ tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder));
+
+ return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 tmp = 0;
+
+ tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX(cpu_transcoder));
+
+ return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 38bf9996b883..e62b8b50aec6 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -42,4 +42,9 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
+
#endif /* __INTEL_VRR_H__ */
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 06/18] drm/i915/vrr: Add DC Balance params to crtc_state
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (4 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 05/18] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 8:14 ` Jani Nikula
2025-06-24 7:49 ` [PATCH v7 07/18] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
` (13 subsequent siblings)
19 siblings, 1 reply; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Add DC Balance params to crtc_state, also add state checker
params for related properties.
--v3:
- Seggregate crtc_state params with this patch. (Ankit)
--v4:
- Update commit message and header. (Ankit)
- Add +1 to VMIN and VMAX only when it is non-zero. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++
.../drm/i915/display/intel_display_types.h | 7 ++++++
drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++++++++++
3 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index de8bf292897c..939366ecea85 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5429,6 +5429,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
PIPE_CONF_CHECK_BOOL(cmrr.enable);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
}
if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 30c7315fc25e..e5461900c15b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1316,6 +1316,13 @@ struct intel_crtc_state {
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
u32 vsync_end, vsync_start;
+ struct {
+ bool enable;
+ u16 vmin, vmax;
+ u16 guardband, slope;
+ u16 max_increase, max_decrease;
+ u16 vblank_target;
+ } dc_balance;
} vrr;
/* Content Match Refresh Rate state */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index d7bc35b07bab..4016da70ece2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -10,6 +10,7 @@
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_dmc_regs.h"
#include "intel_vrr.h"
#include "intel_vrr_regs.h"
@@ -699,6 +700,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
u32 trans_vrr_ctl, trans_vrr_vsync;
bool vrr_enable;
@@ -761,6 +764,25 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
else
crtc_state->vrr.enable = vrr_enable;
+ if (HAS_VRR_DC_BALANCE(display)) {
+ crtc_state->vrr.dc_balance.vmin =
+ intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) ?
+ intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) + 1 : 0;
+ crtc_state->vrr.dc_balance.vmax =
+ intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) ?
+ intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) + 1 : 0;
+ crtc_state->vrr.dc_balance.guardband =
+ intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
+ crtc_state->vrr.dc_balance.max_increase =
+ intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
+ crtc_state->vrr.dc_balance.max_decrease =
+ intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
+ crtc_state->vrr.dc_balance.slope =
+ intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
+ crtc_state->vrr.dc_balance.vblank_target =
+ intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
+ }
+
/*
* #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
* Since CMRR is currently disabled, set this flag for VRR for now.
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 07/18] drm/i915/vrr: Add state dump for DC Balance params
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (5 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 06/18] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 08/18] drm/i915/vrr: Add compute config " Mitul Golani
` (12 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Add state dump for dc balance params to track DC Balance
crtc state config.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 0c7f91046996..7a3d97df24c0 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -304,6 +304,14 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n",
intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config),
intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config));
+ drm_printf(&p, "vrr: dc balance: %s, vmin: %d vmax: %d guardband: %d, slope: %d max increase: %d max decrease: %d Vblank target: %d\n",
+ str_yes_no(pipe_config->vrr.dc_balance.enable),
+ pipe_config->vrr.dc_balance.vmin, pipe_config->vrr.dc_balance.vmax,
+ pipe_config->vrr.dc_balance.guardband,
+ pipe_config->vrr.dc_balance.slope,
+ pipe_config->vrr.dc_balance.max_increase,
+ pipe_config->vrr.dc_balance.max_decrease,
+ pipe_config->vrr.dc_balance.vblank_target);
drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
DRM_MODE_ARG(&pipe_config->hw.mode));
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 08/18] drm/i915/vrr: Add compute config for DC Balance params
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (6 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 07/18] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 09/18] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
` (11 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Compute DC Balance parameters and tunable params based on
experiments.
--v2:
- Document tunable params. (Ankit)
--v3:
- Add line spaces to compute config. (Ankit)
- Remove redundancy checks.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 4016da70ece2..07cd7cb38b97 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -16,6 +16,13 @@
#define FIXED_POINT_PRECISION 100
#define CMRR_PRECISION_TOLERANCE 10
+/*
+ * Tunable parameters for DC Balance correction.
+ * These are captured based on experimentations.
+ */
+#define DCB_CORRECTION_SENSITIVITY 30
+#define DCB_CORRECTION_AGGRESSIVENESS 1000
+#define DCB_BLANK_TARGET 50
bool intel_vrr_is_capable(struct intel_connector *connector)
{
@@ -409,6 +416,24 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
(crtc_state->hw.adjusted_mode.crtc_vtotal -
crtc_state->hw.adjusted_mode.vsync_end);
}
+
+ if (crtc_state->vrr.dc_balance.enable) {
+ crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
+ crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
+ crtc_state->vrr.dc_balance.max_increase =
+ crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+ crtc_state->vrr.dc_balance.max_decrease =
+ crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+ crtc_state->vrr.dc_balance.guardband =
+ DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
+ DCB_CORRECTION_SENSITIVITY, 100);
+ crtc_state->vrr.dc_balance.slope =
+ DIV_ROUND_UP(DCB_CORRECTION_AGGRESSIVENESS * 10,
+ crtc_state->vrr.dc_balance.guardband);
+ crtc_state->vrr.dc_balance.vblank_target =
+ DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
+ DCB_BLANK_TARGET, 100);
+ }
}
void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 09/18] drm/i915/vrr: Write DC balance params to hw registers
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (7 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 08/18] drm/i915/vrr: Add compute config " Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 10/18] drm/i915: Extract vrr_vblank_start() Mitul Golani
` (10 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Write DC Balance parameters to hw registers.
--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)
--v3:
- Write registers at compute config.
- Update condition for write.
--v4:
- Address issue with state checker.
--v5:
- Initialise some more dc balance register while enabling VRR.
--v6:
- FLIPLINE_CFG need to be configure at last, as it is double buffer
arming point.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 43 ++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 07cd7cb38b97..ce23bcab1033 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -622,6 +622,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
if (!crtc_state->vrr.enable)
return;
@@ -648,16 +650,57 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
}
}
+
+ if (crtc_state->vrr.dc_balance.enable) {
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
+ VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+ intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
+ VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+ intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
+ VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
+ VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
+ intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
+ crtc_state->vrr.dc_balance.vmin - 1);
+ intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
+ crtc_state->vrr.dc_balance.vmax - 1);
+ intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
+ crtc_state->vrr.dc_balance.max_increase);
+ intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
+ crtc_state->vrr.dc_balance.max_decrease);
+ intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
+ crtc_state->vrr.dc_balance.guardband);
+ intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
+ crtc_state->vrr.dc_balance.slope);
+ intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
+ crtc_state->vrr.dc_balance.vblank_target);
+ }
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_display *display = to_intel_display(old_crtc_state);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
if (!old_crtc_state->vrr.enable)
return;
+ if (old_crtc_state->vrr.dc_balance.enable) {
+ intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
+ }
+
if (!intel_vrr_always_use_vrr_tg(display)) {
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
trans_vrr_ctl(old_crtc_state));
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 10/18] drm/i915: Extract vrr_vblank_start()
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (8 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 09/18] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 11/18] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
` (9 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Initialise delayed vblank position for evasion logic.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vblank.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 70ba7aa26bf4..d544e274bcfa 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -642,6 +642,14 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
return pre_commit_crtc_state(old_crtc_state, new_crtc_state);
}
+static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+ if (intel_vrr_is_push_sent(crtc_state))
+ return intel_vrr_vmin_vblank_start(crtc_state);
+ else
+ return intel_vrr_vmax_vblank_start(crtc_state);
+}
+
void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state,
struct intel_vblank_evade_ctx *evade)
@@ -668,10 +676,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
new_crtc_state->update_m_n || new_crtc_state->update_lrr);
- if (intel_vrr_is_push_sent(crtc_state))
- evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
- else
- evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
+ evade->vblank_start = vrr_vblank_start(crtc_state);
vblank_delay = intel_vrr_vblank_delay(crtc_state);
} else {
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 11/18] drm/i915/vrr: Implement vblank evasion with DC balancing
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (9 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 10/18] drm/i915: Extract vrr_vblank_start() Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
` (8 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add vblank evasion logic when vrr is already enabled along with
dc balance is computed.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 31 ++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vblank.c | 26 +++++++++++++++--
2 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 53d8ae3a70e9..ec624dc1987e 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -721,7 +721,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
if (crtc_state->has_psr)
intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
- if (pre_commit_is_vrr_active(state, crtc)) {
+ if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
+ int vblank_delay = intel_vrr_vblank_delay(crtc_state);
+ int vmin_vblank_start, vmax_vblank_start;
+
+ vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+
+ if (vmin_vblank_start >= 0) {
+ end = vmin_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ }
+
+ vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+ if (vmax_vblank_start >= 0) {
+ end = vmax_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ }
+
+ vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+ end = vmin_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+
+ vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+ end = vmax_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ } else if (pre_commit_is_vrr_active(state, crtc)) {
int vblank_delay = intel_vrr_vblank_delay(crtc_state);
end = intel_vrr_vmin_vblank_start(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index d544e274bcfa..685768124852 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -644,10 +644,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
{
- if (intel_vrr_is_push_sent(crtc_state))
- return intel_vrr_vmin_vblank_start(crtc_state);
+ bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
+ int vblank_start;
+
+ if (!crtc_state->vrr.dc_balance.enable) {
+ if (is_push_sent)
+ return intel_vrr_vmin_vblank_start(crtc_state);
+ else
+ return intel_vrr_vmax_vblank_start(crtc_state);
+ }
+
+ if (is_push_sent)
+ vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
else
- return intel_vrr_vmax_vblank_start(crtc_state);
+ vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+ if (vblank_start >= 0)
+ return vblank_start;
+
+ if (is_push_sent)
+ vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+ else
+ vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+
+ return vblank_start;
}
void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (10 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 11/18] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 8:25 ` Jani Nikula
2025-06-24 7:49 ` [PATCH v7 13/18] drm/i915/vrr: Restructure VRR enablement bit Mitul Golani
` (7 subsequent siblings)
19 siblings, 1 reply; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add function to control DC balance enable/disable bit via DSB.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 5 +++++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 4572e87d9bfa..1726c0ab18c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1607,3 +1607,21 @@ void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n",
crtc->base.base.id, crtc->base.name, tmp);
}
+
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+
+ intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
+ PIPEDMC_ADAPTIVE_DCB_ENABLE);
+}
+
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+
+ intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 7820fa5aed3e..d45d51bedb87 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -8,11 +8,14 @@
#include <linux/types.h>
+
enum pipe;
+struct intel_crtc;
struct drm_printer;
struct intel_crtc_state;
struct intel_display;
struct intel_dmc_snapshot;
+struct intel_dsb;
void intel_dmc_init(struct intel_display *display);
void intel_dmc_load_program(struct intel_display *display);
@@ -36,5 +39,7 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
void assert_main_dmc_loaded(struct intel_display *display);
void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
#endif /* __INTEL_DMC_H__ */
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 13/18] drm/i915/vrr: Restructure VRR enablement bit
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (11 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 14/18] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
` (6 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Restructure bits for VRR enablement.
--v2:
- Separate multiple enablement from one patch.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 29 ++++++++++++------------
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index ce23bcab1033..91d4fa0d2bf3 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -624,6 +624,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
+ u32 ctl;
if (!crtc_state->vrr.enable)
return;
@@ -638,19 +639,6 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
TRANS_PUSH_EN);
- if (!intel_vrr_always_use_vrr_tg(display)) {
- intel_vrr_set_db_point_and_transmission_line(crtc_state);
-
- if (crtc_state->cmrr.enable) {
- intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
- VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
- trans_vrr_ctl(crtc_state));
- } else {
- intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
- VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
- }
- }
-
if (crtc_state->vrr.dc_balance.enable) {
intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
@@ -675,6 +663,12 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
crtc_state->vrr.dc_balance.vblank_target);
}
+
+ ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
+ if (crtc_state->cmrr.enable)
+ ctl |= VRR_CTL_CMRR_ENABLE;
+
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -683,10 +677,17 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
+ u32 ctl;
if (!old_crtc_state->vrr.enable)
return;
+ ctl = trans_vrr_ctl(old_crtc_state);
+ if (intel_vrr_always_use_vrr_tg(display))
+ ctl |= VRR_CTL_VRR_ENABLE;
+
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
+
if (old_crtc_state->vrr.dc_balance.enable) {
intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
@@ -702,8 +703,6 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
}
if (!intel_vrr_always_use_vrr_tg(display)) {
- intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
- trans_vrr_ctl(old_crtc_state));
intel_de_wait_for_clear(display,
TRANS_VRR_STATUS(display, cpu_transcoder),
VRR_STATUS_VRR_EN_LIVE, 1000);
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 14/18] drm/i915/vrr: Pause DC Balancing for DSB commits
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (12 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 13/18] drm/i915/vrr: Restructure VRR enablement bit Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 15/18] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
` (5 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pause the DMC DC Balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.
--v2:
- Remove typo. (Ankit)
- Separate vrr enable structuring. (Ankit)
--v3:
- Add gaurd before accessing DC balance bits.
- Remove redundancy checks.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.c | 7 +++++++
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 939366ecea85..d1f6ff4bfc99 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7231,6 +7231,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
}
if (new_crtc_state->use_dsb) {
+ if (new_crtc_state->vrr.dc_balance.enable) {
+ /*
+ * Pause the DMC DC balancing for the remainder of
+ * the commit so that vmin/vmax won't change after
+ * we've baked them into the DSB vblank evasion
+ * commands.
+ *
+ * FIXME maybe need a small delay here to make sure
+ * DMC has finished updating the values? Or we need
+ * a better DMC<->driver protocol that gives is real
+ * guarantees about that...
+ */
+ intel_pipedmc_dcb_disable(NULL, crtc);
+ }
+
if (intel_crtc_needs_color_update(new_crtc_state))
intel_color_commit_noarm(new_crtc_state->dsb_commit,
new_crtc_state);
@@ -7276,6 +7291,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
new_crtc_state);
+
+ if (new_crtc_state->vrr.dc_balance.enable)
+ intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
+
intel_dsb_interrupt(new_crtc_state->dsb_commit);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 91d4fa0d2bf3..98d305d02f35 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
+#include "intel_dmc.h"
#include "intel_dp.h"
#include "intel_dmc_regs.h"
#include "intel_vrr.h"
@@ -668,6 +669,9 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
if (crtc_state->cmrr.enable)
ctl |= VRR_CTL_CMRR_ENABLE;
+ if (crtc_state->vrr.dc_balance.enable)
+ intel_pipedmc_dcb_enable(NULL, crtc);
+
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
}
@@ -682,6 +686,9 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->vrr.enable)
return;
+ if (old_crtc_state->vrr.dc_balance.enable)
+ intel_pipedmc_dcb_disable(NULL, crtc);
+
ctl = trans_vrr_ctl(old_crtc_state);
if (intel_vrr_always_use_vrr_tg(display))
ctl |= VRR_CTL_VRR_ENABLE;
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 15/18] drm/i915/vrr: Add function to check if DC Balance Possible
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (13 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 14/18] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 16/18] drm/i915/display: Add function to configure PIPEDMC_EVT_CTL Mitul Golani
` (4 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Add function to check if DC Balance possibile on
requested PIPE and also validate along with DISPLAY_VER
check.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 98d305d02f35..8d7d19b86376 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -256,6 +256,22 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
+static
+int intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
+
+ /*
+ * FIXME: Currently Firmware supports DC Balancing on PIPE A
+ * and PIPE B. Account those limitation while computing DC
+ * Balance parameters.
+ */
+ return (HAS_VRR_DC_BALANCE(display) &&
+ ((pipe == PIPE_A) || (pipe == PIPE_B)));
+}
+
static
void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
{
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 16/18] drm/i915/display: Add function to configure PIPEDMC_EVT_CTL
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (14 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 15/18] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 17/18] drm/i915/vrr: Enable Adaptive sync counter bit Mitul Golani
` (3 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Configure PIPEDMC_EVT_CTL_3 register with required event flags.
--v2:
- Initialize with redundant flags. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 17 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++++--
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1726c0ab18c2..3b81a7b48035 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -810,6 +810,23 @@ void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0);
}
+void intel_dmc_configure_dc_balance_ctl_regs(struct intel_display *display,
+ enum pipe pipe, bool enable)
+{
+ u32 val = REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+ DMC_EVT_CTL_TYPE_EDGE_0_1);
+
+ if (enable)
+ val |= DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING |
+ REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+ PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER);
+ else
+ val |= REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+ DMC_EVENT_FALSE);
+
+ intel_de_write(display, PIPEDMC_EVT_CTL_3(pipe), val);
+}
+
/**
* intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG
* C-state exit
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index d45d51bedb87..032f3e3072ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -24,6 +24,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state);
void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state);
void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
bool block);
+void intel_dmc_configure_dc_balance_ctl_regs(struct intel_display *display,
+ enum pipe pipe, bool enable);
void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
enum pipe pipe, bool enable);
void intel_dmc_fini(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8d7d19b86376..5eb4a7e97291 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -685,8 +685,10 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
if (crtc_state->cmrr.enable)
ctl |= VRR_CTL_CMRR_ENABLE;
- if (crtc_state->vrr.dc_balance.enable)
+ if (crtc_state->vrr.dc_balance.enable) {
+ intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true);
intel_pipedmc_dcb_enable(NULL, crtc);
+ }
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
}
@@ -702,8 +704,10 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->vrr.enable)
return;
- if (old_crtc_state->vrr.dc_balance.enable)
+ if (old_crtc_state->vrr.dc_balance.enable) {
intel_pipedmc_dcb_disable(NULL, crtc);
+ intel_dmc_configure_dc_balance_ctl_regs(display, pipe, false);
+ }
ctl = trans_vrr_ctl(old_crtc_state);
if (intel_vrr_always_use_vrr_tg(display))
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 17/18] drm/i915/vrr: Enable Adaptive sync counter bit
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (15 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 16/18] drm/i915/display: Add function to configure PIPEDMC_EVT_CTL Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 7:49 ` [PATCH v7 18/18] drm/i915/vrr: Enable DC Balance Mitul Golani
` (2 subsequent siblings)
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Add enable/disable frame counters for DC Balance odd and even
frame count calculation.
--v2:
Update commit message
--v3:
- Driver should not control adjustment enable bit, as that
is already being controlled by firmware. Release bit from
driver computation.
- Commit message update.
--v4:
- Configure PIPEDMC_EVT_CTL enable/disable call.
--v5:
- Add Adaptive sync counter enable.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5eb4a7e97291..d5359a96054b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -686,6 +686,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
ctl |= VRR_CTL_CMRR_ENABLE;
if (crtc_state->vrr.dc_balance.enable) {
+ intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
+ ADAPTIVE_SYNC_COUNTER_EN);
intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true);
intel_pipedmc_dcb_enable(NULL, crtc);
}
@@ -707,6 +709,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
if (old_crtc_state->vrr.dc_balance.enable) {
intel_pipedmc_dcb_disable(NULL, crtc);
intel_dmc_configure_dc_balance_ctl_regs(display, pipe, false);
+ intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
}
ctl = trans_vrr_ctl(old_crtc_state);
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7 18/18] drm/i915/vrr: Enable DC Balance
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (16 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 17/18] drm/i915/vrr: Enable Adaptive sync counter bit Mitul Golani
@ 2025-06-24 7:49 ` Mitul Golani
2025-06-24 8:54 ` ✓ i915.CI.BAT: success for Enable/Disable DC balance along with VRR DSB (rev7) Patchwork
2025-06-24 12:40 ` ✗ i915.CI.Full: failure " Patchwork
19 siblings, 0 replies; 24+ messages in thread
From: Mitul Golani @ 2025-06-24 7:49 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal, jani.nikula
Enable DC Balance from vrr compute config and related hw flag.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index d5359a96054b..e48a795a8c18 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -277,6 +277,9 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
{
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+ if (intel_vrr_dc_balance_possible(crtc_state))
+ crtc_state->vrr.dc_balance.enable = true;
}
/*
@@ -686,6 +689,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
ctl |= VRR_CTL_CMRR_ENABLE;
if (crtc_state->vrr.dc_balance.enable) {
+ ctl |= VRR_CTL_DCB_ADJ_ENABLE;
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
ADAPTIVE_SYNC_COUNTER_EN);
intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true);
--
2.48.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v7 04/18] drm/i915/display: Add VRR DC balance registers
2025-06-24 7:49 ` [PATCH v7 04/18] drm/i915/display: Add VRR DC balance registers Mitul Golani
@ 2025-06-24 8:13 ` Jani Nikula
0 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2025-06-24 8:13 UTC (permalink / raw)
To: Mitul Golani, intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal
On Tue, 24 Jun 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Add VRR register offsets and bits to access DC Balance configuration.
>
> --v2:
> - Separate register definitions. (Ankit)
> - Remove usage of dev_priv. (Jani, Nikula)
>
> --v3:
> - Convert register address offset, from capital to small. (Ankit)
> - Move mask bits near to register offsets. (Ankit)
>
> --v4:
> - Use _MMIO_TRANS wherever possible. (Jani)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
I just took the time to clean this file up. See commit 880e07d53849
("drm/i915/vrr: fix register file style"). Please follow the style.
> ---
> drivers/gpu/drm/i915/display/intel_vrr_regs.h | 45 +++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index ba9b9215dc11..c5cba5879f40 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -8,6 +8,50 @@
>
> #include "intel_display_reg_defs.h"
>
> +/* VRR registers */
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604d4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614d4
> +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans) _MMIO_TRANS(trans, \
> + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
> + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
> +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24)
> +#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0)
> +#define VRR_DCB_ADJ_FLIPLINE(flipline) REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \
> + (flipline))
> +
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604d8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614d8
> +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans) _MMIO_TRANS(trans, \
> + _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
> + _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
> +#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24)
> +#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0)
> +#define VRR_DCB_ADJ_VMAX(vmax) REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax))
> +
> +#define _TRANS_VRR_DCB_FLIPLINE_A 0x60418
> +#define _TRANS_VRR_DCB_FLIPLINE_B 0x61418
> +#define TRANS_VRR_DCB_FLIPLINE(trans) _MMIO_TRANS(trans, \
> + _TRANS_VRR_DCB_FLIPLINE_A, \
> + _TRANS_VRR_DCB_FLIPLINE_B)
> +#define VRR_DCB_FLIPLINE_MASK REG_GENMASK(19, 0)
> +#define VRR_DCB_FLIPLINE(flipline) REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \
> + (flipline))
> +
> +#define _TRANS_VRR_DCB_VMAX_A 0x60414
> +#define _TRANS_VRR_DCB_VMAX_B 0x61414
> +#define TRANS_VRR_DCB_VMAX(trans) _MMIO_TRANS(trans, \
> + _TRANS_VRR_DCB_VMAX_A, \
> + _TRANS_VRR_DCB_VMAX_B)
> +#define VRR_DCB_VMAX_MASK REG_GENMASK(19, 0)
> +#define VRR_DCB_VMAX(vmax) REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax))
> +
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604c0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614c0
> +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans) _MMIO_TRANS(trans, \
> + _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
> + _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
> +#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31)
> +
> #define _TRANS_VRR_CTL_A 0x60420
> #define _TRANS_VRR_CTL_B 0x61420
> #define _TRANS_VRR_CTL_C 0x62420
> @@ -20,6 +64,7 @@
> #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
> #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
> #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
> +#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28)
Highest to lowest bit.
> #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
> #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v7 06/18] drm/i915/vrr: Add DC Balance params to crtc_state
2025-06-24 7:49 ` [PATCH v7 06/18] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
@ 2025-06-24 8:14 ` Jani Nikula
0 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2025-06-24 8:14 UTC (permalink / raw)
To: Mitul Golani, intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal
On Tue, 24 Jun 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Add DC Balance params to crtc_state, also add state checker
> params for related properties.
>
> --v3:
> - Seggregate crtc_state params with this patch. (Ankit)
>
> --v4:
> - Update commit message and header. (Ankit)
> - Add +1 to VMIN and VMAX only when it is non-zero. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++
> .../drm/i915/display/intel_display_types.h | 7 ++++++
> drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++++++++++
> 3 files changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index de8bf292897c..939366ecea85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5429,6 +5429,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
> PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
> PIPE_CONF_CHECK_BOOL(cmrr.enable);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
> }
>
> if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 30c7315fc25e..e5461900c15b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1316,6 +1316,13 @@ struct intel_crtc_state {
> u8 pipeline_full;
> u16 flipline, vmin, vmax, guardband;
> u32 vsync_end, vsync_start;
> + struct {
> + bool enable;
> + u16 vmin, vmax;
> + u16 guardband, slope;
> + u16 max_increase, max_decrease;
> + u16 vblank_target;
> + } dc_balance;
> } vrr;
>
> /* Content Match Refresh Rate state */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index d7bc35b07bab..4016da70ece2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -10,6 +10,7 @@
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_dmc_regs.h"
Please keep the includes sorted.
> #include "intel_vrr.h"
> #include "intel_vrr_regs.h"
>
> @@ -699,6 +700,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum pipe pipe = crtc->pipe;
> u32 trans_vrr_ctl, trans_vrr_vsync;
> bool vrr_enable;
>
> @@ -761,6 +764,25 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> else
> crtc_state->vrr.enable = vrr_enable;
>
> + if (HAS_VRR_DC_BALANCE(display)) {
> + crtc_state->vrr.dc_balance.vmin =
> + intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) ?
> + intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) + 1 : 0;
> + crtc_state->vrr.dc_balance.vmax =
> + intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) ?
> + intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) + 1 : 0;
> + crtc_state->vrr.dc_balance.guardband =
> + intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
> + crtc_state->vrr.dc_balance.max_increase =
> + intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
> + crtc_state->vrr.dc_balance.max_decrease =
> + intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
> + crtc_state->vrr.dc_balance.slope =
> + intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
> + crtc_state->vrr.dc_balance.vblank_target =
> + intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
> + }
> +
> /*
> * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
> * Since CMRR is currently disabled, set this flag for VRR for now.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable
2025-06-24 7:49 ` [PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
@ 2025-06-24 8:25 ` Jani Nikula
0 siblings, 0 replies; 24+ messages in thread
From: Jani Nikula @ 2025-06-24 8:25 UTC (permalink / raw)
To: Mitul Golani, intel-xe, intel-gfx; +Cc: ville.syrjala, ankit.k.nautiyal
On Tue, 24 Jun 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add function to control DC balance enable/disable bit via DSB.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 18 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dmc.h | 5 +++++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 4572e87d9bfa..1726c0ab18c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1607,3 +1607,21 @@ void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
> drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n",
> crtc->base.base.id, crtc->base.name, tmp);
> }
> +
> +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
> +{
> + struct intel_display *display = to_intel_display(crtc);
> + enum pipe pipe = crtc->pipe;
> +
> + intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
> + PIPEDMC_ADAPTIVE_DCB_ENABLE);
> +}
> +
> +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
> +{
> + struct intel_display *display = to_intel_display(crtc);
> + enum pipe pipe = crtc->pipe;
> +
> + intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 7820fa5aed3e..d45d51bedb87 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -8,11 +8,14 @@
>
> #include <linux/types.h>
>
> +
Please run checkpatch before sending.
> enum pipe;
> +struct intel_crtc;
> struct drm_printer;
> struct intel_crtc_state;
> struct intel_display;
> struct intel_dmc_snapshot;
> +struct intel_dsb;
>
> void intel_dmc_init(struct intel_display *display);
> void intel_dmc_load_program(struct intel_display *display);
> @@ -36,5 +39,7 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
> void assert_main_dmc_loaded(struct intel_display *display);
>
> void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
> +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
> +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
>
> #endif /* __INTEL_DMC_H__ */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ i915.CI.BAT: success for Enable/Disable DC balance along with VRR DSB (rev7)
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (17 preceding siblings ...)
2025-06-24 7:49 ` [PATCH v7 18/18] drm/i915/vrr: Enable DC Balance Mitul Golani
@ 2025-06-24 8:54 ` Patchwork
2025-06-24 12:40 ` ✗ i915.CI.Full: failure " Patchwork
19 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2025-06-24 8:54 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5256 bytes --]
== Series Details ==
Series: Enable/Disable DC balance along with VRR DSB (rev7)
URL : https://patchwork.freedesktop.org/series/147799/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16747 -> Patchwork_147799v7
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/index.html
Participating hosts (45 -> 44)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_147799v7 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@load:
- bat-mtlp-9: [PASS][1] -> [ABORT][2] ([i915#13494])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/bat-mtlp-9/igt@i915_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/bat-mtlp-9/igt@i915_module_load@load.html
* igt@i915_selftest@live@sanitycheck:
- fi-kbl-7567u: [PASS][3] -> [DMESG-WARN][4] ([i915#13735]) +67 other tests dmesg-warn
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
* igt@i915_selftest@live@workarounds:
- bat-dg2-9: [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/bat-dg2-9/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/bat-dg2-9/igt@i915_selftest@live@workarounds.html
- bat-dg2-14: [PASS][7] -> [DMESG-FAIL][8] ([i915#12061]) +1 other test dmesg-fail
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/bat-dg2-14/igt@i915_selftest@live@workarounds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/bat-dg2-14/igt@i915_selftest@live@workarounds.html
* igt@kms_busy@basic@flip:
- fi-kbl-7567u: [PASS][9] -> [DMESG-WARN][10] ([i915#13735] / [i915#180])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/fi-kbl-7567u/igt@kms_busy@basic@flip.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/fi-kbl-7567u/igt@kms_busy@basic@flip.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- fi-kbl-7567u: [PASS][11] -> [DMESG-WARN][12] ([i915#13735] / [i915#13890] / [i915#180]) +52 other tests dmesg-warn
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html
#### Possible fixes ####
* igt@i915_selftest@live:
- bat-mtlp-8: [DMESG-FAIL][13] ([i915#12061]) -> [PASS][14] +1 other test pass
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/bat-mtlp-8/igt@i915_selftest@live.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/bat-mtlp-8/igt@i915_selftest@live.html
- bat-adlp-9: [ABORT][15] ([i915#14365]) -> [PASS][16] +1 other test pass
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/bat-adlp-9/igt@i915_selftest@live.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/bat-adlp-9/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-arls-5: [DMESG-FAIL][17] ([i915#12061]) -> [PASS][18] +1 other test pass
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/bat-arls-5/igt@i915_selftest@live@workarounds.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/bat-arls-5/igt@i915_selftest@live@workarounds.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-bsw-n3050: [DMESG-WARN][19] ([i915#13736]) -> [PASS][20] +1 other test pass
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
[i915#13735]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13735
[i915#13736]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13736
[i915#13890]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13890
[i915#14365]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14365
[i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
Build changes
-------------
* Linux: CI_DRM_16747 -> Patchwork_147799v7
CI-20190529: 20190529
CI_DRM_16747: da56936fad6f5e1d5f0cef8b50277bfb071eefe7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8422: 9b9c9136b17a2ed0680fb9589d51446c03698b37 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_147799v7: da56936fad6f5e1d5f0cef8b50277bfb071eefe7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/index.html
[-- Attachment #2: Type: text/html, Size: 6494 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ i915.CI.Full: failure for Enable/Disable DC balance along with VRR DSB (rev7)
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (18 preceding siblings ...)
2025-06-24 8:54 ` ✓ i915.CI.BAT: success for Enable/Disable DC balance along with VRR DSB (rev7) Patchwork
@ 2025-06-24 12:40 ` Patchwork
19 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2025-06-24 12:40 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 97868 bytes --]
== Series Details ==
Series: Enable/Disable DC balance along with VRR DSB (rev7)
URL : https://patchwork.freedesktop.org/series/147799/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16747_full -> Patchwork_147799v7_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_147799v7_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_147799v7_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_147799v7_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_cursor@viewport:
- shard-dg2: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-10/igt@kms_plane_cursor@viewport.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_plane_cursor@viewport.html
* igt@kms_plane_cursor@viewport@pipe-d-hdmi-a-3-size-64:
- shard-dg2: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_plane_cursor@viewport@pipe-d-hdmi-a-3-size-64.html
Known issues
------------
Here are the changes found in Patchwork_147799v7_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8411])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8411])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-tglu-1: NOTRUN -> [SKIP][6] ([i915#11078])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@device_reset@unbind-cold-reset-rebind.html
- shard-dg2-9: NOTRUN -> [SKIP][7] ([i915#11078])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@device_reset@unbind-cold-reset-rebind.html
* igt@gem_ccs@suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][8] ([i915#9323])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-4/igt@gem_ccs@suspend-resume.html
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#9323])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-process:
- shard-dg2-9: NOTRUN -> [SKIP][10] ([i915#7697])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-tglu-1: NOTRUN -> [SKIP][11] ([i915#6335])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_persistence@hang:
- shard-dg2-9: NOTRUN -> [SKIP][12] ([i915#8555])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-mtlp: NOTRUN -> [SKIP][13] ([i915#8555]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#8555])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-6/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_persistence@legacy-engines-hang:
- shard-snb: NOTRUN -> [SKIP][15] ([i915#1099])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-snb4/igt@gem_ctx_persistence@legacy-engines-hang.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg2: NOTRUN -> [SKIP][16] ([i915#280])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglu-1: NOTRUN -> [SKIP][17] ([i915#280])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_exec_balancer@bonded-pair:
- shard-dg2-9: NOTRUN -> [SKIP][18] ([i915#4771])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-tglu: NOTRUN -> [SKIP][19] ([i915#4525]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-tglu-1: NOTRUN -> [SKIP][20] ([i915#4525])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_fence@submit3:
- shard-mtlp: NOTRUN -> [SKIP][21] ([i915#4812])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@gem_exec_fence@submit3.html
* igt@gem_exec_fence@submit67:
- shard-dg2-9: NOTRUN -> [SKIP][22] ([i915#4812])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_exec_fence@submit67.html
* igt@gem_exec_flush@basic-batch-kernel-default-uc:
- shard-dg2-9: NOTRUN -> [SKIP][23] ([i915#3539] / [i915#4852]) +1 other test skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-dg2-9: NOTRUN -> [SKIP][24] ([i915#3539])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_exec_flush@basic-wb-prw-default:
- shard-dg2: NOTRUN -> [SKIP][25] ([i915#3539] / [i915#4852])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#5107])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-cpu-wc-active:
- shard-mtlp: NOTRUN -> [SKIP][27] ([i915#3281]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@gem_exec_reloc@basic-cpu-wc-active.html
* igt@gem_exec_reloc@basic-gtt-wc-noreloc:
- shard-dg2-9: NOTRUN -> [SKIP][28] ([i915#3281]) +4 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
* igt@gem_exec_reloc@basic-wc:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#3281]) +4 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@gem_exec_reloc@basic-wc.html
* igt@gem_exec_schedule@fairslice:
- shard-rkl: [PASS][30] -> [DMESG-WARN][31] ([i915#12964]) +22 other tests dmesg-warn
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-8/igt@gem_exec_schedule@fairslice.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-7/igt@gem_exec_schedule@fairslice.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#4537] / [i915#4812]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_fence_thrash@bo-write-verify-y:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#4860]) +2 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@gem_fence_thrash@bo-write-verify-y.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][34] ([i915#4860])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-dg2-9: NOTRUN -> [SKIP][35] ([i915#4860])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gem_lmem_swapping@massive-random:
- shard-tglu-1: NOTRUN -> [SKIP][36] ([i915#4613]) +2 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@gem_lmem_swapping@massive-random.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-mtlp: NOTRUN -> [SKIP][37] ([i915#4613]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][38] -> [TIMEOUT][39] ([i915#5493]) +1 other test timeout
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-4/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_media_vme:
- shard-tglu: NOTRUN -> [SKIP][40] ([i915#284])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@gem_media_vme.html
* igt@gem_mmap@pf-nonblock:
- shard-dg2-9: NOTRUN -> [SKIP][41] ([i915#4083]) +3 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_mmap@pf-nonblock.html
* igt@gem_mmap_gtt@basic-short:
- shard-dg2-9: NOTRUN -> [SKIP][42] ([i915#4077]) +3 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_mmap_gtt@basic-short.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#4077]) +5 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_mmap_wc@read-write-distinct:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#4083]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@gem_mmap_wc@read-write-distinct.html
* igt@gem_mmap_wc@set-cache-level:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4083]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@gem_mmap_wc@set-cache-level.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-dg2-9: NOTRUN -> [SKIP][46] ([i915#3282]) +2 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_pread@display:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#3282]) +3 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@gem_pread@display.html
* igt@gem_pread@exhaustion:
- shard-tglu-1: NOTRUN -> [WARN][48] ([i915#2658])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@gem_pread@exhaustion.html
* igt@gem_pxp@create-regular-buffer:
- shard-dg2-9: NOTRUN -> [SKIP][49] ([i915#4270]) +1 other test skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_pxp@create-regular-buffer.html
* igt@gem_pxp@create-regular-context-1:
- shard-rkl: NOTRUN -> [TIMEOUT][50] ([i915#12917] / [i915#12964])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-4/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@display-protected-crc:
- shard-rkl: [PASS][51] -> [TIMEOUT][52] ([i915#12917] / [i915#12964]) +1 other test timeout
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-8/igt@gem_pxp@display-protected-crc.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-7/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@hw-rejects-pxp-context:
- shard-tglu-1: NOTRUN -> [SKIP][53] ([i915#13398])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@gem_pxp@hw-rejects-pxp-context.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-rkl: [PASS][54] -> [TIMEOUT][55] ([i915#12964]) +1 other test timeout
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-8/igt@gem_pxp@regular-baseline-src-copy-readible.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-2/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#4270]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@gem_pxp@reject-modify-context-protection-off-3.html
* igt@gem_readwrite@new-obj:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#3282]) +2 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@gem_readwrite@new-obj.html
* igt@gem_render_copy@x-tiled-to-vebox-y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][58] ([i915#8428]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@gem_render_copy@x-tiled-to-vebox-y-tiled.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][59] ([i915#5190] / [i915#8428]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#5190] / [i915#8428]) +3 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#4079])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_tiled_pread_pwrite:
- shard-dg2-9: NOTRUN -> [SKIP][62] ([i915#4079])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_tiled_pread_pwrite.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-dg2-9: NOTRUN -> [SKIP][63] ([i915#3297]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-tglu-1: NOTRUN -> [SKIP][64] ([i915#3297])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-tglu: NOTRUN -> [SKIP][65] ([i915#3297])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@gem_userptr_blits@readonly-unsync.html
* igt@gem_userptr_blits@relocations:
- shard-dg2-9: NOTRUN -> [SKIP][66] ([i915#3281] / [i915#3297])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gem_userptr_blits@relocations.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#3297])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@gem_userptr_blits@unsync-overlap.html
- shard-rkl: NOTRUN -> [SKIP][68] ([i915#3297])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-4/igt@gem_userptr_blits@unsync-overlap.html
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#3297]) +1 other test skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@gem_userptr_blits@unsync-overlap.html
* igt@gem_workarounds@suspend-resume:
- shard-rkl: [PASS][70] -> [INCOMPLETE][71] ([i915#13356])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-8/igt@gem_workarounds@suspend-resume.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-3/igt@gem_workarounds@suspend-resume.html
* igt@gen7_exec_parse@basic-allocation:
- shard-dg2-9: NOTRUN -> [SKIP][72] +3 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gen7_exec_parse@basic-allocation.html
* igt@gen9_exec_parse@bb-large:
- shard-tglu: NOTRUN -> [SKIP][73] ([i915#2527] / [i915#2856]) +1 other test skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@gen9_exec_parse@bb-large.html
* igt@gen9_exec_parse@bb-oversize:
- shard-tglu-1: NOTRUN -> [SKIP][74] ([i915#2527] / [i915#2856]) +2 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@gen9_exec_parse@bb-oversize.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-dg2-9: NOTRUN -> [SKIP][75] ([i915#2856]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#2856]) +2 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@gen9_exec_parse@shadow-peek.html
* igt@gen9_exec_parse@valid-registers:
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#2527])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-4/igt@gen9_exec_parse@valid-registers.html
- shard-mtlp: NOTRUN -> [SKIP][78] ([i915#2856])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@gen9_exec_parse@valid-registers.html
* igt@i915_drm_fdinfo@busy-idle-check-all@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#11527]) +6 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@i915_drm_fdinfo@busy-idle-check-all@rcs0.html
* igt@i915_drm_fdinfo@virtual-busy-hang-all:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#14118])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@i915_drm_fdinfo@virtual-busy-hang-all.html
- shard-mtlp: NOTRUN -> [SKIP][81] ([i915#14118])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@i915_drm_fdinfo@virtual-busy-hang-all.html
* igt@i915_drm_fdinfo@virtual-busy-idle:
- shard-dg2-9: NOTRUN -> [SKIP][82] ([i915#14118])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@i915_drm_fdinfo@virtual-busy-idle.html
* igt@i915_module_load@reload-no-display:
- shard-dg2-9: NOTRUN -> [DMESG-WARN][83] ([i915#13029])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@i915_module_load@reload-no-display.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-tglu-1: NOTRUN -> [SKIP][84] ([i915#8399])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_freq_api@freq-suspend@gt0:
- shard-dg2: NOTRUN -> [INCOMPLETE][85] ([i915#12455] / [i915#13820]) +1 other test incomplete
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-6/igt@i915_pm_freq_api@freq-suspend@gt0.html
* igt@i915_pm_rps@basic-api:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#11681] / [i915#6621])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@i915_pm_rps@basic-api.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-dg2-9: NOTRUN -> [SKIP][87] ([i915#6188])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-tglu: NOTRUN -> [INCOMPLETE][88] ([i915#4817] / [i915#7443])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- shard-dg2-9: NOTRUN -> [SKIP][89] ([i915#4212]) +1 other test skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#4212])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-b-hdmi-a-2-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][91] ([i915#8709]) +1 other test skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-5/igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-b-hdmi-a-2-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-b-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#8709]) +7 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-2/igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-b-hdmi-a-3-4-mc-ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-d-edp-1-4-mc-ccs:
- shard-mtlp: NOTRUN -> [SKIP][93] ([i915#8709]) +7 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-d-edp-1-4-mc-ccs.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-tglu: NOTRUN -> [SKIP][94] ([i915#1769] / [i915#3555])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][95] -> [FAIL][96] ([i915#11808]) +1 other test fail
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-tglu-7/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-7/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-tglu-1: NOTRUN -> [SKIP][97] ([i915#5286]) +4 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-tglu: NOTRUN -> [SKIP][98] ([i915#5286])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-glk: NOTRUN -> [SKIP][99] +4 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-glk1/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-270:
- shard-dg2-9: NOTRUN -> [SKIP][100] ([i915#4538] / [i915#5190]) +4 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#5190]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][102] ([i915#4538] / [i915#5190]) +5 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: NOTRUN -> [SKIP][103] +9 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#6187])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-a-hdmi-a-2:
- shard-dg2-9: NOTRUN -> [SKIP][105] ([i915#10307] / [i915#6095]) +29 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-a-hdmi-a-2.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc:
- shard-mtlp: NOTRUN -> [SKIP][106] ([i915#6095]) +24 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
- shard-tglu: NOTRUN -> [SKIP][107] ([i915#12313])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-a-dp-3:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#10307] / [i915#6095]) +128 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-11/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-a-dp-3.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#12805])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][110] ([i915#6095]) +24 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2:
- shard-dg2-9: NOTRUN -> [SKIP][111] ([i915#6095]) +4 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-c-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#6095]) +7 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-2/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-c-hdmi-a-3.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][113] ([i915#12313])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
- shard-dg2-9: NOTRUN -> [SKIP][114] ([i915#12313])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][115] ([i915#6095]) +67 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][116] ([i915#6095]) +79 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg1-17/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#10307] / [i915#10434] / [i915#6095])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-4/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][118] ([i915#6095]) +44 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][119] ([i915#14098] / [i915#6095]) +50 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-5/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_cdclk@mode-transition:
- shard-tglu-1: NOTRUN -> [SKIP][120] ([i915#3742])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-tglu: NOTRUN -> [SKIP][121] ([i915#3742]) +1 other test skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#13783]) +3 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-4/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_frames@dp-crc-multiple:
- shard-dg2-9: NOTRUN -> [SKIP][123] ([i915#11151] / [i915#7828]) +3 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_chamelium_frames@dp-crc-multiple.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#11151] / [i915#7828]) +4 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_frames@dp-frame-dump:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#11151] / [i915#7828]) +3 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_chamelium_frames@dp-frame-dump.html
* igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#11151] / [i915#7828])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-4/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-tglu: NOTRUN -> [SKIP][127] ([i915#11151] / [i915#7828])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@dp-hpd-storm-disable:
- shard-tglu-1: NOTRUN -> [SKIP][128] ([i915#11151] / [i915#7828]) +5 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html
* igt@kms_content_protection@content-type-change:
- shard-tglu-1: NOTRUN -> [SKIP][129] ([i915#6944] / [i915#9424])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2-9: NOTRUN -> [SKIP][130] ([i915#3299])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-tglu-1: NOTRUN -> [SKIP][131] ([i915#3116] / [i915#3299]) +1 other test skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#3299])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy@pipe-a-dp-3:
- shard-dg2: NOTRUN -> [FAIL][133] ([i915#7173])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-11/igt@kms_content_protection@legacy@pipe-a-dp-3.html
* igt@kms_content_protection@lic-type-1:
- shard-tglu: NOTRUN -> [SKIP][134] ([i915#6944] / [i915#9424])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@uevent:
- shard-dg2-9: NOTRUN -> [SKIP][135] ([i915#7118] / [i915#9424])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-128x42:
- shard-mtlp: NOTRUN -> [SKIP][136] ([i915#8814]) +2 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_cursor_crc@cursor-offscreen-128x42.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-dg2-9: NOTRUN -> [SKIP][137] ([i915#3555]) +1 other test skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2: NOTRUN -> [SKIP][138] ([i915#13049]) +1 other test skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-tglu-1: NOTRUN -> [SKIP][139] ([i915#13049])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [FAIL][140] ([i915#13566]) +1 other test fail
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][141] ([i915#13566]) +1 other test fail
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-2/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#3555]) +4 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-tglu-1: NOTRUN -> [SKIP][143] ([i915#3555]) +1 other test skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_crc@cursor-suspend:
- shard-dg2: [PASS][144] -> [INCOMPLETE][145] ([i915#12358] / [i915#14152] / [i915#7882])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-2/igt@kms_cursor_crc@cursor-suspend.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-11/igt@kms_cursor_crc@cursor-suspend.html
* igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-3:
- shard-dg2: NOTRUN -> [INCOMPLETE][146] ([i915#14152] / [i915#7882])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-11/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-3.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglu: NOTRUN -> [SKIP][147] ([i915#4103]) +2 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#9809])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-dg2-9: NOTRUN -> [SKIP][149] ([i915#13046] / [i915#5354]) +2 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-rkl: [PASS][150] -> [FAIL][151] ([i915#2346])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-4/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-tglu-1: NOTRUN -> [SKIP][152] ([i915#9067])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#4103] / [i915#4213])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-tglu-1: NOTRUN -> [SKIP][154] ([i915#4103])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
- shard-dg2-9: NOTRUN -> [SKIP][155] ([i915#4103] / [i915#4213])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-tglu-1: NOTRUN -> [SKIP][156] ([i915#9723])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-tglu-1: NOTRUN -> [SKIP][157] ([i915#1769] / [i915#3555] / [i915#3804])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][158] ([i915#3804])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#3804])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#13749])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-tglu: NOTRUN -> [SKIP][161] ([i915#13748])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-dg2: [PASS][162] -> [SKIP][163] ([i915#13707])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-10/igt@kms_dp_linktrain_fallback@dp-fallback.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_dp_linktrain_fallback@dp-fallback.html
- shard-mtlp: NOTRUN -> [SKIP][164] ([i915#13707])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_dsc@dsc-basic:
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#3555] / [i915#3840] / [i915#9159])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-tglu: NOTRUN -> [SKIP][166] ([i915#3840])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2-9: NOTRUN -> [SKIP][167] ([i915#3840])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2: NOTRUN -> [SKIP][168] ([i915#3555] / [i915#3840])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_fbcon_fbt@psr:
- shard-tglu: NOTRUN -> [SKIP][169] ([i915#3469])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_fbcon_fbt@psr.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-dg2-9: NOTRUN -> [SKIP][170] ([i915#3469])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2-9: NOTRUN -> [SKIP][171] ([i915#4854])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-2x:
- shard-mtlp: NOTRUN -> [SKIP][172] ([i915#1839])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@display-4x:
- shard-tglu-1: NOTRUN -> [SKIP][173] ([i915#1839]) +1 other test skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_feature_discovery@display-4x.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-mtlp: NOTRUN -> [SKIP][174] ([i915#9934])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#3637] / [i915#9934]) +3 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-flip-vs-wf_vblank:
- shard-dg2-9: NOTRUN -> [SKIP][176] ([i915#9934]) +2 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_flip@2x-flip-vs-wf_vblank.html
* igt@kms_flip@2x-plain-flip:
- shard-tglu-1: NOTRUN -> [SKIP][177] ([i915#3637] / [i915#9934]) +2 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#9934])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-dg2-9: NOTRUN -> [FAIL][179] ([i915#13734]) +1 other test fail
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_flip@plain-flip-fb-recreate@a-vga1:
- shard-snb: [PASS][180] -> [FAIL][181] ([i915#13734]) +3 other tests fail
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-snb5/igt@kms_flip@plain-flip-fb-recreate@a-vga1.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-snb6/igt@kms_flip@plain-flip-fb-recreate@a-vga1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][182] ([i915#2587] / [i915#2672]) +3 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][183] ([i915#3555] / [i915#8810] / [i915#8813]) +1 other test skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][184] ([i915#2587] / [i915#2672]) +1 other test skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][185] ([i915#2587] / [i915#2672] / [i915#3555])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
- shard-dg2-9: NOTRUN -> [SKIP][186] ([i915#2672]) +2 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][187] ([i915#2672] / [i915#3555]) +2 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-tglu: NOTRUN -> [SKIP][188] ([i915#2672] / [i915#3555]) +1 other test skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][189] ([i915#2672] / [i915#3555] / [i915#8813])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][190] ([i915#2672] / [i915#8813])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-dg2-9: NOTRUN -> [SKIP][191] ([i915#2672] / [i915#3555] / [i915#5190]) +2 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][192] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][193] ([i915#2672]) +1 other test skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt:
- shard-rkl: [PASS][194] -> [DMESG-WARN][195] ([i915#12917] / [i915#12964])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#8708]) +6 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-dg2: NOTRUN -> [FAIL][197] ([i915#6880])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-pwrite:
- shard-mtlp: NOTRUN -> [SKIP][198] ([i915#1825]) +16 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][199] ([i915#1825]) +1 other test skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][200] ([i915#8708]) +3 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-tglu-1: NOTRUN -> [SKIP][201] ([i915#5439])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-dg2-9: NOTRUN -> [SKIP][202] ([i915#8708]) +8 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#5354]) +18 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#10055])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-dg2-9: NOTRUN -> [SKIP][205] ([i915#3458]) +5 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- shard-tglu: NOTRUN -> [SKIP][206] +27 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-snb: NOTRUN -> [SKIP][207] +21 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-snb4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff:
- shard-dg2-9: NOTRUN -> [SKIP][208] ([i915#5354]) +17 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-dg2: NOTRUN -> [SKIP][209] ([i915#3458]) +9 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-tglu-1: NOTRUN -> [SKIP][210] +60 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-tglu-1: NOTRUN -> [SKIP][211] ([i915#3555] / [i915#8228])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@static-toggle:
- shard-dg2: [PASS][212] -> [SKIP][213] ([i915#3555] / [i915#8228])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-11/igt@kms_hdr@static-toggle.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-1/igt@kms_hdr@static-toggle.html
* igt@kms_hdr@static-toggle-dpms:
- shard-dg2-9: NOTRUN -> [SKIP][214] ([i915#3555] / [i915#8228]) +1 other test skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-dg2: NOTRUN -> [SKIP][215] ([i915#12388])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_joiner@basic-force-big-joiner.html
- shard-rkl: NOTRUN -> [SKIP][216] ([i915#12388])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-4/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-mtlp: NOTRUN -> [SKIP][217] ([i915#13688])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][218] ([i915#12394])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
- shard-dg2-9: NOTRUN -> [SKIP][219] ([i915#10656])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-mtlp: NOTRUN -> [SKIP][220] ([i915#13522])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-dg2-9: NOTRUN -> [SKIP][221] ([i915#4816])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane@plane-panning-bottom-right-suspend:
- shard-glk: NOTRUN -> [INCOMPLETE][222] ([i915#13026]) +1 other test incomplete
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-glk1/igt@kms_plane@plane-panning-bottom-right-suspend.html
* igt@kms_plane_multiple@2x-tiling-none:
- shard-dg2: NOTRUN -> [SKIP][223] ([i915#13958]) +1 other test skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_plane_multiple@2x-tiling-none.html
- shard-rkl: NOTRUN -> [SKIP][224] ([i915#13958])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-4/igt@kms_plane_multiple@2x-tiling-none.html
- shard-mtlp: NOTRUN -> [SKIP][225] ([i915#13958])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_plane_multiple@2x-tiling-none.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-dg2-9: NOTRUN -> [SKIP][226] ([i915#13958])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_plane_multiple@2x-tiling-x.html
- shard-tglu-1: NOTRUN -> [SKIP][227] ([i915#13958])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-tglu: NOTRUN -> [SKIP][228] ([i915#13958])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-tglu-1: NOTRUN -> [SKIP][229] ([i915#6953])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c:
- shard-rkl: NOTRUN -> [SKIP][230] ([i915#12247]) +2 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-8/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-d:
- shard-mtlp: NOTRUN -> [SKIP][231] ([i915#12247]) +10 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-d.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][232] ([i915#12247] / [i915#6953] / [i915#9423])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b:
- shard-dg2: NOTRUN -> [SKIP][233] ([i915#12247]) +3 other tests skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-tglu-1: NOTRUN -> [SKIP][234] ([i915#12247] / [i915#6953])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c:
- shard-tglu-1: NOTRUN -> [SKIP][235] ([i915#12247]) +13 other tests skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
- shard-mtlp: NOTRUN -> [SKIP][236] ([i915#12247] / [i915#6953])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html
* igt@kms_pm_backlight@bad-brightness:
- shard-tglu-1: NOTRUN -> [SKIP][237] ([i915#9812])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@fade:
- shard-tglu: NOTRUN -> [SKIP][238] ([i915#9812])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@kms_pm_backlight@fade.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-tglu: NOTRUN -> [SKIP][239] ([i915#9685])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-tglu-1: NOTRUN -> [SKIP][240] ([i915#8430])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@i2c:
- shard-dg1: [PASS][241] -> [DMESG-WARN][242] ([i915#4423])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg1-18/igt@kms_pm_rpm@i2c.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg1-18/igt@kms_pm_rpm@i2c.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2-9: NOTRUN -> [SKIP][243] ([i915#9519])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [PASS][244] -> [SKIP][245] ([i915#9519]) +2 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-tglu-1: NOTRUN -> [SKIP][246] ([i915#9519]) +2 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [PASS][247] -> [SKIP][248] ([i915#9519])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@pm-caching:
- shard-mtlp: NOTRUN -> [SKIP][249] ([i915#4077]) +7 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_pm_rpm@pm-caching.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-tglu-1: NOTRUN -> [SKIP][250] ([i915#6524])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_prime@d3hot:
- shard-dg2: NOTRUN -> [SKIP][251] ([i915#6524] / [i915#6805])
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
- shard-tglu-1: NOTRUN -> [SKIP][252] ([i915#11520]) +5 other tests skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][253] ([i915#11520]) +2 other tests skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html
- shard-snb: NOTRUN -> [SKIP][254] ([i915#11520]) +1 other test skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-snb4/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][255] ([i915#9808])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
- shard-tglu: NOTRUN -> [SKIP][256] ([i915#11520]) +2 other tests skip
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf:
- shard-mtlp: NOTRUN -> [SKIP][257] ([i915#12316]) +4 other tests skip
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
- shard-dg2-9: NOTRUN -> [SKIP][258] ([i915#11520]) +3 other tests skip
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-tglu: NOTRUN -> [SKIP][259] ([i915#9683])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg2: NOTRUN -> [SKIP][260] ([i915#9683])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-mtlp: NOTRUN -> [SKIP][261] ([i915#4348])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-primary-blt:
- shard-mtlp: NOTRUN -> [SKIP][262] ([i915#9688]) +7 other tests skip
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_psr@fbc-pr-primary-blt.html
* igt@kms_psr@fbc-psr2-cursor-plane-move:
- shard-tglu: NOTRUN -> [SKIP][263] ([i915#9732]) +6 other tests skip
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-5/igt@kms_psr@fbc-psr2-cursor-plane-move.html
* igt@kms_psr@pr-primary-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][264] ([i915#9732]) +14 other tests skip
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_psr@pr-primary-mmap-gtt.html
* igt@kms_psr@psr-cursor-render:
- shard-dg2: NOTRUN -> [SKIP][265] ([i915#1072] / [i915#9732]) +9 other tests skip
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_psr@psr-cursor-render.html
* igt@kms_psr@psr2-no-drrs:
- shard-dg2-9: NOTRUN -> [SKIP][266] ([i915#1072] / [i915#9732]) +9 other tests skip
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_psr@psr2-no-drrs.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg2-9: NOTRUN -> [SKIP][267] ([i915#9685])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglu-1: NOTRUN -> [SKIP][268] ([i915#9685])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@bad-tiling:
- shard-mtlp: NOTRUN -> [SKIP][269] ([i915#12755])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-tglu-1: NOTRUN -> [SKIP][270] ([i915#5289])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-dg2-9: NOTRUN -> [SKIP][271] ([i915#5190])
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-tglu: NOTRUN -> [SKIP][272] ([i915#5289]) +1 other test skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_setmode@basic:
- shard-snb: [PASS][273] -> [FAIL][274] ([i915#5465]) +2 other tests fail
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-snb7/igt@kms_setmode@basic.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-snb2/igt@kms_setmode@basic.html
- shard-dg1: [PASS][275] -> [FAIL][276] ([i915#5465]) +2 other tests fail
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg1-14/igt@kms_setmode@basic.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg1-14/igt@kms_setmode@basic.html
* igt@kms_setmode@basic@pipe-b-hdmi-a-3:
- shard-dg2: [PASS][277] -> [FAIL][278] ([i915#5465]) +2 other tests fail
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-8/igt@kms_setmode@basic@pipe-b-hdmi-a-3.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-2/igt@kms_setmode@basic@pipe-b-hdmi-a-3.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-mtlp: NOTRUN -> [SKIP][279] ([i915#3555] / [i915#8809])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-mtlp: [PASS][280] -> [FAIL][281] ([i915#9196]) +1 other test fail
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-3/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_vrr@flip-suspend:
- shard-tglu: NOTRUN -> [SKIP][282] ([i915#3555]) +1 other test skip
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-6/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@negative-basic:
- shard-dg2: [PASS][283] -> [SKIP][284] ([i915#3555] / [i915#9906])
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-11/igt@kms_vrr@negative-basic.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-1/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-tglu-1: NOTRUN -> [SKIP][285] ([i915#9906])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-check-output:
- shard-mtlp: NOTRUN -> [SKIP][286] ([i915#2437])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg2: NOTRUN -> [SKIP][287] ([i915#2437])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@blocking@0-rcs0:
- shard-rkl: NOTRUN -> [DMESG-WARN][288] ([i915#12964]) +8 other tests dmesg-warn
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-4/igt@perf@blocking@0-rcs0.html
* igt@perf@global-sseu-config-invalid:
- shard-dg2-9: NOTRUN -> [SKIP][289] ([i915#7387])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@perf@global-sseu-config-invalid.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: NOTRUN -> [FAIL][290] ([i915#9100]) +1 other test fail
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@busy-idle-no-semaphores:
- shard-mtlp: [PASS][291] -> [FAIL][292] ([i915#14354]) +1 other test fail
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-mtlp-8/igt@perf_pmu@busy-idle-no-semaphores.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-3/igt@perf_pmu@busy-idle-no-semaphores.html
* igt@perf_pmu@event-wait@rcs0:
- shard-dg2: NOTRUN -> [SKIP][293] +5 other tests skip
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@perf_pmu@event-wait@rcs0.html
* igt@perf_pmu@module-unload:
- shard-tglu-1: NOTRUN -> [FAIL][294] ([i915#14433])
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@perf_pmu@module-unload.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg2-9: NOTRUN -> [SKIP][295] ([i915#8516])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@perf_pmu@rc6-all-gts.html
* igt@sriov_basic@bind-unbind-vf:
- shard-dg2-9: NOTRUN -> [SKIP][296] ([i915#9917])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-9/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@bind-unbind-vf@vf-1:
- shard-tglu-1: NOTRUN -> [FAIL][297] ([i915#12910]) +9 other tests fail
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-1/igt@sriov_basic@bind-unbind-vf@vf-1.html
* igt@tools_test@sysfs_l3_parity:
- shard-mtlp: NOTRUN -> [SKIP][298] ([i915#4818])
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-8/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-rkl: [TIMEOUT][299] ([i915#12964]) -> [PASS][300]
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-4/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-8/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-rkl: [TIMEOUT][301] ([i915#12917] / [i915#12964]) -> [PASS][302] +2 other tests pass
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-4/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-8/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@i915_hangman@detector:
- shard-rkl: [DMESG-WARN][303] ([i915#12964]) -> [PASS][304] +12 other tests pass
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-4/igt@i915_hangman@detector.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-8/igt@i915_hangman@detector.html
* igt@kms_color@deep-color:
- shard-dg2: [SKIP][305] ([i915#3555]) -> [PASS][306]
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-5/igt@kms_color@deep-color.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-11/igt@kms_color@deep-color.html
* igt@kms_cursor_crc@cursor-sliding-256x85:
- shard-rkl: [FAIL][307] ([i915#13566]) -> [PASS][308] +1 other test pass
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-256x85.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-256x85.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-rkl: [FAIL][309] ([i915#2346]) -> [PASS][310]
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-5/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-dg2: [INCOMPLETE][311] ([i915#9878]) -> [PASS][312]
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-7/igt@kms_fbcon_fbt@fbc-suspend.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-10/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-rkl: [FAIL][313] ([i915#11832] / [i915#13734]) -> [PASS][314]
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-2/igt@kms_flip@plain-flip-fb-recreate.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-8/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-mtlp: [FAIL][315] ([i915#13734]) -> [PASS][316] +2 other tests pass
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-mtlp-2/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-mtlp-4/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_flip@wf_vblank-ts-check:
- shard-rkl: [FAIL][317] ([i915#13734]) -> [PASS][318]
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-5/igt@kms_flip@wf_vblank-ts-check.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-7/igt@kms_flip@wf_vblank-ts-check.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: [FAIL][319] ([i915#9295]) -> [PASS][320]
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-7/igt@kms_pm_dc@dc6-dpms.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-2/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][321] ([i915#9519]) -> [PASS][322] +3 other tests pass
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-3/igt@kms_pm_rpm@dpms-lpsp.html
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-2/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [SKIP][323] ([i915#9519]) -> [PASS][324]
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-1/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_properties@crtc-properties-atomic:
- shard-dg1: [DMESG-WARN][325] ([i915#4423]) -> [PASS][326] +4 other tests pass
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg1-18/igt@kms_properties@crtc-properties-atomic.html
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg1-14/igt@kms_properties@crtc-properties-atomic.html
* igt@kms_setmode@basic:
- shard-rkl: [FAIL][327] ([i915#5465]) -> [PASS][328]
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-4/igt@kms_setmode@basic.html
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-8/igt@kms_setmode@basic.html
* igt@kms_vblank@ts-continuation-suspend:
- shard-dg2: [ABORT][329] ([i915#8213]) -> [PASS][330]
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-10/igt@kms_vblank@ts-continuation-suspend.html
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-8/igt@kms_vblank@ts-continuation-suspend.html
- shard-rkl: [INCOMPLETE][331] ([i915#12276]) -> [PASS][332]
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-3/igt@kms_vblank@ts-continuation-suspend.html
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-4/igt@kms_vblank@ts-continuation-suspend.html
#### Warnings ####
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [ABORT][333] ([i915#13427]) -> [INCOMPLETE][334] ([i915#13427])
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-11/igt@gem_create@create-ext-cpu-access-big.html
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-1/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_pxp@hw-rejects-pxp-buffer:
- shard-rkl: [TIMEOUT][335] ([i915#12917] / [i915#12964]) -> [SKIP][336] ([i915#13717])
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-2/igt@gem_pxp@hw-rejects-pxp-buffer.html
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-8/igt@gem_pxp@hw-rejects-pxp-buffer.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: [SKIP][337] ([i915#6095]) -> [SKIP][338] ([i915#14098] / [i915#6095])
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-2.html
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-3/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_content_protection@legacy:
- shard-dg2: [SKIP][339] ([i915#7118] / [i915#9424]) -> [FAIL][340] ([i915#7173])
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-5/igt@kms_content_protection@legacy.html
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-11/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2: [FAIL][341] ([i915#7173]) -> [SKIP][342] ([i915#9424])
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-11/igt@kms_content_protection@lic-type-0.html
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-1/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][343] ([i915#7118] / [i915#9424]) -> [SKIP][344] ([i915#7118] / [i915#7162] / [i915#9424])
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-2/igt@kms_content_protection@type1.html
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-11/igt@kms_content_protection@type1.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
- shard-dg2: [SKIP][345] ([i915#3458]) -> [SKIP][346] ([i915#10433] / [i915#3458]) +3 other tests skip
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
- shard-dg1: [SKIP][347] ([i915#4423]) -> [SKIP][348]
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [SKIP][349] ([i915#3828]) -> [SKIP][350] ([i915#9340])
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-rkl-8/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_setmode@basic:
- shard-tglu: [FAIL][351] ([i915#14353] / [i915#5465]) -> [FAIL][352] ([i915#5465])
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-tglu-6/igt@kms_setmode@basic.html
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-2/igt@kms_setmode@basic.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-1:
- shard-tglu: [FAIL][353] -> [FAIL][354] ([i915#5465])
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16747/shard-tglu-6/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/shard-tglu-2/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
[i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11527
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808
[i915#11832]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11832
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
[i915#12358]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12358
[i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
[i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
[i915#12455]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12455
[i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
[i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
[i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
[i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
[i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
[i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
[i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
[i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
[i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
[i915#13427]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13427
[i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
[i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
[i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
[i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
[i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
[i915#13734]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13734
[i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
[i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
[i915#13783]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13783
[i915#13820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13820
[i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
[i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
[i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
[i915#14152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14152
[i915#14353]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14353
[i915#14354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14354
[i915#14433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14433
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4348
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4818
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#5107]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5107
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5465
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
[i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7162
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
[i915#7443]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7443
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7882
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
[i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
[i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
[i915#9159]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9159
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9878]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9878
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_16747 -> Patchwork_147799v7
CI-20190529: 20190529
CI_DRM_16747: da56936fad6f5e1d5f0cef8b50277bfb071eefe7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8422: 9b9c9136b17a2ed0680fb9589d51446c03698b37 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_147799v7: da56936fad6f5e1d5f0cef8b50277bfb071eefe7 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v7/index.html
[-- Attachment #2: Type: text/html, Size: 122350 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2025-06-24 12:40 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-06-24 7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-06-24 7:49 ` [PATCH v7 01/18] drm/i915/vrr: Refactor vmin/vmax stuff Mitul Golani
2025-06-24 7:49 ` [PATCH v7 02/18] drm/i915/display: Add source param for dc balance Mitul Golani
2025-06-24 7:49 ` [PATCH v7 03/18] drm/i915/display: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-06-24 7:49 ` [PATCH v7 04/18] drm/i915/display: Add VRR DC balance registers Mitul Golani
2025-06-24 8:13 ` Jani Nikula
2025-06-24 7:49 ` [PATCH v7 05/18] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-06-24 7:49 ` [PATCH v7 06/18] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-06-24 8:14 ` Jani Nikula
2025-06-24 7:49 ` [PATCH v7 07/18] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-06-24 7:49 ` [PATCH v7 08/18] drm/i915/vrr: Add compute config " Mitul Golani
2025-06-24 7:49 ` [PATCH v7 09/18] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-06-24 7:49 ` [PATCH v7 10/18] drm/i915: Extract vrr_vblank_start() Mitul Golani
2025-06-24 7:49 ` [PATCH v7 11/18] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-06-24 7:49 ` [PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-06-24 8:25 ` Jani Nikula
2025-06-24 7:49 ` [PATCH v7 13/18] drm/i915/vrr: Restructure VRR enablement bit Mitul Golani
2025-06-24 7:49 ` [PATCH v7 14/18] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-06-24 7:49 ` [PATCH v7 15/18] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-06-24 7:49 ` [PATCH v7 16/18] drm/i915/display: Add function to configure PIPEDMC_EVT_CTL Mitul Golani
2025-06-24 7:49 ` [PATCH v7 17/18] drm/i915/vrr: Enable Adaptive sync counter bit Mitul Golani
2025-06-24 7:49 ` [PATCH v7 18/18] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-06-24 8:54 ` ✓ i915.CI.BAT: success for Enable/Disable DC balance along with VRR DSB (rev7) Patchwork
2025-06-24 12:40 ` ✗ i915.CI.Full: failure " Patchwork
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