[PATCH 00/16] Basic enabling patches for Xe3p_LPG and NVL-P

[PATCH 00/16] Basic enabling patches for Xe3p_LPG and NVL-P

[Gustavo Sousa]

NVL-P is a new Intel platform that comes with the following IPs:

- Xe3p_LPG graphics;
- Xe3p_LPM media;
- Xe3p_LPD display.

Enabling patches for Xe3p_LPM and Xe3p_LPD are already integrated in our
driver.  In this series we add patches enabling Xe3p_LPG and then follow
up with patches enabling NVL-P as a platform in our driver.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Aradhya Bhatia (1):
      drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB

Dnyaneshwar Bhadane (1):
      drm/xe/nvlp: Attach MOCS table for nvlp

Gustavo Sousa (3):
      drm/xe/pat: Differentiate between primary and media for PTA
      drm/xe/xe3p_lpg: Update LRC sizes
      drm/xe/xe3p_lpg: Enable multi-queue feature

John Harrison (1):
      drm/xe/nvlp: Define GuC firmware for NVL-P

Matt Roper (7):
      drm/xe/xe3p_lpg: Add new PAT table
      drm/xe/xe3p_lpg: Add MCR steering
      drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state
      drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP
      drm/xe/xe3p_lpg: Drop unnecessary tuning settings
      drm/xe/xe3p_lpg: Extend 'group ID' mask size
      drm/i915/nvlp: Hook up display support

Shekhar Chauhan (3):
      drm/xe/xe3p_lpg: Add support for graphics IP 35.10
      drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10
      drm/xe/nvlp: Add NVL-P platform definition

 .../gpu/drm/i915/display/intel_display_device.c    |  1 +
 .../gpu/drm/xe/instructions/xe_gfxpipe_commands.h  | 10 +++
 drivers/gpu/drm/xe/regs/xe_gt_regs.h               | 23 +++++-
 drivers/gpu/drm/xe/xe_bo.c                         |  4 +-
 drivers/gpu/drm/xe/xe_device_types.h               |  8 ++-
 drivers/gpu/drm/xe/xe_gt_mcr.c                     | 18 ++++-
 drivers/gpu/drm/xe/xe_lrc.c                        | 18 ++++-
 drivers/gpu/drm/xe/xe_mocs.c                       |  1 +
 drivers/gpu/drm/xe/xe_pat.c                        | 82 +++++++++++++++++++---
 drivers/gpu/drm/xe/xe_pci.c                        | 21 ++++++
 drivers/gpu/drm/xe/xe_platform_types.h             |  1 +
 drivers/gpu/drm/xe/xe_reg_whitelist.c              |  8 +++
 drivers/gpu/drm/xe/xe_tuning.c                     | 22 +++++-
 drivers/gpu/drm/xe/xe_uc_fw.c                      |  2 +
 drivers/gpu/drm/xe/xe_wa.c                         | 48 +++++++++++++
 include/drm/intel/pciids.h                         | 12 ++++
 16 files changed, 257 insertions(+), 22 deletions(-)
---
base-commit: c716d3fcf63ff63e6ecab8769c949e1cdbfb7a79
change-id: 20260130-nvl-p-upstreaming-e69efaf1db91

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>

[PATCH 01/16] drm/xe/xe3p_lpg: Add support for graphics IP 35.10

[Gustavo Sousa]

From: Shekhar Chauhan <shekhar.chauhan@intel.com>

Add graphics IP versions 35.10. Since there will be features enabled
that are not present in graphics_xe2, already create a new
graphics_xe3p, although currently it only enables the same features as
graphics_xe2.

Here is a list of fields, associated Bspec references and eventual
comments:

 .va_bits (Bspec 74198)
 .vm_max_level (Bspec 59507)
    The spec says "The PPGTT is always a 5-level structure even when the
    virtual address space is less than 57 bits."
 .vram_flags
   - ~XE_VRAM_FLAGS_NEED64K
     That limitation that does not exist for Xe3p_LPG.
 .hw_engine_mask (Bspec 60149)
 .tile_gsm_size (Bspec 52961)
    This is queried directly from the hardware.
 .has_asid (Bspec 71132)
 .has_atomic_enable_pte_bit (Bspec 59510, 74675)
 .has_flat_ccs (Bspec 65255)
 .has_indirect_ring_state (Bspec 67296)
 .has_range_tlb_inval (Bspec 71126)
 .has_usm (Bspec 59651)

Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index b5e8935fff1d..edca562462fa 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -106,6 +106,10 @@ static const struct xe_graphics_desc graphics_xe2 = {
 	XE2_GFX_FEATURES,
 };
 
+static const struct xe_graphics_desc graphics_xe3p = {
+	XE2_GFX_FEATURES,
+};
+
 static const struct xe_graphics_desc graphics_xe3p_xpc = {
 	XE2_GFX_FEATURES,
 	.has_indirect_ring_state = 1,
@@ -148,6 +152,7 @@ static const struct xe_ip graphics_ips[] = {
 	{ 3003, "Xe3_LPG", &graphics_xe2 },
 	{ 3004, "Xe3_LPG", &graphics_xe2 },
 	{ 3005, "Xe3_LPG", &graphics_xe2 },
+	{ 3510, "Xe3p_LPG", &graphics_xe3p },
 	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
 };
 

-- 
2.52.0

[PATCH 02/16] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10

[Gustavo Sousa]

From: Shekhar Chauhan <shekhar.chauhan@intel.com>

Add the initial set of workarounds for Xe3p_LPG graphics version 35.10.

Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Co-developed-by: Nitin Gote <nitin.r.gote@intel.com>
Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
Co-developed-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
Co-developed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Signed-off-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Co-developed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h  | 19 ++++++++++++++
 drivers/gpu/drm/xe/xe_reg_whitelist.c |  8 ++++++
 drivers/gpu/drm/xe/xe_wa.c            | 48 +++++++++++++++++++++++++++++++++++
 3 files changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 24fc64fc832e..b5a7cc45f13d 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -100,6 +100,9 @@
 #define VE1_AUX_INV				XE_REG(0x42b8)
 #define   AUX_INV				REG_BIT(0)
 
+#define GAMSTLB_CTRL2				XE_REG_MCR(0x4788)
+#define   STLB_SINGLE_BANK_MODE			REG_BIT(11)
+
 #define XE2_LMEM_CFG				XE_REG(0x48b0)
 
 #define XE2_GAMWALK_CTRL			0x47e4
@@ -107,12 +110,18 @@
 #define XE2_GAMWALK_CTRL_3D			XE_REG_MCR(XE2_GAMWALK_CTRL)
 #define   EN_CMP_1WCOH_GW			REG_BIT(14)
 
+#define MMIOATSREQLIMIT_GAM_WALK_3D             XE_REG_MCR(0x47f8)
+#define   DIS_ATS_WRONLY_PG                     REG_BIT(18)
+
 #define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)
 #define XEHP_FLAT_CCS_PTR			REG_GENMASK(31, 8)
 
 #define WM_CHICKEN3				XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
 #define   HIZ_PLANE_COMPRESSION_DIS		REG_BIT(10)
 
+#define TBIMR_MODE				XE_REG_MCR(0x6200, XE_REG_OPTION_MASKED)
+#define   RXBAR_NO_UAV_DEC_SYNC			REG_BIT(12)
+
 #define CHICKEN_RASTER_1			XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
 #define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
 #define   DIS_CLIP_NEGATIVE_BOUNDING_BOX	REG_BIT(6)
@@ -210,6 +219,9 @@
 
 #define GSCPSMI_BASE				XE_REG(0x880c)
 
+#define CCCHKNREG2				XE_REG_MCR(0x881c)
+#define  LOCALITYDIS				REG_BIT(7)
+
 #define CCCHKNREG1				XE_REG_MCR(0x8828)
 #define   L3CMPCTRL				REG_BIT(23)
 #define   ENCOMPPERFFIX				REG_BIT(18)
@@ -420,6 +432,8 @@
 #define   LSN_DIM_Z_WGT(value)			REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
 
 #define L3SQCREG2				XE_REG_MCR(0xb104)
+#define   L3_SQ_DISABLE_COAMA_2WAY_COH		REG_BIT(30)
+#define   L3_SQ_DISABLE_COAMA			REG_BIT(22)
 #define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)
 
 #define L3SQCREG3				XE_REG_MCR(0xb108)
@@ -550,11 +564,16 @@
 #define   UGM_FRAGMENT_THRESHOLD_TO_3		REG_BIT(58 - 32)
 #define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)
 #define   XE2_ALLOC_DPA_STARVE_FIX_DIS		REG_BIT(47 - 32)
+#define   SAMPLER_LD_LSC_DISABLE                REG_BIT(45 - 32)
 #define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL	REG_BIT(44 - 32)
 #define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)
 #define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)
 #define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)
 #define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
+#define   LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE	REG_BIT(35 - 32)
+
+#define ROW_CHICKEN5				XE_REG_MCR(0xe7f0)
+#define   CPSS_AWARE_DIS			REG_BIT(3)
 
 #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
 #define   COMP_CKN_IN				REG_GENMASK(30, 29)
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 1d36c09681aa..9c513778d370 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -81,6 +81,14 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
 			 WHITELIST(VFLSKPD,
 				   RING_FORCE_TO_NONPRIV_ACCESS_RW))
 	},
+	{ XE_RTP_NAME("14024997852"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
+		       ENGINE_CLASS(RENDER)),
+	  XE_RTP_ACTIONS(WHITELIST(FF_MODE,
+				   RING_FORCE_TO_NONPRIV_ACCESS_RW),
+			 WHITELIST(VFLSKPD,
+				   RING_FORCE_TO_NONPRIV_ACCESS_RW))
+	},
 
 #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
 	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index a991ee2b8781..68a494743b34 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -306,6 +306,31 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)),
 	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
 	},
+
+	/* Xe3P_LPG */
+
+	{ XE_RTP_NAME("14025160223"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
+	  XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,
+			     DIS_ATS_WRONLY_PG))
+	},
+	{ XE_RTP_NAME("16028780921"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
+	  XE_RTP_ACTIONS(SET(CCCHKNREG2, LOCALITYDIS))
+	},
+	{ XE_RTP_NAME("14026144927"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
+	  XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |
+			     L3_SQ_DISABLE_COAMA))
+	},
+	{ XE_RTP_NAME("14025635424"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
+	  XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE))
+	},
+	{ XE_RTP_NAME("16028005424"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
+	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
+	},
 };
 
 static const struct xe_rtp_entry_sr engine_was[] = {
@@ -680,6 +705,24 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
 	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
 	},
+
+	/* Xe3p_LPG*/
+
+	{ XE_RTP_NAME("22021149932"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))
+	},
+	{ XE_RTP_NAME("14025676848"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))
+	},
+	{ XE_RTP_NAME("16028951944"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
+	},
 };
 
 static const struct xe_rtp_entry_sr lrc_was[] = {
@@ -879,6 +922,11 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 		       ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
 	},
+	{ XE_RTP_NAME("14025780377"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
+		       ENGINE_CLASS(RENDER)),
+	  XE_RTP_ACTIONS(SET(TBIMR_MODE, RXBAR_NO_UAV_DEC_SYNC))
+	},
 };
 
 static __maybe_unused const struct xe_rtp_entry oob_was[] = {

-- 
2.52.0

[PATCH 03/16] drm/xe/pat: Differentiate between primary and media for PTA

[Gustavo Sousa]

Differently from currently supported platforms, in upcoming changes we
will need to have different PAT entries for PTA based on the GT type. As
such, let's prepare the code to support that by having two separate
PTA-specific members in the pat struct, one for each type of GT.

While at it, also fix the kerneldoc for pat_ats.

Co-developed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h |  8 +++++---
 drivers/gpu/drm/xe/xe_pat.c          | 27 ++++++++++++++++++---------
 2 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 34feef79fa4e..4508ed54d1d5 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -568,10 +568,12 @@ struct xe_device {
 		const struct xe_pat_table_entry *table;
 		/** @pat.n_entries: Number of PAT entries */
 		int n_entries;
-		/** @pat.ats_entry: PAT entry for PCIe ATS responses */
+		/** @pat.pat_ats: PAT entry for PCIe ATS responses */
 		const struct xe_pat_table_entry *pat_ats;
-		/** @pat.pta_entry: PAT entry for page table accesses */
-		const struct xe_pat_table_entry *pat_pta;
+		/** @pat.pat_primary_pta: primary GT PAT entry for page table accesses */
+		const struct xe_pat_table_entry *pat_primary_pta;
+		/** @pat.pat_media_pta: media GT PAT entry for page table accesses */
+		const struct xe_pat_table_entry *pat_media_pta;
 		u32 idx[__XE_CACHE_LEVEL_COUNT];
 	} pat;
 
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 14d0dce5190a..5776ea67fe02 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -284,8 +284,10 @@ static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[
 
 	if (xe->pat.pat_ats)
 		xe_mmio_write32(&gt->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value);
-	if (xe->pat.pat_pta)
-		xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe->pat.pat_pta->value);
+	if (xe->pat.pat_primary_pta && xe_gt_is_main_type(gt))
+		xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe->pat.pat_primary_pta->value);
+	if (xe->pat.pat_media_pta && xe_gt_is_media_type(gt))
+		xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe->pat.pat_media_pta->value);
 }
 
 static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[],
@@ -301,8 +303,10 @@ static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry ta
 
 	if (xe->pat.pat_ats)
 		xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value);
-	if (xe->pat.pat_pta)
-		xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_pta->value);
+	if (xe->pat.pat_primary_pta && xe_gt_is_main_type(gt))
+		xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_primary_pta->value);
+	if (xe->pat.pat_media_pta && xe_gt_is_media_type(gt))
+		xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_media_pta->value);
 }
 
 static int xelp_dump(struct xe_gt *gt, struct drm_printer *p)
@@ -527,7 +531,8 @@ void xe_pat_init_early(struct xe_device *xe)
 		xe->pat.ops = &xe3p_xpc_pat_ops;
 		xe->pat.table = xe3p_xpc_pat_table;
 		xe->pat.pat_ats = &xe3p_xpc_pat_ats;
-		xe->pat.pat_pta = &xe3p_xpc_pat_pta;
+		xe->pat.pat_primary_pta = &xe3p_xpc_pat_pta;
+		xe->pat.pat_media_pta = &xe3p_xpc_pat_pta;
 		xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
 		xe->pat.idx[XE_CACHE_NONE] = 3;
 		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
@@ -541,8 +546,10 @@ void xe_pat_init_early(struct xe_device *xe)
 			xe->pat.table = xe2_pat_table;
 		}
 		xe->pat.pat_ats = &xe2_pat_ats;
-		if (IS_DGFX(xe))
-			xe->pat.pat_pta = &xe2_pat_pta;
+		if (IS_DGFX(xe)) {
+			xe->pat.pat_primary_pta = &xe2_pat_pta;
+			xe->pat.pat_media_pta = &xe2_pat_pta;
+		}
 
 		/* Wa_16023588340. XXX: Should use XE_WA */
 		if (GRAPHICS_VERx100(xe) == 2001)
@@ -649,6 +656,8 @@ int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p)
 int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
 {
 	struct xe_device *xe = gt_to_xe(gt);
+	const struct xe_pat_table_entry *pta_entry = xe_gt_is_main_type(gt) ?
+		xe->pat.pat_primary_pta : xe->pat.pat_media_pta;
 	char label[PAT_LABEL_LEN];
 
 	if (!xe->pat.table || !xe->pat.n_entries)
@@ -675,8 +684,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
 		}
 	}
 
-	if (xe->pat.pat_pta) {
-		u32 pat = xe->pat.pat_pta->value;
+	if (pta_entry) {
+		u32 pat = pta_entry->value;
 
 		drm_printf(p, "Page Table Access:\n");
 		xe2_pat_entry_dump(p, "PTA_MODE", pat, false);

-- 
2.52.0

[PATCH 04/16] drm/xe/xe3p_lpg: Add new PAT table

[Gustavo Sousa]

From: Matt Roper <matthew.d.roper@intel.com>

PAT programming for Xe3p_LPG is more similar to Xe2 and Xe3 than it is
to Xe3p_XPC.  Compared to Xe2/Xe3 we have:

* There's a slight update to the PAT table, where two new indices (18
  and 19) are added to expose a new "WB - Transient App" L3 caching
  mode.

* The PTA_MODE entry must be programmed differently according to the
  media type, and both differ from Xe2.

There are no changes to the underlying registers, so the Xe2 ops can be
re-used for Xe3p.

Bspec: 71582, 74160
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_pat.c | 55 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 54 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 5776ea67fe02..3ba89e80be1f 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -123,7 +123,8 @@ static const struct xe_pat_table_entry xelpg_pat_table[] = {
  *   - no_promote:  0=promotable, 1=no promote
  *   - comp_en:     0=disable, 1=enable
  *   - l3clos:      L3 class of service (0-3)
- *   - l3_policy:   0=WB, 1=XD ("WB - Transient Display"), 3=UC
+ *   - l3_policy:   0=WB, 1=XD ("WB - Transient Display"),
+ *                  2=XA ("WB - Transient App" for Xe3p), 3=UC
  *   - l4_policy:   0=WB, 1=WT, 3=UC
  *   - coh_mode:    0=no snoop, 2=1-way coherent, 3=2-way coherent
  *
@@ -252,6 +253,44 @@ static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
 	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
 };
 
+static const struct xe_pat_table_entry xe3p_primary_pat_pta = XE2_PAT(0, 0, 0, 0, 0, 3);
+static const struct xe_pat_table_entry xe3p_media_pat_pta = XE2_PAT(0, 0, 0, 0, 0, 2);
+
+static const struct xe_pat_table_entry xe3p_lpg_pat_table[] = {
+	[ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ),
+	[ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ),
+	[ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ),
+	[ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ),
+	[ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ),
+	[ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ),
+	[ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ),
+	[ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ),
+	[ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ),
+	[ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ),
+	[10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ),
+	[11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ),
+	[12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ),
+	[13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ),
+	[14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ),
+	[15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ),
+	[16] = XE2_PAT( 0, 1, 0, 0, 3, 2 ),
+	/* 17 is reserved; leave set to all 0's */
+	[18] = XE2_PAT( 1, 0, 0, 2, 3, 0 ),
+	[19] = XE2_PAT( 1, 0, 0, 2, 3, 2 ),
+	[20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ),
+	[21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ),
+	[22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ),
+	[23] = XE2_PAT( 0, 0, 1, 0, 3, 3 ),
+	[24] = XE2_PAT( 0, 0, 2, 0, 3, 0 ),
+	[25] = XE2_PAT( 0, 1, 2, 0, 3, 0 ),
+	[26] = XE2_PAT( 0, 0, 2, 0, 3, 2 ),
+	[27] = XE2_PAT( 0, 0, 2, 0, 3, 3 ),
+	[28] = XE2_PAT( 0, 0, 3, 0, 3, 0 ),
+	[29] = XE2_PAT( 0, 1, 3, 0, 3, 0 ),
+	[30] = XE2_PAT( 0, 0, 3, 0, 3, 2 ),
+	[31] = XE2_PAT( 0, 0, 3, 0, 3, 3 ),
+};
+
 u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
 {
 	WARN_ON(pat_index >= xe->pat.n_entries);
@@ -537,6 +576,20 @@ void xe_pat_init_early(struct xe_device *xe)
 		xe->pat.idx[XE_CACHE_NONE] = 3;
 		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
 		xe->pat.idx[XE_CACHE_WB] = 2;
+	} else if (GRAPHICS_VER(xe) == 35) {
+		xe->pat.ops = &xe2_pat_ops;
+		xe->pat.table = xe3p_lpg_pat_table;
+		xe->pat.pat_ats = &xe2_pat_ats;
+		if (!IS_DGFX(xe)) {
+			xe->pat.pat_primary_pta = &xe3p_primary_pat_pta;
+			xe->pat.pat_media_pta = &xe3p_media_pat_pta;
+		}
+		xe->pat.n_entries = ARRAY_SIZE(xe3p_lpg_pat_table);
+		xe->pat.idx[XE_CACHE_NONE] = 3;
+		xe->pat.idx[XE_CACHE_WT] = 15;
+		xe->pat.idx[XE_CACHE_WB] = 2;
+		xe->pat.idx[XE_CACHE_NONE_COMPRESSION] = 12;
+		xe->pat.idx[XE_CACHE_WB_COMPRESSION] = 16;
 	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
 		xe->pat.ops = &xe2_pat_ops;
 		if (GRAPHICS_VER(xe) == 30) {

-- 
2.52.0

[PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering

[Gustavo Sousa]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_LPG has nearly identical steering to Xe2 and Xe3.  The only
DSS/XeCore change from those IPs is an additional range from
0xDE00-0xDE7F that was previously reserved, so we can simply grow one of
the existing ranges in the Xe2 table to include it.  Similarly, the
"instance0" table is also almost identical, but gains one additional
PSMI range and requires a separate table.

Bspec: 75242
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_mcr.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 7c1fe9ac120d..b112e551fc79 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -201,7 +201,7 @@ static const struct xe_mmio_range xe2lpg_dss_steering_table[] = {
 	{ 0x009680, 0x0096FF },         /* DSS */
 	{ 0x00D800, 0x00D87F },         /* SLICE */
 	{ 0x00DC00, 0x00DCFF },         /* SLICE */
-	{ 0x00DE80, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
+	{ 0x00DE00, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
 	{ 0x00E980, 0x00E9FF },         /* SLICE */
 	{ 0x013000, 0x0133FF },         /* DSS (0x13000-0x131FF), SLICE (0x13200-0x133FF) */
 	{},
@@ -280,6 +280,19 @@ static const struct xe_mmio_range xe3p_xpc_instance0_steering_table[] = {
 	{},
 };
 
+static const struct xe_mmio_range xe3p_lpg_instance0_steering_table[] = {
+	{ 0x004000, 0x004AFF },         /* GAM, rsvd, GAMWKR */
+	{ 0x008700, 0x00887F },         /* NODE */
+	{ 0x00B000, 0x00B3FF },         /* NODE, L3BANK */
+	{ 0x00B500, 0x00B6FF },		/* PSMI */
+	{ 0x00C800, 0x00CFFF },         /* GAM */
+	{ 0x00D880, 0x00D8FF },         /* NODE */
+	{ 0x00DD00, 0x00DDFF },         /* MEMPIPE */
+	{ 0x00F000, 0x00FFFF },         /* GAM, GAMWKR */
+	{ 0x013400, 0x0135FF },         /* MEMPIPE */
+	{},
+};
+
 static void init_steering_l3bank(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
@@ -533,6 +546,9 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
 			gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;
 			gt->steering[L3BANK].ranges = xelpg_l3bank_steering_table;
 			gt->steering[NODE].ranges = xe3p_xpc_node_steering_table;
+		} else if (GRAPHICS_VERx100(xe) >= 3510) {
+			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
+			gt->steering[INSTANCE0].ranges = xe3p_lpg_instance0_steering_table;
 		} else if (GRAPHICS_VER(xe) >= 20) {
 			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
 			gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;

-- 
2.52.0

[PATCH 06/16] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state

[Gustavo Sousa]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_LPG adds some additional state instructions to the RCS engine's
LRC.  Add support for these to the debugfs LRC parser.

Note that the bspec's LRC description page seems to have a few mistakes
in the name/spelling of these new instructions (e.g.,
"3DSTATE_TASK_DATA_EXT" instead of "3DSTATE_TASK_SHADER_DATA_EXT" or
"3DSTATE_VIEWPORT_STATE_POINTERS_CL_SF_2" instead of
"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2").

Bspec: 65182
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h | 10 ++++++++++
 drivers/gpu/drm/xe/xe_lrc.c                           | 10 ++++++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h b/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
index 457881af8af9..4d854c85e588 100644
--- a/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
+++ b/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
@@ -55,6 +55,7 @@
 #define PIPELINE_SELECT				GFXPIPE_SINGLE_DW_CMD(0x1, 0x4)
 
 #define CMD_3DSTATE_DRAWING_RECTANGLE_FAST	GFXPIPE_3D_CMD(0x0, 0x0)
+#define CMD_3DSTATE_CUSTOM_SAMPLE_PATTERN	GFXPIPE_3D_CMD(0x0, 0x2)
 #define CMD_3DSTATE_CLEAR_PARAMS		GFXPIPE_3D_CMD(0x0, 0x4)
 #define CMD_3DSTATE_DEPTH_BUFFER		GFXPIPE_3D_CMD(0x0, 0x5)
 #define CMD_3DSTATE_STENCIL_BUFFER		GFXPIPE_3D_CMD(0x0, 0x6)
@@ -138,8 +139,16 @@
 #define CMD_3DSTATE_SBE_MESH			GFXPIPE_3D_CMD(0x0, 0x82)
 #define CMD_3DSTATE_CPSIZE_CONTROL_BUFFER	GFXPIPE_3D_CMD(0x0, 0x83)
 #define CMD_3DSTATE_COARSE_PIXEL		GFXPIPE_3D_CMD(0x0, 0x89)
+#define CMD_3DSTATE_MESH_SHADER_DATA_EXT	GFXPIPE_3D_CMD(0x0, 0x8A)
+#define CMD_3DSTATE_TASK_SHADER_DATA_EXT	GFXPIPE_3D_CMD(0x0, 0x8B)
+#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_CC_2	GFXPIPE_3D_CMD(0x0, 0x8D)
+#define CMD_3DSTATE_CC_STATE_POINTERS_2		GFXPIPE_3D_CMD(0x0, 0x8E)
+#define CMD_3DSTATE_SCISSOR_STATE_POINTERS_2	GFXPIPE_3D_CMD(0x0, 0x8F)
+#define CMD_3DSTATE_BLEND_STATE_POINTERS_2	GFXPIPE_3D_CMD(0x0, 0xA0)
+#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2	GFXPIPE_3D_CMD(0x0, 0xA1)
 
 #define CMD_3DSTATE_DRAWING_RECTANGLE		GFXPIPE_3D_CMD(0x1, 0x0)
+#define CMD_3DSTATE_URB_MEMORY			GFXPIPE_3D_CMD(0x1, 0x1)
 #define CMD_3DSTATE_CHROMA_KEY			GFXPIPE_3D_CMD(0x1, 0x4)
 #define CMD_3DSTATE_POLY_STIPPLE_OFFSET		GFXPIPE_3D_CMD(0x1, 0x6)
 #define CMD_3DSTATE_POLY_STIPPLE_PATTERN	GFXPIPE_3D_CMD(0x1, 0x7)
@@ -160,5 +169,6 @@
 #define CMD_3DSTATE_SUBSLICE_HASH_TABLE		GFXPIPE_3D_CMD(0x1, 0x1F)
 #define CMD_3DSTATE_SLICE_TABLE_STATE_POINTERS	GFXPIPE_3D_CMD(0x1, 0x20)
 #define CMD_3DSTATE_PTBR_TILE_PASS_INFO		GFXPIPE_3D_CMD(0x1, 0x22)
+#define CMD_3DSTATE_SLICE_TABLE_STATE_POINTER_2	GFXPIPE_3D_CMD(0x1, 0xA0)
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 3db7968aa5e2..e58eb8b9db78 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1966,6 +1966,7 @@ static int dump_gfxpipe_command(struct drm_printer *p,
 	MATCH(PIPELINE_SELECT);
 
 	MATCH3D(3DSTATE_DRAWING_RECTANGLE_FAST);
+	MATCH3D(3DSTATE_CUSTOM_SAMPLE_PATTERN);
 	MATCH3D(3DSTATE_CLEAR_PARAMS);
 	MATCH3D(3DSTATE_DEPTH_BUFFER);
 	MATCH3D(3DSTATE_STENCIL_BUFFER);
@@ -2049,8 +2050,16 @@ static int dump_gfxpipe_command(struct drm_printer *p,
 	MATCH3D(3DSTATE_SBE_MESH);
 	MATCH3D(3DSTATE_CPSIZE_CONTROL_BUFFER);
 	MATCH3D(3DSTATE_COARSE_PIXEL);
+	MATCH3D(3DSTATE_MESH_SHADER_DATA_EXT);
+	MATCH3D(3DSTATE_TASK_SHADER_DATA_EXT);
+	MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_CC_2);
+	MATCH3D(3DSTATE_CC_STATE_POINTERS_2);
+	MATCH3D(3DSTATE_SCISSOR_STATE_POINTERS_2);
+	MATCH3D(3DSTATE_BLEND_STATE_POINTERS_2);
+	MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2);
 
 	MATCH3D(3DSTATE_DRAWING_RECTANGLE);
+	MATCH3D(3DSTATE_URB_MEMORY);
 	MATCH3D(3DSTATE_CHROMA_KEY);
 	MATCH3D(3DSTATE_POLY_STIPPLE_OFFSET);
 	MATCH3D(3DSTATE_POLY_STIPPLE_PATTERN);
@@ -2070,6 +2079,7 @@ static int dump_gfxpipe_command(struct drm_printer *p,
 	MATCH3D(3DSTATE_SUBSLICE_HASH_TABLE);
 	MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTERS);
 	MATCH3D(3DSTATE_PTBR_TILE_PASS_INFO);
+	MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTER_2);
 
 	default:
 		drm_printf(p, "[%#010x] unknown GFXPIPE command (pipeline=%#x, opcode=%#x, subopcode=%#x), likely %d dwords\n",

-- 
2.52.0

[PATCH 07/16] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP

[Gustavo Sousa]

From: Matt Roper <matthew.d.roper@intel.com>

By default the hardware reports context switch status into the global
hardware status page.  The Xe driver doesn't use this information for
anything, and as of Xe3p, leaving this setting enabled will prevent
other hardware optimizations from being enabled.  Disable this reporting
as suggested by the tuning guide.

Bspec: 72161
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_tuning.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 5766fa7742d3..a97872b3214b 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -10,6 +10,7 @@
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
 
+#include "regs/xe_engine_regs.h"
 #include "regs/xe_gt_regs.h"
 #include "xe_gt_types.h"
 #include "xe_platform_types.h"
@@ -107,6 +108,12 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
 	},
+	{ XE_RTP_NAME("Tuning: disable HW reporting of ctx switch to GHWSP"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3500, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
+			     GHWSP_CSB_REPORT_DIS,
+			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+	},
 };
 
 static const struct xe_rtp_entry_sr lrc_tunings[] = {

-- 
2.52.0

[PATCH 08/16] drm/xe/xe3p_lpg: Drop unnecessary tuning settings

[Gustavo Sousa]

From: Matt Roper <matthew.d.roper@intel.com>

From Xe3p onward, the desired settings are now the hardware's
default values and the driver does not need to program them explicitly.

Since 35.xx seems to be the starting point for "Xe3p" version numbers;
we'll adjust the bounds of the old programming to stop at 34.99.  Even
though there's no platform with version 35.00 at the moment, this is
simplest in case one does show up in the future.

Bspec: 72161, 59928, 59930
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_tuning.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index a97872b3214b..694385ae75f1 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -32,12 +32,12 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 	/* Xe2 */
 
 	{ XE_RTP_NAME("Tuning: L3 cache"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499)),
 	  XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
 				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
 	},
 	{ XE_RTP_NAME("Tuning: L3 cache - media"),
-	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, 3499)),
 	  XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
 				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
 	},
@@ -53,7 +53,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 			 SET(XE2LPM_CCCHKNREG1, L3CMPCTRL))
 	},
 	{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499)),
 	  XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
 	},
 	{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3 - media"),

-- 
2.52.0

[PATCH 09/16] drm/xe/xe3p_lpg: Extend 'group ID' mask size

[Gustavo Sousa]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_LPG extends the 'group ID' register mask by one bit.  Since the new
upper bit (12) was unused on previous platforms, we can safely extend
the existing mask size without worrying about adding conditional version
checks to the register programming.

Bspec: 67175
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index b5a7cc45f13d..19f053a7f9be 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -58,7 +58,7 @@
 #define   MCR_SLICE(slice)			REG_FIELD_PREP(MCR_SLICE_MASK, slice)
 #define   MCR_SUBSLICE_MASK			REG_GENMASK(26, 24)
 #define   MCR_SUBSLICE(subslice)		REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
-#define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)
+#define   MTL_MCR_GROUPID			REG_GENMASK(12, 8)
 #define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)
 
 #define PS_INVOCATION_COUNT			XE_REG(0x2348)

-- 
2.52.0

[PATCH 10/16] drm/xe/xe3p_lpg: Update LRC sizes

[Gustavo Sousa]

Like with previous generations, the engine context images for of both
RCS and CCS in Xe3p_LPG contain a common layout at the end for the
context related to the "Compute Pipeline".

The size of the memory area written to such section varies; it depends
on the type of preemption has taken place during the execution and type
of command streamer instruction that was used on the pipeline. For
Xe3p_LPG, the maximum possible size, including NOOPs for cache line
alignment, is 4368 dwords, which would be the case of a mid-thread
preemption during the execution of a COMPUTE_WALKER_2 instruction.

The maximum size has increased in such a way that we need to update
xe_gt_lrc_size() to match the new sizing requirement. When we add that
to the engine-specific parts, we have:

  - RCS context image: 6672 dwords = 26688 bytes -> 7 pages
  - CCS context image: 5024 dwords = 20096 bytes -> 5 pages

Bspec: 65182, 55793, 73590
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_lrc.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index e58eb8b9db78..38f648b98868 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -113,13 +113,17 @@ size_t xe_gt_lrc_hang_replay_size(struct xe_gt *gt, enum xe_engine_class class)
 	/* Engine context image */
 	switch (class) {
 	case XE_ENGINE_CLASS_RENDER:
-		if (GRAPHICS_VER(xe) >= 20)
+		if (GRAPHICS_VERx100(xe) >= 3510)
+			size += 7 * SZ_4K;
+		else if (GRAPHICS_VER(xe) >= 20)
 			size += 3 * SZ_4K;
 		else
 			size += 13 * SZ_4K;
 		break;
 	case XE_ENGINE_CLASS_COMPUTE:
-		if (GRAPHICS_VER(xe) >= 20)
+		if (GRAPHICS_VERx100(xe) >= 3510)
+			size += 5 * SZ_4K;
+		else if (GRAPHICS_VER(xe) >= 20)
 			size += 2 * SZ_4K;
 		else
 			size += 13 * SZ_4K;

-- 
2.52.0

[PATCH 11/16] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB

[Gustavo Sousa]

From: Aradhya Bhatia <aradhya.bhatia@intel.com>

Since the dominant size of the pages referred in an i-gpu, such as
Xe3p_LPG, will be 4KB, the HW default of mix of 64K and 2M for STLB bank
hash mode does not make sense.

Allow the SW to change it to 4KB Mode, for Xe3p_LPG.

Signed-off-by: Aradhya Bhatia <aradhya.bhatia@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 ++
 drivers/gpu/drm/xe/xe_tuning.c       | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 19f053a7f9be..cd84b8945a5d 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -473,6 +473,8 @@
 #define   FORCE_MISS_FTLB			REG_BIT(3)
 
 #define XEHP_GAMSTLB_CTRL			XE_REG_MCR(0xcf4c)
+#define   BANK_HASH_MODE			REG_GENMASK(27, 26)
+#define   BANK_HASH_4KB_MODE			REG_FIELD_PREP(BANK_HASH_MODE, 0x3)
 #define   CONTROL_BLOCK_CLKGATE_DIS		REG_BIT(12)
 #define   EGRESS_BLOCK_CLKGATE_DIS		REG_BIT(11)
 #define   TAG_BLOCK_CLKGATE_DIS			REG_BIT(7)
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 694385ae75f1..316f5e2b2e48 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -90,6 +90,15 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 	  XE_RTP_RULES(MEDIA_VERSION(2000)),
 	  XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3_LBCF, RWFLUSHALLEN))
 	},
+
+	/* Xe3p */
+
+	{ XE_RTP_NAME("Tuning: Set STLB Bank Hash Mode to 4KB"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED),
+		       IS_INTEGRATED),
+	  XE_RTP_ACTIONS(FIELD_SET(XEHP_GAMSTLB_CTRL, BANK_HASH_MODE,
+				   BANK_HASH_4KB_MODE))
+	},
 };
 
 static const struct xe_rtp_entry_sr engine_tunings[] = {

-- 
2.52.0

[PATCH 12/16] drm/xe/xe3p_lpg: Enable multi-queue feature

[Gustavo Sousa]

Xe3p_LPG supports multi-queue on both CCS and BCS. Add the necessary
multi_queue_engine_class_mask to enable that feature.

Bspec: 74110
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index edca562462fa..9bcf7c067479 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -108,6 +108,7 @@ static const struct xe_graphics_desc graphics_xe2 = {
 
 static const struct xe_graphics_desc graphics_xe3p = {
 	XE2_GFX_FEATURES,
+	.multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE),
 };
 
 static const struct xe_graphics_desc graphics_xe3p_xpc = {

-- 
2.52.0

[PATCH 13/16] drm/xe/nvlp: Add NVL-P platform definition

[Gustavo Sousa]

From: Shekhar Chauhan <shekhar.chauhan@intel.com>

Add platform definition along with device IDs for NVL-P.

BSpec: 74201
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_bo.c             |  4 ++--
 drivers/gpu/drm/xe/xe_pci.c            | 15 +++++++++++++++
 drivers/gpu/drm/xe/xe_platform_types.h |  1 +
 include/drm/intel/pciids.h             | 12 ++++++++++++
 4 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 8bf16d60b9a5..9e998f9708df 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -512,8 +512,8 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
 		/*
 		 * Display scanout is always non-coherent with the CPU cache.
 		 *
-		 * For Xe_LPG and beyond, PPGTT PTE lookups are also
-		 * non-coherent and require a CPU:WC mapping.
+		 * For Xe_LPG and beyond up to NVL-P (excluding), PPGTT PTE
+		 * lookups are also non-coherent and require a CPU:WC mapping.
 		 */
 		if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
 		     (!xe->info.has_cached_pt && bo->flags & XE_BO_FLAG_PAGETABLE))
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 9bcf7c067479..1ce4115e117e 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -438,6 +438,20 @@ static const struct xe_device_desc cri_desc = {
 	.vm_max_level = 4,
 };
 
+static const struct xe_device_desc nvlp_desc = {
+	PLATFORM(NOVALAKE_P),
+	.dma_mask_size = 46,
+	.has_cached_pt = true,
+	.has_display = true,
+	.has_flat_ccs = 1,
+	.has_page_reclaim_hw_assist = true,
+	.has_pre_prod_wa = true,
+	.max_gt_per_tile = 2,
+	.require_force_probe = true,
+	.va_bits = 48,
+	.vm_max_level = 4,
+};
+
 #undef PLATFORM
 __diag_pop();
 
@@ -468,6 +482,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
 	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
 	INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc),
+	INTEL_NVLP_IDS(INTEL_VGA_DEVICE, &nvlp_desc),
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index f516dbddfd88..6cff385227ea 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -26,6 +26,7 @@ enum xe_platform {
 	XE_PANTHERLAKE,
 	XE_NOVALAKE_S,
 	XE_CRESCENTISLAND,
+	XE_NOVALAKE_P,
 };
 
 enum xe_subplatform {
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index 52520e684ab1..33b91cb2e684 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -900,4 +900,16 @@
 #define INTEL_CRI_IDS(MACRO__, ...) \
 	MACRO__(0x674C, ## __VA_ARGS__)
 
+/* NVL-P */
+#define INTEL_NVLP_IDS(MACRO__, ...) \
+	MACRO__(0xD750, ## __VA_ARGS__), \
+	MACRO__(0xD751, ## __VA_ARGS__), \
+	MACRO__(0xD752, ## __VA_ARGS__), \
+	MACRO__(0xD753, ## __VA_ARGS__), \
+	MACRO__(0XD754, ## __VA_ARGS__), \
+	MACRO__(0XD755, ## __VA_ARGS__), \
+	MACRO__(0XD756, ## __VA_ARGS__), \
+	MACRO__(0XD757, ## __VA_ARGS__), \
+	MACRO__(0xD75F, ## __VA_ARGS__)
+
 #endif /* __PCIIDS_H__ */

-- 
2.52.0

[PATCH 14/16] drm/xe/nvlp: Attach MOCS table for nvlp

[Gustavo Sousa]

From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>

The MOCS table for nvl-p is same as xe2/xe3.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_mocs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 54822497c21e..1d19df860bea 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -600,6 +600,7 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
 		info->wb_index = 4;
 		info->unused_entries_index = 4;
 		break;
+	case XE_NOVALAKE_P:
 	case XE_NOVALAKE_S:
 	case XE_PANTHERLAKE:
 	case XE_LUNARLAKE:

-- 
2.52.0

[PATCH 15/16] drm/i915/nvlp: Hook up display support

[Gustavo Sousa]

From: Matt Roper <matthew.d.roper@intel.com>

Although NVL-S and NVL-P are quite different on the GT side, they use
identical Xe3p_LPD display IP and should take all the same codepaths.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 471f236c9ddf..1a7f3ca079e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1500,6 +1500,7 @@ static const struct {
 	INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
 	INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
 	INTEL_NVLS_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
+	INTEL_NVLP_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
 };
 
 static const struct {

-- 
2.52.0

[PATCH 16/16] drm/xe/nvlp: Define GuC firmware for NVL-P

[Gustavo Sousa]

From: John Harrison <John.C.Harrison@Intel.com>

Novalake P has different IP on each GT and requires a different GuC
for each. So add separate graphics and media GT entries or NVL-P.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_uc_fw.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 6a8e692fd7a1..60c82b920f47 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -115,6 +115,8 @@ struct fw_blobs_by_type {
 #define XE_GT_TYPE_ANY XE_GT_TYPE_UNINITIALIZED
 
 #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver)					\
+	fw_def(NOVALAKE_P,	GT_TYPE_MAIN,	mmp_ver(xe,	guc,	nvlpg,	70, 55, 4))	\
+	fw_def(NOVALAKE_P,	GT_TYPE_MEDIA,	mmp_ver(xe,	guc,	nvlpm,	70, 55, 4))	\
 	fw_def(CRESCENTISLAND,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	cri,	70, 55, 4))	\
 	fw_def(NOVALAKE_S,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	nvl,	70, 55, 4))	\
 	fw_def(PANTHERLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	ptl,	70, 54, 0))	\

-- 
2.52.0

Re: [PATCH 01/16] drm/xe/xe3p_lpg: Add support for graphics IP 35.10

[Matt Roper]

On Mon, Feb 02, 2026 at 06:43:07PM -0300, Gustavo Sousa wrote:
> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
> 
> Add graphics IP versions 35.10. Since there will be features enabled
> that are not present in graphics_xe2, already create a new
> graphics_xe3p, although currently it only enables the same features as
> graphics_xe2.
> 
> Here is a list of fields, associated Bspec references and eventual
> comments:
> 
>  .va_bits (Bspec 74198)
>  .vm_max_level (Bspec 59507)
>     The spec says "The PPGTT is always a 5-level structure even when the
>     virtual address space is less than 57 bits."
>  .vram_flags
>    - ~XE_VRAM_FLAGS_NEED64K
>      That limitation that does not exist for Xe3p_LPG.

These three aren't part of the graphics descriptor anymore, so they're
not relevant to this patch.

>  .hw_engine_mask (Bspec 60149)
>  .tile_gsm_size (Bspec 52961)
>     This is queried directly from the hardware.

I don't think this flag has ever existed, outside of some temporary
development patches that never moved forward.

>  .has_asid (Bspec 71132)
>  .has_atomic_enable_pte_bit (Bspec 59510, 74675)
>  .has_flat_ccs (Bspec 65255)

This one also isn't part of the graphics descriptor anymore.

>  .has_indirect_ring_state (Bspec 67296)
>  .has_range_tlb_inval (Bspec 71126)
>  .has_usm (Bspec 59651)
> 

We should probably add a reference for has_64bit_timestamp (bspec 60318)
since it's set in XE2_GFX_FEATURES.

Is there any reason not to go ahead and squash in
multi_queue_engine_class_mask from patch #12 here?


Matt

> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pci.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index b5e8935fff1d..edca562462fa 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -106,6 +106,10 @@ static const struct xe_graphics_desc graphics_xe2 = {
>  	XE2_GFX_FEATURES,
>  };
>  
> +static const struct xe_graphics_desc graphics_xe3p = {
> +	XE2_GFX_FEATURES,
> +};
> +
>  static const struct xe_graphics_desc graphics_xe3p_xpc = {
>  	XE2_GFX_FEATURES,
>  	.has_indirect_ring_state = 1,
> @@ -148,6 +152,7 @@ static const struct xe_ip graphics_ips[] = {
>  	{ 3003, "Xe3_LPG", &graphics_xe2 },
>  	{ 3004, "Xe3_LPG", &graphics_xe2 },
>  	{ 3005, "Xe3_LPG", &graphics_xe2 },
> +	{ 3510, "Xe3p_LPG", &graphics_xe3p },
>  	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
>  };
>  
> 
> -- 
> 2.52.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 02/16] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10

[Matt Roper]

On Mon, Feb 02, 2026 at 06:43:08PM -0300, Gustavo Sousa wrote:
> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
> 
> Add the initial set of workarounds for Xe3p_LPG graphics version 35.10.
> 
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Co-developed-by: Nitin Gote <nitin.r.gote@intel.com>
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> Co-developed-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> Co-developed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Signed-off-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Co-developed-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h  | 19 ++++++++++++++
>  drivers/gpu/drm/xe/xe_reg_whitelist.c |  8 ++++++
>  drivers/gpu/drm/xe/xe_wa.c            | 48 +++++++++++++++++++++++++++++++++++
>  3 files changed, 75 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 24fc64fc832e..b5a7cc45f13d 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -100,6 +100,9 @@
>  #define VE1_AUX_INV				XE_REG(0x42b8)
>  #define   AUX_INV				REG_BIT(0)
>  
> +#define GAMSTLB_CTRL2				XE_REG_MCR(0x4788)
> +#define   STLB_SINGLE_BANK_MODE			REG_BIT(11)
> +
>  #define XE2_LMEM_CFG				XE_REG(0x48b0)
>  
>  #define XE2_GAMWALK_CTRL			0x47e4
> @@ -107,12 +110,18 @@
>  #define XE2_GAMWALK_CTRL_3D			XE_REG_MCR(XE2_GAMWALK_CTRL)
>  #define   EN_CMP_1WCOH_GW			REG_BIT(14)
>  
> +#define MMIOATSREQLIMIT_GAM_WALK_3D             XE_REG_MCR(0x47f8)
> +#define   DIS_ATS_WRONLY_PG                     REG_BIT(18)
> +
>  #define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)
>  #define XEHP_FLAT_CCS_PTR			REG_GENMASK(31, 8)
>  
>  #define WM_CHICKEN3				XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
>  #define   HIZ_PLANE_COMPRESSION_DIS		REG_BIT(10)
>  
> +#define TBIMR_MODE				XE_REG_MCR(0x6200, XE_REG_OPTION_MASKED)
> +#define   RXBAR_NO_UAV_DEC_SYNC			REG_BIT(12)
> +
>  #define CHICKEN_RASTER_1			XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
>  #define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
>  #define   DIS_CLIP_NEGATIVE_BOUNDING_BOX	REG_BIT(6)
> @@ -210,6 +219,9 @@
>  
>  #define GSCPSMI_BASE				XE_REG(0x880c)
>  
> +#define CCCHKNREG2				XE_REG_MCR(0x881c)
> +#define  LOCALITYDIS				REG_BIT(7)

Nitpick: the formatting is slightly off here (the field name should be
spaced over one more column).

> +
>  #define CCCHKNREG1				XE_REG_MCR(0x8828)
>  #define   L3CMPCTRL				REG_BIT(23)
>  #define   ENCOMPPERFFIX				REG_BIT(18)
> @@ -420,6 +432,8 @@
>  #define   LSN_DIM_Z_WGT(value)			REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
>  
>  #define L3SQCREG2				XE_REG_MCR(0xb104)
> +#define   L3_SQ_DISABLE_COAMA_2WAY_COH		REG_BIT(30)
> +#define   L3_SQ_DISABLE_COAMA			REG_BIT(22)
>  #define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)
>  
>  #define L3SQCREG3				XE_REG_MCR(0xb108)
> @@ -550,11 +564,16 @@
>  #define   UGM_FRAGMENT_THRESHOLD_TO_3		REG_BIT(58 - 32)
>  #define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)
>  #define   XE2_ALLOC_DPA_STARVE_FIX_DIS		REG_BIT(47 - 32)
> +#define   SAMPLER_LD_LSC_DISABLE                REG_BIT(45 - 32)
>  #define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL	REG_BIT(44 - 32)
>  #define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)
>  #define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)
>  #define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)
>  #define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
> +#define   LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE	REG_BIT(35 - 32)
> +
> +#define ROW_CHICKEN5				XE_REG_MCR(0xe7f0)
> +#define   CPSS_AWARE_DIS			REG_BIT(3)
>  
>  #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
>  #define   COMP_CKN_IN				REG_GENMASK(30, 29)
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index 1d36c09681aa..9c513778d370 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -81,6 +81,14 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
>  			 WHITELIST(VFLSKPD,
>  				   RING_FORCE_TO_NONPRIV_ACCESS_RW))
>  	},
> +	{ XE_RTP_NAME("14024997852"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> +		       ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(WHITELIST(FF_MODE,
> +				   RING_FORCE_TO_NONPRIV_ACCESS_RW),
> +			 WHITELIST(VFLSKPD,
> +				   RING_FORCE_TO_NONPRIV_ACCESS_RW))
> +	},
>  
>  #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
>  	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index a991ee2b8781..68a494743b34 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -306,6 +306,31 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)),
>  	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
>  	},
> +
> +	/* Xe3P_LPG */
> +
> +	{ XE_RTP_NAME("14025160223"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> +	  XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,
> +			     DIS_ATS_WRONLY_PG))
> +	},
> +	{ XE_RTP_NAME("16028780921"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> +	  XE_RTP_ACTIONS(SET(CCCHKNREG2, LOCALITYDIS))
> +	},
> +	{ XE_RTP_NAME("14026144927"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> +	  XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |
> +			     L3_SQ_DISABLE_COAMA))
> +	},
> +	{ XE_RTP_NAME("14025635424"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> +	  XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE))
> +	},
> +	{ XE_RTP_NAME("16028005424"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> +	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> +	},
>  };
>  
>  static const struct xe_rtp_entry_sr engine_was[] = {
> @@ -680,6 +705,24 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
>  	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
>  	},
> +
> +	/* Xe3p_LPG*/
> +
> +	{ XE_RTP_NAME("22021149932"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> +		       FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))
> +	},
> +	{ XE_RTP_NAME("14025676848"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> +		       FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))
> +	},
> +	{ XE_RTP_NAME("16028951944"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> +		       FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
> +	},
>  };
>  
>  static const struct xe_rtp_entry_sr lrc_was[] = {
> @@ -879,6 +922,11 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  		       ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
>  	},
> +	{ XE_RTP_NAME("14025780377"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> +		       ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(SET(TBIMR_MODE, RXBAR_NO_UAV_DEC_SYNC))

I'm not sure if this one is actually needed.  Originally the workaround
ticket just said "program 0x6200[12]" but it's since been updated to an
"if (por) no workaround needed, else if (non-POR thing) program the
register and add a stalling flush."  There are also comments in the
ticket itself that indicate it shouldn't actually be relevant to this
specific platform due to other characteristics of the platform; it's
just something that they'll need to fix or workaround in the future so
that it doesn't impact future derivative platforms.


Matt

> +	},
>  };
>  
>  static __maybe_unused const struct xe_rtp_entry oob_was[] = {
> 
> -- 
> 2.52.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 03/16] drm/xe/pat: Differentiate between primary and media for PTA

[Matt Roper]

On Mon, Feb 02, 2026 at 06:43:09PM -0300, Gustavo Sousa wrote:
> Differently from currently supported platforms, in upcoming changes we
> will need to have different PAT entries for PTA based on the GT type. As
> such, let's prepare the code to support that by having two separate
> PTA-specific members in the pat struct, one for each type of GT.
> 
> While at it, also fix the kerneldoc for pat_ats.
> 
> Co-developed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_device_types.h |  8 +++++---
>  drivers/gpu/drm/xe/xe_pat.c          | 27 ++++++++++++++++++---------
>  2 files changed, 23 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 34feef79fa4e..4508ed54d1d5 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -568,10 +568,12 @@ struct xe_device {
>  		const struct xe_pat_table_entry *table;
>  		/** @pat.n_entries: Number of PAT entries */
>  		int n_entries;
> -		/** @pat.ats_entry: PAT entry for PCIe ATS responses */
> +		/** @pat.pat_ats: PAT entry for PCIe ATS responses */
>  		const struct xe_pat_table_entry *pat_ats;
> -		/** @pat.pta_entry: PAT entry for page table accesses */
> -		const struct xe_pat_table_entry *pat_pta;
> +		/** @pat.pat_primary_pta: primary GT PAT entry for page table accesses */
> +		const struct xe_pat_table_entry *pat_primary_pta;
> +		/** @pat.pat_media_pta: media GT PAT entry for page table accesses */
> +		const struct xe_pat_table_entry *pat_media_pta;
>  		u32 idx[__XE_CACHE_LEVEL_COUNT];
>  	} pat;
>  
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 14d0dce5190a..5776ea67fe02 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -284,8 +284,10 @@ static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[
>  
>  	if (xe->pat.pat_ats)
>  		xe_mmio_write32(&gt->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value);
> -	if (xe->pat.pat_pta)
> -		xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe->pat.pat_pta->value);
> +	if (xe->pat.pat_primary_pta && xe_gt_is_main_type(gt))
> +		xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe->pat.pat_primary_pta->value);
> +	if (xe->pat.pat_media_pta && xe_gt_is_media_type(gt))
> +		xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe->pat.pat_media_pta->value);
>  }
>  
>  static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[],
> @@ -301,8 +303,10 @@ static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry ta
>  
>  	if (xe->pat.pat_ats)
>  		xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value);
> -	if (xe->pat.pat_pta)
> -		xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_pta->value);
> +	if (xe->pat.pat_primary_pta && xe_gt_is_main_type(gt))
> +		xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_primary_pta->value);
> +	if (xe->pat.pat_media_pta && xe_gt_is_media_type(gt))
> +		xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_media_pta->value);
>  }
>  
>  static int xelp_dump(struct xe_gt *gt, struct drm_printer *p)
> @@ -527,7 +531,8 @@ void xe_pat_init_early(struct xe_device *xe)
>  		xe->pat.ops = &xe3p_xpc_pat_ops;
>  		xe->pat.table = xe3p_xpc_pat_table;
>  		xe->pat.pat_ats = &xe3p_xpc_pat_ats;
> -		xe->pat.pat_pta = &xe3p_xpc_pat_pta;
> +		xe->pat.pat_primary_pta = &xe3p_xpc_pat_pta;
> +		xe->pat.pat_media_pta = &xe3p_xpc_pat_pta;
>  		xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
>  		xe->pat.idx[XE_CACHE_NONE] = 3;
>  		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
> @@ -541,8 +546,10 @@ void xe_pat_init_early(struct xe_device *xe)
>  			xe->pat.table = xe2_pat_table;
>  		}
>  		xe->pat.pat_ats = &xe2_pat_ats;
> -		if (IS_DGFX(xe))
> -			xe->pat.pat_pta = &xe2_pat_pta;
> +		if (IS_DGFX(xe)) {
> +			xe->pat.pat_primary_pta = &xe2_pat_pta;
> +			xe->pat.pat_media_pta = &xe2_pat_pta;
> +		}
>  
>  		/* Wa_16023588340. XXX: Should use XE_WA */
>  		if (GRAPHICS_VERx100(xe) == 2001)
> @@ -649,6 +656,8 @@ int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p)
>  int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
>  {
>  	struct xe_device *xe = gt_to_xe(gt);
> +	const struct xe_pat_table_entry *pta_entry = xe_gt_is_main_type(gt) ?
> +		xe->pat.pat_primary_pta : xe->pat.pat_media_pta;
>  	char label[PAT_LABEL_LEN];
>  
>  	if (!xe->pat.table || !xe->pat.n_entries)
> @@ -675,8 +684,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
>  		}
>  	}
>  
> -	if (xe->pat.pat_pta) {
> -		u32 pat = xe->pat.pat_pta->value;
> +	if (pta_entry) {
> +		u32 pat = pta_entry->value;
>  
>  		drm_printf(p, "Page Table Access:\n");
>  		xe2_pat_entry_dump(p, "PTA_MODE", pat, false);
> 
> -- 
> 2.52.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 10/16] drm/xe/xe3p_lpg: Update LRC sizes

[Matt Roper]

On Mon, Feb 02, 2026 at 06:43:16PM -0300, Gustavo Sousa wrote:
> Like with previous generations, the engine context images for of both
> RCS and CCS in Xe3p_LPG contain a common layout at the end for the
> context related to the "Compute Pipeline".
> 
> The size of the memory area written to such section varies; it depends
> on the type of preemption has taken place during the execution and type
> of command streamer instruction that was used on the pipeline. For
> Xe3p_LPG, the maximum possible size, including NOOPs for cache line
> alignment, is 4368 dwords, which would be the case of a mid-thread
> preemption during the execution of a COMPUTE_WALKER_2 instruction.

Double checking:

CW_INTERNAL_STATE_2: 22 dwords each * 128 instances = 2816 dwords
CFE_SS_RESTORE:  2 dwords
COMPUTE_WALKER_2:  64 dwords * 24 instances = 1536

2816 + 2 + 1536 = 4354 rounded up to cacheline (16 dword) alignment is
4368 which matches what you calculated.

I didn't carefully re-count all the non-computepipeline dwords again,
but eyeballing the list there aren't any major differences in that part
that would meaningfully change the size of the LRC once we round up to
page size, so replacing the old Xe2/Xe3 compute pipeline (~1128 dwords)
with the new Xe3p 4368 value gives me a rounded up value of 7 pages and
5 pages for the RCS and CCS respectively, which is what you have here.
So your numbers look good to me.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Hopefully in future platforms they'll make these numbers easier to
verify in the bspec without requiring us to carefully count up hundreds
of instructions by hand...


Matt

> 
> The maximum size has increased in such a way that we need to update
> xe_gt_lrc_size() to match the new sizing requirement. When we add that
> to the engine-specific parts, we have:
> 
>   - RCS context image: 6672 dwords = 26688 bytes -> 7 pages
>   - CCS context image: 5024 dwords = 20096 bytes -> 5 pages
> 
> Bspec: 65182, 55793, 73590
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_lrc.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index e58eb8b9db78..38f648b98868 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -113,13 +113,17 @@ size_t xe_gt_lrc_hang_replay_size(struct xe_gt *gt, enum xe_engine_class class)
>  	/* Engine context image */
>  	switch (class) {
>  	case XE_ENGINE_CLASS_RENDER:
> -		if (GRAPHICS_VER(xe) >= 20)
> +		if (GRAPHICS_VERx100(xe) >= 3510)
> +			size += 7 * SZ_4K;
> +		else if (GRAPHICS_VER(xe) >= 20)
>  			size += 3 * SZ_4K;
>  		else
>  			size += 13 * SZ_4K;
>  		break;
>  	case XE_ENGINE_CLASS_COMPUTE:
> -		if (GRAPHICS_VER(xe) >= 20)
> +		if (GRAPHICS_VERx100(xe) >= 3510)
> +			size += 5 * SZ_4K;
> +		else if (GRAPHICS_VER(xe) >= 20)
>  			size += 2 * SZ_4K;
>  		else
>  			size += 13 * SZ_4K;
> 
> -- 
> 2.52.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 11/16] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB

[Matt Roper]

On Mon, Feb 02, 2026 at 06:43:17PM -0300, Gustavo Sousa wrote:
> From: Aradhya Bhatia <aradhya.bhatia@intel.com>
> 
> Since the dominant size of the pages referred in an i-gpu, such as
> Xe3p_LPG, will be 4KB, the HW default of mix of 64K and 2M for STLB bank
> hash mode does not make sense.
> 
> Allow the SW to change it to 4KB Mode, for Xe3p_LPG.
> 
> Signed-off-by: Aradhya Bhatia <aradhya.bhatia@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

It was a bit hard to track down the source of this since it isn't on the
usual "tuning" page of the bspec.  We should make sure we add a bspec
reference, especially so this can be double checked for accuracy on
future platforms.

Bspec: 78248
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 ++
>  drivers/gpu/drm/xe/xe_tuning.c       | 9 +++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 19f053a7f9be..cd84b8945a5d 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -473,6 +473,8 @@
>  #define   FORCE_MISS_FTLB			REG_BIT(3)
>  
>  #define XEHP_GAMSTLB_CTRL			XE_REG_MCR(0xcf4c)
> +#define   BANK_HASH_MODE			REG_GENMASK(27, 26)
> +#define   BANK_HASH_4KB_MODE			REG_FIELD_PREP(BANK_HASH_MODE, 0x3)
>  #define   CONTROL_BLOCK_CLKGATE_DIS		REG_BIT(12)
>  #define   EGRESS_BLOCK_CLKGATE_DIS		REG_BIT(11)
>  #define   TAG_BLOCK_CLKGATE_DIS			REG_BIT(7)
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 694385ae75f1..316f5e2b2e48 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -90,6 +90,15 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  	  XE_RTP_RULES(MEDIA_VERSION(2000)),
>  	  XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3_LBCF, RWFLUSHALLEN))
>  	},
> +
> +	/* Xe3p */
> +
> +	{ XE_RTP_NAME("Tuning: Set STLB Bank Hash Mode to 4KB"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED),
> +		       IS_INTEGRATED),
> +	  XE_RTP_ACTIONS(FIELD_SET(XEHP_GAMSTLB_CTRL, BANK_HASH_MODE,
> +				   BANK_HASH_4KB_MODE))
> +	},
>  };
>  
>  static const struct xe_rtp_entry_sr engine_tunings[] = {
> 
> -- 
> 2.52.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 12/16] drm/xe/xe3p_lpg: Enable multi-queue feature

[Matt Roper]

On Mon, Feb 02, 2026 at 06:43:18PM -0300, Gustavo Sousa wrote:
> Xe3p_LPG supports multi-queue on both CCS and BCS. Add the necessary
> multi_queue_engine_class_mask to enable that feature.
> 
> Bspec: 74110
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

As mentioned previously, I think we can just squash this into the
general IP definition; no real need to keep it as a separate patch.


Matt

> ---
>  drivers/gpu/drm/xe/xe_pci.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index edca562462fa..9bcf7c067479 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -108,6 +108,7 @@ static const struct xe_graphics_desc graphics_xe2 = {
>  
>  static const struct xe_graphics_desc graphics_xe3p = {
>  	XE2_GFX_FEATURES,
> +	.multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE),
>  };
>  
>  static const struct xe_graphics_desc graphics_xe3p_xpc = {
> 
> -- 
> 2.52.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 01/16] drm/xe/xe3p_lpg: Add support for graphics IP 35.10

[Matt Roper]

On Mon, Feb 02, 2026 at 02:11:04PM -0800, Matt Roper wrote:
> On Mon, Feb 02, 2026 at 06:43:07PM -0300, Gustavo Sousa wrote:
> > From: Shekhar Chauhan <shekhar.chauhan@intel.com>
> > 
> > Add graphics IP versions 35.10. Since there will be features enabled
> > that are not present in graphics_xe2, already create a new
> > graphics_xe3p, although currently it only enables the same features as
> > graphics_xe2.
> > 
> > Here is a list of fields, associated Bspec references and eventual
> > comments:
> > 
> >  .va_bits (Bspec 74198)
> >  .vm_max_level (Bspec 59507)
> >     The spec says "The PPGTT is always a 5-level structure even when the
> >     virtual address space is less than 57 bits."
> >  .vram_flags
> >    - ~XE_VRAM_FLAGS_NEED64K
> >      That limitation that does not exist for Xe3p_LPG.
> 
> These three aren't part of the graphics descriptor anymore, so they're
> not relevant to this patch.
> 
> >  .hw_engine_mask (Bspec 60149)
> >  .tile_gsm_size (Bspec 52961)
> >     This is queried directly from the hardware.
> 
> I don't think this flag has ever existed, outside of some temporary
> development patches that never moved forward.
> 
> >  .has_asid (Bspec 71132)
> >  .has_atomic_enable_pte_bit (Bspec 59510, 74675)
> >  .has_flat_ccs (Bspec 65255)
> 
> This one also isn't part of the graphics descriptor anymore.
> 
> >  .has_indirect_ring_state (Bspec 67296)
> >  .has_range_tlb_inval (Bspec 71126)
> >  .has_usm (Bspec 59651)
> > 
> 
> We should probably add a reference for has_64bit_timestamp (bspec 60318)
> since it's set in XE2_GFX_FEATURES.
> 
> Is there any reason not to go ahead and squash in
> multi_queue_engine_class_mask from patch #12 here?
> 
> 
> Matt
> 
> > Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_pci.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > index b5e8935fff1d..edca562462fa 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -106,6 +106,10 @@ static const struct xe_graphics_desc graphics_xe2 = {
> >  	XE2_GFX_FEATURES,
> >  };
> >  
> > +static const struct xe_graphics_desc graphics_xe3p = {

One more comment: we may want to name this "graphics_xe3p_lpg" to help
distinguish it from graphics_xe3p_xpc below.


Matt

> > +	XE2_GFX_FEATURES,
> > +};
> > +
> >  static const struct xe_graphics_desc graphics_xe3p_xpc = {
> >  	XE2_GFX_FEATURES,
> >  	.has_indirect_ring_state = 1,
> > @@ -148,6 +152,7 @@ static const struct xe_ip graphics_ips[] = {
> >  	{ 3003, "Xe3_LPG", &graphics_xe2 },
> >  	{ 3004, "Xe3_LPG", &graphics_xe2 },
> >  	{ 3005, "Xe3_LPG", &graphics_xe2 },
> > +	{ 3510, "Xe3p_LPG", &graphics_xe3p },
> >  	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
> >  };
> >  
> > 
> > -- 
> > 2.52.0
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

✓ i915.CI.BAT: success for Basic enabling patches for Xe3p_LPG and NVL-P

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2998 bytes --]

== Series Details ==

Series: Basic enabling patches for Xe3p_LPG and NVL-P
URL   : https://patchwork.freedesktop.org/series/161036/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17921 -> Patchwork_161036v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/index.html

Participating hosts (43 -> 41)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_161036v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [PASS][1] -> [DMESG-FAIL][2] ([i915#12061]) +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/bat-dg2-9/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-arlh-3:         [INCOMPLETE][3] ([i915#15622]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/bat-arlh-3/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/bat-arlh-3/igt@i915_selftest@live.html

  * igt@i915_selftest@live@memory_region:
    - bat-arlh-3:         [INCOMPLETE][5] -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/bat-arlh-3/igt@i915_selftest@live@memory_region.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/bat-arlh-3/igt@i915_selftest@live@memory_region.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-14:         [DMESG-FAIL][7] ([i915#12061]) -> [PASS][8] +1 other test pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/bat-dg2-14/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [DMESG-FAIL][9] ([i915#12061]) -> [PASS][10] +1 other test pass
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#15622]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15622


Build changes
-------------

  * Linux: CI_DRM_17921 -> Patchwork_161036v1

  CI-20190529: 20190529
  CI_DRM_17921: 67c3b61c4451b33dbf846f97cb2389b7fb6db09d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8729: 8729
  Patchwork_161036v1: 67c3b61c4451b33dbf846f97cb2389b7fb6db09d @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/index.html

[-- Attachment #2: Type: text/html, Size: 3835 bytes --]

Re: [PATCH 13/16] drm/xe/nvlp: Add NVL-P platform definition

[Matt Roper]

On Mon, Feb 02, 2026 at 06:43:19PM -0300, Gustavo Sousa wrote:
> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
> 
> Add platform definition along with device IDs for NVL-P.

Not sure if you wanted to add bspec references to this one like you had
for the Xe3p_LPG descriptor, but the flags you have here look correct to
me for now and the PCI IDs look correct so,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> 
> BSpec: 74201
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_bo.c             |  4 ++--
>  drivers/gpu/drm/xe/xe_pci.c            | 15 +++++++++++++++
>  drivers/gpu/drm/xe/xe_platform_types.h |  1 +
>  include/drm/intel/pciids.h             | 12 ++++++++++++
>  4 files changed, 30 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index 8bf16d60b9a5..9e998f9708df 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -512,8 +512,8 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
>  		/*
>  		 * Display scanout is always non-coherent with the CPU cache.
>  		 *
> -		 * For Xe_LPG and beyond, PPGTT PTE lookups are also
> -		 * non-coherent and require a CPU:WC mapping.
> +		 * For Xe_LPG and beyond up to NVL-P (excluding), PPGTT PTE
> +		 * lookups are also non-coherent and require a CPU:WC mapping.
>  		 */
>  		if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
>  		     (!xe->info.has_cached_pt && bo->flags & XE_BO_FLAG_PAGETABLE))
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 9bcf7c067479..1ce4115e117e 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -438,6 +438,20 @@ static const struct xe_device_desc cri_desc = {
>  	.vm_max_level = 4,
>  };
>  
> +static const struct xe_device_desc nvlp_desc = {
> +	PLATFORM(NOVALAKE_P),
> +	.dma_mask_size = 46,
> +	.has_cached_pt = true,
> +	.has_display = true,
> +	.has_flat_ccs = 1,
> +	.has_page_reclaim_hw_assist = true,
> +	.has_pre_prod_wa = true,
> +	.max_gt_per_tile = 2,
> +	.require_force_probe = true,
> +	.va_bits = 48,
> +	.vm_max_level = 4,
> +};
> +
>  #undef PLATFORM
>  __diag_pop();
>  
> @@ -468,6 +482,7 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>  	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
>  	INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc),
> +	INTEL_NVLP_IDS(INTEL_VGA_DEVICE, &nvlp_desc),
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
> index f516dbddfd88..6cff385227ea 100644
> --- a/drivers/gpu/drm/xe/xe_platform_types.h
> +++ b/drivers/gpu/drm/xe/xe_platform_types.h
> @@ -26,6 +26,7 @@ enum xe_platform {
>  	XE_PANTHERLAKE,
>  	XE_NOVALAKE_S,
>  	XE_CRESCENTISLAND,
> +	XE_NOVALAKE_P,
>  };
>  
>  enum xe_subplatform {
> diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
> index 52520e684ab1..33b91cb2e684 100644
> --- a/include/drm/intel/pciids.h
> +++ b/include/drm/intel/pciids.h
> @@ -900,4 +900,16 @@
>  #define INTEL_CRI_IDS(MACRO__, ...) \
>  	MACRO__(0x674C, ## __VA_ARGS__)
>  
> +/* NVL-P */
> +#define INTEL_NVLP_IDS(MACRO__, ...) \
> +	MACRO__(0xD750, ## __VA_ARGS__), \
> +	MACRO__(0xD751, ## __VA_ARGS__), \
> +	MACRO__(0xD752, ## __VA_ARGS__), \
> +	MACRO__(0xD753, ## __VA_ARGS__), \
> +	MACRO__(0XD754, ## __VA_ARGS__), \
> +	MACRO__(0XD755, ## __VA_ARGS__), \
> +	MACRO__(0XD756, ## __VA_ARGS__), \
> +	MACRO__(0XD757, ## __VA_ARGS__), \
> +	MACRO__(0xD75F, ## __VA_ARGS__)
> +
>  #endif /* __PCIIDS_H__ */
> 
> -- 
> 2.52.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 14/16] drm/xe/nvlp: Attach MOCS table for nvlp

[Matt Roper]

On Mon, Feb 02, 2026 at 06:43:20PM -0300, Gustavo Sousa wrote:
> From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> 
> The MOCS table for nvl-p is same as xe2/xe3.
> 
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_mocs.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index 54822497c21e..1d19df860bea 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -600,6 +600,7 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
>  		info->wb_index = 4;
>  		info->unused_entries_index = 4;
>  		break;
> +	case XE_NOVALAKE_P:
>  	case XE_NOVALAKE_S:
>  	case XE_PANTHERLAKE:
>  	case XE_LUNARLAKE:
> 
> -- 
> 2.52.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 16/16] drm/xe/nvlp: Define GuC firmware for NVL-P

[Matt Roper]

On Mon, Feb 02, 2026 at 06:43:22PM -0300, Gustavo Sousa wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> Novalake P has different IP on each GT and requires a different GuC
> for each. So add separate graphics and media GT entries or NVL-P.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

I think we'll need to land this patch in topic/xe-for-CI initially
rather than drm-xe-next, but otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_uc_fw.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
> index 6a8e692fd7a1..60c82b920f47 100644
> --- a/drivers/gpu/drm/xe/xe_uc_fw.c
> +++ b/drivers/gpu/drm/xe/xe_uc_fw.c
> @@ -115,6 +115,8 @@ struct fw_blobs_by_type {
>  #define XE_GT_TYPE_ANY XE_GT_TYPE_UNINITIALIZED
>  
>  #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver)					\
> +	fw_def(NOVALAKE_P,	GT_TYPE_MAIN,	mmp_ver(xe,	guc,	nvlpg,	70, 55, 4))	\
> +	fw_def(NOVALAKE_P,	GT_TYPE_MEDIA,	mmp_ver(xe,	guc,	nvlpm,	70, 55, 4))	\
>  	fw_def(CRESCENTISLAND,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	cri,	70, 55, 4))	\
>  	fw_def(NOVALAKE_S,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	nvl,	70, 55, 4))	\
>  	fw_def(PANTHERLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	ptl,	70, 54, 0))	\
> 
> -- 
> 2.52.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

RE: [PATCH 15/16] drm/i915/nvlp: Hook up display support

[Kandpal, Suraj]

> Subject: [PATCH 15/16] drm/i915/nvlp: Hook up display support
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Although NVL-S and NVL-P are quite different on the GT side, they use
> identical Xe3p_LPD display IP and should take all the same codepaths.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 471f236c9ddf..1a7f3ca079e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1500,6 +1500,7 @@ static const struct {
>  	INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
>  	INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
>  	INTEL_NVLS_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
> +	INTEL_NVLP_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
>  };
> 
>  static const struct {
> 
> --
> 2.52.0

✓ i915.CI.Full: success for Basic enabling patches for Xe3p_LPG and NVL-P

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 98055 bytes --]

== Series Details ==

Series: Basic enabling patches for Xe3p_LPG and NVL-P
URL   : https://patchwork.freedesktop.org/series/161036/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17921_full -> Patchwork_161036v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_161036v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_buddy@drm_buddy@drm_test_buddy_fragmentation_performance:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][1] ([i915#15095]) +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@drm_buddy@drm_buddy@drm_test_buddy_fragmentation_performance.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][2] ([i915#13008])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][3] ([i915#9323])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@gem_ccs@suspend-resume.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-rkl:          NOTRUN -> [SKIP][4] ([i915#4525]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-tglu-1:       NOTRUN -> [SKIP][5] ([i915#4525])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-dg2:          NOTRUN -> [SKIP][6] ([i915#3539] / [i915#4852])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-dg2:          NOTRUN -> [SKIP][7] ([i915#5107])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_exec_reloc@basic-active:
    - shard-mtlp:         NOTRUN -> [SKIP][8] ([i915#3281])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@gem_exec_reloc@basic-active.html

  * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][9] ([i915#3281]) +5 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html

  * igt@gem_exec_reloc@basic-cpu-read-active:
    - shard-dg2:          NOTRUN -> [SKIP][10] ([i915#3281]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@gem_exec_reloc@basic-cpu-read-active.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-rkl:          [PASS][11] -> [INCOMPLETE][12] ([i915#13356]) +1 other test incomplete
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-5/igt@gem_exec_suspend@basic-s0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_fence_thrash@bo-write-verify-none:
    - shard-mtlp:         NOTRUN -> [SKIP][13] ([i915#4860])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@gem_fence_thrash@bo-write-verify-none.html

  * igt@gem_huc_copy@huc-copy:
    - shard-rkl:          NOTRUN -> [SKIP][14] ([i915#2190])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-glk:          NOTRUN -> [SKIP][15] ([i915#4613]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk5/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][16] ([i915#4613]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
    - shard-tglu-1:       NOTRUN -> [SKIP][17] ([i915#4613]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_media_vme:
    - shard-rkl:          NOTRUN -> [SKIP][18] ([i915#284])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@gem_media_vme.html

  * igt@gem_mmap_gtt@cpuset-big-copy:
    - shard-mtlp:         NOTRUN -> [SKIP][19] ([i915#4077])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@gem_mmap_gtt@cpuset-big-copy.html

  * igt@gem_mmap_wc@write-gtt-read-wc:
    - shard-dg2:          NOTRUN -> [SKIP][20] ([i915#4083]) +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@gem_mmap_wc@write-gtt-read-wc.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-rkl:          NOTRUN -> [SKIP][21] ([i915#3282]) +4 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_pread@exhaustion:
    - shard-dg2:          NOTRUN -> [SKIP][22] ([i915#3282])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-tglu:         NOTRUN -> [SKIP][23] ([i915#13398])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#4270]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][25] ([i915#8428])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html

  * igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#5190] / [i915#8428]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html

  * igt@gem_set_tiling_vs_pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#4079])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_tiling_max_stride:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#4077]) +3 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@gem_tiling_max_stride.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][29] ([i915#3297])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-rkl:          NOTRUN -> [SKIP][30] ([i915#3297]) +3 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@gem_userptr_blits@unsync-overlap.html
    - shard-tglu-1:       NOTRUN -> [SKIP][31] ([i915#3297])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-rkl:          NOTRUN -> [SKIP][32] ([i915#2527])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#2856])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@gen9_exec_parse@bb-chained.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-tglu:         NOTRUN -> [SKIP][34] ([i915#2527] / [i915#2856]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-tglu-1:       NOTRUN -> [SKIP][35] ([i915#2527] / [i915#2856]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@i915_drm_fdinfo@all-busy-check-all:
    - shard-dg2:          NOTRUN -> [SKIP][36] ([i915#14123])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@i915_drm_fdinfo@all-busy-check-all.html

  * igt@i915_drm_fdinfo@virtual-busy-hang-all:
    - shard-dg2:          NOTRUN -> [SKIP][37] ([i915#14118])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@i915_drm_fdinfo@virtual-busy-hang-all.html

  * igt@i915_module_load@resize-bar:
    - shard-tglu:         NOTRUN -> [SKIP][38] ([i915#6412])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_api@freq-reset:
    - shard-tglu-1:       NOTRUN -> [SKIP][39] ([i915#8399])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@i915_pm_freq_api@freq-reset.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglu:         [PASS][40] -> [WARN][41] ([i915#13790] / [i915#2681]) +1 other test warn
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-tglu-6/igt@i915_pm_rc6_residency@rc6-fence.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-10/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-rkl:          NOTRUN -> [SKIP][42] ([i915#14498])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_query@hwconfig_table:
    - shard-rkl:          NOTRUN -> [SKIP][43] ([i915#6245])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@i915_query@hwconfig_table.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          NOTRUN -> [SKIP][44] ([i915#5723])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@i915_query@test-query-geometry-subslices.html
    - shard-tglu-1:       NOTRUN -> [SKIP][45] ([i915#5723])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-glk:          NOTRUN -> [INCOMPLETE][46] ([i915#4817])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk1/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@intel_hwmon@hwmon-write:
    - shard-tglu:         NOTRUN -> [SKIP][47] ([i915#7707])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@intel_hwmon@hwmon-write.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][48] ([i915#4212]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_addfb_basic@basic-x-tiled-legacy.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#1769] / [i915#3555])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
    - shard-tglu-1:       NOTRUN -> [SKIP][50] ([i915#1769] / [i915#3555])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-rkl:          NOTRUN -> [SKIP][51] ([i915#5286]) +4 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
    - shard-mtlp:         [PASS][52] -> [FAIL][53] ([i915#5138])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-mtlp-5/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][54] ([i915#5286]) +3 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         NOTRUN -> [FAIL][55] ([i915#5138])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][56] ([i915#5286]) +3 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][57] ([i915#3638]) +3 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][58] ([i915#3828])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-tglu:         NOTRUN -> [SKIP][59] ([i915#3828])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#4538] / [i915#5190]) +4 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][61] +26 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-rkl:          NOTRUN -> [SKIP][62] +17 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-1:
    - shard-glk10:        NOTRUN -> [SKIP][63] +122 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk10/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][64] ([i915#6095]) +29 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs@pipe-c-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([i915#6095]) +62 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs@pipe-c-dp-3.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][66] ([i915#12313]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][67] ([i915#12805])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
    - shard-tglu-1:       NOTRUN -> [SKIP][68] ([i915#12805])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][69] ([i915#10307] / [i915#6095]) +134 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#6095]) +43 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([i915#14098] / [i915#6095]) +32 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1.html
    - shard-tglu-1:       NOTRUN -> [SKIP][72] ([i915#6095]) +29 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][73] ([i915#6095]) +167 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg1-14/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][74] ([i915#12313])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][75] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-4/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-tglu:         NOTRUN -> [SKIP][76] ([i915#3742])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#13781]) +3 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_cdclk@plane-scaling:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#3742])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-tglu:         NOTRUN -> [SKIP][79] ([i915#11151] / [i915#7828]) +4 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-rkl:          NOTRUN -> [SKIP][80] ([i915#11151] / [i915#7828]) +5 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-dg2:          NOTRUN -> [SKIP][81] ([i915#11151] / [i915#7828]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-tglu-1:       NOTRUN -> [SKIP][82] ([i915#11151] / [i915#7828]) +3 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_color@deep-color:
    - shard-tglu:         NOTRUN -> [SKIP][83] ([i915#3555] / [i915#9979])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][84] ([i915#6944] / [i915#7118] / [i915#9424]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0-hdcp14:
    - shard-tglu:         NOTRUN -> [SKIP][85] ([i915#15330])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_content_protection@dp-mst-lic-type-0-hdcp14.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([i915#15330] / [i915#3116] / [i915#3299])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-dg2:          NOTRUN -> [SKIP][87] ([i915#15330])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@legacy:
    - shard-tglu-1:       NOTRUN -> [SKIP][88] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0:
    - shard-rkl:          NOTRUN -> [SKIP][89] ([i915#6944] / [i915#9424])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@uevent-hdcp14:
    - shard-tglu-1:       NOTRUN -> [SKIP][90] ([i915#6944])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_content_protection@uevent-hdcp14.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][91] ([i915#13049]) +1 other test skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][92] ([i915#13566]) +1 other test fail
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-tglu:         NOTRUN -> [SKIP][93] ([i915#13049]) +1 other test skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][94] ([i915#3555])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-tglu-1:       NOTRUN -> [SKIP][95] ([i915#13049])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#13046] / [i915#5354]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][97] ([i915#4103])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-tglu-1:       NOTRUN -> [SKIP][98] ([i915#9723])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-rkl:          NOTRUN -> [SKIP][99] ([i915#9723]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-rkl:          NOTRUN -> [SKIP][100] ([i915#13691])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-tglu:         NOTRUN -> [SKIP][101] ([i915#13748])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-tglu:         NOTRUN -> [SKIP][102] ([i915#13707])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#13707])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-dg2:          NOTRUN -> [SKIP][104] ([i915#3840] / [i915#9688])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-tglu-1:       NOTRUN -> [SKIP][105] ([i915#3555] / [i915#3840])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          NOTRUN -> [SKIP][106] ([i915#3555] / [i915#3840])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][107] ([i915#3955])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@chamelium:
    - shard-tglu:         NOTRUN -> [SKIP][108] ([i915#2065] / [i915#4854])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-4x:
    - shard-rkl:          NOTRUN -> [SKIP][109] ([i915#1839])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_feature_discovery@display-4x.html
    - shard-tglu-1:       NOTRUN -> [SKIP][110] ([i915#1839])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][111] ([i915#9934]) +1 other test skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-tglu-1:       NOTRUN -> [SKIP][112] ([i915#9934])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][113] ([i915#12745] / [i915#4839])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk10/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][114] ([i915#4839])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk10/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-plain-flip-ts-check:
    - shard-rkl:          NOTRUN -> [SKIP][115] ([i915#9934]) +6 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_flip@2x-plain-flip-ts-check.html
    - shard-tglu-1:       NOTRUN -> [SKIP][116] ([i915#3637] / [i915#9934]) +1 other test skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_flip@2x-plain-flip-ts-check.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][117] ([i915#3637] / [i915#9934]) +3 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-fences:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#8381])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][119] ([i915#15643])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][120] ([i915#15643])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([i915#15643] / [i915#5190]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][122] ([i915#15643]) +1 other test skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][123] ([i915#15643]) +1 other test skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x:
    - shard-rkl:          NOTRUN -> [SKIP][124] ([i915#15645])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x.html
    - shard-tglu-1:       NOTRUN -> [SKIP][125] ([i915#15645])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#15104])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][127] ([i915#15574]) +3 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][128] ([i915#15574]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render:
    - shard-tglu:         NOTRUN -> [SKIP][129] ([i915#15574])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#5439])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][131] ([i915#15102]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][132] ([i915#8708]) +7 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][133] ([i915#5354]) +8 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][134] ([i915#15574])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][135] ([i915#15102])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw:
    - shard-dg2:          NOTRUN -> [SKIP][136] ([i915#15102] / [i915#3458]) +6 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-tglu:         NOTRUN -> [SKIP][137] ([i915#15102]) +7 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw:
    - shard-mtlp:         NOTRUN -> [SKIP][138] ([i915#1825]) +1 other test skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][139] ([i915#1825]) +33 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-tglu:         NOTRUN -> [SKIP][140] +28 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][141] ([i915#15102]) +11 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
    - shard-rkl:          NOTRUN -> [SKIP][142] ([i915#15102] / [i915#3023]) +12 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html

  * igt@kms_hdr@static-toggle:
    - shard-tglu-1:       NOTRUN -> [SKIP][143] ([i915#3555] / [i915#8228])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][144] ([i915#3555] / [i915#8228])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][145] ([i915#15460])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#15458])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-tglu:         NOTRUN -> [SKIP][147] ([i915#6301]) +1 other test skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-rkl:          NOTRUN -> [SKIP][148] ([i915#14712])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
    - shard-tglu-1:       NOTRUN -> [SKIP][149] ([i915#14712])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier-source-clamping@pipe-a-plane-4:
    - shard-glk:          NOTRUN -> [SKIP][150] +178 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk5/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier-source-clamping@pipe-a-plane-4.html

  * igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-b-plane-5:
    - shard-dg2:          NOTRUN -> [SKIP][151] ([i915#15608] / [i915#8825]) +1 other test skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping:
    - shard-dg2:          NOTRUN -> [SKIP][152] ([i915#15608] / [i915#15609] / [i915#8825])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-a-plane-5:
    - shard-dg2:          NOTRUN -> [SKIP][153] ([i915#15609]) +2 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-b-plane-0:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#15608]) +8 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-b-plane-0.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-b-plane-5:
    - shard-dg2:          NOTRUN -> [SKIP][155] ([i915#15609] / [i915#8825])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-modifier@pipe-b-plane-5:
    - shard-rkl:          NOTRUN -> [SKIP][156] ([i915#15608] / [i915#8825]) +3 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_plane@pixel-format-4-tiled-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-modifier@pipe-b-plane-7:
    - shard-tglu-1:       NOTRUN -> [SKIP][157] ([i915#15608] / [i915#8825]) +5 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-modifier@pipe-b-plane-7.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#15608] / [i915#15609] / [i915#8825]) +1 other test skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping@pipe-a-plane-0:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#15608]) +17 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping@pipe-a-plane-0.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping@pipe-b-plane-5:
    - shard-rkl:          NOTRUN -> [SKIP][160] ([i915#15609] / [i915#8825]) +1 other test skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier-source-clamping:
    - shard-tglu:         NOTRUN -> [SKIP][161] ([i915#15608] / [i915#15609] / [i915#8825])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier-source-clamping@pipe-a-plane-3:
    - shard-tglu:         NOTRUN -> [SKIP][162] ([i915#15608]) +5 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier-source-clamping@pipe-a-plane-3.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier-source-clamping@pipe-b-plane-7:
    - shard-tglu:         NOTRUN -> [SKIP][163] ([i915#15609] / [i915#8825])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier-source-clamping@pipe-b-plane-7.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier@pipe-a-plane-7:
    - shard-tglu-1:       NOTRUN -> [SKIP][164] ([i915#15608]) +20 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier@pipe-a-plane-7.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping@pipe-a-plane-5:
    - shard-rkl:          NOTRUN -> [SKIP][165] ([i915#15609]) +3 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier-source-clamping@pipe-b-plane-7:
    - shard-tglu:         NOTRUN -> [SKIP][166] ([i915#15609]) +2 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier-source-clamping@pipe-b-plane-7.html

  * igt@kms_plane_lowres@tiling-x:
    - shard-mtlp:         NOTRUN -> [SKIP][167] ([i915#11614] / [i915#3582]) +1 other test skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@kms_plane_lowres@tiling-x.html

  * igt@kms_plane_lowres@tiling-x@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][168] ([i915#10226] / [i915#11614] / [i915#3582]) +2 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@kms_plane_lowres@tiling-x@pipe-c-edp-1.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-tglu-1:       NOTRUN -> [SKIP][169] ([i915#13958])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-tglu:         NOTRUN -> [SKIP][170] ([i915#13958])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#14259]) +1 other test skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][172] ([i915#15329]) +4 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-c.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-tglu:         NOTRUN -> [SKIP][173] ([i915#9812])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade:
    - shard-rkl:          NOTRUN -> [SKIP][174] ([i915#5354])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][175] ([i915#9812])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#9685])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][177] ([i915#4281])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([i915#15073])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-rkl:          [PASS][179] -> [SKIP][180] ([i915#15073])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-3/igt@kms_pm_rpm@dpms-non-lpsp.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_pm_rpm@dpms-non-lpsp.html
    - shard-dg1:          [PASS][181] -> [SKIP][182] ([i915#15073]) +1 other test skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg1-18/igt@kms_pm_rpm@dpms-non-lpsp.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg1-14/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-tglu-1:       NOTRUN -> [SKIP][183] ([i915#15073])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@package-g7:
    - shard-rkl:          NOTRUN -> [SKIP][184] ([i915#15403])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_pm_rpm@package-g7.html

  * igt@kms_pm_rpm@system-suspend-idle:
    - shard-rkl:          [PASS][185] -> [INCOMPLETE][186] ([i915#14419])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_pm_rpm@system-suspend-idle.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_pm_rpm@system-suspend-idle.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-rkl:          NOTRUN -> [SKIP][187] ([i915#6524])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_prime@basic-crc-hybrid.html
    - shard-tglu-1:       NOTRUN -> [SKIP][188] ([i915#6524])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][189] ([i915#11520]) +3 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
    - shard-tglu:         NOTRUN -> [SKIP][190] ([i915#11520]) +3 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][191] ([i915#11520]) +6 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-dg2:          NOTRUN -> [SKIP][192] ([i915#11520]) +1 other test skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][193] ([i915#11520]) +4 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk3/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf:
    - shard-glk10:        NOTRUN -> [SKIP][194] ([i915#11520]) +3 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk10/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-psr-basic:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([i915#1072] / [i915#9732]) +6 other tests skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_psr@fbc-psr-basic.html

  * igt@kms_psr@pr-sprite-plane-onoff:
    - shard-tglu:         NOTRUN -> [SKIP][196] ([i915#9732]) +9 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_psr@pr-sprite-plane-onoff.html

  * igt@kms_psr@psr-cursor-mmap-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][197] ([i915#1072] / [i915#9732]) +14 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_psr@psr-cursor-mmap-cpu.html
    - shard-tglu-1:       NOTRUN -> [SKIP][198] ([i915#9732]) +9 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_psr@psr-cursor-mmap-cpu.html

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][199] ([i915#15492])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk10/igt@kms_rotation_crc@multiplane-rotation.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-rkl:          NOTRUN -> [SKIP][200] ([i915#5289])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][201] ([i915#5289]) +1 other test skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-dg2:          NOTRUN -> [SKIP][202] ([i915#12755])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-tglu:         NOTRUN -> [SKIP][203] ([i915#3555]) +3 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-rkl:          NOTRUN -> [ABORT][204] ([i915#13179]) +1 other test abort
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-dg2:          NOTRUN -> [SKIP][205] ([i915#3555]) +3 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-tglu-1:       NOTRUN -> [SKIP][206] ([i915#3555])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-1/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-tglu:         NOTRUN -> [SKIP][207] ([i915#8623])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@flip-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][208] ([i915#15243] / [i915#3555])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-tglu:         NOTRUN -> [SKIP][209] ([i915#9906])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-7/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-rkl:          NOTRUN -> [SKIP][210] ([i915#9906]) +1 other test skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@perf@non-zero-reason@0-rcs0:
    - shard-dg2:          NOTRUN -> [FAIL][211] ([i915#9100]) +1 other test fail
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html

  * igt@perf_pmu@module-unload:
    - shard-rkl:          NOTRUN -> [FAIL][212] ([i915#14433])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-rkl:          NOTRUN -> [SKIP][213] ([i915#8516])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_udl:
    - shard-dg2:          NOTRUN -> [SKIP][214] +2 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@prime_udl.html

  * igt@prime_vgem@basic-write:
    - shard-rkl:          NOTRUN -> [SKIP][215] ([i915#3291] / [i915#3708])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-8/igt@prime_vgem@basic-write.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-dg2:          NOTRUN -> [SKIP][216] ([i915#9917])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@sriov_basic@enable-vfs-autoprobe-off.html

  
#### Possible fixes ####

  * igt@gem_eio@throttle:
    - shard-dg1:          [DMESG-WARN][217] ([i915#4423]) -> [PASS][218] +4 other tests pass
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg1-13/igt@gem_eio@throttle.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg1-12/igt@gem_eio@throttle.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [INCOMPLETE][219] ([i915#13356] / [i915#13820]) -> [PASS][220] +1 other test pass
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg2-4/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@i915_selftest@live:
    - shard-mtlp:         [DMESG-FAIL][221] ([i915#12061] / [i915#15560]) -> [PASS][222]
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-mtlp-5/igt@i915_selftest@live.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - shard-mtlp:         [DMESG-FAIL][223] ([i915#12061]) -> [PASS][224]
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-mtlp-5/igt@i915_selftest@live@workarounds.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@i915_selftest@live@workarounds.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3:
    - shard-dg2:          [FAIL][225] ([i915#5956]) -> [PASS][226] +1 other test pass
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg2-1/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-7/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [FAIL][227] ([i915#15588] / [i915#2346]) -> [PASS][228]
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-rkl:          [INCOMPLETE][229] ([i915#6113]) -> [PASS][230]
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_flip@flip-vs-suspend.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-dg2:          [SKIP][231] ([i915#3555] / [i915#8228]) -> [PASS][232]
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg2-6/igt@kms_hdr@static-toggle-dpms.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-dg2:          [SKIP][233] ([i915#15073]) -> [PASS][234] +1 other test pass
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  
#### Warnings ####

  * igt@gem_bad_reloc@negative-reloc-lut:
    - shard-rkl:          [SKIP][235] ([i915#14544] / [i915#3281]) -> [SKIP][236] ([i915#3281]) +1 other test skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@gem_bad_reloc@negative-reloc-lut.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@gem_bad_reloc@negative-reloc-lut.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-rkl:          [SKIP][237] ([i915#14544] / [i915#4525]) -> [SKIP][238] ([i915#4525])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@gem_exec_balancer@parallel-keep-in-fence.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_reloc@basic-write-wc-noreloc:
    - shard-rkl:          [SKIP][239] ([i915#3281]) -> [SKIP][240] ([i915#14544] / [i915#3281]) +4 other tests skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@gem_exec_reloc@basic-write-wc-noreloc.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@gem_exec_reloc@basic-write-wc-noreloc.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-rkl:          [SKIP][241] ([i915#14544] / [i915#4613]) -> [SKIP][242] ([i915#4613])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@gem_lmem_swapping@heavy-random.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@massive-random:
    - shard-rkl:          [SKIP][243] ([i915#4613]) -> [SKIP][244] ([i915#14544] / [i915#4613])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@gem_lmem_swapping@massive-random.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@gem_lmem_swapping@massive-random.html

  * igt@gem_partial_pwrite_pread@reads-snoop:
    - shard-rkl:          [SKIP][245] ([i915#14544] / [i915#3282]) -> [SKIP][246] ([i915#3282])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@gem_partial_pwrite_pread@reads-snoop.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@gem_partial_pwrite_pread@reads-snoop.html

  * igt@gen7_exec_parse@basic-allocation:
    - shard-rkl:          [SKIP][247] ([i915#14544]) -> [SKIP][248]
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@gen7_exec_parse@basic-allocation.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@gen7_exec_parse@basic-allocation.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-rkl:          [SKIP][249] ([i915#14544] / [i915#2527]) -> [SKIP][250] ([i915#2527])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@gen9_exec_parse@allowed-all.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-rkl:          [SKIP][251] ([i915#2527]) -> [SKIP][252] ([i915#14544] / [i915#2527])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@gen9_exec_parse@bb-start-far.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@gen9_exec_parse@bb-start-far.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-rkl:          [SKIP][253] ([i915#5286]) -> [SKIP][254] ([i915#14544] / [i915#5286]) +1 other test skip
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-rkl:          [SKIP][255] ([i915#14544] / [i915#3638]) -> [SKIP][256] ([i915#3638]) +1 other test skip
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][257] ([i915#6095]) -> [SKIP][258] ([i915#14544] / [i915#6095]) +9 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][259] ([i915#14098] / [i915#6095]) -> [SKIP][260] ([i915#14098] / [i915#14544] / [i915#6095]) +9 other tests skip
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-2.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][261] ([i915#12313] / [i915#14544]) -> [SKIP][262] ([i915#12313])
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][263] ([i915#14544] / [i915#6095]) -> [SKIP][264] ([i915#6095]) +1 other test skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-3/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][265] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][266] ([i915#14098] / [i915#6095]) +2 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-3/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-rkl:          [SKIP][267] ([i915#11151] / [i915#7828]) -> [SKIP][268] ([i915#11151] / [i915#14544] / [i915#7828]) +1 other test skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_chamelium_audio@dp-audio.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-rkl:          [SKIP][269] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][270] ([i915#11151] / [i915#7828])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_chamelium_hpd@hdmi-hpd.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-dg2:          [FAIL][271] ([i915#7173]) -> [SKIP][272] ([i915#6944])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg2-11/igt@kms_content_protection@atomic-hdcp14.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-1/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          [SKIP][273] ([i915#6944] / [i915#9424]) -> [SKIP][274] ([i915#14544] / [i915#6944] / [i915#9424])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_content_protection@mei-interface.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          [SKIP][275] ([i915#6944] / [i915#7118] / [i915#9424]) -> [SKIP][276] ([i915#6944] / [i915#7118] / [i915#7162] / [i915#9424])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg2-6/igt@kms_content_protection@type1.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-rkl:          [SKIP][277] ([i915#3555]) -> [SKIP][278] ([i915#14544] / [i915#3555])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_cursor_crc@cursor-offscreen-32x10.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x32:
    - shard-dg1:          [SKIP][279] ([i915#3555] / [i915#4423]) -> [SKIP][280] ([i915#3555])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg1-13/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg1-12/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-rkl:          [SKIP][281] -> [SKIP][282] ([i915#14544]) +6 other tests skip
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-dg1:          [SKIP][283] -> [SKIP][284] ([i915#4423])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg1-14/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg1-16/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-rkl:          [SKIP][285] ([i915#13749]) -> [SKIP][286] ([i915#13749] / [i915#14544])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_dp_link_training@non-uhbr-mst.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_feature_discovery@display-3x:
    - shard-rkl:          [SKIP][287] ([i915#1839]) -> [SKIP][288] ([i915#14544] / [i915#1839])
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_feature_discovery@display-3x.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-rkl:          [SKIP][289] ([i915#9934]) -> [SKIP][290] ([i915#14544] / [i915#9934]) +1 other test skip
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-rkl:          [SKIP][291] ([i915#14544] / [i915#9934]) -> [SKIP][292] ([i915#9934])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-glk:          [INCOMPLETE][293] ([i915#12314] / [i915#12745] / [i915#4839] / [i915#6113]) -> [INCOMPLETE][294] ([i915#12745] / [i915#4839])
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-glk5/igt@kms_flip@flip-vs-suspend.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@a-hdmi-a1:
    - shard-glk:          [INCOMPLETE][295] ([i915#12314] / [i915#12745] / [i915#6113]) -> [INCOMPLETE][296] ([i915#12745])
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-glk5/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-glk6/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-dg2:          [SKIP][297] -> [SKIP][298] ([i915#15643]) +13 other tests skip
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
    - shard-rkl:          [SKIP][299] ([i915#14544]) -> [SKIP][300] ([i915#14544] / [i915#15643]) +1 other test skip
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x:
    - shard-rkl:          [SKIP][301] ([i915#15645]) -> [SKIP][302] ([i915#14544] / [i915#15645])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-dg1:          [SKIP][303] -> [SKIP][304] ([i915#15643]) +21 other tests skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg1-12/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-tglu:         [SKIP][305] -> [SKIP][306] ([i915#15643]) +13 other tests skip
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-tglu-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
    - shard-rkl:          [SKIP][307] -> [SKIP][308] ([i915#14544] / [i915#15643])
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-rkl:          [SKIP][309] ([i915#14544]) -> [SKIP][310] ([i915#15643]) +1 other test skip
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-rkl:          [SKIP][311] -> [SKIP][312] ([i915#15643]) +7 other tests skip
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2:          [SKIP][313] ([i915#5190]) -> [SKIP][314] ([i915#15643] / [i915#5190]) +9 other tests skip
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg2-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-11/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-mtlp:         [SKIP][315] -> [SKIP][316] ([i915#15643]) +26 other tests skip
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
    - shard-rkl:          [SKIP][317] ([i915#14544] / [i915#1825]) -> [SKIP][318] ([i915#1825]) +4 other tests skip
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg1:          [SKIP][319] ([i915#4423]) -> [SKIP][320] +2 other tests skip
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-dg2:          [SKIP][321] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][322] ([i915#15102] / [i915#3458]) +1 other test skip
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][323] ([i915#1825]) -> [SKIP][324] ([i915#14544] / [i915#1825]) +9 other tests skip
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
    - shard-rkl:          [SKIP][325] ([i915#15574]) -> [SKIP][326] ([i915#14544] / [i915#15574])
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
    - shard-rkl:          [SKIP][327] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][328] ([i915#15102] / [i915#3023]) +2 other tests skip
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
    - shard-dg2:          [SKIP][329] ([i915#15102] / [i915#3458]) -> [SKIP][330] ([i915#10433] / [i915#15102] / [i915#3458]) +2 other tests skip
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][331] ([i915#15102]) -> [SKIP][332] ([i915#14544] / [i915#15102])
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-wc.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-pwrite:
    - shard-rkl:          [SKIP][333] ([i915#14544] / [i915#15102]) -> [SKIP][334] ([i915#15102])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-pwrite.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-rkl:          [SKIP][335] ([i915#15102] / [i915#3023]) -> [SKIP][336] ([i915#14544] / [i915#15102] / [i915#3023]) +3 other tests skip
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-suspend.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-rkl:          [SKIP][337] ([i915#13958]) -> [SKIP][338] ([i915#13958] / [i915#14544])
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_plane_multiple@2x-tiling-none.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-rkl:          [SKIP][339] ([i915#5354]) -> [SKIP][340] ([i915#14544] / [i915#5354])
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_pm_backlight@bad-brightness.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          [SKIP][341] ([i915#14544] / [i915#6524]) -> [SKIP][342] ([i915#6524])
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_prime@basic-modeset-hybrid.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-3/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area:
    - shard-rkl:          [SKIP][343] ([i915#11520]) -> [SKIP][344] ([i915#11520] / [i915#14544]) +1 other test skip
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-rkl:          [SKIP][345] ([i915#11520] / [i915#14544]) -> [SKIP][346] ([i915#11520])
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-rkl:          [SKIP][347] ([i915#9683]) -> [SKIP][348] ([i915#14544] / [i915#9683])
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_psr2_su@page_flip-nv12.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@psr2-basic:
    - shard-rkl:          [SKIP][349] ([i915#1072] / [i915#9732]) -> [SKIP][350] ([i915#1072] / [i915#14544] / [i915#9732]) +4 other tests skip
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_psr@psr2-basic.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_psr@psr2-basic.html

  * igt@kms_psr@psr2-primary-mmap-gtt:
    - shard-rkl:          [SKIP][351] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][352] ([i915#1072] / [i915#9732]) +2 other tests skip
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-6/igt@kms_psr@psr2-primary-mmap-gtt.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-5/igt@kms_psr@psr2-primary-mmap-gtt.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-rkl:          [SKIP][353] ([i915#5289]) -> [SKIP][354] ([i915#14544] / [i915#5289])
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_vrr@lobf:
    - shard-rkl:          [SKIP][355] ([i915#11920]) -> [SKIP][356] ([i915#11920] / [i915#14544])
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@kms_vrr@lobf.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@kms_vrr@lobf.html

  * igt@prime_vgem@fence-write-hang:
    - shard-rkl:          [SKIP][357] ([i915#3708]) -> [SKIP][358] ([i915#14544] / [i915#3708])
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@prime_vgem@fence-write-hang.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-rkl:          [SKIP][359] ([i915#9917]) -> [SKIP][360] ([i915#14544] / [i915#9917])
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17921/shard-rkl-4/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/shard-rkl-6/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10226]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10226
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11614]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11614
  [i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13790
  [i915#13820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13820
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
  [i915#14123]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14123
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14419]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14419
  [i915#14433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14433
  [i915#14498]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14498
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15095
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15403]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15403
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
  [i915#15492]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15492
  [i915#15560]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15560
  [i915#15574]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15574
  [i915#15588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15588
  [i915#15608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15608
  [i915#15609]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15609
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15645]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15645
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2065]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2065
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3582
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#5107]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5107
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7162
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8825
  [i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
  [i915#9979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9979


Build changes
-------------

  * Linux: CI_DRM_17921 -> Patchwork_161036v1

  CI-20190529: 20190529
  CI_DRM_17921: 67c3b61c4451b33dbf846f97cb2389b7fb6db09d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8729: 8729
  Patchwork_161036v1: 67c3b61c4451b33dbf846f97cb2389b7fb6db09d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161036v1/index.html

[-- Attachment #2: Type: text/html, Size: 129462 bytes --]

RE: [PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering

[Bhadane, Dnyaneshwar]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Gustavo
> Sousa
> Sent: Tuesday, February 3, 2026 3:13 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sousa, Gustavo <gustavo.sousa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe3p_LPG has nearly identical steering to Xe2 and Xe3.  The only DSS/XeCore
> change from those IPs is an additional range from 0xDE00-0xDE7F that was
> previously reserved, so we can simply grow one of the existing ranges in the Xe2
> table to include it.  Similarly, the "instance0" table is also almost identical, but
> gains one additional PSMI range and requires a separate table.
> 
> Bspec: 75242
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_gt_mcr.c | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index 7c1fe9ac120d..b112e551fc79 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -201,7 +201,7 @@ static const struct xe_mmio_range
> xe2lpg_dss_steering_table[] = {
>  	{ 0x009680, 0x0096FF },         /* DSS */
>  	{ 0x00D800, 0x00D87F },         /* SLICE */
>  	{ 0x00DC00, 0x00DCFF },         /* SLICE */
> -	{ 0x00DE80, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
> +	{ 0x00DE00, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
>  	{ 0x00E980, 0x00E9FF },         /* SLICE */
>  	{ 0x013000, 0x0133FF },         /* DSS (0x13000-0x131FF), SLICE (0x13200-
> 0x133FF) */
>  	{},
> @@ -280,6 +280,19 @@ static const struct xe_mmio_range
> xe3p_xpc_instance0_steering_table[] = {
>  	{},
>  };
> 
> +static const struct xe_mmio_range xe3p_lpg_instance0_steering_table[] = {
> +	{ 0x004000, 0x004AFF },         /* GAM, rsvd, GAMWKR */
> +	{ 0x008700, 0x00887F },         /* NODE */
> +	{ 0x00B000, 0x00B3FF },         /* NODE, L3BANK */
> +	{ 0x00B500, 0x00B6FF },		/* PSMI */
Hi,
Could we extend the range till 0x00BEFF ?
> +	{ 0x00C800, 0x00CFFF },         /* GAM */
> +	{ 0x00D880, 0x00D8FF },         /* NODE */
> +	{ 0x00DD00, 0x00DDFF },         /* MEMPIPE */
Same as we did here extend till reserved.

Dnyaneshwar, 

> +	{ 0x00F000, 0x00FFFF },         /* GAM, GAMWKR */
> +	{ 0x013400, 0x0135FF },         /* MEMPIPE */
> +	{},
> +};
> +
>  static void init_steering_l3bank(struct xe_gt *gt)  {
>  	struct xe_device *xe = gt_to_xe(gt);
> @@ -533,6 +546,9 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
>  			gt->steering[INSTANCE0].ranges =
> xe3p_xpc_instance0_steering_table;
>  			gt->steering[L3BANK].ranges =
> xelpg_l3bank_steering_table;
>  			gt->steering[NODE].ranges =
> xe3p_xpc_node_steering_table;
> +		} else if (GRAPHICS_VERx100(xe) >= 3510) {
> +			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
> +			gt->steering[INSTANCE0].ranges =
> xe3p_lpg_instance0_steering_table;
>  		} else if (GRAPHICS_VER(xe) >= 20) {
>  			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
>  			gt->steering[SQIDI_PSMI].ranges =
> xe2lpg_sqidi_psmi_steering_table;
> 
> --
> 2.52.0

Re: [PATCH 01/16] drm/xe/xe3p_lpg: Add support for graphics IP 35.10

[Gustavo Sousa]

Matt Roper <matthew.d.roper@intel.com> writes:

> On Mon, Feb 02, 2026 at 02:11:04PM -0800, Matt Roper wrote:
>> On Mon, Feb 02, 2026 at 06:43:07PM -0300, Gustavo Sousa wrote:
>> > From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>> > 
>> > Add graphics IP versions 35.10. Since there will be features enabled
>> > that are not present in graphics_xe2, already create a new
>> > graphics_xe3p, although currently it only enables the same features as
>> > graphics_xe2.
>> > 
>> > Here is a list of fields, associated Bspec references and eventual
>> > comments:
>> > 
>> >  .va_bits (Bspec 74198)
>> >  .vm_max_level (Bspec 59507)
>> >     The spec says "The PPGTT is always a 5-level structure even when the
>> >     virtual address space is less than 57 bits."
>> >  .vram_flags
>> >    - ~XE_VRAM_FLAGS_NEED64K
>> >      That limitation that does not exist for Xe3p_LPG.
>> 
>> These three aren't part of the graphics descriptor anymore, so they're
>> not relevant to this patch.
>> 
>> >  .hw_engine_mask (Bspec 60149)
>> >  .tile_gsm_size (Bspec 52961)
>> >     This is queried directly from the hardware.
>> 
>> I don't think this flag has ever existed, outside of some temporary
>> development patches that never moved forward.
>> 
>> >  .has_asid (Bspec 71132)
>> >  .has_atomic_enable_pte_bit (Bspec 59510, 74675)
>> >  .has_flat_ccs (Bspec 65255)
>> 
>> This one also isn't part of the graphics descriptor anymore.
>> 
>> >  .has_indirect_ring_state (Bspec 67296)
>> >  .has_range_tlb_inval (Bspec 71126)
>> >  .has_usm (Bspec 59651)
>> > 
>> 
>> We should probably add a reference for has_64bit_timestamp (bspec 60318)
>> since it's set in XE2_GFX_FEATURES.
>> 
>> Is there any reason not to go ahead and squash in
>> multi_queue_engine_class_mask from patch #12 here?
>> 
>> 
>> Matt
>> 
>> > Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> > ---
>> >  drivers/gpu/drm/xe/xe_pci.c | 5 +++++
>> >  1 file changed, 5 insertions(+)
>> > 
>> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> > index b5e8935fff1d..edca562462fa 100644
>> > --- a/drivers/gpu/drm/xe/xe_pci.c
>> > +++ b/drivers/gpu/drm/xe/xe_pci.c
>> > @@ -106,6 +106,10 @@ static const struct xe_graphics_desc graphics_xe2 = {
>> >  	XE2_GFX_FEATURES,
>> >  };
>> >  
>> > +static const struct xe_graphics_desc graphics_xe3p = {
>
> One more comment: we may want to name this "graphics_xe3p_lpg" to help
> distinguish it from graphics_xe3p_xpc below.

Incorporated all of the suggestions and they will be present in v2.

Thanks!

>
>
> Matt
>
>> > +	XE2_GFX_FEATURES,
>> > +};
>> > +
>> >  static const struct xe_graphics_desc graphics_xe3p_xpc = {
>> >  	XE2_GFX_FEATURES,
>> >  	.has_indirect_ring_state = 1,
>> > @@ -148,6 +152,7 @@ static const struct xe_ip graphics_ips[] = {
>> >  	{ 3003, "Xe3_LPG", &graphics_xe2 },
>> >  	{ 3004, "Xe3_LPG", &graphics_xe2 },
>> >  	{ 3005, "Xe3_LPG", &graphics_xe2 },
>> > +	{ 3510, "Xe3p_LPG", &graphics_xe3p },
>> >  	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
>> >  };
>> >  
>> > 
>> > -- 
>> > 2.52.0
>> > 
>> 
>> -- 
>> Matt Roper
>> Graphics Software Engineer
>> Linux GPU Platform Enablement
>> Intel Corporation
>
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

Re: [PATCH 02/16] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10

[Gustavo Sousa]

Matt Roper <matthew.d.roper@intel.com> writes:

> On Mon, Feb 02, 2026 at 06:43:08PM -0300, Gustavo Sousa wrote:
>> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>> 
>> Add the initial set of workarounds for Xe3p_LPG graphics version 35.10.
>> 
>> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>> Co-developed-by: Nitin Gote <nitin.r.gote@intel.com>
>> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
>> Co-developed-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
>> Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
>> Co-developed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
>> Signed-off-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
>> Co-developed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/xe/regs/xe_gt_regs.h  | 19 ++++++++++++++
>>  drivers/gpu/drm/xe/xe_reg_whitelist.c |  8 ++++++
>>  drivers/gpu/drm/xe/xe_wa.c            | 48 +++++++++++++++++++++++++++++++++++
>>  3 files changed, 75 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 24fc64fc832e..b5a7cc45f13d 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -100,6 +100,9 @@
>>  #define VE1_AUX_INV				XE_REG(0x42b8)
>>  #define   AUX_INV				REG_BIT(0)
>>  
>> +#define GAMSTLB_CTRL2				XE_REG_MCR(0x4788)
>> +#define   STLB_SINGLE_BANK_MODE			REG_BIT(11)
>> +
>>  #define XE2_LMEM_CFG				XE_REG(0x48b0)
>>  
>>  #define XE2_GAMWALK_CTRL			0x47e4
>> @@ -107,12 +110,18 @@
>>  #define XE2_GAMWALK_CTRL_3D			XE_REG_MCR(XE2_GAMWALK_CTRL)
>>  #define   EN_CMP_1WCOH_GW			REG_BIT(14)
>>  
>> +#define MMIOATSREQLIMIT_GAM_WALK_3D             XE_REG_MCR(0x47f8)
>> +#define   DIS_ATS_WRONLY_PG                     REG_BIT(18)
>> +
>>  #define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)
>>  #define XEHP_FLAT_CCS_PTR			REG_GENMASK(31, 8)
>>  
>>  #define WM_CHICKEN3				XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
>>  #define   HIZ_PLANE_COMPRESSION_DIS		REG_BIT(10)
>>  
>> +#define TBIMR_MODE				XE_REG_MCR(0x6200, XE_REG_OPTION_MASKED)
>> +#define   RXBAR_NO_UAV_DEC_SYNC			REG_BIT(12)
>> +
>>  #define CHICKEN_RASTER_1			XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
>>  #define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
>>  #define   DIS_CLIP_NEGATIVE_BOUNDING_BOX	REG_BIT(6)
>> @@ -210,6 +219,9 @@
>>  
>>  #define GSCPSMI_BASE				XE_REG(0x880c)
>>  
>> +#define CCCHKNREG2				XE_REG_MCR(0x881c)
>> +#define  LOCALITYDIS				REG_BIT(7)
>
> Nitpick: the formatting is slightly off here (the field name should be
> spaced over one more column).
>
>> +
>>  #define CCCHKNREG1				XE_REG_MCR(0x8828)
>>  #define   L3CMPCTRL				REG_BIT(23)
>>  #define   ENCOMPPERFFIX				REG_BIT(18)
>> @@ -420,6 +432,8 @@
>>  #define   LSN_DIM_Z_WGT(value)			REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
>>  
>>  #define L3SQCREG2				XE_REG_MCR(0xb104)
>> +#define   L3_SQ_DISABLE_COAMA_2WAY_COH		REG_BIT(30)
>> +#define   L3_SQ_DISABLE_COAMA			REG_BIT(22)
>>  #define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)
>>  
>>  #define L3SQCREG3				XE_REG_MCR(0xb108)
>> @@ -550,11 +564,16 @@
>>  #define   UGM_FRAGMENT_THRESHOLD_TO_3		REG_BIT(58 - 32)
>>  #define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)
>>  #define   XE2_ALLOC_DPA_STARVE_FIX_DIS		REG_BIT(47 - 32)
>> +#define   SAMPLER_LD_LSC_DISABLE                REG_BIT(45 - 32)
>>  #define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL	REG_BIT(44 - 32)
>>  #define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)
>>  #define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)
>>  #define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)
>>  #define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
>> +#define   LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE	REG_BIT(35 - 32)
>> +
>> +#define ROW_CHICKEN5				XE_REG_MCR(0xe7f0)
>> +#define   CPSS_AWARE_DIS			REG_BIT(3)
>>  
>>  #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
>>  #define   COMP_CKN_IN				REG_GENMASK(30, 29)
>> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> index 1d36c09681aa..9c513778d370 100644
>> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> @@ -81,6 +81,14 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
>>  			 WHITELIST(VFLSKPD,
>>  				   RING_FORCE_TO_NONPRIV_ACCESS_RW))
>>  	},
>> +	{ XE_RTP_NAME("14024997852"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
>> +		       ENGINE_CLASS(RENDER)),
>> +	  XE_RTP_ACTIONS(WHITELIST(FF_MODE,
>> +				   RING_FORCE_TO_NONPRIV_ACCESS_RW),
>> +			 WHITELIST(VFLSKPD,
>> +				   RING_FORCE_TO_NONPRIV_ACCESS_RW))
>> +	},
>>  
>>  #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
>>  	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
>> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>> index a991ee2b8781..68a494743b34 100644
>> --- a/drivers/gpu/drm/xe/xe_wa.c
>> +++ b/drivers/gpu/drm/xe/xe_wa.c
>> @@ -306,6 +306,31 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)),
>>  	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
>>  	},
>> +
>> +	/* Xe3P_LPG */
>> +
>> +	{ XE_RTP_NAME("14025160223"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>> +	  XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,
>> +			     DIS_ATS_WRONLY_PG))
>> +	},
>> +	{ XE_RTP_NAME("16028780921"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>> +	  XE_RTP_ACTIONS(SET(CCCHKNREG2, LOCALITYDIS))
>> +	},
>> +	{ XE_RTP_NAME("14026144927"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>> +	  XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |
>> +			     L3_SQ_DISABLE_COAMA))
>> +	},
>> +	{ XE_RTP_NAME("14025635424"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>> +	  XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE))
>> +	},
>> +	{ XE_RTP_NAME("16028005424"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>> +	  XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
>> +	},
>>  };
>>  
>>  static const struct xe_rtp_entry_sr engine_was[] = {
>> @@ -680,6 +705,24 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>>  		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
>>  	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
>>  	},
>> +
>> +	/* Xe3p_LPG*/
>> +
>> +	{ XE_RTP_NAME("22021149932"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
>> +		       FUNC(xe_rtp_match_first_render_or_compute)),
>> +	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))
>> +	},
>> +	{ XE_RTP_NAME("14025676848"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
>> +		       FUNC(xe_rtp_match_first_render_or_compute)),
>> +	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))
>> +	},
>> +	{ XE_RTP_NAME("16028951944"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
>> +		       FUNC(xe_rtp_match_first_render_or_compute)),
>> +	  XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
>> +	},
>>  };
>>  
>>  static const struct xe_rtp_entry_sr lrc_was[] = {
>> @@ -879,6 +922,11 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>>  		       ENGINE_CLASS(RENDER)),
>>  	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
>>  	},
>> +	{ XE_RTP_NAME("14025780377"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
>> +		       ENGINE_CLASS(RENDER)),
>> +	  XE_RTP_ACTIONS(SET(TBIMR_MODE, RXBAR_NO_UAV_DEC_SYNC))
>
> I'm not sure if this one is actually needed.  Originally the workaround
> ticket just said "program 0x6200[12]" but it's since been updated to an
> "if (por) no workaround needed, else if (non-POR thing) program the
> register and add a stalling flush."  There are also comments in the
> ticket itself that indicate it shouldn't actually be relevant to this
> specific platform due to other characteristics of the platform; it's
> just something that they'll need to fix or workaround in the future so
> that it doesn't impact future derivative platforms.

Incorporated feedback and they will be in v2 of this series.

Thanks!

Gustavo Sousa

>
>
> Matt
>
>> +	},
>>  };
>>  
>>  static __maybe_unused const struct xe_rtp_entry oob_was[] = {
>> 
>> -- 
>> 2.52.0
>> 
>
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

RE: [PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering

[Gustavo Sousa]

"Bhadane, Dnyaneshwar" <dnyaneshwar.bhadane@intel.com> writes:

>> -----Original Message-----
>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Gustavo
>> Sousa
>> Sent: Tuesday, February 3, 2026 3:13 AM
>> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> Cc: Sousa, Gustavo <gustavo.sousa@intel.com>; Roper, Matthew D
>> <matthew.d.roper@intel.com>
>> Subject: [PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering
>> 
>> From: Matt Roper <matthew.d.roper@intel.com>
>> 
>> Xe3p_LPG has nearly identical steering to Xe2 and Xe3.  The only DSS/XeCore
>> change from those IPs is an additional range from 0xDE00-0xDE7F that was
>> previously reserved, so we can simply grow one of the existing ranges in the Xe2
>> table to include it.  Similarly, the "instance0" table is also almost identical, but
>> gains one additional PSMI range and requires a separate table.
>> 
>> Bspec: 75242
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_gt_mcr.c | 18 +++++++++++++++++-
>>  1 file changed, 17 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>> index 7c1fe9ac120d..b112e551fc79 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>> @@ -201,7 +201,7 @@ static const struct xe_mmio_range
>> xe2lpg_dss_steering_table[] = {
>>  	{ 0x009680, 0x0096FF },         /* DSS */
>>  	{ 0x00D800, 0x00D87F },         /* SLICE */
>>  	{ 0x00DC00, 0x00DCFF },         /* SLICE */
>> -	{ 0x00DE80, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
>> +	{ 0x00DE00, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
>>  	{ 0x00E980, 0x00E9FF },         /* SLICE */
>>  	{ 0x013000, 0x0133FF },         /* DSS (0x13000-0x131FF), SLICE (0x13200-
>> 0x133FF) */
>>  	{},
>> @@ -280,6 +280,19 @@ static const struct xe_mmio_range
>> xe3p_xpc_instance0_steering_table[] = {
>>  	{},
>>  };
>> 
>> +static const struct xe_mmio_range xe3p_lpg_instance0_steering_table[] = {
>> +	{ 0x004000, 0x004AFF },         /* GAM, rsvd, GAMWKR */
>> +	{ 0x008700, 0x00887F },         /* NODE */
>> +	{ 0x00B000, 0x00B3FF },         /* NODE, L3BANK */
>> +	{ 0x00B500, 0x00B6FF },		/* PSMI */
> Hi,
> Could we extend the range till 0x00BEFF ?
>> +	{ 0x00C800, 0x00CFFF },         /* GAM */
>> +	{ 0x00D880, 0x00D8FF },         /* NODE */
>> +	{ 0x00DD00, 0x00DDFF },         /* MEMPIPE */
> Same as we did here extend till reserved.

We usually only include a reserved range if the range is preceeded and
followed by MCR ranges of the same steering group.

This doesn't seem to be the case here.

--
Gustavo Sousa

RE: [PATCH 09/16] drm/xe/xe3p_lpg: Extend 'group ID' mask size

[Bhadane, Dnyaneshwar]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Gustavo
> Sousa
> Sent: Tuesday, February 3, 2026 3:13 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sousa, Gustavo <gustavo.sousa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH 09/16] drm/xe/xe3p_lpg: Extend 'group ID' mask size
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe3p_LPG extends the 'group ID' register mask by one bit.  Since the new upper
> bit (12) was unused on previous platforms, we can safely extend the existing mask
> size without worrying about adding conditional version checks to the register
> programming.
> 
> Bspec: 67175
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

LGTM,
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>


> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index b5a7cc45f13d..19f053a7f9be 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -58,7 +58,7 @@
>  #define   MCR_SLICE(slice)
> 	REG_FIELD_PREP(MCR_SLICE_MASK, slice)
>  #define   MCR_SUBSLICE_MASK			REG_GENMASK(26, 24)
>  #define   MCR_SUBSLICE(subslice)
> 	REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
> -#define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)
> +#define   MTL_MCR_GROUPID			REG_GENMASK(12, 8)
>  #define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)
> 
>  #define PS_INVOCATION_COUNT			XE_REG(0x2348)
> 
> --
> 2.52.0

Re: [PATCH 13/16] drm/xe/nvlp: Add NVL-P platform definition

[Gustavo Sousa]

Matt Roper <matthew.d.roper@intel.com> writes:

> On Mon, Feb 02, 2026 at 06:43:19PM -0300, Gustavo Sousa wrote:
>> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>> 
>> Add platform definition along with device IDs for NVL-P.
>
> Not sure if you wanted to add bspec references to this one like you had
> for the Xe3p_LPG descriptor, but the flags you have here look correct to
> me for now and the PCI IDs look correct so,
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Thanks!

I'll send v2 with the list of fields and Bspec references. I'm
copying/pasting them here as well, just in case you can spot any errors
before I post v2:

      .dma_mask_size (Bspec 74198)
      .has_cached_pt (Bspec 71582)
      .has_display (Bspec 74196)
      .has_flat_ccs (Bspec 65255)
      .has_page_reclaim_hw_assist (Bspec 73451)
      .max_gt_per_tile (Bspec 74196)
      .va_bits (Bspec 74198)
      .vm_max_level (Bspec 59507)

--
Gustavo Sousa

Re: [PATCH 13/16] drm/xe/nvlp: Add NVL-P platform definition

[Matt Roper]

On Wed, Feb 04, 2026 at 09:59:22AM -0300, Gustavo Sousa wrote:
> Matt Roper <matthew.d.roper@intel.com> writes:
> 
> > On Mon, Feb 02, 2026 at 06:43:19PM -0300, Gustavo Sousa wrote:
> >> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
> >> 
> >> Add platform definition along with device IDs for NVL-P.
> >
> > Not sure if you wanted to add bspec references to this one like you had
> > for the Xe3p_LPG descriptor, but the flags you have here look correct to
> > me for now and the PCI IDs look correct so,
> >
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> Thanks!
> 
> I'll send v2 with the list of fields and Bspec references. I'm
> copying/pasting them here as well, just in case you can spot any errors
> before I post v2:
> 
>       .dma_mask_size (Bspec 74198)

This matches the way we've justified this field on past platforms,
although we've discovered that the "physical address range" value on
that page doesn't necessarily directly translate to the dma_mask_size we
need to use in software; there are cases like ADL-S where it isn't an
exact match due to other characteristics of the base platform (MKTE and
such).  But that extra information isn't really available in the
graphics bspec, so I don't think we have any better reference that can
be given.

>       .has_cached_pt (Bspec 71582)
>       .has_display (Bspec 74196)
>       .has_flat_ccs (Bspec 65255)

Not sure if this is the best page for FlatCCS since it doesn't really
indicate that a platform does/doesn't support it (e.g., the page doesn't
drop out when the bspec is filtered to platforms like CRI that lack
compression).

A better reference might be 74110 since it has a yes/no on compression
support by platform.


Matt

>       .has_page_reclaim_hw_assist (Bspec 73451)
>       .max_gt_per_tile (Bspec 74196)
>       .va_bits (Bspec 74198)
>       .vm_max_level (Bspec 59507)
> 
> --
> Gustavo Sousa

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 13/16] drm/xe/nvlp: Add NVL-P platform definition

[Gustavo Sousa]

Matt Roper <matthew.d.roper@intel.com> writes:

> On Wed, Feb 04, 2026 at 09:59:22AM -0300, Gustavo Sousa wrote:
>> Matt Roper <matthew.d.roper@intel.com> writes:
>> 
>> > On Mon, Feb 02, 2026 at 06:43:19PM -0300, Gustavo Sousa wrote:
>> >> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>> >> 
>> >> Add platform definition along with device IDs for NVL-P.
>> >
>> > Not sure if you wanted to add bspec references to this one like you had
>> > for the Xe3p_LPG descriptor, but the flags you have here look correct to
>> > me for now and the PCI IDs look correct so,
>> >
>> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>> 
>> Thanks!
>> 
>> I'll send v2 with the list of fields and Bspec references. I'm
>> copying/pasting them here as well, just in case you can spot any errors
>> before I post v2:
>> 
>>       .dma_mask_size (Bspec 74198)
>
> This matches the way we've justified this field on past platforms,
> although we've discovered that the "physical address range" value on
> that page doesn't necessarily directly translate to the dma_mask_size we
> need to use in software; there are cases like ADL-S where it isn't an
> exact match due to other characteristics of the base platform (MKTE and
> such).  But that extra information isn't really available in the
> graphics bspec, so I don't think we have any better reference that can
> be given.
>
>>       .has_cached_pt (Bspec 71582)
>>       .has_display (Bspec 74196)
>>       .has_flat_ccs (Bspec 65255)
>
> Not sure if this is the best page for FlatCCS since it doesn't really
> indicate that a platform does/doesn't support it (e.g., the page doesn't
> drop out when the bspec is filtered to platforms like CRI that lack
> compression).
>
> A better reference might be 74110 since it has a yes/no on compression
> support by platform.

Updated. Thanks!

--
Gustavo Sousa

Re: [PATCH 04/16] drm/xe/xe3p_lpg: Add new PAT table

[Matt Atwood]

On Mon, Feb 02, 2026 at 06:43:10PM -0300, Gustavo Sousa wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> PAT programming for Xe3p_LPG is more similar to Xe2 and Xe3 than it is
> to Xe3p_XPC.  Compared to Xe2/Xe3 we have:
> 
> * There's a slight update to the PAT table, where two new indices (18
>   and 19) are added to expose a new "WB - Transient App" L3 caching
>   mode.
> 
> * The PTA_MODE entry must be programmed differently according to the
>   media type, and both differ from Xe2.
> 
> There are no changes to the underlying registers, so the Xe2 ops can be
> re-used for Xe3p.
> 
> Bspec: 71582, 74160
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pat.c | 55 ++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 54 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 5776ea67fe02..3ba89e80be1f 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -123,7 +123,8 @@ static const struct xe_pat_table_entry xelpg_pat_table[] = {
>   *   - no_promote:  0=promotable, 1=no promote
>   *   - comp_en:     0=disable, 1=enable
>   *   - l3clos:      L3 class of service (0-3)
> - *   - l3_policy:   0=WB, 1=XD ("WB - Transient Display"), 3=UC
> + *   - l3_policy:   0=WB, 1=XD ("WB - Transient Display"),
> + *                  2=XA ("WB - Transient App" for Xe3p), 3=UC
>   *   - l4_policy:   0=WB, 1=WT, 3=UC
>   *   - coh_mode:    0=no snoop, 2=1-way coherent, 3=2-way coherent
>   *
> @@ -252,6 +253,44 @@ static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
>  	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
>  };
>  
> +static const struct xe_pat_table_entry xe3p_primary_pat_pta = XE2_PAT(0, 0, 0, 0, 0, 3);
> +static const struct xe_pat_table_entry xe3p_media_pat_pta = XE2_PAT(0, 0, 0, 0, 0, 2);
> +
> +static const struct xe_pat_table_entry xe3p_lpg_pat_table[] = {
> +	[ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ),
> +	[ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ),
> +	[ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ),
> +	[ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ),
> +	[ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ),
> +	[ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ),
> +	[ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ),
> +	[ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ),
> +	[ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ),
> +	[ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ),
> +	[10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ),
> +	[11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ),
> +	[12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ),
> +	[13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ),
> +	[14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ),
> +	[15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ),
> +	[16] = XE2_PAT( 0, 1, 0, 0, 3, 2 ),
> +	/* 17 is reserved; leave set to all 0's */
> +	[18] = XE2_PAT( 1, 0, 0, 2, 3, 0 ),
> +	[19] = XE2_PAT( 1, 0, 0, 2, 3, 2 ),
> +	[20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ),
> +	[21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ),
> +	[22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ),
> +	[23] = XE2_PAT( 0, 0, 1, 0, 3, 3 ),
> +	[24] = XE2_PAT( 0, 0, 2, 0, 3, 0 ),
> +	[25] = XE2_PAT( 0, 1, 2, 0, 3, 0 ),
> +	[26] = XE2_PAT( 0, 0, 2, 0, 3, 2 ),
> +	[27] = XE2_PAT( 0, 0, 2, 0, 3, 3 ),
> +	[28] = XE2_PAT( 0, 0, 3, 0, 3, 0 ),
> +	[29] = XE2_PAT( 0, 1, 3, 0, 3, 0 ),
> +	[30] = XE2_PAT( 0, 0, 3, 0, 3, 2 ),
> +	[31] = XE2_PAT( 0, 0, 3, 0, 3, 3 ),
> +};
> +
>  u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
>  {
>  	WARN_ON(pat_index >= xe->pat.n_entries);
> @@ -537,6 +576,20 @@ void xe_pat_init_early(struct xe_device *xe)
>  		xe->pat.idx[XE_CACHE_NONE] = 3;
>  		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
>  		xe->pat.idx[XE_CACHE_WB] = 2;
> +	} else if (GRAPHICS_VER(xe) == 35) {
> +		xe->pat.ops = &xe2_pat_ops;
> +		xe->pat.table = xe3p_lpg_pat_table;
> +		xe->pat.pat_ats = &xe2_pat_ats;
> +		if (!IS_DGFX(xe)) {
> +			xe->pat.pat_primary_pta = &xe3p_primary_pat_pta;
> +			xe->pat.pat_media_pta = &xe3p_media_pat_pta;
> +		}
> +		xe->pat.n_entries = ARRAY_SIZE(xe3p_lpg_pat_table);
> +		xe->pat.idx[XE_CACHE_NONE] = 3;
> +		xe->pat.idx[XE_CACHE_WT] = 15;
> +		xe->pat.idx[XE_CACHE_WB] = 2;
> +		xe->pat.idx[XE_CACHE_NONE_COMPRESSION] = 12;
> +		xe->pat.idx[XE_CACHE_WB_COMPRESSION] = 16;
>  	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
>  		xe->pat.ops = &xe2_pat_ops;
>  		if (GRAPHICS_VER(xe) == 30) {
> 
> -- 
> 2.52.0
> 

Re: [PATCH 08/16] drm/xe/xe3p_lpg: Drop unnecessary tuning settings

[Matt Atwood]

On Mon, Feb 02, 2026 at 06:43:14PM -0300, Gustavo Sousa wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> From Xe3p onward, the desired settings are now the hardware's
> default values and the driver does not need to program them explicitly.
> 
> Since 35.xx seems to be the starting point for "Xe3p" version numbers;
> we'll adjust the bounds of the old programming to stop at 34.99.  Even
> though there's no platform with version 35.00 at the moment, this is
> simplest in case one does show up in the future.
> 
> Bspec: 72161, 59928, 59930
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_tuning.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index a97872b3214b..694385ae75f1 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -32,12 +32,12 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  	/* Xe2 */
>  
>  	{ XE_RTP_NAME("Tuning: L3 cache"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499)),
>  	  XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
>  				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>  	},
>  	{ XE_RTP_NAME("Tuning: L3 cache - media"),
> -	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, 3499)),
>  	  XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
>  				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>  	},
> @@ -53,7 +53,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  			 SET(XE2LPM_CCCHKNREG1, L3CMPCTRL))
>  	},
>  	{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499)),
>  	  XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
>  	},
>  	{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3 - media"),
> 
> -- 
> 2.52.0
> 

Re: [PATCH 07/16] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP

[Matt Atwood]

On Mon, Feb 02, 2026 at 06:43:13PM -0300, Gustavo Sousa wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> By default the hardware reports context switch status into the global
> hardware status page.  The Xe driver doesn't use this information for
> anything, and as of Xe3p, leaving this setting enabled will prevent
> other hardware optimizations from being enabled.  Disable this reporting
> as suggested by the tuning guide.
> 
> Bspec: 72161
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_tuning.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 5766fa7742d3..a97872b3214b 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -10,6 +10,7 @@
>  #include <drm/drm_managed.h>
>  #include <drm/drm_print.h>
>  
> +#include "regs/xe_engine_regs.h"
>  #include "regs/xe_gt_regs.h"
>  #include "xe_gt_types.h"
>  #include "xe_platform_types.h"
> @@ -107,6 +108,12 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
>  	},
> +	{ XE_RTP_NAME("Tuning: disable HW reporting of ctx switch to GHWSP"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3500, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
> +			     GHWSP_CSB_REPORT_DIS,
> +			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> +	},
>  };
>  
>  static const struct xe_rtp_entry_sr lrc_tunings[] = {
> 
> -- 
> 2.52.0
> 

Re: [PATCH 06/16] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state

[Matt Atwood]

On Mon, Feb 02, 2026 at 06:43:12PM -0300, Gustavo Sousa wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe3p_LPG adds some additional state instructions to the RCS engine's
> LRC.  Add support for these to the debugfs LRC parser.
> 
> Note that the bspec's LRC description page seems to have a few mistakes
> in the name/spelling of these new instructions (e.g.,
> "3DSTATE_TASK_DATA_EXT" instead of "3DSTATE_TASK_SHADER_DATA_EXT" or
> "3DSTATE_VIEWPORT_STATE_POINTERS_CL_SF_2" instead of
> "3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2").
> 
> Bspec: 65182
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h | 10 ++++++++++
>  drivers/gpu/drm/xe/xe_lrc.c                           | 10 ++++++++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h b/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
> index 457881af8af9..4d854c85e588 100644
> --- a/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
> +++ b/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
> @@ -55,6 +55,7 @@
>  #define PIPELINE_SELECT				GFXPIPE_SINGLE_DW_CMD(0x1, 0x4)
>  
>  #define CMD_3DSTATE_DRAWING_RECTANGLE_FAST	GFXPIPE_3D_CMD(0x0, 0x0)
> +#define CMD_3DSTATE_CUSTOM_SAMPLE_PATTERN	GFXPIPE_3D_CMD(0x0, 0x2)
>  #define CMD_3DSTATE_CLEAR_PARAMS		GFXPIPE_3D_CMD(0x0, 0x4)
>  #define CMD_3DSTATE_DEPTH_BUFFER		GFXPIPE_3D_CMD(0x0, 0x5)
>  #define CMD_3DSTATE_STENCIL_BUFFER		GFXPIPE_3D_CMD(0x0, 0x6)
> @@ -138,8 +139,16 @@
>  #define CMD_3DSTATE_SBE_MESH			GFXPIPE_3D_CMD(0x0, 0x82)
>  #define CMD_3DSTATE_CPSIZE_CONTROL_BUFFER	GFXPIPE_3D_CMD(0x0, 0x83)
>  #define CMD_3DSTATE_COARSE_PIXEL		GFXPIPE_3D_CMD(0x0, 0x89)
> +#define CMD_3DSTATE_MESH_SHADER_DATA_EXT	GFXPIPE_3D_CMD(0x0, 0x8A)
> +#define CMD_3DSTATE_TASK_SHADER_DATA_EXT	GFXPIPE_3D_CMD(0x0, 0x8B)
> +#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_CC_2	GFXPIPE_3D_CMD(0x0, 0x8D)
> +#define CMD_3DSTATE_CC_STATE_POINTERS_2		GFXPIPE_3D_CMD(0x0, 0x8E)
> +#define CMD_3DSTATE_SCISSOR_STATE_POINTERS_2	GFXPIPE_3D_CMD(0x0, 0x8F)
> +#define CMD_3DSTATE_BLEND_STATE_POINTERS_2	GFXPIPE_3D_CMD(0x0, 0xA0)
> +#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2	GFXPIPE_3D_CMD(0x0, 0xA1)
>  
>  #define CMD_3DSTATE_DRAWING_RECTANGLE		GFXPIPE_3D_CMD(0x1, 0x0)
> +#define CMD_3DSTATE_URB_MEMORY			GFXPIPE_3D_CMD(0x1, 0x1)
>  #define CMD_3DSTATE_CHROMA_KEY			GFXPIPE_3D_CMD(0x1, 0x4)
>  #define CMD_3DSTATE_POLY_STIPPLE_OFFSET		GFXPIPE_3D_CMD(0x1, 0x6)
>  #define CMD_3DSTATE_POLY_STIPPLE_PATTERN	GFXPIPE_3D_CMD(0x1, 0x7)
> @@ -160,5 +169,6 @@
>  #define CMD_3DSTATE_SUBSLICE_HASH_TABLE		GFXPIPE_3D_CMD(0x1, 0x1F)
>  #define CMD_3DSTATE_SLICE_TABLE_STATE_POINTERS	GFXPIPE_3D_CMD(0x1, 0x20)
>  #define CMD_3DSTATE_PTBR_TILE_PASS_INFO		GFXPIPE_3D_CMD(0x1, 0x22)
> +#define CMD_3DSTATE_SLICE_TABLE_STATE_POINTER_2	GFXPIPE_3D_CMD(0x1, 0xA0)
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 3db7968aa5e2..e58eb8b9db78 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -1966,6 +1966,7 @@ static int dump_gfxpipe_command(struct drm_printer *p,
>  	MATCH(PIPELINE_SELECT);
>  
>  	MATCH3D(3DSTATE_DRAWING_RECTANGLE_FAST);
> +	MATCH3D(3DSTATE_CUSTOM_SAMPLE_PATTERN);
>  	MATCH3D(3DSTATE_CLEAR_PARAMS);
>  	MATCH3D(3DSTATE_DEPTH_BUFFER);
>  	MATCH3D(3DSTATE_STENCIL_BUFFER);
> @@ -2049,8 +2050,16 @@ static int dump_gfxpipe_command(struct drm_printer *p,
>  	MATCH3D(3DSTATE_SBE_MESH);
>  	MATCH3D(3DSTATE_CPSIZE_CONTROL_BUFFER);
>  	MATCH3D(3DSTATE_COARSE_PIXEL);
> +	MATCH3D(3DSTATE_MESH_SHADER_DATA_EXT);
> +	MATCH3D(3DSTATE_TASK_SHADER_DATA_EXT);
> +	MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_CC_2);
> +	MATCH3D(3DSTATE_CC_STATE_POINTERS_2);
> +	MATCH3D(3DSTATE_SCISSOR_STATE_POINTERS_2);
> +	MATCH3D(3DSTATE_BLEND_STATE_POINTERS_2);
> +	MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2);
>  
>  	MATCH3D(3DSTATE_DRAWING_RECTANGLE);
> +	MATCH3D(3DSTATE_URB_MEMORY);
>  	MATCH3D(3DSTATE_CHROMA_KEY);
>  	MATCH3D(3DSTATE_POLY_STIPPLE_OFFSET);
>  	MATCH3D(3DSTATE_POLY_STIPPLE_PATTERN);
> @@ -2070,6 +2079,7 @@ static int dump_gfxpipe_command(struct drm_printer *p,
>  	MATCH3D(3DSTATE_SUBSLICE_HASH_TABLE);
>  	MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTERS);
>  	MATCH3D(3DSTATE_PTBR_TILE_PASS_INFO);
> +	MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTER_2);
>  
>  	default:
>  		drm_printf(p, "[%#010x] unknown GFXPIPE command (pipeline=%#x, opcode=%#x, subopcode=%#x), likely %d dwords\n",
> 
> -- 
> 2.52.0
> 

Re: [PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering

[Bhadane, Dnyaneshwar]

On 04-Feb-26 6:03 AM, Gustavo Sousa wrote:
> "Bhadane, Dnyaneshwar" <dnyaneshwar.bhadane@intel.com> writes:
> 
>>> -----Original Message-----
>>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Gustavo
>>> Sousa
>>> Sent: Tuesday, February 3, 2026 3:13 AM
>>> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>>> Cc: Sousa, Gustavo <gustavo.sousa@intel.com>; Roper, Matthew D
>>> <matthew.d.roper@intel.com>
>>> Subject: [PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering
>>>
>>> From: Matt Roper <matthew.d.roper@intel.com>
>>>
>>> Xe3p_LPG has nearly identical steering to Xe2 and Xe3.  The only DSS/XeCore
>>> change from those IPs is an additional range from 0xDE00-0xDE7F that was
>>> previously reserved, so we can simply grow one of the existing ranges in the Xe2
>>> table to include it.  Similarly, the "instance0" table is also almost identical, but
>>> gains one additional PSMI range and requires a separate table.
>>>
>>> Bspec: 75242
>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> ---
>>>   drivers/gpu/drm/xe/xe_gt_mcr.c | 18 +++++++++++++++++-
>>>   1 file changed, 17 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>> index 7c1fe9ac120d..b112e551fc79 100644
>>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>> @@ -201,7 +201,7 @@ static const struct xe_mmio_range
>>> xe2lpg_dss_steering_table[] = {
>>>   	{ 0x009680, 0x0096FF },         /* DSS */
>>>   	{ 0x00D800, 0x00D87F },         /* SLICE */
>>>   	{ 0x00DC00, 0x00DCFF },         /* SLICE */
>>> -	{ 0x00DE80, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
>>> +	{ 0x00DE00, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
>>>   	{ 0x00E980, 0x00E9FF },         /* SLICE */
>>>   	{ 0x013000, 0x0133FF },         /* DSS (0x13000-0x131FF), SLICE (0x13200-
>>> 0x133FF) */
>>>   	{},
>>> @@ -280,6 +280,19 @@ static const struct xe_mmio_range
>>> xe3p_xpc_instance0_steering_table[] = {
>>>   	{},
>>>   };
>>>
>>> +static const struct xe_mmio_range xe3p_lpg_instance0_steering_table[] = {
>>> +	{ 0x004000, 0x004AFF },         /* GAM, rsvd, GAMWKR */
>>> +	{ 0x008700, 0x00887F },         /* NODE */
>>> +	{ 0x00B000, 0x00B3FF },         /* NODE, L3BANK */
>>> +	{ 0x00B500, 0x00B6FF },		/* PSMI */
>> Hi,
>> Could we extend the range till 0x00BEFF ?
>>> +	{ 0x00C800, 0x00CFFF },         /* GAM */
>>> +	{ 0x00D880, 0x00D8FF },         /* NODE */
>>> +	{ 0x00DD00, 0x00DDFF },         /* MEMPIPE */
>> Same as we did here extend till reserved.
> 
> We usually only include a reserved range if the range is preceeded and
> followed by MCR ranges of the same steering group.
Yes, But there's a bit of confusion here. We are extending 0x00DDFF for 
MEMPIPE, but we are not extending the PSMI group to 0x00BEFF?

BR,
Dnyaneshwar
> 
> This doesn't seem to be the case here.


> 
> --
> Gustavo Sousa

Re: [PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering

[Gustavo Sousa]

"Bhadane, Dnyaneshwar" <dnyaneshwar.bhadane@intel.com> writes:

> On 04-Feb-26 6:03 AM, Gustavo Sousa wrote:
>> "Bhadane, Dnyaneshwar" <dnyaneshwar.bhadane@intel.com> writes:
>> 
>>>> -----Original Message-----
>>>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Gustavo
>>>> Sousa
>>>> Sent: Tuesday, February 3, 2026 3:13 AM
>>>> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>>>> Cc: Sousa, Gustavo <gustavo.sousa@intel.com>; Roper, Matthew D
>>>> <matthew.d.roper@intel.com>
>>>> Subject: [PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering
>>>>
>>>> From: Matt Roper <matthew.d.roper@intel.com>
>>>>
>>>> Xe3p_LPG has nearly identical steering to Xe2 and Xe3.  The only DSS/XeCore
>>>> change from those IPs is an additional range from 0xDE00-0xDE7F that was
>>>> previously reserved, so we can simply grow one of the existing ranges in the Xe2
>>>> table to include it.  Similarly, the "instance0" table is also almost identical, but
>>>> gains one additional PSMI range and requires a separate table.
>>>>
>>>> Bspec: 75242
>>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/xe/xe_gt_mcr.c | 18 +++++++++++++++++-
>>>>   1 file changed, 17 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>>> index 7c1fe9ac120d..b112e551fc79 100644
>>>> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>>>> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>>> @@ -201,7 +201,7 @@ static const struct xe_mmio_range
>>>> xe2lpg_dss_steering_table[] = {
>>>>   	{ 0x009680, 0x0096FF },         /* DSS */
>>>>   	{ 0x00D800, 0x00D87F },         /* SLICE */
>>>>   	{ 0x00DC00, 0x00DCFF },         /* SLICE */
>>>> -	{ 0x00DE80, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
>>>> +	{ 0x00DE00, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
>>>>   	{ 0x00E980, 0x00E9FF },         /* SLICE */
>>>>   	{ 0x013000, 0x0133FF },         /* DSS (0x13000-0x131FF), SLICE (0x13200-
>>>> 0x133FF) */
>>>>   	{},
>>>> @@ -280,6 +280,19 @@ static const struct xe_mmio_range
>>>> xe3p_xpc_instance0_steering_table[] = {
>>>>   	{},
>>>>   };
>>>>
>>>> +static const struct xe_mmio_range xe3p_lpg_instance0_steering_table[] = {
>>>> +	{ 0x004000, 0x004AFF },         /* GAM, rsvd, GAMWKR */
>>>> +	{ 0x008700, 0x00887F },         /* NODE */
>>>> +	{ 0x00B000, 0x00B3FF },         /* NODE, L3BANK */
>>>> +	{ 0x00B500, 0x00B6FF },		/* PSMI */
>>> Hi,
>>> Could we extend the range till 0x00BEFF ?
>>>> +	{ 0x00C800, 0x00CFFF },         /* GAM */
>>>> +	{ 0x00D880, 0x00D8FF },         /* NODE */
>>>> +	{ 0x00DD00, 0x00DDFF },         /* MEMPIPE */
>>> Same as we did here extend till reserved.
>> 
>> We usually only include a reserved range if the range is preceeded and
>> followed by MCR ranges of the same steering group.
> Yes, But there's a bit of confusion here. We are extending 0x00DDFF for 
> MEMPIPE, but we are not extending the PSMI group to 0x00BEFF?

I took a look at Bspec history and the range has been split into ranges
[0x00DD00:0x00DD7F] and [0x00DD80:0x00DDFF], with the later being tagged
as reserved.

I believe, by the time we wrote this patch, the range was still
[0x00DD00:0x00DDFF].

Good catch! I'll update this.

Thanks!

--
Gustavo Sousa

>
> BR,
> Dnyaneshwar
>> 
>> This doesn't seem to be the case here.
>
>
>> 
>> --
>> Gustavo Sousa