* [PATCH 1/3] drm/i915: rip out the pipe A quirk for i855gm
@ 2012-10-10 21:13 Daniel Vetter
2012-10-10 21:14 ` [PATCH 2/3] drm/i915: fixup the plane->pipe fixup code Daniel Vetter
2012-10-10 21:14 ` [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2 Daniel Vetter
0 siblings, 2 replies; 8+ messages in thread
From: Daniel Vetter @ 2012-10-10 21:13 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
This seems to be the root-cause that breaks resume on my i855gm when I
apply the "drm/i915: fixup the plane->pipe fixup code" patch. And that
code doesn't even run on my machine, so it's pure timing changes
causing the regression.
Furthermore resume has been constantly switching between working and
broken on this machine ever since kms support has been merged,
seemingly with no related change as a root cause. And always with the
same symptoms of the backlight lighting up, but the lvds panel only
displaying black.
Also, of both i855gm variants only one is in the table. And in the
past we've only ever removed entries from this quirk table because it
breaks things.
So let's just remove it - in case there's indeed a bios out there
relying on a running pipe A, we can add back in a more precise quirk
entry, like all the others (save for i830/i845).
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8d51e52..735f8d7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7790,8 +7790,7 @@ static struct intel_quirk intel_quirks[] = {
/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
- /* 855 & before need to leave pipe A & dpll A up */
- { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+ /* 830/845 need to leave pipe A & dpll A up */
{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
--
1.7.11.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/3] drm/i915: fixup the plane->pipe fixup code
2012-10-10 21:13 [PATCH 1/3] drm/i915: rip out the pipe A quirk for i855gm Daniel Vetter
@ 2012-10-10 21:14 ` Daniel Vetter
2012-10-11 8:03 ` Chris Wilson
2012-10-10 21:14 ` [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2 Daniel Vetter
1 sibling, 1 reply; 8+ messages in thread
From: Daniel Vetter @ 2012-10-10 21:14 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
We need to check whether the _other plane is on our pipe, not whether
our plane is on the other pipe. Otherwise if not both pipes/planes are
active, we won't properly clean up the mess and set up our desired
plane->pipe mapping.
v2: Fixup the logic, I've totally fumbled it. Noticed by Chris Wilson.
v3: I've checked Bspec, and the flexible plane->pipe mapping is a
gen2/3 feature, so test for that instead of PCH_SPLIT
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51265
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49838
Tested-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 735f8d7..1109e0a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7946,11 +7946,27 @@ static void intel_enable_pipe_a(struct drm_device *dev)
}
+static bool
+intel_check_plane_mapping(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+ u32 reg, val;
+
+ reg = DSPCNTR(!crtc->plane);
+ val = I915_READ(reg);
+
+ if ((val & DISPLAY_PLANE_ENABLE) &&
+ (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
+ return false;
+
+ return true;
+}
+
static void intel_sanitize_crtc(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 reg, val;
+ u32 reg;
/* Clear any frame start delays used for debugging left by the BIOS */
reg = PIPECONF(crtc->pipe);
@@ -7958,17 +7974,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
/* We need to sanitize the plane -> pipe mapping first because this will
* disable the crtc (and hence change the state) if it is wrong. */
- if (!HAS_PCH_SPLIT(dev)) {
+ if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
struct intel_connector *connector;
bool plane;
- reg = DSPCNTR(crtc->plane);
- val = I915_READ(reg);
-
- if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
- (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
- goto ok;
-
DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
crtc->base.base.id);
@@ -7992,7 +8001,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
WARN_ON(crtc->active);
crtc->base.enabled = false;
}
-ok:
if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
crtc->pipe == PIPE_A && !crtc->active) {
--
1.7.11.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/3] drm/i915: fixup the plane->pipe fixup code
2012-10-10 21:14 ` [PATCH 2/3] drm/i915: fixup the plane->pipe fixup code Daniel Vetter
@ 2012-10-11 8:03 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2012-10-11 8:03 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
On Wed, 10 Oct 2012 23:14:00 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> We need to check whether the _other plane is on our pipe, not whether
> our plane is on the other pipe. Otherwise if not both pipes/planes are
> active, we won't properly clean up the mess and set up our desired
> plane->pipe mapping.
>
> v2: Fixup the logic, I've totally fumbled it. Noticed by Chris Wilson.
>
> v3: I've checked Bspec, and the flexible plane->pipe mapping is a
> gen2/3 feature, so test for that instead of PCH_SPLIT
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51265
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49838
> Tested-by: Dave Airlie <airlied@gmail.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
With these patches applied my 855gm is still in good working order (the
best it has been). Though I'm still spammed by modeset_check failing in
every possible way!
Tested-by: Chris Wilson <chris@chris-wilson.co.uk> #855gm
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2
2012-10-10 21:13 [PATCH 1/3] drm/i915: rip out the pipe A quirk for i855gm Daniel Vetter
2012-10-10 21:14 ` [PATCH 2/3] drm/i915: fixup the plane->pipe fixup code Daniel Vetter
@ 2012-10-10 21:14 ` Daniel Vetter
2012-10-10 22:37 ` Chris Wilson
1 sibling, 1 reply; 8+ messages in thread
From: Daniel Vetter @ 2012-10-10 21:14 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
It doesn't work since the gtt pte range sits in the middle of the mmio
bar. We didn't notice that since both my and Chris' gen2 machines
don't support PAT and hence all wc io mapping request will
automatically be demoted to uc.
This regression has been introduce in
commit edef7e685da05c13cce50c0126189c80fe2c8f71
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Sep 14 11:57:47 2012 +0100
agp/intel: Use a write-combining map for updating PTEs
Reported-by: Egbert Eich <eich@pdx.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/char/agp/intel-gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index e01f5ea..38390f7 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -667,7 +667,7 @@ static int intel_gtt_init(void)
gtt_map_size = intel_private.base.gtt_total_entries * 4;
intel_private.gtt = NULL;
- if (INTEL_GTT_GEN < 6)
+ if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
gtt_map_size);
if (intel_private.gtt == NULL)
--
1.7.11.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2
2012-10-10 21:14 ` [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2 Daniel Vetter
@ 2012-10-10 22:37 ` Chris Wilson
2012-10-11 8:37 ` Daniel Vetter
0 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2012-10-10 22:37 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
On Wed, 10 Oct 2012 23:14:01 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> It doesn't work since the gtt pte range sits in the middle of the mmio
> bar. We didn't notice that since both my and Chris' gen2 machines
> don't support PAT and hence all wc io mapping request will
> automatically be demoted to uc.
>
> This regression has been introduce in
>
> commit edef7e685da05c13cce50c0126189c80fe2c8f71
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date: Fri Sep 14 11:57:47 2012 +0100
>
> agp/intel: Use a write-combining map for updating PTEs
>
> Reported-by: Egbert Eich <eich@pdx.freedesktop.org>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Thanks for the explanation,
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2
2012-10-10 22:37 ` Chris Wilson
@ 2012-10-11 8:37 ` Daniel Vetter
2012-10-11 8:45 ` Chris Wilson
0 siblings, 1 reply; 8+ messages in thread
From: Daniel Vetter @ 2012-10-11 8:37 UTC (permalink / raw)
To: Chris Wilson; +Cc: Daniel Vetter, Intel Graphics Development
On Wed, Oct 10, 2012 at 11:37:36PM +0100, Chris Wilson wrote:
> On Wed, 10 Oct 2012 23:14:01 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > It doesn't work since the gtt pte range sits in the middle of the mmio
> > bar. We didn't notice that since both my and Chris' gen2 machines
> > don't support PAT and hence all wc io mapping request will
> > automatically be demoted to uc.
> >
> > This regression has been introduce in
> >
> > commit edef7e685da05c13cce50c0126189c80fe2c8f71
> > Author: Chris Wilson <chris@chris-wilson.co.uk>
> > Date: Fri Sep 14 11:57:47 2012 +0100
> >
> > agp/intel: Use a write-combining map for updating PTEs
> >
> > Reported-by: Egbert Eich <eich@pdx.freedesktop.org>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Thanks for the explanation,
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Patch merged to -fixes.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2
2012-10-11 8:37 ` Daniel Vetter
@ 2012-10-11 8:45 ` Chris Wilson
2012-10-11 9:05 ` Daniel Vetter
0 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2012-10-11 8:45 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development
On Thu, 11 Oct 2012 10:37:54 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, Oct 10, 2012 at 11:37:36PM +0100, Chris Wilson wrote:
> > On Wed, 10 Oct 2012 23:14:01 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > > It doesn't work since the gtt pte range sits in the middle of the mmio
> > > bar. We didn't notice that since both my and Chris' gen2 machines
> > > don't support PAT and hence all wc io mapping request will
> > > automatically be demoted to uc.
> > >
> > > This regression has been introduce in
> > >
> > > commit edef7e685da05c13cce50c0126189c80fe2c8f71
> > > Author: Chris Wilson <chris@chris-wilson.co.uk>
> > > Date: Fri Sep 14 11:57:47 2012 +0100
> > >
> > > agp/intel: Use a write-combining map for updating PTEs
> > >
> > > Reported-by: Egbert Eich <eich@pdx.freedesktop.org>
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834
> > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >
> > Thanks for the explanation,
> > Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> Patch merged to -fixes.
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
From: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915: fixup the plane->pipe fixup code
To: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
In-Reply-To: <1349903641-18378-2-git-send-email-daniel.vetter@ffwll.ch>
References: <1349903641-18378-1-git-send-email-daniel.vetter@ffwll.ch> <1349903641-18378-2-git-send-email-daniel.vetter@ffwll.ch>
On Wed, 10 Oct 2012 23:14:00 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> We need to check whether the _other plane is on our pipe, not whether
> our plane is on the other pipe. Otherwise if not both pipes/planes are
> active, we won't properly clean up the mess and set up our desired
> plane->pipe mapping.
>
> v2: Fixup the logic, I've totally fumbled it. Noticed by Chris Wilson.
>
> v3: I've checked Bspec, and the flexible plane->pipe mapping is a
> gen2/3 feature, so test for that instead of PCH_SPLIT
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51265
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49838
> Tested-by: Dave Airlie <airlied@gmail.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ok, looks good. I would move the gen check into
intel_check_plane_mapping() itself with a short note that gen4+ has a
fixed mapping.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2
2012-10-11 8:45 ` Chris Wilson
@ 2012-10-11 9:05 ` Daniel Vetter
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Vetter @ 2012-10-11 9:05 UTC (permalink / raw)
To: Chris Wilson; +Cc: Daniel Vetter, Intel Graphics Development
On Thu, Oct 11, 2012 at 09:45:56AM +0100, Chris Wilson wrote:
> On Thu, 11 Oct 2012 10:37:54 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Wed, Oct 10, 2012 at 11:37:36PM +0100, Chris Wilson wrote:
> > > On Wed, 10 Oct 2012 23:14:01 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > > > It doesn't work since the gtt pte range sits in the middle of the mmio
> > > > bar. We didn't notice that since both my and Chris' gen2 machines
> > > > don't support PAT and hence all wc io mapping request will
> > > > automatically be demoted to uc.
> > > >
> > > > This regression has been introduce in
> > > >
> > > > commit edef7e685da05c13cce50c0126189c80fe2c8f71
> > > > Author: Chris Wilson <chris@chris-wilson.co.uk>
> > > > Date: Fri Sep 14 11:57:47 2012 +0100
> > > >
> > > > agp/intel: Use a write-combining map for updating PTEs
> > > >
> > > > Reported-by: Egbert Eich <eich@pdx.freedesktop.org>
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834
> > > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > >
> > > Thanks for the explanation,
> > > Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Patch merged to -fixes.
> > -Daniel
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> From: Chris Wilson <chris@chris-wilson.co.uk>
> Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915: fixup the plane->pipe fixup code
> To: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> In-Reply-To: <1349903641-18378-2-git-send-email-daniel.vetter@ffwll.ch>
> References: <1349903641-18378-1-git-send-email-daniel.vetter@ffwll.ch> <1349903641-18378-2-git-send-email-daniel.vetter@ffwll.ch>
>
> On Wed, 10 Oct 2012 23:14:00 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > We need to check whether the _other plane is on our pipe, not whether
> > our plane is on the other pipe. Otherwise if not both pipes/planes are
> > active, we won't properly clean up the mess and set up our desired
> > plane->pipe mapping.
> >
> > v2: Fixup the logic, I've totally fumbled it. Noticed by Chris Wilson.
> >
> > v3: I've checked Bspec, and the flexible plane->pipe mapping is a
> > gen2/3 feature, so test for that instead of PCH_SPLIT
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51265
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49838
> > Tested-by: Dave Airlie <airlied@gmail.com>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Ok, looks good. I would move the gen check into
> intel_check_plane_mapping() itself with a short note that gen4+ has a
> fixed mapping.
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Applied them both, although I did not move the gen < 4 check, only added a
comment - that way it's clear that the fixup code only ever runs on hw
with at most 2 pipes. And all the !plane tricks it does depend upon that.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2012-10-11 9:04 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
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2012-10-10 21:13 [PATCH 1/3] drm/i915: rip out the pipe A quirk for i855gm Daniel Vetter
2012-10-10 21:14 ` [PATCH 2/3] drm/i915: fixup the plane->pipe fixup code Daniel Vetter
2012-10-11 8:03 ` Chris Wilson
2012-10-10 21:14 ` [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2 Daniel Vetter
2012-10-10 22:37 ` Chris Wilson
2012-10-11 8:37 ` Daniel Vetter
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