[PATCH 00/11] Panel Replay + Adaptive sync

[PATCH 00/11] Panel Replay + Adaptive sync

[Jouni Högander]

This patch set is adding missing configuration to have Panel Replay
and Adaptive Sync enabled simultaneously. Also some issues identified
while debugging are fixed:

1. Source PORT ALPM configuration has to made during modeset.
2. PHY_CMN1_CONTROL is not written according to HAS document
3. Wrong register field definitions for PORT_ALPM_LFPS_CTL.

Patches are tested on LunarLake and PantheLake using our reference panel supporting
Adaptive Sync and Panel Replay.

EMP_AS_SDP_TL is currently missing completely from drm-tip. There is a patch for that which is needed if testing these patches:

https://patchwork.freedesktop.org/series/148421/

Otherwise "PSR idle timeout" errors are seen while testing.

Jouni Högander (11):
  drm/dp: Add Panel Replay capability bits from DP2.1 specification
  drm/i915/psr: Read both Panel Replay capability registers from DPCD
  drm/i915/alpm: Add PR_ALPM_CTL register definitions
  drm/i915/alpm: Write PR_ALPM_CTL register
  drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSR
  drm/i915/alpm: Add new interface to check if AUXLess ALPM is used
  drm/i915/alpm: Move port alpm configuration
  drm/i915/display: Add PHY_CMN1_CONTROL register definitions
  drm/i915/display: Add function to configure LFPS sending
  drm/i915/psr: Fix using wrong mask in REG_FIELD_PREP
  drm/i915/psr: Do not disable Panel Replay in case VRR is enabled

 drivers/gpu/drm/i915/display/intel_alpm.c     | 83 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_alpm.h     |  4 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 30 +++++++
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  2 +
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |  3 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 12 +++
 .../drm/i915/display/intel_display_types.h    |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 40 ++++++---
 drivers/gpu/drm/i915/display/intel_psr.h      |  2 +
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 14 +++-
 include/drm/display/drm_dp.h                  | 10 ++-
 11 files changed, 164 insertions(+), 38 deletions(-)

-- 
2.43.0

[PATCH 01/11] drm/dp: Add Panel Replay capability bits from DP2.1 specification

[Jouni Högander]

Add PANEL REPLAY CAPABILITY register (0xb1) bits.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 include/drm/display/drm_dp.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 3001c0b6e7bb3..47e7d55e2803f 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -552,8 +552,14 @@
 # define DP_PANEL_REPLAY_SU_SUPPORT			(1 << 1)
 # define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT	(1 << 2) /* eDP 1.5 */
 
-#define DP_PANEL_PANEL_REPLAY_CAPABILITY		0xb1
-# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED	(1 << 5)
+#define DP_PANEL_PANEL_REPLAY_CAPABILITY					0xb1
+# define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT			1 /* DP 2.1 */
+# define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK			(3 << 1)
+# define DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR			(1 << 3)
+# define DP_PANEL_REPLAY_DSC_CRC_OF_MULTIPLE_SUS_SUPPORTED			(1 << 4)
+# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED				(1 << 5)
+# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_SUPPORTED		(1 << 6)
+# define DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP	(1 << 7)
 
 #define DP_PANEL_PANEL_REPLAY_X_GRANULARITY		0xb2
 #define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY		0xb4
-- 
2.43.0

Re: [PATCH 01/11] drm/dp: Add Panel Replay capability bits from DP2.1 specification

[Jani Nikula]

On Fri, 02 May 2025, Jouni Högander <jouni.hogander@intel.com> wrote:
> Add PANEL REPLAY CAPABILITY register (0xb1) bits.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  include/drm/display/drm_dp.h | 10 ++++++++--

Needs Cc: dri-devel too.

>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 3001c0b6e7bb3..47e7d55e2803f 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -552,8 +552,14 @@
>  # define DP_PANEL_REPLAY_SU_SUPPORT			(1 << 1)
>  # define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT	(1 << 2) /* eDP 1.5 */
>  
> -#define DP_PANEL_PANEL_REPLAY_CAPABILITY		0xb1
> -# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED	(1 << 5)
> +#define DP_PANEL_PANEL_REPLAY_CAPABILITY					0xb1
> +# define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT			1 /* DP 2.1 */
> +# define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK			(3 << 1)
> +# define DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR			(1 << 3)
> +# define DP_PANEL_REPLAY_DSC_CRC_OF_MULTIPLE_SUS_SUPPORTED			(1 << 4)
> +# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED				(1 << 5)
> +# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_SUPPORTED		(1 << 6)
> +# define DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP	(1 << 7)
>  
>  #define DP_PANEL_PANEL_REPLAY_X_GRANULARITY		0xb2
>  #define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY		0xb4

-- 
Jani Nikula, Intel

Re: [PATCH 01/11] drm/dp: Add Panel Replay capability bits from DP2.1 specification

[Hogander, Jouni]

On Fri, 2025-05-02 at 12:19 +0300, Jani Nikula wrote:
> On Fri, 02 May 2025, Jouni Högander <jouni.hogander@intel.com> wrote:
> > Add PANEL REPLAY CAPABILITY register (0xb1) bits.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  include/drm/display/drm_dp.h | 10 ++++++++--
> 
> Needs Cc: dri-devel too.

Just sent this separately after your reminder.

BR,

Jouni Högander

> 
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/include/drm/display/drm_dp.h
> > b/include/drm/display/drm_dp.h
> > index 3001c0b6e7bb3..47e7d55e2803f 100644
> > --- a/include/drm/display/drm_dp.h
> > +++ b/include/drm/display/drm_dp.h
> > @@ -552,8 +552,14 @@
> >  # define DP_PANEL_REPLAY_SU_SUPPORT			(1 << 1)
> >  # define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT	(1 << 2)
> > /* eDP 1.5 */
> >  
> > -#define DP_PANEL_PANEL_REPLAY_CAPABILITY		0xb1
> > -# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED	(1 << 5)
> > +#define
> > DP_PANEL_PANEL_REPLAY_CAPABILITY					0xb1
> > +# define
> > DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT			1 /* DP 2.1 */
> > +# define
> > DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK			(3 << 1)
> > +# define
> > DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR			(1
> > << 3)
> > +# define
> > DP_PANEL_REPLAY_DSC_CRC_OF_MULTIPLE_SUS_SUPPORTED			(1 << 4)
> > +# define
> > DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED				(1 << 5)
> > +# define
> > DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_SUPPORTED	
> > 	(1 << 6)
> > +# define
> > DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP
> > 	(1 << 7)
> >  
> >  #define DP_PANEL_PANEL_REPLAY_X_GRANULARITY		0xb2
> >  #define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY		0xb4
> 

Re: [PATCH 01/11] drm/dp: Add Panel Replay capability bits from DP2.1 specification

[Nautiyal, Ankit K]

On 5/2/2025 2:28 PM, Jouni Högander wrote:
> Add PANEL REPLAY CAPABILITY register (0xb1) bits.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   include/drm/display/drm_dp.h | 10 ++++++++--
>   1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 3001c0b6e7bb3..47e7d55e2803f 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -552,8 +552,14 @@
>   # define DP_PANEL_REPLAY_SU_SUPPORT			(1 << 1)
>   # define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT	(1 << 2) /* eDP 1.5 */
>   
> -#define DP_PANEL_PANEL_REPLAY_CAPABILITY		0xb1


Though not introduced in this patch, the name 
DP_PANEL_PANEL_REPLAY_CAPABILITY doesn’t seem quite right.

Since we are adding bits for Panel Replay capabilities, would it be more 
appropriate to use DP_PANEL_REPLAY_CAPABILITY instead?

Also, IMHO, DP_PANEL_REPLAY_CAP could be renamed to 
DP_PANEL_REPLAY_CAP_SUPPORT for better clarity.

Lastly, since Panel Replay capabilities are defined from 0xb0 to 0xb6, 
perhaps we could introduce a DP_PANEL_REPLAY_CAP_SIZE to reflect the range?


Regards,

Ankit


> -# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED	(1 << 5)
> +#define DP_PANEL_PANEL_REPLAY_CAPABILITY					0xb1
> +# define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT			1 /* DP 2.1 */
> +# define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK			(3 << 1)
> +# define DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR			(1 << 3)
> +# define DP_PANEL_REPLAY_DSC_CRC_OF_MULTIPLE_SUS_SUPPORTED			(1 << 4)
> +# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED				(1 << 5)
> +# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_SUPPORTED		(1 << 6)
> +# define DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP	(1 << 7)
>   
>   #define DP_PANEL_PANEL_REPLAY_X_GRANULARITY		0xb2
>   #define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY		0xb4

Re: [PATCH 01/11] drm/dp: Add Panel Replay capability bits from DP2.1 specification

[Hogander, Jouni]

On Tue, 2025-05-20 at 14:06 +0530, Nautiyal, Ankit K wrote:
> 
> On 5/2/2025 2:28 PM, Jouni Högander wrote:
> > Add PANEL REPLAY CAPABILITY register (0xb1) bits.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   include/drm/display/drm_dp.h | 10 ++++++++--
> >   1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/include/drm/display/drm_dp.h
> > b/include/drm/display/drm_dp.h
> > index 3001c0b6e7bb3..47e7d55e2803f 100644
> > --- a/include/drm/display/drm_dp.h
> > +++ b/include/drm/display/drm_dp.h
> > @@ -552,8 +552,14 @@
> >   # define DP_PANEL_REPLAY_SU_SUPPORT			(1 << 1)
> >   # define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT	(1 << 2)
> > /* eDP 1.5 */
> >   
> > -#define DP_PANEL_PANEL_REPLAY_CAPABILITY		0xb1
> 
> 
> Though not introduced in this patch, the name 
> DP_PANEL_PANEL_REPLAY_CAPABILITY doesn’t seem quite right.
> 
> Since we are adding bits for Panel Replay capabilities, would it be
> more 
> appropriate to use DP_PANEL_REPLAY_CAPABILITY instead?
> 
> Also, IMHO, DP_PANEL_REPLAY_CAP could be renamed to 
> DP_PANEL_REPLAY_CAP_SUPPORT for better clarity.
> 
> Lastly, since Panel Replay capabilities are defined from 0xb0 to
> 0xb6, 
> perhaps we could introduce a DP_PANEL_REPLAY_CAP_SIZE to reflect the
> range?

I have made these changes. Thank you for these ideas.

BR,

Jouni Högander
> 
> 
> Regards,
> 
> Ankit
> 
> 
> > -# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED	(1 << 5)
> > +#define
> > DP_PANEL_PANEL_REPLAY_CAPABILITY					0xb1
> > +# define
> > DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT			1 /* DP 2.1 */
> > +# define
> > DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK			(3 << 1)
> > +# define
> > DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR			(1
> > << 3)
> > +# define
> > DP_PANEL_REPLAY_DSC_CRC_OF_MULTIPLE_SUS_SUPPORTED			(1 << 4)
> > +# define
> > DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED				(1 << 5)
> > +# define
> > DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_SUPPORTED	
> > 	(1 << 6)
> > +# define
> > DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP
> > 	(1 << 7)
> >   
> >   #define DP_PANEL_PANEL_REPLAY_X_GRANULARITY		0xb2
> >   #define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY		0xb4

[PATCH 02/11] drm/i915/psr: Read both Panel Replay capability registers from DPCD

[Jouni Högander]

There is a second Panel Replay capability register in DPCD. Read that as
well for later use.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c           | 14 +++++++-------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7415564d058a2..356287309817e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1665,7 +1665,7 @@ struct intel_dp {
 	bool use_max_params;
 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
 	u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
-	u8 pr_dpcd;
+	u8 pr_dpcd[2];
 	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 	u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ccd66bbc72f79..2d78d64b8db8d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -608,7 +608,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 			return;
 		}
 
-		if (!(intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
+		if (!(intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
 			drm_dbg_kms(display->drm,
 				    "Panel doesn't support early transport, eDP Panel Replay not possible\n");
 			return;
@@ -617,7 +617,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 
 	intel_dp->psr.sink_panel_replay_support = true;
 
-	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
+	if (intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_SU_SUPPORT)
 		intel_dp->psr.sink_panel_replay_su_support = true;
 
 	drm_dbg_kms(display->drm,
@@ -676,10 +676,10 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 {
 	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 			 sizeof(intel_dp->psr_dpcd));
-	drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
-			  &intel_dp->pr_dpcd);
+	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
+			 &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));
 
-	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
+	if (intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_SUPPORT)
 		_panel_replay_init_dpcd(intel_dp);
 
 	if (intel_dp->psr_dpcd[0])
@@ -736,7 +736,7 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay
 		return false;
 
 	return panel_replay ?
-		intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
+		intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
 		intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
 		psr2_su_region_et_global_enabled(intel_dp);
 }
@@ -3909,7 +3909,7 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
 	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
 	seq_printf(m, ", Panel Replay Selective Update = %s",
 		   str_yes_no(psr->sink_panel_replay_su_support));
-	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
+	if (intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
 		seq_printf(m, " (Early Transport)");
 	seq_printf(m, "\n");
 }
-- 
2.43.0

Re: [PATCH 02/11] drm/i915/psr: Read both Panel Replay capability registers from DPCD

[Nautiyal, Ankit K]

On 5/2/2025 2:28 PM, Jouni Högander wrote:
> There is a second Panel Replay capability register in DPCD. Read that as
> well for later use.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display_types.h |  2 +-
>   drivers/gpu/drm/i915/display/intel_psr.c           | 14 +++++++-------
>   2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 7415564d058a2..356287309817e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1665,7 +1665,7 @@ struct intel_dp {
>   	bool use_max_params;
>   	u8 dpcd[DP_RECEIVER_CAP_SIZE];
>   	u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> -	u8 pr_dpcd;
> +	u8 pr_dpcd[2];


As mentioned in my comments on the previous patch, defining a 
DP_PANEL_REPLAY_CAP_SIZE could be helpful here.

Also, using pr_dpcd[Some_PR_FEATURE_CAP - DP_PANEL_REPLAY_CAP_SUPPORT] 
for accessing specific Panel Replay features would allow us to avoid 
hardcoded indices.

Regards,

Ankit

>   	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>   	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
>   	u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index ccd66bbc72f79..2d78d64b8db8d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -608,7 +608,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
>   			return;
>   		}
>   
> -		if (!(intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
> +		if (!(intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
>   			drm_dbg_kms(display->drm,
>   				    "Panel doesn't support early transport, eDP Panel Replay not possible\n");
>   			return;
> @@ -617,7 +617,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
>   
>   	intel_dp->psr.sink_panel_replay_support = true;
>   
> -	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> +	if (intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_SU_SUPPORT)
>   		intel_dp->psr.sink_panel_replay_su_support = true;
>   
>   	drm_dbg_kms(display->drm,
> @@ -676,10 +676,10 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>   {
>   	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
>   			 sizeof(intel_dp->psr_dpcd));
> -	drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> -			  &intel_dp->pr_dpcd);
> +	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> +			 &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));
>   
> -	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
> +	if (intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_SUPPORT)
>   		_panel_replay_init_dpcd(intel_dp);
>   
>   	if (intel_dp->psr_dpcd[0])
> @@ -736,7 +736,7 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay
>   		return false;
>   
>   	return panel_replay ?
> -		intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
> +		intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
>   		intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
>   		psr2_su_region_et_global_enabled(intel_dp);
>   }
> @@ -3909,7 +3909,7 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
>   	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
>   	seq_printf(m, ", Panel Replay Selective Update = %s",
>   		   str_yes_no(psr->sink_panel_replay_su_support));
> -	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
> +	if (intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
>   		seq_printf(m, " (Early Transport)");
>   	seq_printf(m, "\n");
>   }

Re: [PATCH 02/11] drm/i915/psr: Read both Panel Replay capability registers from DPCD

[Hogander, Jouni]

On Tue, 2025-05-20 at 14:15 +0530, Nautiyal, Ankit K wrote:
> 
> On 5/2/2025 2:28 PM, Jouni Högander wrote:
> > There is a second Panel Replay capability register in DPCD. Read
> > that as
> > well for later use.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_display_types.h |  2 +-
> >   drivers/gpu/drm/i915/display/intel_psr.c           | 14 +++++++--
> > -----
> >   2 files changed, 8 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 7415564d058a2..356287309817e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1665,7 +1665,7 @@ struct intel_dp {
> >   	bool use_max_params;
> >   	u8 dpcd[DP_RECEIVER_CAP_SIZE];
> >   	u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> > -	u8 pr_dpcd;
> > +	u8 pr_dpcd[2];
> 
> 
> As mentioned in my comments on the previous patch, defining a 
> DP_PANEL_REPLAY_CAP_SIZE could be helpful here.
> 
> Also, using pr_dpcd[Some_PR_FEATURE_CAP -
> DP_PANEL_REPLAY_CAP_SUPPORT] 
> for accessing specific Panel Replay features would allow us to avoid 
> hardcoded indices.

I have made these changes in recent version.

BR,

Jouni Högander

> 
> Regards,
> 
> Ankit
> 
> >   	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> >   	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> >   	u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index ccd66bbc72f79..2d78d64b8db8d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -608,7 +608,7 @@ static void _panel_replay_init_dpcd(struct
> > intel_dp *intel_dp)
> >   			return;
> >   		}
> >   
> > -		if (!(intel_dp->pr_dpcd &
> > DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
> > +		if (!(intel_dp->pr_dpcd[0] &
> > DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
> >   			drm_dbg_kms(display->drm,
> >   				    "Panel doesn't support early
> > transport, eDP Panel Replay not possible\n");
> >   			return;
> > @@ -617,7 +617,7 @@ static void _panel_replay_init_dpcd(struct
> > intel_dp *intel_dp)
> >   
> >   	intel_dp->psr.sink_panel_replay_support = true;
> >   
> > -	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> > +	if (intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_SU_SUPPORT)
> >   		intel_dp->psr.sink_panel_replay_su_support = true;
> >   
> >   	drm_dbg_kms(display->drm,
> > @@ -676,10 +676,10 @@ void intel_psr_init_dpcd(struct intel_dp
> > *intel_dp)
> >   {
> >   	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> > >psr_dpcd,
> >   			 sizeof(intel_dp->psr_dpcd));
> > -	drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> > -			  &intel_dp->pr_dpcd);
> > +	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> > +			 &intel_dp->pr_dpcd, sizeof(intel_dp-
> > >pr_dpcd));
> >   
> > -	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
> > +	if (intel_dp->pr_dpcd[0] & DP_PANEL_REPLAY_SUPPORT)
> >   		_panel_replay_init_dpcd(intel_dp);
> >   
> >   	if (intel_dp->psr_dpcd[0])
> > @@ -736,7 +736,7 @@ static bool psr2_su_region_et_valid(struct
> > intel_dp *intel_dp, bool panel_replay
> >   		return false;
> >   
> >   	return panel_replay ?
> > -		intel_dp->pr_dpcd &
> > DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
> > +		intel_dp->pr_dpcd[0] &
> > DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
> >   		intel_dp->psr_dpcd[0] ==
> > DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
> >   		psr2_su_region_et_global_enabled(intel_dp);
> >   }
> > @@ -3909,7 +3909,7 @@ static void intel_psr_sink_capability(struct
> > intel_dp *intel_dp,
> >   	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr-
> > >sink_panel_replay_support));
> >   	seq_printf(m, ", Panel Replay Selective Update = %s",
> >   		   str_yes_no(psr->sink_panel_replay_su_support));
> > -	if (intel_dp->pr_dpcd &
> > DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
> > +	if (intel_dp->pr_dpcd[0] &
> > DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
> >   		seq_printf(m, " (Early Transport)");
> >   	seq_printf(m, "\n");
> >   }

[PATCH 03/11] drm/i915/alpm: Add PR_ALPM_CTL register definitions

[Jouni Högander]

Add PR_ALPM_CTL register definition and bits for it.

Bspec: 71014
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 795e6b9cc575c..aad3ac5f502ed 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -266,6 +266,16 @@
 #define _PIPE_SRCSZ_ERLY_TPT_B	0x71074
 #define PIPE_SRCSZ_ERLY_TPT(pipe)	_MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
 
+#define _PR_ALPM_CTL_A	0x60948
+#define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)
+#define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)
+#define  PR_ALPM_CTL_RFB_UPDATE_CONTROL				BIT(5)
+#define  PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE	BIT(4)
+#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK		REG_GENMASK(1, 0)
+#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2	REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)
+#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)
+#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)
+
 #define _ALPM_CTL_A	0x60950
 #define ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
 #define  ALPM_CTL_ALPM_ENABLE				REG_BIT(31)
-- 
2.43.0

Re: [PATCH 03/11] drm/i915/alpm: Add PR_ALPM_CTL register definitions

[Nautiyal, Ankit K]

On 5/2/2025 2:28 PM, Jouni Högander wrote:
> Add PR_ALPM_CTL register definition and bits for it.
>
> Bspec: 71014
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 795e6b9cc575c..aad3ac5f502ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -266,6 +266,16 @@
>   #define _PIPE_SRCSZ_ERLY_TPT_B	0x71074
>   #define PIPE_SRCSZ_ERLY_TPT(pipe)	_MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
>   
> +#define _PR_ALPM_CTL_A	0x60948
> +#define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)
> +#define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)
> +#define  PR_ALPM_CTL_RFB_UPDATE_CONTROL				BIT(5)
> +#define  PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE	BIT(4)
> +#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK		REG_GENMASK(1, 0)
> +#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2	REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)
> +#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)
> +#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)
> +
>   #define _ALPM_CTL_A	0x60950
>   #define ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
>   #define  ALPM_CTL_ALPM_ENABLE				REG_BIT(31)

[PATCH 04/11] drm/i915/alpm: Write PR_ALPM_CTL register

[Jouni Högander]

PR_ALPM_CTL register contains configurations related to Adaptive sync
sdp. Configure these if Adaptive Sync SDP is supported.

Bspec: 71014
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 1bf08b80c23f9..5e5bc91ca7b76 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -348,6 +348,18 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
 			ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);
 
+		if (intel_dp->as_sdp_supported) {
+			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+
+			if (intel_dp->pr_dpcd[1] & DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)
+				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
+			if (!(intel_dp->pr_dpcd[1] & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
+				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
+
+			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
+				       pr_alpm_ctl);
+		}
+
 		intel_de_write(display,
 			       PORT_ALPM_CTL(port),
 			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
-- 
2.43.0

Re: [PATCH 04/11] drm/i915/alpm: Write PR_ALPM_CTL register

[Nautiyal, Ankit K]

On 5/2/2025 2:28 PM, Jouni Högander wrote:
> PR_ALPM_CTL register contains configurations related to Adaptive sync
> sdp. Configure these if Adaptive Sync SDP is supported.
>
> Bspec: 71014
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 1bf08b80c23f9..5e5bc91ca7b76 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -348,6 +348,18 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
>   			ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);
>   
> +		if (intel_dp->as_sdp_supported) {
> +			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +
> +			if (intel_dp->pr_dpcd[1] & DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)

Can use pr_dpcd [DP_PANEL_REPLAY_CAPABILITY - 
DP_PANEL_REPLAY_CAP_SUPPORT] to avoid hardcoded index.


> +				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> +			if (!(intel_dp->pr_dpcd[1] & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))

Same as above.

Apart from the above, patch looks good to me.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

> +				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> +
> +			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> +				       pr_alpm_ctl);
> +		}
> +
>   		intel_de_write(display,
>   			       PORT_ALPM_CTL(port),
>   			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |

Re: [PATCH 04/11] drm/i915/alpm: Write PR_ALPM_CTL register

[Hogander, Jouni]

On Tue, 2025-05-20 at 14:19 +0530, Nautiyal, Ankit K wrote:
> 
> On 5/2/2025 2:28 PM, Jouni Högander wrote:
> > PR_ALPM_CTL register contains configurations related to Adaptive
> > sync
> > sdp. Configure these if Adaptive Sync SDP is supported.
> > 
> > Bspec: 71014
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_alpm.c | 12 ++++++++++++
> >   1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 1bf08b80c23f9..5e5bc91ca7b76 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -348,6 +348,18 @@ static void lnl_alpm_configure(struct intel_dp
> > *intel_dp,
> >   			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBO
> > LS |
> >   			ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp-
> > >alpm_parameters.aux_less_wake_lines);
> >   
> > +		if (intel_dp->as_sdp_supported) {
> > +			u32 pr_alpm_ctl =
> > PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> > +
> > +			if (intel_dp->pr_dpcd[1] &
> > DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)
> 
> Can use pr_dpcd [DP_PANEL_REPLAY_CAPABILITY - 
> DP_PANEL_REPLAY_CAP_SUPPORT] to avoid hardcoded index.
> 
> 
> > +				pr_alpm_ctl |=
> > PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> > +			if (!(intel_dp->pr_dpcd[1] &
> > DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
> 
> Same as above.
> 
> Apart from the above, patch looks good to me.

These are changed as per your suggestion. Thank you for your review.

BR,

Jouni Högander

> 
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> > +				pr_alpm_ctl |=
> > PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> > +
> > +			intel_de_write(display,
> > PR_ALPM_CTL(display, cpu_transcoder),
> > +				       pr_alpm_ctl);
> > +		}
> > +
> >   		intel_de_write(display,
> >   			       PORT_ALPM_CTL(port),
> >   			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE
> > |

[PATCH 05/11] drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSR

[Jouni Högander]

Currently we spread ugly PSR details into ALPM code to check if AUXLess
ALPM is needed. Prepare to hide these details to PSR code by adding new
interface for checking if AUXLess ALPM is needed.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_psr.h |  2 ++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2d78d64b8db8d..8d8fe1c34479d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4227,3 +4227,17 @@ bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_sta
 	return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
 					     crtc_state->has_panel_replay);
 }
+
+/**
+ * intel_psr_needs_alpm_aux_less - Check if PSR needs ALPM AUXLess
+ * @intel_dp: Intel DP
+ * @crtc_state: CRTC status
+ *
+ * This returns true if PSR needs AUXLess ALPM. I.e. if it's Panel Replay in
+ * eDP.
+ */
+bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
+				   const struct intel_crtc_state *crtc_state)
+{
+	return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 73c3fa40844bc..0cf53184f13f9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -77,5 +77,7 @@ int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state);
 void intel_psr_connector_debugfs_add(struct intel_connector *connector);
 void intel_psr_debugfs_register(struct intel_display *display);
 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
+bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
+				   const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_PSR_H__ */
-- 
2.43.0

Re: [PATCH 05/11] drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSR

[Nautiyal, Ankit K]

On 5/2/2025 2:28 PM, Jouni Högander wrote:
> Currently we spread ugly PSR details into ALPM code to check if AUXLess
> ALPM is needed. Prepare to hide these details to PSR code by adding new
> interface for checking if AUXLess ALPM is needed.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++++++
>   drivers/gpu/drm/i915/display/intel_psr.h |  2 ++
>   2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2d78d64b8db8d..8d8fe1c34479d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -4227,3 +4227,17 @@ bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_sta
>   	return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
>   					     crtc_state->has_panel_replay);
>   }
> +
> +/**
> + * intel_psr_needs_alpm_aux_less - Check if PSR needs ALPM AUXLess
> + * @intel_dp: Intel DP
> + * @crtc_state: CRTC status

I think you mean crtc state.


> + *
> + * This returns true if PSR needs AUXLess ALPM. I.e. if it's Panel Replay in
> + * eDP.

Lets use `Return:` as per kernel docs.

Patch LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

> + */
> +bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
> +				   const struct intel_crtc_state *crtc_state)
> +{
> +	return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 73c3fa40844bc..0cf53184f13f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -77,5 +77,7 @@ int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state);
>   void intel_psr_connector_debugfs_add(struct intel_connector *connector);
>   void intel_psr_debugfs_register(struct intel_display *display);
>   bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
> +bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
> +				   const struct intel_crtc_state *crtc_state);
>   
>   #endif /* __INTEL_PSR_H__ */

Re: [PATCH 05/11] drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSR

[Nautiyal, Ankit K]

On 5/20/2025 2:22 PM, Nautiyal, Ankit K wrote:
>
> On 5/2/2025 2:28 PM, Jouni Högander wrote:
>> Currently we spread ugly PSR details into ALPM code to check if AUXLess
>> ALPM is needed. Prepare to hide these details to PSR code by adding new
>> interface for checking if AUXLess ALPM is needed.
>>
>> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_psr.h |  2 ++
>>   2 files changed, 16 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 2d78d64b8db8d..8d8fe1c34479d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -4227,3 +4227,17 @@ bool intel_psr_needs_alpm(struct intel_dp 
>> *intel_dp, const struct intel_crtc_sta
>>       return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
>>                            crtc_state->has_panel_replay);
>>   }
>> +
>> +/**
>> + * intel_psr_needs_alpm_aux_less - Check if PSR needs ALPM AUXLess
>> + * @intel_dp: Intel DP
>> + * @crtc_state: CRTC status
>
> I think you mean crtc state.
>
>
>> + *
>> + * This returns true if PSR needs AUXLess ALPM. I.e. if it's Panel 
>> Replay in
>> + * eDP.
>
> Lets use `Return:` as per kernel docs.

Or we can just drop the kernel doc comments, and have regular comments 
for smaller helpers like this.

Same for the subsequent patches.

Regards,

Ankit

>
> Patch LGTM.
>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
>> + */
>> +bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>> +                   const struct intel_crtc_state *crtc_state)
>> +{
>> +    return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h 
>> b/drivers/gpu/drm/i915/display/intel_psr.h
>> index 73c3fa40844bc..0cf53184f13f9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>> @@ -77,5 +77,7 @@ int intel_psr_min_vblank_delay(const struct 
>> intel_crtc_state *crtc_state);
>>   void intel_psr_connector_debugfs_add(struct intel_connector 
>> *connector);
>>   void intel_psr_debugfs_register(struct intel_display *display);
>>   bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct 
>> intel_crtc_state *crtc_state);
>> +bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>> +                   const struct intel_crtc_state *crtc_state);
>>     #endif /* __INTEL_PSR_H__ */

Re: [PATCH 05/11] drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSR

[Hogander, Jouni]

On Tue, 2025-05-20 at 14:22 +0530, Nautiyal, Ankit K wrote:
> 
> On 5/2/2025 2:28 PM, Jouni Högander wrote:
> > Currently we spread ugly PSR details into ALPM code to check if
> > AUXLess
> > ALPM is needed. Prepare to hide these details to PSR code by adding
> > new
> > interface for checking if AUXLess ALPM is needed.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++++++
> >   drivers/gpu/drm/i915/display/intel_psr.h |  2 ++
> >   2 files changed, 16 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 2d78d64b8db8d..8d8fe1c34479d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -4227,3 +4227,17 @@ bool intel_psr_needs_alpm(struct intel_dp
> > *intel_dp, const struct intel_crtc_sta
> >   	return intel_dp_is_edp(intel_dp) && (crtc_state-
> > >has_sel_update ||
> >   					     crtc_state-
> > >has_panel_replay);
> >   }
> > +
> > +/**
> > + * intel_psr_needs_alpm_aux_less - Check if PSR needs ALPM AUXLess
> > + * @intel_dp: Intel DP
> > + * @crtc_state: CRTC status
> 
> I think you mean crtc state.
> 
> 
> > + *
> > + * This returns true if PSR needs AUXLess ALPM. I.e. if it's Panel
> > Replay in
> > + * eDP.
> 
> Lets use `Return:` as per kernel docs.

Dropped kerneldoc comments.

BR,

Jouni Högander

> 
> Patch LGTM.
> 
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> > + */
> > +bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
> > +				   const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +	return intel_dp_is_edp(intel_dp) && crtc_state-
> > >has_panel_replay;
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 73c3fa40844bc..0cf53184f13f9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -77,5 +77,7 @@ int intel_psr_min_vblank_delay(const struct
> > intel_crtc_state *crtc_state);
> >   void intel_psr_connector_debugfs_add(struct intel_connector
> > *connector);
> >   void intel_psr_debugfs_register(struct intel_display *display);
> >   bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct
> > intel_crtc_state *crtc_state);
> > +bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
> > +				   const struct intel_crtc_state
> > *crtc_state);
> >   
> >   #endif /* __INTEL_PSR_H__ */

[PATCH 06/11] drm/i915/alpm: Add new interface to check if AUXLess ALPM is used

[Jouni Högander]

we need to know if AUXLess ALPM is used when preparing for link
training. Add new interface for this and use it in existing code where
possible.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 18 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_alpm.h |  2 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 5e5bc91ca7b76..4a8d4b34fa89e 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -26,6 +26,21 @@ bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
 	return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
 }
 
+/**
+ * intel_alpm_is_alpm_aux_less - Check if AUXLess ALPM is used
+ * @intel_dp: Intel DP
+ * @crtc_state: CRTC status
+ *
+ * Check if AUXLess ALPM is used by LOBF (Link Off Between Frames) or by PSR
+ * (Panel Self Refresh)
+ */
+bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
+{
+	return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||
+		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
+}
+
 void intel_alpm_init(struct intel_dp *intel_dp)
 {
 	u8 dpcd;
@@ -341,8 +356,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to
 	 * check panel support at this point.
 	 */
-	if ((crtc_state->has_panel_replay && intel_dp_is_edp(intel_dp)) ||
-	    (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp))) {
+	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
 		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
 			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
 			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index d7126d65b60fb..83bbe0b7ff100 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -30,6 +30,8 @@ void intel_alpm_post_plane_update(struct intel_atomic_state *state,
 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
 bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
+bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state);
 void intel_alpm_disable(struct intel_dp *intel_dp);
 bool intel_alpm_get_error(struct intel_dp *intel_dp);
 #endif
-- 
2.43.0

Re: [PATCH 06/11] drm/i915/alpm: Add new interface to check if AUXLess ALPM is used

[Nautiyal, Ankit K]

On 5/2/2025 2:28 PM, Jouni Högander wrote:
> we need to know if AUXLess ALPM is used when preparing for link
> training. Add new interface for this and use it in existing code where
> possible.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c | 18 ++++++++++++++++--
>   drivers/gpu/drm/i915/display/intel_alpm.h |  2 ++
>   2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 5e5bc91ca7b76..4a8d4b34fa89e 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -26,6 +26,21 @@ bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
>   	return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
>   }
>   
> +/**
> + * intel_alpm_is_alpm_aux_less - Check if AUXLess ALPM is used
> + * @intel_dp: Intel DP
> + * @crtc_state: CRTC status

crtc state


> + *
> + * Check if AUXLess ALPM is used by LOBF (Link Off Between Frames) or by PSR
> + * (Panel Self Refresh)

Similar to comment in previous patch lets use `Return:` in line with 
kernel doc.

Patch LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

> + */
> +bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
> +				 const struct intel_crtc_state *crtc_state)
> +{
> +	return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||
> +		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
> +}
> +
>   void intel_alpm_init(struct intel_dp *intel_dp)
>   {
>   	u8 dpcd;
> @@ -341,8 +356,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   	 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to
>   	 * check panel support at this point.
>   	 */
> -	if ((crtc_state->has_panel_replay && intel_dp_is_edp(intel_dp)) ||
> -	    (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp))) {
> +	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
>   		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
>   			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
>   			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
> index d7126d65b60fb..83bbe0b7ff100 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -30,6 +30,8 @@ void intel_alpm_post_plane_update(struct intel_atomic_state *state,
>   void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
>   bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
>   bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
> +bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
> +				 const struct intel_crtc_state *crtc_state);
>   void intel_alpm_disable(struct intel_dp *intel_dp);
>   bool intel_alpm_get_error(struct intel_dp *intel_dp);
>   #endif

Re: [PATCH 06/11] drm/i915/alpm: Add new interface to check if AUXLess ALPM is used

[Hogander, Jouni]

On Tue, 2025-05-20 at 14:24 +0530, Nautiyal, Ankit K wrote:
> 
> On 5/2/2025 2:28 PM, Jouni Högander wrote:
> > we need to know if AUXLess ALPM is used when preparing for link
> > training. Add new interface for this and use it in existing code
> > where
> > possible.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_alpm.c | 18 ++++++++++++++++--
> >   drivers/gpu/drm/i915/display/intel_alpm.h |  2 ++
> >   2 files changed, 18 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 5e5bc91ca7b76..4a8d4b34fa89e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -26,6 +26,21 @@ bool intel_alpm_aux_less_wake_supported(struct
> > intel_dp *intel_dp)
> >   	return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
> >   }
> >   
> > +/**
> > + * intel_alpm_is_alpm_aux_less - Check if AUXLess ALPM is used
> > + * @intel_dp: Intel DP
> > + * @crtc_state: CRTC status
> 
> crtc state
> 
> 
> > + *
> > + * Check if AUXLess ALPM is used by LOBF (Link Off Between Frames)
> > or by PSR
> > + * (Panel Self Refresh)
> 
> Similar to comment in previous patch lets use `Return:` in line with 
> kernel doc.

Decided to left out these kernel doc comments completely on this patch
as well. Thank you for you review.

BR,

Jouni Högander

> 
> Patch LGTM.
> 
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> > + */
> > +bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
> > +				 const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +	return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)
> > ||
> > +		(crtc_state->has_lobf &&
> > intel_alpm_aux_less_wake_supported(intel_dp));
> > +}
> > +
> >   void intel_alpm_init(struct intel_dp *intel_dp)
> >   {
> >   	u8 dpcd;
> > @@ -341,8 +356,7 @@ static void lnl_alpm_configure(struct intel_dp
> > *intel_dp,
> >   	 * Panel Replay on eDP is always using ALPM aux less. I.e.
> > no need to
> >   	 * check panel support at this point.
> >   	 */
> > -	if ((crtc_state->has_panel_replay &&
> > intel_dp_is_edp(intel_dp)) ||
> > -	    (crtc_state->has_lobf &&
> > intel_alpm_aux_less_wake_supported(intel_dp))) {
> > +	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
> >   		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
> >   			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
> >   			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBO
> > LS |
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index d7126d65b60fb..83bbe0b7ff100 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -30,6 +30,8 @@ void intel_alpm_post_plane_update(struct
> > intel_atomic_state *state,
> >   void intel_alpm_lobf_debugfs_add(struct intel_connector
> > *connector);
> >   bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
> >   bool intel_alpm_aux_less_wake_supported(struct intel_dp
> > *intel_dp);
> > +bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
> > +				 const struct intel_crtc_state
> > *crtc_state);
> >   void intel_alpm_disable(struct intel_dp *intel_dp);
> >   bool intel_alpm_get_error(struct intel_dp *intel_dp);
> >   #endif

[PATCH 07/11] drm/i915/alpm: Move port alpm configuration

[Jouni Högander]

It is specified in Bspec where port alpm configuration is supposed to be
performed. Change accordingly.

HAS: 14012758795
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c    | 53 +++++++++++++-------
 drivers/gpu/drm/i915/display/intel_alpm.h    |  2 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  1 +
 drivers/gpu/drm/i915/display/intel_ddi.c     |  6 +++
 4 files changed, 44 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 4a8d4b34fa89e..857ce83075d8d 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -344,7 +344,6 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	enum port port = dp_to_dig_port(intel_dp)->base.port;
 	u32 alpm_ctl;
 
 	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
@@ -374,23 +373,6 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 				       pr_alpm_ctl);
 		}
 
-		intel_de_write(display,
-			       PORT_ALPM_CTL(port),
-			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
-			       PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
-			       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
-			       PORT_ALPM_CTL_SILENCE_PERIOD(
-				       intel_dp->alpm_parameters.silence_period_sym_clocks));
-
-		intel_de_write(display,
-			       PORT_ALPM_LFPS_CTL(port),
-			       PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
-			       PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
-				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
-			       PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
-				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
-			       PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
-				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms));
 	} else {
 		alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
 			ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);
@@ -414,6 +396,41 @@ void intel_alpm_configure(struct intel_dp *intel_dp,
 	intel_dp->alpm_parameters.transcoder = crtc_state->cpu_transcoder;
 }
 
+/**
+ * intel_alpm_port_configure - Port ALPM configuration
+ * @intel_dp: Intel DP
+ * @crtc_state: CRTC state
+ *
+ * Perfrom port ALPM configuration based on crtc_state setup. This is called as
+ * a part of link training preparation.
+ */
+void intel_alpm_port_configure(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	enum port port = dp_to_dig_port(intel_dp)->base.port;
+	u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
+
+	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+		alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
+			PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
+			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
+			PORT_ALPM_CTL_SILENCE_PERIOD(
+				intel_dp->alpm_parameters.silence_period_sym_clocks);
+		lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
+			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
+				intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
+			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
+				intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
+			PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
+				intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms);
+	}
+
+	intel_de_write(display, PORT_ALPM_CTL(port), alpm_ctl_val);
+
+	intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val);
+}
+
 void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
 				 struct intel_crtc *crtc)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 83bbe0b7ff100..c9ddb2113fe0d 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -25,6 +25,8 @@ void intel_alpm_configure(struct intel_dp *intel_dp,
 			  const struct intel_crtc_state *crtc_state);
 void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
 				 struct intel_crtc *crtc);
+void intel_alpm_port_configure(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state);
 void intel_alpm_post_plane_update(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc);
 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b09f724c3046b..1318886e34dd7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -10,6 +10,7 @@
 
 #include "i915_reg.h"
 #include "i915_utils.h"
+#include "intel_alpm.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 74132c1d63858..ce7a4765b10ea 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3743,6 +3743,12 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 
 	intel_ddi_buf_enable(encoder, intel_dp->DP);
 	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
+
+	/*
+	 * 6.k If AUX-Less ALPM is going to be enabled
+	 *     i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here
+	 */
+	intel_alpm_port_configure(intel_dp, crtc_state);
 }
 
 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
-- 
2.43.0

Re: [PATCH 07/11] drm/i915/alpm: Move port alpm configuration

[Nautiyal, Ankit K]

On 5/2/2025 2:28 PM, Jouni Högander wrote:
> It is specified in Bspec where port alpm configuration is supposed to be
> performed. Change accordingly.
>
> HAS: 14012758795
Lets drop references to HAS and add Bspec: 68849
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c    | 53 +++++++++++++-------
>   drivers/gpu/drm/i915/display/intel_alpm.h    |  2 +
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c |  1 +
>   drivers/gpu/drm/i915/display/intel_ddi.c     |  6 +++
>   4 files changed, 44 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 4a8d4b34fa89e..857ce83075d8d 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -344,7 +344,6 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   {
>   	struct intel_display *display = to_intel_display(intel_dp);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -	enum port port = dp_to_dig_port(intel_dp)->base.port;
>   	u32 alpm_ctl;
>   
>   	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
> @@ -374,23 +373,6 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   				       pr_alpm_ctl);
>   		}
>   
> -		intel_de_write(display,
> -			       PORT_ALPM_CTL(port),
> -			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
> -			       PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
> -			       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
> -			       PORT_ALPM_CTL_SILENCE_PERIOD(
> -				       intel_dp->alpm_parameters.silence_period_sym_clocks));
> -
> -		intel_de_write(display,
> -			       PORT_ALPM_LFPS_CTL(port),
> -			       PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
> -			       PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
> -				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
> -			       PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
> -				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
> -			       PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
> -				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms));
>   	} else {
>   		alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
>   			ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);
> @@ -414,6 +396,41 @@ void intel_alpm_configure(struct intel_dp *intel_dp,
>   	intel_dp->alpm_parameters.transcoder = crtc_state->cpu_transcoder;
>   }
>   
> +/**
> + * intel_alpm_port_configure - Port ALPM configuration
> + * @intel_dp: Intel DP
> + * @crtc_state: CRTC state
> + *
> + * Perfrom port ALPM configuration based on crtc_state setup. This is called as
> + * a part of link training preparation.
> + */
> +void intel_alpm_port_configure(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	enum port port = dp_to_dig_port(intel_dp)->base.port;
> +	u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
> +
> +	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
> +		alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
> +			PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
> +			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
> +			PORT_ALPM_CTL_SILENCE_PERIOD(
> +				intel_dp->alpm_parameters.silence_period_sym_clocks);
> +		lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
> +			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
> +				intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
> +			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
> +				intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
> +			PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
> +				intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms);
> +	}
> +
> +	intel_de_write(display, PORT_ALPM_CTL(port), alpm_ctl_val);
> +
> +	intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val);
> +}
> +
>   void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
>   				 struct intel_crtc *crtc)
>   {
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 83bbe0b7ff100..c9ddb2113fe0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -25,6 +25,8 @@ void intel_alpm_configure(struct intel_dp *intel_dp,
>   			  const struct intel_crtc_state *crtc_state);
>   void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
>   				 struct intel_crtc *crtc);
> +void intel_alpm_port_configure(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state);
>   void intel_alpm_post_plane_update(struct intel_atomic_state *state,
>   				  struct intel_crtc *crtc);
>   void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index b09f724c3046b..1318886e34dd7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -10,6 +10,7 @@
>   
>   #include "i915_reg.h"
>   #include "i915_utils.h"
> +#include "intel_alpm.h"
>   #include "intel_cx0_phy.h"
>   #include "intel_cx0_phy_regs.h"
>   #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 74132c1d63858..ce7a4765b10ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3743,6 +3743,12 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>   
>   	intel_ddi_buf_enable(encoder, intel_dp->DP);
>   	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> +
> +	/*
> +	 * 6.k If AUX-Less ALPM is going to be enabled
> +	 *     i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here
> +	 */
> +	intel_alpm_port_configure(intel_dp, crtc_state);

I think we should add a check to ensure this code runs only on LNL+ 
platforms (which supports ALPM).

Otherwise, we might end up writing 
|PORT_ALPM_CTL|and|PORT_ALPM_LFPS_CTL| that are not defined on earlier 
platforms, which could lead to unintended behavior.

Regards,

Ankit

>   }
>   
>   static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,

Re: [PATCH 07/11] drm/i915/alpm: Move port alpm configuration

[Hogander, Jouni]

On Tue, 2025-05-20 at 14:30 +0530, Nautiyal, Ankit K wrote:
> 
> On 5/2/2025 2:28 PM, Jouni Högander wrote:
> > It is specified in Bspec where port alpm configuration is supposed
> > to be
> > performed. Change accordingly.
> > 
> > HAS: 14012758795
> Lets drop references to HAS and add Bspec: 68849

I have changed this.

> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_alpm.c    | 53 +++++++++++++--
> > -----
> >   drivers/gpu/drm/i915/display/intel_alpm.h    |  2 +
> >   drivers/gpu/drm/i915/display/intel_cx0_phy.c |  1 +
> >   drivers/gpu/drm/i915/display/intel_ddi.c     |  6 +++
> >   4 files changed, 44 insertions(+), 18 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 4a8d4b34fa89e..857ce83075d8d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -344,7 +344,6 @@ static void lnl_alpm_configure(struct intel_dp
> > *intel_dp,
> >   {
> >   	struct intel_display *display =
> > to_intel_display(intel_dp);
> >   	enum transcoder cpu_transcoder = crtc_state-
> > >cpu_transcoder;
> > -	enum port port = dp_to_dig_port(intel_dp)->base.port;
> >   	u32 alpm_ctl;
> >   
> >   	if (DISPLAY_VER(display) < 20 ||
> > (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
> > @@ -374,23 +373,6 @@ static void lnl_alpm_configure(struct intel_dp
> > *intel_dp,
> >   				       pr_alpm_ctl);
> >   		}
> >   
> > -		intel_de_write(display,
> > -			       PORT_ALPM_CTL(port),
> > -			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE
> > |
> > -			      
> > PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
> > -			       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0)
> > |
> > -			       PORT_ALPM_CTL_SILENCE_PERIOD(
> > -				       intel_dp-
> > >alpm_parameters.silence_period_sym_clocks));
> > -
> > -		intel_de_write(display,
> > -			       PORT_ALPM_LFPS_CTL(port),
> > -			      
> > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
> > -			      
> > PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
> > -				       intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms) |
> > -			      
> > PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
> > -				       intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms) |
> > -			      
> > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
> > -				       intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms));
> >   	} else {
> >   		alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
> >   			ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp-
> > >alpm_parameters.fast_wake_lines);
> > @@ -414,6 +396,41 @@ void intel_alpm_configure(struct intel_dp
> > *intel_dp,
> >   	intel_dp->alpm_parameters.transcoder = crtc_state-
> > >cpu_transcoder;
> >   }
> >   
> > +/**
> > + * intel_alpm_port_configure - Port ALPM configuration
> > + * @intel_dp: Intel DP
> > + * @crtc_state: CRTC state
> > + *
> > + * Perfrom port ALPM configuration based on crtc_state setup. This
> > is called as
> > + * a part of link training preparation.
> > + */
> > +void intel_alpm_port_configure(struct intel_dp *intel_dp,
> > +			       const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +	struct intel_display *display =
> > to_intel_display(intel_dp);
> > +	enum port port = dp_to_dig_port(intel_dp)->base.port;
> > +	u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
> > +
> > +	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
> > +		alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE
> > |
> > +			PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
> > +			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
> > +			PORT_ALPM_CTL_SILENCE_PERIOD(
> > +				intel_dp-
> > >alpm_parameters.silence_period_sym_clocks);
> > +		lfps_ctl_val =
> > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
> > +			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATIO
> > N(
> > +				intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms) |
> > +			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_D
> > URATION(
> > +				intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms) |
> > +			PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DU
> > RATION(
> > +				intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms);
> > +	}
> > +
> > +	intel_de_write(display, PORT_ALPM_CTL(port),
> > alpm_ctl_val);
> > +
> > +	intel_de_write(display, PORT_ALPM_LFPS_CTL(port),
> > lfps_ctl_val);
> > +}
> > +
> >   void intel_alpm_pre_plane_update(struct intel_atomic_state
> > *state,
> >   				 struct intel_crtc *crtc)
> >   {
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index 83bbe0b7ff100..c9ddb2113fe0d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -25,6 +25,8 @@ void intel_alpm_configure(struct intel_dp
> > *intel_dp,
> >   			  const struct intel_crtc_state
> > *crtc_state);
> >   void intel_alpm_pre_plane_update(struct intel_atomic_state
> > *state,
> >   				 struct intel_crtc *crtc);
> > +void intel_alpm_port_configure(struct intel_dp *intel_dp,
> > +			       const struct intel_crtc_state
> > *crtc_state);
> >   void intel_alpm_post_plane_update(struct intel_atomic_state
> > *state,
> >   				  struct intel_crtc *crtc);
> >   void intel_alpm_lobf_debugfs_add(struct intel_connector
> > *connector);
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index b09f724c3046b..1318886e34dd7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -10,6 +10,7 @@
> >   
> >   #include "i915_reg.h"
> >   #include "i915_utils.h"
> > +#include "intel_alpm.h"
> >   #include "intel_cx0_phy.h"
> >   #include "intel_cx0_phy_regs.h"
> >   #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 74132c1d63858..ce7a4765b10ea 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3743,6 +3743,12 @@ static void
> > mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> >   
> >   	intel_ddi_buf_enable(encoder, intel_dp->DP);
> >   	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> > +
> > +	/*
> > +	 * 6.k If AUX-Less ALPM is going to be enabled
> > +	 *     i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL
> > here
> > +	 */
> > +	intel_alpm_port_configure(intel_dp, crtc_state);
> 
> I think we should add a check to ensure this code runs only on LNL+ 
> platforms (which supports ALPM).
> 
> Otherwise, we might end up writing 
> > PORT_ALPM_CTL|and|PORT_ALPM_LFPS_CTL| that are not defined on
> > earlier 
> platforms, which could lead to unintended behavior.

You are right. I have added display version check in recent version.
Thank you for pointing this out.

BR,

Jouni Högander

> 
> Regards,
> 
> Ankit
> 
> >   }
> >   
> >   static void intel_ddi_prepare_link_retrain(struct intel_dp
> > *intel_dp,

[PATCH 08/11] drm/i915/display: Add PHY_CMN1_CONTROL register definitions

[Jouni Högander]

Add PHY_CMN1_CONTROL register and its definitions to configure port LFPS
sending.

Bspec: 68962
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 960f7f778fb81..94b6384cdf019 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -278,6 +278,9 @@
 #define PHY_CX0_TX_CONTROL(tx, control)	(0x400 + ((tx) - 1) * 0x200 + (control))
 #define   CONTROL2_DISABLE_SINGLE_TX	REG_BIT(6)
 
+#define PHY_CMN1_CONTROL(tx, control)	(0x800 + ((tx) - 1) * 0x200 + (control))
+#define   CONTROL0_MAC_TRANSMIT_LFPS	REG_BIT(1)
+
 /* C20 Registers */
 #define PHY_C20_WR_ADDRESS_L		0xC02
 #define PHY_C20_WR_ADDRESS_H		0xC03
-- 
2.43.0

Re: [PATCH 08/11] drm/i915/display: Add PHY_CMN1_CONTROL register definitions

[Nautiyal, Ankit K]

On 5/2/2025 2:28 PM, Jouni Högander wrote:
> Add PHY_CMN1_CONTROL register and its definitions to configure port LFPS
> sending.
>
> Bspec: 68962
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 960f7f778fb81..94b6384cdf019 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -278,6 +278,9 @@
>   #define PHY_CX0_TX_CONTROL(tx, control)	(0x400 + ((tx) - 1) * 0x200 + (control))
>   #define   CONTROL2_DISABLE_SINGLE_TX	REG_BIT(6)
>   
> +#define PHY_CMN1_CONTROL(tx, control)	(0x800 + ((tx) - 1) * 0x200 + (control))
> +#define   CONTROL0_MAC_TRANSMIT_LFPS	REG_BIT(1)
> +
>   /* C20 Registers */
>   #define PHY_C20_WR_ADDRESS_L		0xC02
>   #define PHY_C20_WR_ADDRESS_H		0xC03

[PATCH 09/11] drm/i915/display: Add function to configure LFPS sending

[Jouni Högander]

Add function to configre LFPS sending for Panel Replay according to link
training sequence in HAS document.

This assumes we are using AUX Less always if it's supported by the sink and
the source.

HAS: 14012758795
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 29 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  2 ++
 drivers/gpu/drm/i915/display/intel_ddi.c     |  8 +++++-
 3 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1318886e34dd7..d8c1d372339c6 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3232,6 +3232,35 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
 		intel_cx0pll_enable(encoder, crtc_state);
 }
 
+/**
+ * intel_lnl_mac_transmit_lfps - Enable MAC transmitting LFPS
+ * @encoder: Intel encoder
+ * @crtc_state: Intel CRTC State
+ *
+ * Enable MAC transmitting LFPS in case of AUX Less ALPM.
+ */
+void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
+	bool enable = intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
+						  crtc_state);
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		int tx = i % 2 + 1;
+		u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+
+		if (!(owned_lane_mask & lane_mask))
+			continue;
+
+		intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0),
+			      CONTROL0_MAC_TRANSMIT_LFPS,
+			      enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0,
+			      MB_WRITE_COMMITTED);
+	}
+}
+
 static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index a8f811ca5e7bc..c5a7b529955b0 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -43,5 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 				     const struct intel_crtc_state *crtc_state);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
+void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ce7a4765b10ea..f8cdaae52ccfe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3745,10 +3745,16 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
 
 	/*
-	 * 6.k If AUX-Less ALPM is going to be enabled
+	 * 6.k If AUX-Less ALPM is going to be enabled:
 	 *     i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here
 	 */
 	intel_alpm_port_configure(intel_dp, crtc_state);
+
+	/*
+	 *     ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE
+	 *         register
+	 */
+	intel_lnl_mac_transmit_lfps(encoder, crtc_state);
 }
 
 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
-- 
2.43.0

Re: [PATCH 09/11] drm/i915/display: Add function to configure LFPS sending

[Nautiyal, Ankit K]

On 5/2/2025 2:29 PM, Jouni Högander wrote:
> Add function to configre LFPS sending for Panel Replay according to link
> training sequence in HAS document.
>
> This assumes we are using AUX Less always if it's supported by the sink and
> the source.
>
> HAS: 14012758795

Lets drop reference to HAS and just use Bspec: 68849


> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c | 29 ++++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_cx0_phy.h |  2 ++
>   drivers/gpu/drm/i915/display/intel_ddi.c     |  8 +++++-
>   3 files changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 1318886e34dd7..d8c1d372339c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3232,6 +3232,35 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
>   		intel_cx0pll_enable(encoder, crtc_state);
>   }
>   
> +/**
> + * intel_lnl_mac_transmit_lfps - Enable MAC transmitting LFPS
> + * @encoder: Intel encoder
> + * @crtc_state: Intel CRTC State
> + *
> + * Enable MAC transmitting LFPS in case of AUX Less ALPM.
> + */
> +void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> +				 const struct intel_crtc_state *crtc_state)
> +{
> +	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
> +	bool enable = intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> +						  crtc_state);
> +	int i;
> +
> +	for (i = 0; i < 4; i++) {
> +		int tx = i % 2 + 1;
> +		u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
> +
> +		if (!(owned_lane_mask & lane_mask))
> +			continue;

Similar loop is used in other place while writing other similar 
register. Would it make sense to use a macro?


> +
> +		intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0),
> +			      CONTROL0_MAC_TRANSMIT_LFPS,
> +			      enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0,
> +			      MB_WRITE_COMMITTED);
> +	}
> +}
> +
>   static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
>   {
>   	struct intel_display *display = to_intel_display(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index a8f811ca5e7bc..c5a7b529955b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -43,5 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
>   				     const struct intel_crtc_state *crtc_state);
>   int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
>   void intel_cx0_pll_power_save_wa(struct intel_display *display);
> +void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> +				 const struct intel_crtc_state *crtc_state);
>   
>   #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ce7a4765b10ea..f8cdaae52ccfe 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3745,10 +3745,16 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>   	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
>   
>   	/*
> -	 * 6.k If AUX-Less ALPM is going to be enabled
> +	 * 6.k If AUX-Less ALPM is going to be enabled:
>   	 *     i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here
>   	 */
>   	intel_alpm_port_configure(intel_dp, crtc_state);
> +
> +	/*
> +	 *     ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE
> +	 *         register
> +	 */
> +	intel_lnl_mac_transmit_lfps(encoder, crtc_state);

Here too a platform check should be there to avoid writing registers for 
older platforms.


Regards,

Ankit

>   }
>   
>   static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,

Re: [PATCH 09/11] drm/i915/display: Add function to configure LFPS sending

[Hogander, Jouni]

On Tue, 2025-05-20 at 14:38 +0530, Nautiyal, Ankit K wrote:
> 
> On 5/2/2025 2:29 PM, Jouni Högander wrote:
> > Add function to configre LFPS sending for Panel Replay according to
> > link
> > training sequence in HAS document.
> > 
> > This assumes we are using AUX Less always if it's supported by the
> > sink and
> > the source.
> > 
> > HAS: 14012758795
> 
> Lets drop reference to HAS and just use Bspec: 68849
> 
> 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_cx0_phy.c | 29
> > ++++++++++++++++++++
> >   drivers/gpu/drm/i915/display/intel_cx0_phy.h |  2 ++
> >   drivers/gpu/drm/i915/display/intel_ddi.c     |  8 +++++-
> >   3 files changed, 38 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 1318886e34dd7..d8c1d372339c6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -3232,6 +3232,35 @@ void intel_mtl_pll_enable(struct
> > intel_encoder *encoder,
> >   		intel_cx0pll_enable(encoder, crtc_state);
> >   }
> >   
> > +/**
> > + * intel_lnl_mac_transmit_lfps - Enable MAC transmitting LFPS
> > + * @encoder: Intel encoder
> > + * @crtc_state: Intel CRTC State
> > + *
> > + * Enable MAC transmitting LFPS in case of AUX Less ALPM.
> > + */
> > +void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> > +				 const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +	u8 owned_lane_mask =
> > intel_cx0_get_owned_lane_mask(encoder);
> > +	bool enable =
> > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> > +						  crtc_state);
> > +	int i;
> > +
> > +	for (i = 0; i < 4; i++) {
> > +		int tx = i % 2 + 1;
> > +		u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
> > INTEL_CX0_LANE1;
> > +
> > +		if (!(owned_lane_mask & lane_mask))
> > +			continue;
> 
> Similar loop is used in other place while writing other similar 
> register. Would it make sense to use a macro?
> 
> 
> > +
> > +		intel_cx0_rmw(encoder, lane_mask,
> > PHY_CMN1_CONTROL(tx, 0),
> > +			      CONTROL0_MAC_TRANSMIT_LFPS,
> > +			      enable ? CONTROL0_MAC_TRANSMIT_LFPS
> > : 0,
> > +			      MB_WRITE_COMMITTED);
> > +	}
> > +}
> > +
> >   static u8 cx0_power_control_disable_val(struct intel_encoder
> > *encoder)
> >   {
> >   	struct intel_display *display = to_intel_display(encoder);
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > index a8f811ca5e7bc..c5a7b529955b0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -43,5 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct
> > intel_encoder *encoder,
> >   				     const struct intel_crtc_state
> > *crtc_state);
> >   int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
> >   void intel_cx0_pll_power_save_wa(struct intel_display *display);
> > +void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> > +				 const struct intel_crtc_state
> > *crtc_state);
> >   
> >   #endif /* __INTEL_CX0_PHY_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index ce7a4765b10ea..f8cdaae52ccfe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3745,10 +3745,16 @@ static void
> > mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> >   	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> >   
> >   	/*
> > -	 * 6.k If AUX-Less ALPM is going to be enabled
> > +	 * 6.k If AUX-Less ALPM is going to be enabled:
> >   	 *     i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL
> > here
> >   	 */
> >   	intel_alpm_port_configure(intel_dp, crtc_state);
> > +
> > +	/*
> > +	 *     ii. Enable MAC Transmits LFPS in the "PHY Common
> > Control 0" PIPE
> > +	 *         register
> > +	 */
> > +	intel_lnl_mac_transmit_lfps(encoder, crtc_state);
> 
> Here too a platform check should be there to avoid writing registers
> for 
> older platforms.

I have added platform check. Please check latest version.

BR,

Jouni Högander

> 
> 
> Regards,
> 
> Ankit
> 
> >   }
> >   
> >   static void intel_ddi_prepare_link_retrain(struct intel_dp
> > *intel_dp,

[PATCH 10/11] drm/i915/psr: Fix using wrong mask in REG_FIELD_PREP

[Jouni Högander]

Wrong mask is used in PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and
PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION.

Fixes: 295099580f04 ("drm/i915/psr: Add missing ALPM AUX-Less register definitions")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index aad3ac5f502ed..8afbf5a383353 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -335,8 +335,8 @@
 #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(20, 16)
 #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
 #define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(12, 8)
-#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
+#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)
 #define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(4, 0)
-#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
+#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)
 
 #endif /* __INTEL_PSR_REGS_H__ */
-- 
2.43.0

Re: [PATCH 10/11] drm/i915/psr: Fix using wrong mask in REG_FIELD_PREP

[Nautiyal, Ankit K]

On 5/2/2025 2:29 PM, Jouni Högander wrote:
> Wrong mask is used in PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and
> PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION.
>
> Fixes: 295099580f04 ("drm/i915/psr: Add missing ALPM AUX-Less register definitions")
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index aad3ac5f502ed..8afbf5a383353 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -335,8 +335,8 @@
>   #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(20, 16)
>   #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
>   #define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(12, 8)
> -#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
> +#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)
>   #define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(4, 0)
> -#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
> +#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)
>   
>   #endif /* __INTEL_PSR_REGS_H__ */

[PATCH 11/11] drm/i915/psr: Do not disable Panel Replay in case VRR is enabled

[Jouni Högander]

This patch is allowing Panel Replay with VRR. All VRR modes are supposed to
work with Panel Replay.

Bspec: 68920, 68925
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8d8fe1c34479d..3657dd5800f9a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1572,6 +1572,12 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
 	if (!CAN_PSR(intel_dp))
 		return false;
 
+	/*
+	 * Currently PSR doesn't work reliably with VRR enabled.
+	 */
+	if (crtc_state->vrr.enable)
+		return false;
+
 	entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode);
 
 	if (entry_setup_frames >= 0) {
@@ -1689,12 +1695,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 		return;
 	}
 
-	/*
-	 * Currently PSR/PR doesn't work reliably with VRR enabled.
-	 */
-	if (crtc_state->vrr.enable)
-		return;
-
 	crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
 								    crtc_state,
 								    conn_state);
-- 
2.43.0

Re: [PATCH 11/11] drm/i915/psr: Do not disable Panel Replay in case VRR is enabled

[Nautiyal, Ankit K]

On 5/2/2025 2:29 PM, Jouni Högander wrote:
> This patch is allowing Panel Replay with VRR. All VRR modes are supposed to

Lets drop `patch` as it will no longer will remain patch after commit.


> work with Panel Replay.
>
> Bspec: 68920, 68925
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8d8fe1c34479d..3657dd5800f9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1572,6 +1572,12 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
>   	if (!CAN_PSR(intel_dp))
>   		return false;
>   
> +	/*
> +	 * Currently PSR doesn't work reliably with VRR enabled.
> +	 */
> +	if (crtc_state->vrr.enable)
> +		return false;
> +
>   	entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode);
>   
>   	if (entry_setup_frames >= 0) {
> @@ -1689,12 +1695,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>   		return;
>   	}
>   
> -	/*
> -	 * Currently PSR/PR doesn't work reliably with VRR enabled.
> -	 */
> -	if (crtc_state->vrr.enable)
> -		return;
> -
>   	crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
>   								    crtc_state,
>   								    conn_state);

✗ Fi.CI.CHECKPATCH: warning for Panel Replay + Adaptive sync

[Patchwork]

== Series Details ==

Series: Panel Replay + Adaptive sync
URL   : https://patchwork.freedesktop.org/series/148539/
State : warning

== Summary ==

Error: dim checkpatch failed
2fb125469e9e drm/dp: Add Panel Replay capability bits from DP2.1 specification
c882d05090c7 drm/i915/psr: Read both Panel Replay capability registers from DPCD
64c11e0b0388 drm/i915/alpm: Add PR_ALPM_CTL register definitions
-:28: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#28: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:275:
+#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2	REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)

-:29: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#29: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:276:
+#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)

-:30: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#30: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:277:
+#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)

total: 0 errors, 3 warnings, 0 checks, 16 lines checked
ecd3ed005310 drm/i915/alpm: Write PR_ALPM_CTL register
-:26: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#26: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:354:
+			if (intel_dp->pr_dpcd[1] & DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)

-:28: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#28: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:356:
+			if (!(intel_dp->pr_dpcd[1] & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))

total: 0 errors, 2 warnings, 0 checks, 18 lines checked
ddb7db6a0cd9 drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSR
b89a3d9b1fa6 drm/i915/alpm: Add new interface to check if AUXLess ALPM is used
cd1da4b4beae drm/i915/alpm: Move port alpm configuration
-:74: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#74: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:418:
+			PORT_ALPM_CTL_SILENCE_PERIOD(

-:77: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#77: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:421:
+			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(

-:79: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#79: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:423:
+			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(

-:81: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#81: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:425:
+			PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(

total: 0 errors, 0 warnings, 4 checks, 98 lines checked
373bd6677560 drm/i915/display: Add PHY_CMN1_CONTROL register definitions
63ab9d3971a2 drm/i915/display: Add function to configure LFPS sending
2b67d7ccc498 drm/i915/psr: Fix using wrong mask in REG_FIELD_PREP
-:24: WARNING:LONG_LINE: line length of 139 exceeds 100 columns
#24: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:338:
+#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)

-:27: WARNING:LONG_LINE: line length of 138 exceeds 100 columns
#27: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:340:
+#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)

total: 0 errors, 2 warnings, 0 checks, 10 lines checked
2ea4bc98f9ec drm/i915/psr: Do not disable Panel Replay in case VRR is enabled

✗ Fi.CI.SPARSE: warning for Panel Replay + Adaptive sync

[Patchwork]

== Series Details ==

Series: Panel Replay + Adaptive sync
URL   : https://patchwork.freedesktop.org/series/148539/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ i915.CI.BAT: success for Panel Replay + Adaptive sync

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3396 bytes --]

== Series Details ==

Series: Panel Replay + Adaptive sync
URL   : https://patchwork.freedesktop.org/series/148539/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16492 -> Patchwork_148539v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/index.html

Participating hosts (43 -> 42)
------------------------------

  Missing    (1): bat-adlp-9 

Known issues
------------

  Here are the changes found in Patchwork_148539v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests:
    - bat-apl-1:          [PASS][1] -> [INCOMPLETE][2] ([i915#12904]) +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/bat-apl-1/igt@dmabuf@all-tests.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/bat-apl-1/igt@dmabuf@all-tests.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-arls-6:         [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/bat-arls-6/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-2:         [DMESG-FAIL][7] ([i915#12061]) -> [PASS][8] +1 other test pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/bat-arlh-2/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/bat-arlh-2/igt@i915_selftest@live@workarounds.html
    - bat-dg2-14:         [DMESG-FAIL][9] ([i915#12061]) -> [PASS][10] +1 other test pass
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/bat-dg2-14/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [DMESG-FAIL][11] ([i915#12061]) -> [PASS][12] +1 other test pass
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904


Build changes
-------------

  * Linux: CI_DRM_16492 -> Patchwork_148539v1

  CI-20190529: 20190529
  CI_DRM_16492: 5303c0e49b49fe27639ba8b2c178931bc22344a2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8351: a994944173f1428dcf7247af03a821d51feae1cc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_148539v1: 5303c0e49b49fe27639ba8b2c178931bc22344a2 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/index.html

[-- Attachment #2: Type: text/html, Size: 4361 bytes --]

✗ i915.CI.Full: failure for Panel Replay + Adaptive sync

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 64989 bytes --]

== Series Details ==

Series: Panel Replay + Adaptive sync
URL   : https://patchwork.freedesktop.org/series/148539/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16492_full -> Patchwork_148539v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_148539v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_148539v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_148539v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_gttfill@engines@bcs0:
    - shard-dg2-9:        NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_exec_gttfill@engines@bcs0.html

  * igt@gem_exec_gttfill@engines@rcs0:
    - shard-dg2-9:        NOTRUN -> [ABORT][2] +1 other test abort
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_exec_gttfill@engines@rcs0.html

  * igt@i915_selftest@live@client:
    - shard-dg2:          [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-5/igt@i915_selftest@live@client.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-1/igt@i915_selftest@live@client.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-dg2-9:        NOTRUN -> [DMESG-WARN][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_pm_dc@dc9-dpms.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - shard-dg2:          [DMESG-FAIL][6] ([i915#12061]) -> [INCOMPLETE][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-5/igt@i915_selftest@live.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-1/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in Patchwork_148539v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@object-reloc-keep-cache:
    - shard-dg2:          NOTRUN -> [SKIP][8] ([i915#8411])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-rkl:          NOTRUN -> [SKIP][9] ([i915#8411]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#3555] / [i915#9323])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-rkl:          NOTRUN -> [SKIP][11] ([i915#9323])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          NOTRUN -> [SKIP][12] ([i915#7697])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-dg2-9:        NOTRUN -> [ABORT][13] ([i915#13427])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_ctx_persistence@heartbeat-close:
    - shard-dg2-9:        NOTRUN -> [SKIP][14] ([i915#8555])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_ctx_persistence@heartbeat-close.html

  * igt@gem_ctx_sseu@engines:
    - shard-dg2:          NOTRUN -> [SKIP][15] ([i915#280])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_ctx_sseu@engines.html

  * igt@gem_eio@unwedge-stress:
    - shard-mtlp:         [PASS][16] -> [ABORT][17] ([i915#13193] / [i915#13723]) +2 other tests abort
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-mtlp-1/igt@gem_eio@unwedge-stress.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-mtlp-7/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-rkl:          NOTRUN -> [SKIP][18] ([i915#4525]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_flush@basic-uc-rw-default:
    - shard-dg2-9:        NOTRUN -> [SKIP][19] ([i915#3539] / [i915#4852])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_exec_flush@basic-uc-rw-default.html

  * igt@gem_exec_flush@basic-uc-set-default:
    - shard-dg2-9:        NOTRUN -> [SKIP][20] ([i915#3539])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_exec_flush@basic-uc-set-default.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-dg2-9:        NOTRUN -> [SKIP][21] ([i915#5107])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_exec_reloc@basic-cpu-wc-active:
    - shard-dg2-9:        NOTRUN -> [SKIP][22] ([i915#3281]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_exec_reloc@basic-cpu-wc-active.html

  * igt@gem_exec_reloc@basic-wc-read-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][23] ([i915#3281]) +9 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@gem_exec_reloc@basic-wc-read-noreloc.html

  * igt@gem_exec_reloc@basic-write-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#3281]) +5 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_exec_reloc@basic-write-gtt.html

  * igt@gem_fence_thrash@bo-write-verify-threaded-none:
    - shard-dg2-9:        NOTRUN -> [SKIP][25] ([i915#4860])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_fence_thrash@bo-write-verify-threaded-none.html

  * igt@gem_fence_thrash@bo-write-verify-y:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#4860])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_fence_thrash@bo-write-verify-y.html

  * igt@gem_lmem_swapping@verify:
    - shard-rkl:          NOTRUN -> [SKIP][27] ([i915#4613]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@gem_lmem_swapping@verify.html

  * igt@gem_media_fill@media-fill:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#8289])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@gem_media_fill@media-fill.html

  * igt@gem_media_vme:
    - shard-dg2:          NOTRUN -> [SKIP][29] ([i915#284])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_media_vme.html

  * igt@gem_mmap_gtt@bad-object:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#4077]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_mmap_gtt@bad-object.html

  * igt@gem_mmap_gtt@basic:
    - shard-dg2-9:        NOTRUN -> [SKIP][31] ([i915#4077]) +2 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_mmap_gtt@basic.html

  * igt@gem_mmap_wc@close:
    - shard-dg2:          NOTRUN -> [SKIP][32] ([i915#4083]) +3 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_mmap_wc@close.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#3282]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-rkl:          NOTRUN -> [SKIP][34] ([i915#3282]) +9 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_pxp@create-regular-context-1:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#4270]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_pxp@create-regular-context-1.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-rkl:          NOTRUN -> [TIMEOUT][36] ([i915#12917] / [i915#12964])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_pxp@verify-pxp-stale-buf-execution:
    - shard-dg2-9:        NOTRUN -> [SKIP][37] ([i915#4270]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_pxp@verify-pxp-stale-buf-execution.html

  * igt@gem_render_copy@yf-tiled-ccs-to-x-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#5190] / [i915#8428]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_render_copy@yf-tiled-ccs-to-x-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#4079])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][40] ([i915#3297]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@forbidden-operations:
    - shard-rkl:          NOTRUN -> [SKIP][41] ([i915#3282] / [i915#3297])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@gem_userptr_blits@forbidden-operations.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-dg2:          NOTRUN -> [SKIP][42] ([i915#3297] / [i915#4880])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-dg2-9:        NOTRUN -> [SKIP][43] ([i915#3297])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][44] ([i915#13356])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@gem_workarounds@suspend-resume-context.html

  * igt@gen3_render_tiledy_blits:
    - shard-dg2-9:        NOTRUN -> [SKIP][45] +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@gen3_render_tiledy_blits.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-rkl:          NOTRUN -> [SKIP][46] ([i915#2527]) +3 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@gen9_exec_parse@bb-start-out.html

  * igt@gen9_exec_parse@unaligned-access:
    - shard-dg2:          NOTRUN -> [SKIP][47] ([i915#2856]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@gen9_exec_parse@unaligned-access.html

  * igt@i915_drm_fdinfo@isolation@rcs0:
    - shard-dg2:          NOTRUN -> [SKIP][48] ([i915#14073]) +7 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@i915_drm_fdinfo@isolation@rcs0.html

  * igt@i915_drm_fdinfo@virtual-busy-idle:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#14118])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@i915_drm_fdinfo@virtual-busy-idle.html

  * igt@i915_fb_tiling@basic-x-tiling:
    - shard-dg2-9:        NOTRUN -> [SKIP][50] ([i915#13786])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@i915_fb_tiling@basic-x-tiling.html

  * igt@i915_module_load@resize-bar:
    - shard-rkl:          NOTRUN -> [SKIP][51] ([i915#6412])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-rkl:          NOTRUN -> [SKIP][52] ([i915#8399])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [PASS][53] -> [INCOMPLETE][54] ([i915#12455] / [i915#13820]) +1 other test incomplete
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-10/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-10/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#11681] / [i915#6621])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@i915_pm_sseu@full-enable:
    - shard-rkl:          NOTRUN -> [SKIP][56] ([i915#4387])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@i915_pm_sseu@full-enable.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [PASS][57] -> [SKIP][58] ([i915#7984])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-mtlp-5/igt@i915_power@sanity.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-mtlp-5/igt@i915_power@sanity.html

  * igt@intel_hwmon@hwmon-read:
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#7707])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#5190])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
    - shard-dg2-9:        NOTRUN -> [SKIP][61] ([i915#4212])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_addfb_basic@basic-x-tiled-legacy.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-a-hdmi-a-3-y-rc-ccs-cc:
    - shard-dg1:          NOTRUN -> [SKIP][62] ([i915#8709]) +3 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-12/igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-a-hdmi-a-3-y-rc-ccs-cc.html

  * igt@kms_atomic_interruptible@atomic-setmode:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][63] ([i915#12964]) +6 other tests dmesg-warn
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_atomic_interruptible@atomic-setmode.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-dg2:          NOTRUN -> [SKIP][64] ([i915#1769] / [i915#3555])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][65] ([i915#5286]) +4 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][66] +4 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][67] ([i915#3638]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-dg2-9:        NOTRUN -> [SKIP][68] ([i915#4538] / [i915#5190]) +4 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-dg2:          NOTRUN -> [SKIP][69] ([i915#4538] / [i915#5190]) +5 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2:
    - shard-dg2-9:        NOTRUN -> [SKIP][70] ([i915#10307] / [i915#6095]) +19 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([i915#14098] / [i915#6095]) +23 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][72] ([i915#4423] / [i915#6095])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-16/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][73] ([i915#12313])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][74] ([i915#10307] / [i915#6095]) +98 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-a-dp-3.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][75] ([i915#12313])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-2:
    - shard-glk:          NOTRUN -> [SKIP][76] +6 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-glk1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-c-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#6095]) +28 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-c-dp-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#12313])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][79] ([i915#6095]) +17 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][80] ([i915#6095]) +174 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-13/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][81] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-4/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition@pipe-b-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#13781]) +3 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_cdclk@mode-transition@pipe-b-dp-3.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#11151] / [i915#7828]) +6 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_edid@dp-mode-timings:
    - shard-dg2-9:        NOTRUN -> [SKIP][84] ([i915#11151] / [i915#7828])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_chamelium_edid@dp-mode-timings.html

  * igt@kms_chamelium_frames@vga-frame-dump:
    - shard-rkl:          NOTRUN -> [SKIP][85] ([i915#11151] / [i915#7828]) +6 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_chamelium_frames@vga-frame-dump.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-dg2-9:        NOTRUN -> [SKIP][86] ([i915#3299])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@legacy@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [FAIL][87] ([i915#7173])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_content_protection@legacy@pipe-a-dp-3.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([i915#9424])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@type1:
    - shard-dg2-9:        NOTRUN -> [SKIP][89] ([i915#7118] / [i915#9424])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#13049]) +2 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-dg2-9:        NOTRUN -> [SKIP][91] ([i915#13049])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#4103] / [i915#4213]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-dg2-9:        NOTRUN -> [SKIP][93] ([i915#13046] / [i915#5354])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][94] ([i915#13046] / [i915#5354]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-dg2:          NOTRUN -> [SKIP][95] ([i915#9067])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          NOTRUN -> [SKIP][96] ([i915#3555] / [i915#3804])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][97] ([i915#3804])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_aux_dev:
    - shard-dg2-9:        NOTRUN -> [SKIP][98] ([i915#1257])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_dp_aux_dev.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#13749])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-dg2:          NOTRUN -> [SKIP][100] ([i915#3555] / [i915#3840])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-rkl:          NOTRUN -> [SKIP][101] +16 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][102] ([i915#3955])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#4854])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-2x:
    - shard-dg2:          NOTRUN -> [SKIP][104] ([i915#1839])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@display-3x:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#1839])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-rkl:          NOTRUN -> [SKIP][106] ([i915#9337])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][107] ([i915#9934]) +3 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][108] ([i915#9934]) +3 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1:
    - shard-snb:          [PASS][109] -> [TIMEOUT][110] ([i915#14033]) +1 other test timeout
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-snb7/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-snb1/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1.html

  * igt@kms_flip@2x-flip-vs-wf_vblank:
    - shard-dg2-9:        NOTRUN -> [SKIP][111] ([i915#9934]) +2 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_flip@2x-flip-vs-wf_vblank.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-vga1:
    - shard-snb:          [PASS][112] -> [FAIL][113] ([i915#13734]) +1 other test fail
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-snb7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-vga1.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-snb4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-vga1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][114] ([i915#2672]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][115] ([i915#2672]) +2 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-dg2-9:        NOTRUN -> [SKIP][116] ([i915#2672] / [i915#3555] / [i915#5190])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
    - shard-dg2-9:        NOTRUN -> [SKIP][117] ([i915#2672]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-dg2-9:        NOTRUN -> [SKIP][118] ([i915#2672] / [i915#3555])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#2672] / [i915#3555]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][120] ([i915#2672] / [i915#3555])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][122] ([i915#5354]) +15 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][123] ([i915#1825]) +24 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-9:        NOTRUN -> [SKIP][124] ([i915#8708]) +3 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-dg2-9:        NOTRUN -> [SKIP][125] ([i915#3458]) +3 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#3458]) +11 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-rkl:          NOTRUN -> [SKIP][127] ([i915#3023]) +22 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][128] ([i915#8708]) +7 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite:
    - shard-dg2-9:        NOTRUN -> [SKIP][129] ([i915#5354]) +10 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#3555] / [i915#8228]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-dg2:          [PASS][131] -> [SKIP][132] ([i915#3555] / [i915#8228]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-11/igt@kms_hdr@bpc-switch-suspend.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-8/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-dg2:          NOTRUN -> [SKIP][133] ([i915#12713])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-dg2-9:        NOTRUN -> [SKIP][134] ([i915#13688])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#12339])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][136] ([i915#12388])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][137] ([i915#10656])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-dg2-9:        NOTRUN -> [SKIP][138] ([i915#13522])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2:          NOTRUN -> [SKIP][139] ([i915#13705])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-dg2:          NOTRUN -> [SKIP][140] ([i915#3555] / [i915#8821])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#13958])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-rkl:          NOTRUN -> [SKIP][142] ([i915#13958])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a:
    - shard-rkl:          NOTRUN -> [SKIP][143] ([i915#12247]) +16 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
    - shard-dg2-9:        NOTRUN -> [SKIP][144] ([i915#12247] / [i915#9423])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-d:
    - shard-dg2-9:        NOTRUN -> [SKIP][145] ([i915#12247]) +3 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-d.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
    - shard-rkl:          NOTRUN -> [SKIP][146] ([i915#12247] / [i915#3555])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][147] ([i915#12343])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg1:          NOTRUN -> [SKIP][148] ([i915#3361])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-14/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][149] ([i915#9519])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg2:          [PASS][150] -> [SKIP][151] ([i915#9519]) +2 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@i2c:
    - shard-dg1:          [PASS][152] -> [DMESG-WARN][153] ([i915#4423]) +1 other test dmesg-warn
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg1-12/igt@kms_pm_rpm@i2c.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-16/igt@kms_pm_rpm@i2c.html

  * igt@kms_prime@basic-crc-vgem:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#6524] / [i915#6805])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_prime@basic-crc-vgem.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          NOTRUN -> [SKIP][155] ([i915#6524])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-dg2-9:        NOTRUN -> [SKIP][156] ([i915#6524] / [i915#6805])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
    - shard-dg2-9:        NOTRUN -> [SKIP][157] ([i915#11520]) +2 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
    - shard-dg2:          NOTRUN -> [SKIP][158] ([i915#11520]) +3 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#11520]) +5 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#9683])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-pr-no-drrs:
    - shard-rkl:          NOTRUN -> [SKIP][161] ([i915#1072] / [i915#9732]) +19 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_psr@fbc-pr-no-drrs.html

  * igt@kms_psr@fbc-psr-primary-page-flip:
    - shard-dg2:          NOTRUN -> [SKIP][162] ([i915#1072] / [i915#9732]) +11 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_psr@fbc-psr-primary-page-flip.html

  * igt@kms_psr@psr-primary-mmap-cpu:
    - shard-dg2-9:        NOTRUN -> [SKIP][163] ([i915#1072] / [i915#9732]) +8 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_psr@psr-primary-mmap-cpu.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-dg2:          NOTRUN -> [SKIP][164] ([i915#12755])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-dg2-9:        NOTRUN -> [SKIP][165] ([i915#12755] / [i915#5190])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-dg2:          NOTRUN -> [SKIP][166] ([i915#3555]) +3 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#3555]) +4 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-rkl:          NOTRUN -> [SKIP][168] ([i915#8623])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@flip-dpms:
    - shard-dg2-9:        NOTRUN -> [SKIP][169] ([i915#3555])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@kms_vrr@flip-dpms.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][170] ([i915#2437] / [i915#9412])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-dg2:          NOTRUN -> [SKIP][171] ([i915#2437])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@perf@non-zero-reason:
    - shard-dg2-9:        NOTRUN -> [FAIL][172] ([i915#9100]) +1 other test fail
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@perf@non-zero-reason.html

  * igt@perf_pmu@module-unload:
    - shard-snb:          [PASS][173] -> [INCOMPLETE][174] ([i915#13520])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-snb5/igt@perf_pmu@module-unload.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-snb6/igt@perf_pmu@module-unload.html

  * igt@prime_vgem@basic-write:
    - shard-rkl:          NOTRUN -> [SKIP][175] ([i915#3291] / [i915#3708])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-3/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@coherency-gtt:
    - shard-dg2-9:        NOTRUN -> [SKIP][176] ([i915#3708] / [i915#4077])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-9/igt@prime_vgem@coherency-gtt.html

  * igt@prime_vgem@fence-write-hang:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([i915#3708])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-2/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-rkl:          NOTRUN -> [SKIP][178] ([i915#9917])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-rkl-8/igt@sriov_basic@enable-vfs-autoprobe-off.html

  
#### Possible fixes ####

  * igt@gem_ccs@suspend-resume:
    - shard-dg2:          [INCOMPLETE][179] ([i915#13356]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-4/igt@gem_ccs@suspend-resume.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@gem_ccs@suspend-resume.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          [INCOMPLETE][181] ([i915#12392]) -> [PASS][182]
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-4/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-dg1:          [FAIL][183] ([i915#3591]) -> [PASS][184] +1 other test pass
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-dg1:          [FAIL][185] ([i915#10991] / [i915#12518] / [i915#12766]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg1-18/igt@kms_async_flips@alternate-sync-async-flip.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-12/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-dg2:          [FAIL][187] ([i915#5956]) -> [PASS][188] +1 other test pass
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0:
    - shard-dg1:          [DMESG-WARN][189] ([i915#4423]) -> [PASS][190] +2 other tests pass
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg1-15/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-15/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-glk:          [SKIP][191] -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-glk4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-glk1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1:
    - shard-mtlp:         [FAIL][193] ([i915#13734]) -> [PASS][194] +2 other tests pass
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-mtlp-6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-mtlp-4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          [SKIP][195] ([i915#3555] / [i915#8228]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-8/igt@kms_hdr@static-toggle.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-dg2:          [SKIP][197] ([i915#12388]) -> [PASS][198]
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-4/igt@kms_joiner@basic-force-big-joiner.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-snb:          [DMESG-WARN][199] -> [PASS][200] +1 other test pass
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-snb4/igt@kms_plane@plane-panning-bottom-right-suspend.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-snb4/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2:          [SKIP][201] ([i915#9340]) -> [PASS][202]
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-11/igt@kms_pm_lpsp@kms-lpsp.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-8/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg2:          [SKIP][203] ([i915#9519]) -> [PASS][204]
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_setmode@basic:
    - shard-mtlp:         [FAIL][205] ([i915#5465]) -> [PASS][206] +1 other test pass
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-mtlp-5/igt@kms_setmode@basic.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-mtlp-8/igt@kms_setmode@basic.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1:
    - shard-mtlp:         [FAIL][207] ([i915#9196]) -> [PASS][208] +1 other test pass
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-mtlp-8/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-mtlp-6/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html

  * igt@perf_pmu@busy-hang@rcs0:
    - shard-mtlp:         [ABORT][209] ([i915#13193] / [i915#13723]) -> [PASS][210]
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-mtlp-7/igt@perf_pmu@busy-hang@rcs0.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-mtlp-7/igt@perf_pmu@busy-hang@rcs0.html

  * igt@perf_pmu@busy-hang@vecs0:
    - shard-mtlp:         [DMESG-WARN][211] ([i915#13723]) -> [PASS][212]
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-mtlp-7/igt@perf_pmu@busy-hang@vecs0.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-mtlp-7/igt@perf_pmu@busy-hang@vecs0.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic:
    - shard-dg2:          [FAIL][213] ([i915#7173]) -> [SKIP][214] ([i915#7118] / [i915#9424])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-11/igt@kms_content_protection@atomic.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-8/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          [SKIP][215] ([i915#7118] / [i915#9424]) -> [FAIL][216] ([i915#7173])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-3/igt@kms_content_protection@legacy.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-11/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          [SKIP][217] ([i915#9424]) -> [SKIP][218] ([i915#9433])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg1-19/igt@kms_content_protection@mei-interface.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-13/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-dg2:          [FAIL][219] ([i915#7173]) -> [SKIP][220] ([i915#7118])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg2-11/igt@kms_content_protection@srm.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg2-8/igt@kms_content_protection@srm.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-dg1:          [SKIP][221] ([i915#8708]) -> [SKIP][222] ([i915#4423] / [i915#8708])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-dg1:          [SKIP][223] ([i915#3555] / [i915#4423]) -> [SKIP][224] ([i915#3555])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-dg1-15/igt@kms_plane_lowres@tiling-yf.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-dg1-15/igt@kms_plane_lowres@tiling-yf.html

  * igt@perf_pmu@busy-hang@ccs0:
    - shard-mtlp:         [DMESG-WARN][225] ([i915#13723]) -> [ABORT][226] ([i915#13193] / [i915#13723])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16492/shard-mtlp-7/igt@perf_pmu@busy-hang@ccs0.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/shard-mtlp-7/igt@perf_pmu@busy-hang@ccs0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10991
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
  [i915#12455]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12455
  [i915#12518]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12518
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12766
  [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
  [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13427]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13427
  [i915#13520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13520
  [i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
  [i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
  [i915#13705]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13705
  [i915#13723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13723
  [i915#13734]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13734
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13786]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13786
  [i915#13820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13820
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14033]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14033
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#5107]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5107
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5465
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8289
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
  [i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_16492 -> Patchwork_148539v1

  CI-20190529: 20190529
  CI_DRM_16492: 5303c0e49b49fe27639ba8b2c178931bc22344a2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8351: a994944173f1428dcf7247af03a821d51feae1cc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_148539v1: 5303c0e49b49fe27639ba8b2c178931bc22344a2 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_148539v1/index.html

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