Re: [PATCH 09/23] drm/xe/xe3p: Determine service copy availability from fuse

[Gustavo Sousa <gustavo.sousa@intel.com>]

Quoting Lucas De Marchi (2025-10-14 00:24:41-03:00)
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Xe3p introduces a dedicated SERVICE_COPY_ENABLE fuse register to reflect
>the availability of the service copy engines (BCS1-BCS8).
>
>Bspec: 74624
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
> drivers/gpu/drm/xe/xe_hw_engine.c    | 43 ++++++++++++++++++++++++++++--------
> 2 files changed, 37 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>index 937dc341abe5e..b73efde21119f 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>@@ -245,6 +245,9 @@
> #define XE2_GT_GEOMETRY_DSS_1                        XE_REG(0x9150)
> #define XE2_GT_GEOMETRY_DSS_2                        XE_REG(0x9154)
> 
>+#define SERVICE_COPY_ENABLE                        XE_REG(0x9170)
>+#define   FUSE_SERVICE_COPY_ENABLE_MASK                REG_GENMASK(7, 0)
>+
> #define GDRST                                        XE_REG(0x941c)
> #define   GRDOM_GUC                                REG_BIT(3)
> #define   GRDOM_FULL                                REG_BIT(0)
>diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>index 5544d91c21e8e..275d522d301a3 100644
>--- a/drivers/gpu/drm/xe/xe_hw_engine.c
>+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>@@ -716,27 +716,52 @@ static void read_media_fuses(struct xe_gt *gt)
>         }
> }
> 
>+static u32 infer_svccopy_from_meml3(struct xe_gt *gt)
>+{
>+        u32 meml3 = REG_FIELD_GET(MEML3_EN_MASK,
>+                                  xe_mmio_read32(&gt->mmio, MIRROR_FUSE3));
>+        u32 svccopy_mask = 0;
>+
>+        /*
>+         * Each of the four meml3 bits determines the fusing of two service
>+         * copy engines.
>+         */
>+        for (int i = 0; i < 4; i++)
>+                svccopy_mask |= (meml3 & BIT(i)) ? 0b11 << 2 * i : 0;
>+
>+        return svccopy_mask;
>+}
>+
>+static u32 read_svccopy_fuses(struct xe_gt *gt)
>+{
>+        return REG_FIELD_GET(FUSE_SERVICE_COPY_ENABLE_MASK,
>+                             xe_mmio_read32(&gt->mmio, SERVICE_COPY_ENABLE));
>+}
>+
> static void read_copy_fuses(struct xe_gt *gt)
> {
>         struct xe_device *xe = gt_to_xe(gt);
>         u32 bcs_mask;
> 
>-        if (GRAPHICS_VERx100(xe) < 1260 || GRAPHICS_VERx100(xe) >= 1270)
>-                return;
>-
>         xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
> 
>-        bcs_mask = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3);
>-        bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
>+        if (GRAPHICS_VER(xe) >= 35)
>+                bcs_mask = read_svccopy_fuses(gt);
>+        else if (GRAPHICS_VERx100(xe) == 1260)
>+                bcs_mask = infer_svccopy_from_meml3(gt);
>+        else
>+                return;
> 
>-        /* BCS0 is always present; only BCS1-BCS8 may be fused off */
>-        for (int i = XE_HW_ENGINE_BCS1, j = 0; i <= XE_HW_ENGINE_BCS8; ++i, ++j) {
>+        /* Only BCS1-BCS8 may be fused off */
>+        bcs_mask <<= XE_HW_ENGINE_BCS1;
>+        for (int i = XE_HW_ENGINE_BCS1; i <= XE_HW_ENGINE_BCS8; ++i) {
>                 if (!(gt->info.engine_mask & BIT(i)))
>                         continue;
> 
>-                if (!(BIT(j / 2) & bcs_mask)) {
>+                if (!(bcs_mask & BIT(i))) {
>                         gt->info.engine_mask &= ~BIT(i);
>-                        xe_gt_info(gt, "bcs%u fused off\n", j);
>+                        xe_gt_info(gt, "bcs%u fused off\n",
>+                                   i - XE_HW_ENGINE_BCS0);
>                 }
>         }
> }
>
>-- 
>2.51.0
>