From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
Shekhar Chauhan <shekhar.chauhan@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
Tejas Upadhyay <tejas.upadhyay@intel.com>
Subject: [PATCH 04/23] drm/xe/xe3p_lpm: Add special check in Media GT for Main GAMCTRL
Date: Mon, 13 Oct 2025 20:24:36 -0700 [thread overview]
Message-ID: <20251013-xe3p-v1-4-bfb74f038215@intel.com> (raw)
In-Reply-To: <20251013-xe3p-v1-0-bfb74f038215@intel.com>
From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
For Xe3p arch some subunits of an IP may be different. The GMD_ID
register returns the Xe3p arch and dedicates the reserved field to mark
possible subunit differences. Generally this is an under-the-hood
implementation detail that drivers don't need to worry about, but the
new Main_GAMCTRL may be enabled or not depending on those.
Those reserved bits are described for Xe3p as: "If Zero, No special case
to be handled. If Non-Zero, special case to be handled by Software
agent.". That special case is defined per Arch. So if media version is
35, also check the additional reserved bits. To avoid confusion with the
usual meaning of "reserved", define them as GMD_ID_SUBIP_FLAG_MASK.
Bspec: 74201
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 6 ++++++
drivers/gpu/drm/xe/xe_guc.c | 19 +++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 47e13a3fb9072..937dc341abe5e 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -37,6 +37,12 @@
#define GMD_ID XE_REG(0xd8c)
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
+/*
+ * Spec defines these bits as "Reserved", but then make them assume some
+ * meaning that depends on the ARCH. To avoid any confusion, call them
+ * SUBIP_FLAG_MASK.
+ */
+#define GMD_ID_SUBIP_FLAG_MASK REG_GENMASK(13, 6)
#define GMD_ID_REVID REG_GENMASK(5, 0)
#define FORCEWAKE_ACK_GSC XE_REG(0xdf8)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 37e3735f34e63..ecc3e091b89e6 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -1681,6 +1681,25 @@ bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
{
struct xe_gt *gt = guc_to_gt(guc);
+ /*
+ * For Xe3p media gt (35), the GuC and the CS subunits may be still Xe3
+ * that lacks the Main GAMCTRL support. Reserved bits from the GMD_ID
+ * inform the IP version of the subunits.
+ */
+ if (xe_gt_is_media_type(gt) && MEDIA_VER(gt_to_xe(gt)) == 35) {
+ u32 val = xe_mmio_read32(>->mmio, GMD_ID);
+ u32 subip = REG_FIELD_GET(GMD_ID_SUBIP_FLAG_MASK, val);
+
+ if (!subip)
+ return true;
+
+ xe_gt_WARN(gt, subip != 1,
+ "GMD_ID has unknown value in the SUBIP_FLAG field - 0x%x\n",
+ subip);
+
+ return false;
+ }
+
return GT_VER(gt) >= 35;
}
--
2.51.0
next prev parent reply other threads:[~2025-10-14 3:25 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-14 3:24 [PATCH 00/23] drm/xe: Add Xe3p support Lucas De Marchi
2025-10-14 3:24 ` [PATCH 01/23] drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05 Lucas De Marchi
2025-10-14 6:17 ` Shekhar Chauhan
2025-10-14 16:11 ` Matt Roper
2025-10-14 3:24 ` [PATCH 02/23] drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03 Lucas De Marchi
2025-10-14 6:22 ` Shekhar Chauhan
2025-10-14 16:14 ` Matt Roper
2025-10-14 3:24 ` [PATCH 03/23] drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT Lucas De Marchi
2025-10-14 16:34 ` Matt Roper
2025-10-15 2:28 ` Lucas De Marchi
2025-10-15 6:36 ` Vivekanandan, Balasubramani
2025-10-15 14:03 ` Lucas De Marchi
2025-10-16 14:20 ` Vivekanandan, Balasubramani
2025-10-15 14:59 ` Matt Roper
2025-10-14 3:24 ` Lucas De Marchi [this message]
2025-10-14 16:36 ` [PATCH 04/23] drm/xe/xe3p_lpm: Add special check in Media GT for Main GAMCTRL Matt Roper
2025-10-14 3:24 ` [PATCH 05/23] drm/xe/xe3p_lpm: Stop reading the CTC_MODE register Lucas De Marchi
2025-10-14 11:58 ` Shekhar Chauhan
2025-10-14 16:52 ` Matt Roper
2025-10-15 3:41 ` Lucas De Marchi
2025-10-15 9:19 ` Vivekanandan, Balasubramani
2025-10-15 15:04 ` Matt Roper
2025-10-14 16:40 ` Matt Roper
2025-10-14 16:53 ` Matt Roper
2025-10-14 3:24 ` [PATCH 06/23] drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs Lucas De Marchi
2025-10-14 17:04 ` Matt Roper
2025-10-14 3:24 ` [PATCH 07/23] drm/xe/xe3p_lpm: Handle MCR steering Lucas De Marchi
2025-10-15 9:56 ` Vivekanandan, Balasubramani
2025-10-14 3:24 ` [PATCH 08/23] drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting Lucas De Marchi
2025-10-15 12:24 ` Vivekanandan, Balasubramani
2025-10-14 3:24 ` [PATCH 09/23] drm/xe/xe3p: Determine service copy availability from fuse Lucas De Marchi
2025-10-15 20:14 ` Gustavo Sousa
2025-10-14 3:24 ` [PATCH 10/23] drm/xe/xe3p: Skip TD flush Lucas De Marchi
2025-10-14 19:35 ` Matt Roper
2025-10-14 3:24 ` [PATCH 11/23] drm/xe/xe3p: Enable L2 flush optimization feature Lucas De Marchi
2025-10-14 19:43 ` Matt Roper
2025-10-15 4:02 ` Lucas De Marchi
2025-10-14 3:24 ` [PATCH 12/23] drm/xe/xe3p: Flush userptr/shrinker bo cachelines manually Lucas De Marchi
2025-10-14 12:58 ` Thomas Hellström
2025-10-15 18:42 ` Lucas De Marchi
2025-10-14 3:24 ` [PATCH 13/23] drm/xe: Dump CURRENT_LRCA and CSMQDEBUG registers Lucas De Marchi
2025-10-14 17:24 ` Matt Roper
2025-10-15 4:07 ` Lucas De Marchi
2025-10-14 3:24 ` [PATCH 14/23] drm/xe/nvl: Define NVL-S platform Lucas De Marchi
2025-10-14 7:34 ` Shekhar Chauhan
2025-10-14 3:24 ` [PATCH 15/23] drm/xe/nvls: Define GuC firmware for NVL-S Lucas De Marchi
2025-10-15 18:49 ` Lucas De Marchi
2025-10-14 3:24 ` [PATCH 16/23] drm/xe/nvls: Attach MOCS table " Lucas De Marchi
2025-10-14 7:45 ` Shekhar Chauhan
2025-10-14 3:24 ` [PATCH 17/23] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition Lucas De Marchi
2025-10-14 8:04 ` Shekhar Chauhan
2025-10-14 8:12 ` Shekhar Chauhan
2025-10-14 17:33 ` Matt Roper
2025-10-15 2:47 ` Shekhar Chauhan
2025-10-14 17:36 ` Matt Roper
2025-10-14 3:24 ` [PATCH 18/23] drm/xe/xe3p_xpc: Add L3 bank mask Lucas De Marchi
2025-10-14 17:46 ` Matt Roper
2025-10-14 3:24 ` [PATCH 19/23] drm/xe/xe3p_xpc: Add MCR steering Lucas De Marchi
2025-10-14 3:24 ` [PATCH 20/23] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx Lucas De Marchi
2025-10-14 18:07 ` Matt Roper
2025-10-15 17:07 ` Lucas De Marchi
2025-10-15 17:12 ` Matt Roper
2025-10-14 3:24 ` [PATCH 21/23] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs Lucas De Marchi
2025-10-14 8:09 ` Shekhar Chauhan
2025-10-14 8:13 ` Shekhar Chauhan
2025-10-14 18:14 ` Matt Roper
2025-10-15 2:52 ` Shekhar Chauhan
2025-10-15 14:38 ` Lucas De Marchi
2025-10-15 15:34 ` Shekhar Chauhan
2025-10-14 3:24 ` [PATCH 22/23] drm/xe/xe3p_xpc: Setup PAT table Lucas De Marchi
2025-10-16 14:07 ` Vivekanandan, Balasubramani
2025-10-14 3:24 ` [PATCH 23/23] drm/xe/xe3p: Add xe3p EU stall data format Lucas De Marchi
2025-10-14 19:11 ` Matt Roper
2025-10-15 23:05 ` Harish Chegondi
2025-10-14 3:45 ` ✗ CI.checkpatch: warning for drm/xe: Add Xe3p support Patchwork
2025-10-14 3:47 ` ✓ CI.KUnit: success " Patchwork
2025-10-14 4:22 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-14 12:06 ` ✓ Xe.CI.Full: " Patchwork
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