Re: [PATCH 07/23] drm/xe/xe3p_lpm: Handle MCR steering

["Vivekanandan, Balasubramani" <balasubramani.vivekanandan@intel.com>]

On 13.10.2025 20:24, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe3p_LPM's MCR steering has the same ranges and behavior as Xe3_LPM.
> However one register range that was reserved on Xe3_LPM has now become a
> unicast range (0x384200-0x38427F), so we need to stop consolidating the
> adjacent MCR ranges into a single table entry in the table.  With this
> change to the Xe3_LPM table, we can continue to use the same table for
> both IP families.
> 
> While we're touching this table, take the opportunity to fix a
> whitespace mistake and clarify that one of the other consolidated range
> entries includes a reserved range.
> 
> Bspec: 76445
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_gt_mcr.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index 8fb1cae917244..e1a2b38fc2a86 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -236,12 +236,13 @@ static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {
>  };
>  
>  static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
> -	{ 0x384000, 0x3847DF },         /* GAM, rsvd, GAM */
> +	{ 0x384000, 0x3841FF },         /* GAM */
> +	{ 0x384400, 0x3847DF },         /* GAM */
>  	{ 0x384900, 0x384AFF },         /* GAM */
>  	{ 0x389560, 0x3895FF },         /* MEDIAINF */
>  	{ 0x38B600, 0x38B8FF },         /* L3BANK */
>  	{ 0x38C800, 0x38D07F },         /* GAM, MEDIAINF */
> -	{ 0x38D0D0, 0x38F0FF },		/* MEDIAINF, GAM */
> +	{ 0x38D0D0, 0x38F0FF },         /* MEDIAINF, rsvd, GAM */
>  	{ 0x393C00, 0x393C7F },         /* MEDIAINF */
>  	{},
>  };
> 
> -- 
> 2.51.0
>