Re: [PATCH 17/23] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

[Matt Roper <matthew.d.roper@intel.com>]

On Tue, Oct 14, 2025 at 01:34:30PM +0530, Shekhar Chauhan wrote:
> 
> On 10/14/2025 8:54, Lucas De Marchi wrote:
> > From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > 
> > Add support for graphics IP Xe3p_XPC having IP version 35.11.
> > 
> > Bspec: 77979, 77975
> > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >   drivers/gpu/drm/xe/xe_pci.c | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > index aa8359a4c5594..83e5e0c314a42 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -119,6 +119,15 @@ static const struct xe_graphics_desc graphics_xe2 = {
> >   	XE2_GFX_FEATURES,
> >   };
> > +static const struct xe_graphics_desc graphics_xe3p_xpc = {
> > +	XE2_GFX_FEATURES,
> > +	.hw_engine_mask =
> > +		GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
> 
> In Bspec, I see the number of RES_COPY_ENGINES as 0, which signals that
> there is no BCS0. But, at the same time, I see SERVICE_COPY_ENGINES as 0.
> So, why are we having a mask from BCS1 to BCS8? Maybe I'm interpreting the
> table wrong in some way.

The table on page 74110?  I see all non-zero values for
SERVICE_COPY_ENGINES (which makes sense because I don't think we'd be
able to function at all without at least one copy engine to assist with
various vram operations).

But note that the details on that page are product/SKU-specific numbers
and not something we're allowed to hardcode in the driver.  In general
we have a way to discover the presence/absence of up to 8 engines via
fuses, so we give a mask that matches what the fuses allow us to
discover.  The actual engine mask will get reduced down during
initialization according to what we discover upon fuse readout.  We do
the same thing with other engine types that are runtime discoverable as
well.


Matt

> 
> But, aside from this change, other changes look fine, I can provide the RB
> once the above query is clarified.
> 
> > +		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
> > +	.va_bits = 57,
> > +	.has_flat_ccs = false,
> > +};
> > +
> >   static const struct xe_media_desc media_xem = {
> >   	.hw_engine_mask =
> >   		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
> > @@ -151,6 +160,7 @@ static const struct xe_ip graphics_ips[] = {
> >   	{ 3003, "Xe3_LPG", &graphics_xe2 },
> >   	{ 3004, "Xe3_LPG", &graphics_xe2 },
> >   	{ 3005, "Xe3_LPG", &graphics_xe2 },
> > +	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
> >   };
> >   /* Pre-GMDID Media IPs */
> > 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation