[PATCH 00/12] drm/xe: Add support for Crescent Island

[PATCH 00/12] drm/xe: Add support for Crescent Island

[Lucas De Marchi]

Now that the support for the base IPs used by Crescent Island are in
place, add the platform and the rest of the basic enabling changes.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Ashutosh Dixit (1):
      drm/xe/oa/uapi: Expose MERT OA unit

Balasubramani Vivekanandan (2):
      drm/xe/cri: Add CRI platform definition
      topic/for-xe-CI: drm/xe/cri: Define GuC firmware for CRI

Lukasz Laguna (5):
      drm/xe: Add device flag to indicate standalone MERT
      drm/xe/pf: Configure LMTT in MERT
      drm/xe: Handle MERT interrupts
      drm/xe/pf: Add TLB invalidation support for MERT
      drm/xe/pf: Handle MERT catastrophic errors

Matt Roper (1):
      drm/xe/cri: Setup MOCS table

Raag Jadav (1):
      drm/xe/pm: Enable D3cold WAKE# support

Sk Anirban (1):
      drm/xe/cri: Add new performance limit reasons bits

Soham Purkait (1):
      drm/xe/cri: Add check to verify if CSC is a PCIe endpoint

 drivers/gpu/drm/xe/regs/xe_gt_regs.h       |  15 ++
 drivers/gpu/drm/xe/regs/xe_irq_regs.h      |   1 +
 drivers/gpu/drm/xe/regs/xe_mert_regs.h     |  21 +++
 drivers/gpu/drm/xe/regs/xe_oa_regs.h       |   9 ++
 drivers/gpu/drm/xe/xe_device.h             |   5 +
 drivers/gpu/drm/xe/xe_device_types.h       |  12 ++
 drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c |  19 +++
 drivers/gpu/drm/xe/xe_gt_throttle.c        | 249 ++++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_heci_gsc.c           |  30 +++-
 drivers/gpu/drm/xe/xe_i2c.c                |  38 +++++
 drivers/gpu/drm/xe/xe_irq.c                |  26 +++
 drivers/gpu/drm/xe/xe_lmtt.c               |  12 +-
 drivers/gpu/drm/xe/xe_mocs.c               |  26 +++
 drivers/gpu/drm/xe/xe_oa.c                 |  36 ++++-
 drivers/gpu/drm/xe/xe_pci.c                |  17 ++
 drivers/gpu/drm/xe/xe_pci_types.h          |   1 +
 drivers/gpu/drm/xe/xe_pcode_api.h          |   6 +
 drivers/gpu/drm/xe/xe_platform_types.h     |   1 +
 drivers/gpu/drm/xe/xe_pm.c                 |  34 ++++
 drivers/gpu/drm/xe/xe_sriov_pf.c           |   3 +
 drivers/gpu/drm/xe/xe_uc_fw.c              |   1 +
 include/drm/intel/pciids.h                 |   4 +
 include/uapi/drm/xe_drm.h                  |   3 +
 23 files changed, 560 insertions(+), 9 deletions(-)

base-commit: fb0f56ad8a2c9953c57c3337a72ccbf9c5050687
change-id: 20251021-cri-928e5dcfde7e

Lucas De Marchi

[PATCH 01/12] drm/xe/cri: Add CRI platform definition

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Add platform definition and PCI IDs for Crescent Island.

Other platforms use INTEL_VGA_DEVICE since they have a
PCI_BASE_CLASS_DISPLAY class.  This is not the case for CRI, so just
match on devid, which should be sufficient.

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c            | 15 +++++++++++++++
 drivers/gpu/drm/xe/xe_platform_types.h |  1 +
 include/drm/intel/pciids.h             |  4 ++++
 3 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index c3136141a9536..000bb30b97712 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -396,6 +396,20 @@ static const struct xe_device_desc nvls_desc = {
 	.vm_max_level = 4,
 };
 
+static const struct xe_device_desc cri_desc = {
+	DGFX_FEATURES,
+	PLATFORM(CRESCENTISLAND),
+	.dma_mask_size = 52,
+	.has_display = false,
+	.has_flat_ccs = false,
+	.has_mbx_power_limits = true,
+	.has_sriov = true,
+	.max_gt_per_tile = 2,
+	.require_force_probe = true,
+	.va_bits = 57,
+	.vm_max_level = 4,
+};
+
 #undef PLATFORM
 __diag_pop();
 
@@ -425,6 +439,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
 	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
 	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
+	INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc),
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index 78286285c2495..f516dbddfd882 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -25,6 +25,7 @@ enum xe_platform {
 	XE_BATTLEMAGE,
 	XE_PANTHERLAKE,
 	XE_NOVALAKE_S,
+	XE_CRESCENTISLAND,
 };
 
 enum xe_subplatform {
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index 13c592e1a28c7..b258e79b437ac 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -896,4 +896,8 @@
 	MACRO__(0xD744, ## __VA_ARGS__), \
 	MACRO__(0xD745, ## __VA_ARGS__)
 
+/* CRI */
+#define INTEL_CRI_IDS(MACRO__, ...) \
+	MACRO__(0x674C, ## __VA_ARGS__)
+
 #endif /* __PCIIDS_H__ */

-- 
2.51.0

Re: [PATCH 01/12] drm/xe/cri: Add CRI platform definition

[Shekhar Chauhan]

On 10/22/2025 10:47, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>
> Add platform definition and PCI IDs for Crescent Island.
>
> Other platforms use INTEL_VGA_DEVICE since they have a
> PCI_BASE_CLASS_DISPLAY class.  This is not the case for CRI, so just
> match on devid, which should be sufficient.
>
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Nitpick: Maybe include the Bspec(s) associated with it;

but other than that, LGTM,

Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>

> ---
>   drivers/gpu/drm/xe/xe_pci.c            | 15 +++++++++++++++
>   drivers/gpu/drm/xe/xe_platform_types.h |  1 +
>   include/drm/intel/pciids.h             |  4 ++++
>   3 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index c3136141a9536..000bb30b97712 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -396,6 +396,20 @@ static const struct xe_device_desc nvls_desc = {
>   	.vm_max_level = 4,
>   };
>   
> +static const struct xe_device_desc cri_desc = {
> +	DGFX_FEATURES,
> +	PLATFORM(CRESCENTISLAND),
> +	.dma_mask_size = 52,
> +	.has_display = false,
> +	.has_flat_ccs = false,
> +	.has_mbx_power_limits = true,
> +	.has_sriov = true,
> +	.max_gt_per_tile = 2,
> +	.require_force_probe = true,
> +	.va_bits = 57,
> +	.vm_max_level = 4,
> +};
> +
>   #undef PLATFORM
>   __diag_pop();
>   
> @@ -425,6 +439,7 @@ static const struct pci_device_id pciidlist[] = {
>   	INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>   	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>   	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
> +	INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc),
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
> index 78286285c2495..f516dbddfd882 100644
> --- a/drivers/gpu/drm/xe/xe_platform_types.h
> +++ b/drivers/gpu/drm/xe/xe_platform_types.h
> @@ -25,6 +25,7 @@ enum xe_platform {
>   	XE_BATTLEMAGE,
>   	XE_PANTHERLAKE,
>   	XE_NOVALAKE_S,
> +	XE_CRESCENTISLAND,
>   };
>   
>   enum xe_subplatform {
> diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
> index 13c592e1a28c7..b258e79b437ac 100644
> --- a/include/drm/intel/pciids.h
> +++ b/include/drm/intel/pciids.h
> @@ -896,4 +896,8 @@
>   	MACRO__(0xD744, ## __VA_ARGS__), \
>   	MACRO__(0xD745, ## __VA_ARGS__)
>   
> +/* CRI */
> +#define INTEL_CRI_IDS(MACRO__, ...) \
> +	MACRO__(0x674C, ## __VA_ARGS__)
> +
>   #endif /* __PCIIDS_H__ */
>

Re: [PATCH 01/12] drm/xe/cri: Add CRI platform definition

[Lucas De Marchi]

On Wed, Oct 22, 2025 at 08:28:32PM +0530, Shekhar Chauhan wrote:
>
>On 10/22/2025 10:47, Lucas De Marchi wrote:
>>From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>
>>Add platform definition and PCI IDs for Crescent Island.
>>
>>Other platforms use INTEL_VGA_DEVICE since they have a
>>PCI_BASE_CLASS_DISPLAY class.  This is not the case for CRI, so just
>>match on devid, which should be sufficient.
>>
>>Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>Nitpick: Maybe include the Bspec(s) associated with it;

Bspec: 77971


will add that in the next version.

>
>but other than that, LGTM,
>
>Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>

thanks
Lucas De Marchi

Re: [PATCH 01/12] drm/xe/cri: Add CRI platform definition

[Lucas De Marchi]

On Wed, Oct 22, 2025 at 02:45:33PM -0500, Lucas De Marchi wrote:
>On Wed, Oct 22, 2025 at 08:28:32PM +0530, Shekhar Chauhan wrote:
>>
>>On 10/22/2025 10:47, Lucas De Marchi wrote:
>>>From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>>
>>>Add platform definition and PCI IDs for Crescent Island.
>>>
>>>Other platforms use INTEL_VGA_DEVICE since they have a
>>>PCI_BASE_CLASS_DISPLAY class.  This is not the case for CRI, so just
>>>match on devid, which should be sufficient.
>>>
>>>Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>
>>Nitpick: Maybe include the Bspec(s) associated with it;
>
>Bspec: 77971
>
>
>will add that in the next version.

thinking about it again... to make it easier to handle the other parts
in different series by different people, I'm going ahead and merging
this.

Merged to drm-xe-next, thanks!

[04/23] drm/xe/xe3p_lpm: Add special check in Media GT for Main GAMCTRL
         commit: e681ddca301931dbea99fcb4bc5a5dacdb7fad06


thanks
Lucas De Marchi

>
>>
>>but other than that, LGTM,
>>
>>Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>
>thanks
>Lucas De Marchi

Re: [PATCH 01/12] drm/xe/cri: Add CRI platform definition

[Lucas De Marchi]

On Thu, Oct 23, 2025 at 05:57:51AM -0500, Lucas De Marchi wrote:
>
>Merged to drm-xe-next, thanks!
>
>[04/23] drm/xe/xe3p_lpm: Add special check in Media GT for Main GAMCTRL
>        commit: e681ddca301931dbea99fcb4bc5a5dacdb7fad06

^ and this was a wrong copy and paste, should have been:

[01/12] drm/xe/cri: Add CRI platform definition
         commit: 5e0de2dfbc1bddbd47fbcc9dabb4917000b0ca27

which was actually what I did.

Lucas De Marchi

[PATCH 02/12] topic/for-xe-CI: drm/xe/cri: Define GuC firmware for CRI

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Define GuC firmware, still using the mpp version that is intended to be
merged only to help with the platform enabling in topic/for-xe-CI.

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_uc_fw.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index e589c7e38f125..b4cd6226ad31d 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -115,6 +115,7 @@ struct fw_blobs_by_type {
 #define XE_GT_TYPE_ANY XE_GT_TYPE_UNINITIALIZED
 
 #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver)					\
+	fw_def(CRESCENTISLAND,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	cri,	70, 49, 4))	\
 	fw_def(NOVALAKE_S,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	nvl,	70, 49, 4))	\
 	fw_def(PANTHERLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	ptl,	70, 49, 4))	\
 	fw_def(BATTLEMAGE,	GT_TYPE_ANY,	major_ver(xe,	guc,	bmg,	70, 49, 4))	\

-- 
2.51.0

Re: [PATCH 02/12] topic/for-xe-CI: drm/xe/cri: Define GuC firmware for CRI

[Lucas De Marchi]

On Tue, Oct 21, 2025 at 10:17:34PM -0700, Lucas De Marchi wrote:
>From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>
>Define GuC firmware, still using the mpp version that is intended to be
>merged only to help with the platform enabling in topic/for-xe-CI.
>
>Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

This is only for the topic branch, so not much to review here.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/xe/xe_uc_fw.c | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
>index e589c7e38f125..b4cd6226ad31d 100644
>--- a/drivers/gpu/drm/xe/xe_uc_fw.c
>+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
>@@ -115,6 +115,7 @@ struct fw_blobs_by_type {
> #define XE_GT_TYPE_ANY XE_GT_TYPE_UNINITIALIZED
>
> #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver)					\
>+	fw_def(CRESCENTISLAND,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	cri,	70, 49, 4))	\
> 	fw_def(NOVALAKE_S,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	nvl,	70, 49, 4))	\
> 	fw_def(PANTHERLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	ptl,	70, 49, 4))	\
> 	fw_def(BATTLEMAGE,	GT_TYPE_ANY,	major_ver(xe,	guc,	bmg,	70, 49, 4))	\
>
>-- 
>2.51.0
>

[PATCH 03/12] drm/xe/cri: Setup MOCS table

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

CRI has a new MOCS table, but uses the same general ops as other Xe2/Xe3
platforms.

Bspec: 71582
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_mocs.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index e8ec4114302e5..6613d3b48a844 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -568,6 +568,23 @@ static const struct xe_mocs_ops xe2_mocs_ops = {
 	.dump = xe2_mocs_dump,
 };
 
+/*
+ * Note that the "L3" and "L4" register fields actually control the L2 and L3
+ * caches respectively on this platform.
+ */
+static const struct xe_mocs_entry xe3p_xpc_mocs_table[] = {
+	/* Defer to PAT */
+	MOCS_ENTRY(0, XE2_L3_0_WB | L4_3_UC, 0),
+	/* UC */
+	MOCS_ENTRY(1, IG_PAT | XE2_L3_3_UC | L4_3_UC, 0),
+	/* L2 */
+	MOCS_ENTRY(2, IG_PAT | XE2_L3_0_WB | L4_3_UC, 0),
+	/* L3 */
+	MOCS_ENTRY(3, IG_PAT | XE2_L3_3_UC | L4_0_WB, 0),
+	/* L2 + L3 */
+	MOCS_ENTRY(4, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0),
+};
+
 static unsigned int get_mocs_settings(struct xe_device *xe,
 				      struct xe_mocs_info *info)
 {
@@ -576,6 +593,15 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
 	memset(info, 0, sizeof(struct xe_mocs_info));
 
 	switch (xe->info.platform) {
+	case XE_CRESCENTISLAND:
+		info->ops = &xe2_mocs_ops;
+		info->table_size = ARRAY_SIZE(xe3p_xpc_mocs_table);
+		info->table = xe3p_xpc_mocs_table;
+		info->num_mocs_regs = XE2_NUM_MOCS_ENTRIES;
+		info->uc_index = 1;
+		info->wb_index = 4;
+		info->unused_entries_index = 4;
+		break;
 	case XE_NOVALAKE_S:
 	case XE_PANTHERLAKE:
 	case XE_LUNARLAKE:

-- 
2.51.0

Re: [PATCH 03/12] drm/xe/cri: Setup MOCS table

[Vivekanandan, Balasubramani]

On 21.10.2025 22:17, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> CRI has a new MOCS table, but uses the same general ops as other Xe2/Xe3
> platforms.
> 
> Bspec: 71582
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_mocs.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index e8ec4114302e5..6613d3b48a844 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -568,6 +568,23 @@ static const struct xe_mocs_ops xe2_mocs_ops = {
>  	.dump = xe2_mocs_dump,
>  };
>  
> +/*
> + * Note that the "L3" and "L4" register fields actually control the L2 and L3
> + * caches respectively on this platform.
> + */
> +static const struct xe_mocs_entry xe3p_xpc_mocs_table[] = {
> +	/* Defer to PAT */
> +	MOCS_ENTRY(0, XE2_L3_0_WB | L4_3_UC, 0),
> +	/* UC */
> +	MOCS_ENTRY(1, IG_PAT | XE2_L3_3_UC | L4_3_UC, 0),
> +	/* L2 */
> +	MOCS_ENTRY(2, IG_PAT | XE2_L3_0_WB | L4_3_UC, 0),
> +	/* L3 */
> +	MOCS_ENTRY(3, IG_PAT | XE2_L3_3_UC | L4_0_WB, 0),
> +	/* L2 + L3 */
> +	MOCS_ENTRY(4, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0),
> +};
> +
>  static unsigned int get_mocs_settings(struct xe_device *xe,
>  				      struct xe_mocs_info *info)
>  {
> @@ -576,6 +593,15 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
>  	memset(info, 0, sizeof(struct xe_mocs_info));
>  
>  	switch (xe->info.platform) {
> +	case XE_CRESCENTISLAND:
> +		info->ops = &xe2_mocs_ops;
> +		info->table_size = ARRAY_SIZE(xe3p_xpc_mocs_table);
> +		info->table = xe3p_xpc_mocs_table;
> +		info->num_mocs_regs = XE2_NUM_MOCS_ENTRIES;
> +		info->uc_index = 1;
> +		info->wb_index = 4;
> +		info->unused_entries_index = 4;
> +		break;
>  	case XE_NOVALAKE_S:
>  	case XE_PANTHERLAKE:
>  	case XE_LUNARLAKE:
> 
> -- 
> 2.51.0
> 

[PATCH 04/12] drm/xe/cri: Add new performance limit reasons bits

[Lucas De Marchi]

From: Sk Anirban <sk.anirban@intel.com>

Add support for additional performance limit reasons in
GT0_PERF_LIMIT_REASONS register.

Signed-off-by: Sk Anirban <sk.anirban@intel.com>
---

There are some improvements to be made here before applying to reduce
the amount of code for one platform. I plan to take a look on that for
v2.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h |  15 +++
 drivers/gpu/drm/xe/xe_gt_throttle.c  | 249 ++++++++++++++++++++++++++++++++++-
 2 files changed, 261 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 3545e0be06dae..bba5500a094ed 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -589,6 +589,8 @@
 #define GT_GFX_RC6				XE_REG(0x138108)
 
 #define GT0_PERF_LIMIT_REASONS			XE_REG(0x1381a8)
+
+/* Common performance limit reason bits - available on all platforms */
 #define   GT0_PERF_LIMIT_REASONS_MASK		0xde3
 #define   PROCHOT_MASK				REG_BIT(0)
 #define   THERMAL_LIMIT_MASK			REG_BIT(1)
@@ -599,6 +601,19 @@
 #define   POWER_LIMIT_1_MASK			REG_BIT(10)
 #define   POWER_LIMIT_2_MASK			REG_BIT(11)
 
+/* Platform-specific performance limit reason bits - for Crescent Island */
+#define   PERF_LIMIT_REASONS_MASK		0xfdff
+#define   SOC_THERMAL_LIMIT_MASK		REG_BIT(1)
+#define   MEM_THERMAL_MASK			REG_BIT(2)
+#define   VR_THERMAL_MASK			REG_BIT(3)
+#define   ICCMAX_MASK				REG_BIT(4)
+#define   SOC_AVG_THERMAL_MASK			REG_BIT(6)
+#define   FASTVMODE_MASK			REG_BIT(7)
+#define   PSYS_PL1_MASK				REG_BIT(12)
+#define   PSYS_PL2_MASK				REG_BIT(13)
+#define   P0_FREQ_MASK				REG_BIT(14)
+#define   PSYS_CRIT_MASK			REG_BIT(15)
+
 #define GT_PERF_STATUS				XE_REG(0x1381b4)
 #define   VOLTAGE_MASK				REG_GENMASK(10, 0)
 
diff --git a/drivers/gpu/drm/xe/xe_gt_throttle.c b/drivers/gpu/drm/xe/xe_gt_throttle.c
index aa962c783cdf7..b38cfd22c6183 100644
--- a/drivers/gpu/drm/xe/xe_gt_throttle.c
+++ b/drivers/gpu/drm/xe/xe_gt_throttle.c
@@ -12,6 +12,7 @@
 #include "xe_gt_sysfs.h"
 #include "xe_gt_throttle.h"
 #include "xe_mmio.h"
+#include "xe_platform_types.h"
 #include "xe_pm.h"
 
 /**
@@ -28,6 +29,24 @@
  * device/gt#/freq0/throttle/reason_ratl - Frequency throttle due to RATL
  * device/gt#/freq0/throttle/reason_vr_thermalert - Frequency throttle due to VR THERMALERT
  * device/gt#/freq0/throttle/reason_vr_tdc -  Frequency throttle due to VR TDC
+ *
+ * The following attributes are available on Crescent Island platform:
+ * device/gt#/freq0/throttle/status - Overall throttle status
+ * device/gt#/freq0/throttle/reason_pl1 - Frequency throttle due to package PL1
+ * device/gt#/freq0/throttle/reason_pl2 - Frequency throttle due to package PL2
+ * device/gt#/freq0/throttle/reason_pl4 - Frequency throttle due to PL4
+ * device/gt#/freq0/throttle/reason_prochot - Frequency throttle due to prochot
+ * device/gt#/freq0/throttle/reason_soc_thermal - Frequency throttle due to SoC thermal
+ * device/gt#/freq0/throttle/reason_mem_thermal - Frequency throttle due to memory thermal
+ * device/gt#/freq0/throttle/reason_vr_thermal - Frequency throttle due to VR thermal
+ * device/gt#/freq0/throttle/reason_iccmax - Frequency throttle due to ICCMAX
+ * device/gt#/freq0/throttle/reason_ratl - Frequency throttle due to RATL thermal algorithm
+ * device/gt#/freq0/throttle/reason_soc_avg_thermal - Frequency throttle due to SoC average temp
+ * device/gt#/freq0/throttle/reason_fastvmode - Frequency throttle due to VR is hitting FastVMode
+ * device/gt#/freq0/throttle/reason_psys_pl1 - Frequency throttle due to PSYS PL1
+ * device/gt#/freq0/throttle/reason_psys_pl2 - Frequency throttle due to PSYS PL2
+ * device/gt#/freq0/throttle/reason_p0_freq - Frequency throttle due to P0 frequency
+ * device/gt#/freq0/throttle/reason_psys_crit - Frequency throttle due to PSYS critical
  */
 
 static struct xe_gt *
@@ -52,7 +71,13 @@ u32 xe_gt_throttle_get_limit_reasons(struct xe_gt *gt)
 
 static u32 read_status(struct xe_gt *gt)
 {
-	u32 status = xe_gt_throttle_get_limit_reasons(gt) & GT0_PERF_LIMIT_REASONS_MASK;
+	struct xe_device *xe = gt_to_xe(gt);
+	u32 status;
+
+	if (xe->info.platform == XE_CRESCENTISLAND)
+		status = xe_gt_throttle_get_limit_reasons(gt) & PERF_LIMIT_REASONS_MASK;
+	else
+		status = xe_gt_throttle_get_limit_reasons(gt) & GT0_PERF_LIMIT_REASONS_MASK;
 
 	xe_gt_dbg(gt, "throttle reasons: 0x%08x\n", status);
 	return status;
@@ -86,6 +111,13 @@ static u32 read_reason_thermal(struct xe_gt *gt)
 	return thermal;
 }
 
+static u32 read_reason_soc_thermal(struct xe_gt *gt)
+{
+	u32 thermal = xe_gt_throttle_get_limit_reasons(gt) & SOC_THERMAL_LIMIT_MASK;
+
+	return thermal;
+}
+
 static u32 read_reason_prochot(struct xe_gt *gt)
 {
 	u32 prochot = xe_gt_throttle_get_limit_reasons(gt) & PROCHOT_MASK;
@@ -107,6 +139,13 @@ static u32 read_reason_vr_thermalert(struct xe_gt *gt)
 	return thermalert;
 }
 
+static u32 read_reason_soc_avg_thermal(struct xe_gt *gt)
+{
+	u32 soc_avg_thermal = xe_gt_throttle_get_limit_reasons(gt) & SOC_AVG_THERMAL_MASK;
+
+	return soc_avg_thermal;
+}
+
 static u32 read_reason_vr_tdc(struct xe_gt *gt)
 {
 	u32 tdc = xe_gt_throttle_get_limit_reasons(gt) & VR_TDC_MASK;
@@ -114,6 +153,62 @@ static u32 read_reason_vr_tdc(struct xe_gt *gt)
 	return tdc;
 }
 
+static u32 read_reason_fastvmode(struct xe_gt *gt)
+{
+	u32 fastvmode = xe_gt_throttle_get_limit_reasons(gt) & FASTVMODE_MASK;
+
+	return fastvmode;
+}
+
+static u32 read_reason_mem_thermal(struct xe_gt *gt)
+{
+	u32 mem_thermal = xe_gt_throttle_get_limit_reasons(gt) & MEM_THERMAL_MASK;
+
+	return mem_thermal;
+}
+
+static u32 read_reason_vr_thermal(struct xe_gt *gt)
+{
+	u32 vr_thermal = xe_gt_throttle_get_limit_reasons(gt) & VR_THERMAL_MASK;
+
+	return vr_thermal;
+}
+
+static u32 read_reason_iccmax(struct xe_gt *gt)
+{
+	u32 iccmax = xe_gt_throttle_get_limit_reasons(gt) & ICCMAX_MASK;
+
+	return iccmax;
+}
+
+static u32 read_reason_psys_pl1(struct xe_gt *gt)
+{
+	u32 psys_pl1 = xe_gt_throttle_get_limit_reasons(gt) & PSYS_PL1_MASK;
+
+	return psys_pl1;
+}
+
+static u32 read_reason_psys_pl2(struct xe_gt *gt)
+{
+	u32 psys_pl2 = xe_gt_throttle_get_limit_reasons(gt) & PSYS_PL2_MASK;
+
+	return psys_pl2;
+}
+
+static u32 read_reason_p0_freq(struct xe_gt *gt)
+{
+	u32 p0_freq = xe_gt_throttle_get_limit_reasons(gt) & P0_FREQ_MASK;
+
+	return p0_freq;
+}
+
+static u32 read_reason_psys_crit(struct xe_gt *gt)
+{
+	u32 psys_crit = xe_gt_throttle_get_limit_reasons(gt) & PSYS_CRIT_MASK;
+
+	return psys_crit;
+}
+
 static ssize_t status_show(struct kobject *kobj,
 			   struct kobj_attribute *attr, char *buff)
 {
@@ -169,6 +264,17 @@ static ssize_t reason_thermal_show(struct kobject *kobj,
 }
 static struct kobj_attribute attr_reason_thermal = __ATTR_RO(reason_thermal);
 
+static ssize_t reason_soc_thermal_show(struct kobject *kobj,
+				       struct kobj_attribute *attr, char *buff)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct xe_gt *gt = dev_to_gt(dev);
+	bool thermal = !!read_reason_soc_thermal(gt);
+
+	return sysfs_emit(buff, "%u\n", thermal);
+}
+static struct kobj_attribute attr_reason_soc_thermal = __ATTR_RO(reason_soc_thermal);
+
 static ssize_t reason_prochot_show(struct kobject *kobj,
 				   struct kobj_attribute *attr, char *buff)
 {
@@ -202,6 +308,17 @@ static ssize_t reason_vr_thermalert_show(struct kobject *kobj,
 }
 static struct kobj_attribute attr_reason_vr_thermalert = __ATTR_RO(reason_vr_thermalert);
 
+static ssize_t reason_soc_avg_thermal_show(struct kobject *kobj,
+					   struct kobj_attribute *attr, char *buff)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct xe_gt *gt = dev_to_gt(dev);
+	bool avg_thermalert = !!read_reason_soc_avg_thermal(gt);
+
+	return sysfs_emit(buff, "%u\n", avg_thermalert);
+}
+static struct kobj_attribute attr_reason_soc_avg_thermal = __ATTR_RO(reason_soc_avg_thermal);
+
 static ssize_t reason_vr_tdc_show(struct kobject *kobj,
 				  struct kobj_attribute *attr, char *buff)
 {
@@ -213,6 +330,94 @@ static ssize_t reason_vr_tdc_show(struct kobject *kobj,
 }
 static struct kobj_attribute attr_reason_vr_tdc = __ATTR_RO(reason_vr_tdc);
 
+static ssize_t reason_fastvmode_show(struct kobject *kobj,
+				     struct kobj_attribute *attr, char *buff)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct xe_gt *gt = dev_to_gt(dev);
+	bool fastvmode = !!read_reason_fastvmode(gt);
+
+	return sysfs_emit(buff, "%u\n", fastvmode);
+}
+static struct kobj_attribute attr_reason_fastvmode = __ATTR_RO(reason_fastvmode);
+
+static ssize_t reason_mem_thermal_show(struct kobject *kobj,
+				       struct kobj_attribute *attr, char *buff)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct xe_gt *gt = dev_to_gt(dev);
+	bool mem_thermal = !!read_reason_mem_thermal(gt);
+
+	return sysfs_emit(buff, "%u\n", mem_thermal);
+}
+static struct kobj_attribute attr_reason_mem_thermal = __ATTR_RO(reason_mem_thermal);
+
+static ssize_t reason_vr_thermal_show(struct kobject *kobj,
+				      struct kobj_attribute *attr, char *buff)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct xe_gt *gt = dev_to_gt(dev);
+	bool vr_thermal = !!read_reason_vr_thermal(gt);
+
+	return sysfs_emit(buff, "%u\n", vr_thermal);
+}
+static struct kobj_attribute attr_reason_vr_thermal = __ATTR_RO(reason_vr_thermal);
+
+static ssize_t reason_iccmax_show(struct kobject *kobj,
+				  struct kobj_attribute *attr, char *buff)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct xe_gt *gt = dev_to_gt(dev);
+	bool iccmax = !!read_reason_iccmax(gt);
+
+	return sysfs_emit(buff, "%u\n", iccmax);
+}
+static struct kobj_attribute attr_reason_iccmax = __ATTR_RO(reason_iccmax);
+
+static ssize_t reason_psys_pl1_show(struct kobject *kobj,
+				    struct kobj_attribute *attr, char *buff)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct xe_gt *gt = dev_to_gt(dev);
+	bool psys_pl1 = !!read_reason_psys_pl1(gt);
+
+	return sysfs_emit(buff, "%u\n", psys_pl1);
+}
+static struct kobj_attribute attr_reason_psys_pl1 = __ATTR_RO(reason_psys_pl1);
+
+static ssize_t reason_psys_pl2_show(struct kobject *kobj,
+				    struct kobj_attribute *attr, char *buff)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct xe_gt *gt = dev_to_gt(dev);
+	bool psys_pl2 = !!read_reason_psys_pl2(gt);
+
+	return sysfs_emit(buff, "%u\n", psys_pl2);
+}
+static struct kobj_attribute attr_reason_psys_pl2 = __ATTR_RO(reason_psys_pl2);
+
+static ssize_t reason_p0_freq_show(struct kobject *kobj,
+				   struct kobj_attribute *attr, char *buff)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct xe_gt *gt = dev_to_gt(dev);
+	bool p0_freq = !!read_reason_p0_freq(gt);
+
+	return sysfs_emit(buff, "%u\n", p0_freq);
+}
+static struct kobj_attribute attr_reason_p0_freq = __ATTR_RO(reason_p0_freq);
+
+static ssize_t reason_psys_crit_show(struct kobject *kobj,
+				     struct kobj_attribute *attr, char *buff)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct xe_gt *gt = dev_to_gt(dev);
+	bool psys_crit = !!read_reason_psys_crit(gt);
+
+	return sysfs_emit(buff, "%u\n", psys_crit);
+}
+static struct kobj_attribute attr_reason_psys_crit = __ATTR_RO(reason_psys_crit);
+
 static struct attribute *throttle_attrs[] = {
 	&attr_status.attr,
 	&attr_reason_pl1.attr,
@@ -226,24 +431,62 @@ static struct attribute *throttle_attrs[] = {
 	NULL
 };
 
+static struct attribute *throttle_cri_specific_attrs[] = {
+	&attr_status.attr,
+	&attr_reason_prochot.attr,
+	&attr_reason_soc_thermal.attr,
+	&attr_reason_mem_thermal.attr,
+	&attr_reason_vr_thermal.attr,
+	&attr_reason_iccmax.attr,
+	&attr_reason_ratl.attr,
+	&attr_reason_soc_avg_thermal.attr,
+	&attr_reason_fastvmode.attr,
+	&attr_reason_pl4.attr,
+	&attr_reason_pl1.attr,
+	&attr_reason_pl2.attr,
+	&attr_reason_psys_pl1.attr,
+	&attr_reason_psys_pl2.attr,
+	&attr_reason_p0_freq.attr,
+	&attr_reason_psys_crit.attr,
+	NULL
+};
+
 static const struct attribute_group throttle_group_attrs = {
 	.name = "throttle",
 	.attrs = throttle_attrs,
 };
 
+static const struct attribute_group cri_throttle_group_attrs = {
+	.name = "throttle",
+	.attrs = throttle_cri_specific_attrs,
+};
+
+static const struct attribute_group *get_platform_throttle_group(struct xe_device *xe)
+{
+	switch (xe->info.platform) {
+	case XE_CRESCENTISLAND:
+		return &cri_throttle_group_attrs;
+	default:
+		return &throttle_group_attrs;
+	}
+}
+
 static void gt_throttle_sysfs_fini(void *arg)
 {
 	struct xe_gt *gt = arg;
+	struct xe_device *xe = gt_to_xe(gt);
+	const struct attribute_group *group = get_platform_throttle_group(xe);
 
-	sysfs_remove_group(gt->freq, &throttle_group_attrs);
+	sysfs_remove_group(gt->freq, group);
 }
 
 int xe_gt_throttle_init(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
+	const struct attribute_group *group = get_platform_throttle_group(xe);
 	int err;
 
-	err = sysfs_create_group(gt->freq, &throttle_group_attrs);
+	err = sysfs_create_group(gt->freq, group);
 	if (err)
 		return err;
 

-- 
2.51.0

Re: [PATCH 4/12] drm/xe/cri: Add new performance limit reasons bits

[Raag Jadav]

On Tue, Oct 21, 2025 at 10:17:36PM -0700, Sk Anirban wrote:
> Add support for additional performance limit reasons in
> GT0_PERF_LIMIT_REASONS register.
> 
> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
> ---
> There are some improvements to be made here before applying to reduce
> the amount of code for one platform. I plan to take a look on that for
> v2.

Yes, I had planned this but there were some concerns related to backporting
(in case there arises such a requirement). I'll leave the final call to you.

Raag

> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---

Re: [PATCH 4/12] drm/xe/cri: Add new performance limit reasons bits

[Lucas De Marchi]

On Wed, Oct 22, 2025 at 08:31:39AM +0200, Raag Jadav wrote:
>On Tue, Oct 21, 2025 at 10:17:36PM -0700, Sk Anirban wrote:
>> Add support for additional performance limit reasons in
>> GT0_PERF_LIMIT_REASONS register.
>>
>> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
>> ---
>> There are some improvements to be made here before applying to reduce
>> the amount of code for one platform. I plan to take a look on that for
>> v2.
>
>Yes, I had planned this but there were some concerns related to backporting
>(in case there arises such a requirement). I'll leave the final call to you.

Not sure for what version it would be backported. It would certainly not
be a clean backport due to other parts of the code. Also, if we do the
cleanup as soon as we notice it will be needed, then hopefully the
kernel version will be already old enough that the other parts on top
apply cleanly. However, since now adding the refactor before the
CRI-specific part would only make it harder to apply, I will do some
minimal cleanup squashed in this patch and tidy up things on top.

thanks
Lucas De Marchi

>
>Raag
>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---

[PATCH 05/12] drm/xe/cri: Add check to verify if CSC is a PCIe endpoint

[Lucas De Marchi]

From: Soham Purkait <soham.purkait@intel.com>

Add check to verify if CSC is a PCIe endpoint via pcode mailbox
during xe modprobe. If this mode is not supported, an auxiliary
child device for the MEI driver is created as a fallback flow.

Signed-off-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_heci_gsc.c  | 30 +++++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_pcode_api.h |  1 +
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c
index a415ca4887914..c2a365b7e0f6f 100644
--- a/drivers/gpu/drm/xe/xe_heci_gsc.c
+++ b/drivers/gpu/drm/xe/xe_heci_gsc.c
@@ -8,11 +8,15 @@
 #include <linux/pci.h>
 #include <linux/sizes.h>
 
+#include "xe_device.h"
 #include "xe_device_types.h"
 #include "xe_drv.h"
 #include "xe_heci_gsc.h"
 #include "regs/xe_gsc_regs.h"
+#include "xe_pcode.h"
+#include "xe_pcode_api.h"
 #include "xe_platform_types.h"
+#include "xe_pm.h"
 #include "xe_survivability_mode.h"
 
 #define GSC_BAR_LENGTH  0x00000FFC
@@ -41,6 +45,25 @@ static int heci_gsc_irq_init(int irq)
 	return irq_set_chip_data(irq, NULL);
 }
 
+/*
+ * is_csc_pci_ep - Check whether CSC is exposed as a PCIe endpoint through
+ * pcode mailbox sub-command PCODE_STATUS_SUBCOMMAND_CSC_PCIE_DEVICE_STATUS.
+ */
+static bool is_csc_pci_ep(struct xe_device *xe)
+{
+	int ret = 0;
+	u32 val;
+
+	xe_pm_runtime_get(xe);
+	ret = xe_pcode_read(xe_device_get_root_tile(xe),
+			    PCODE_MBOX(DGFX_PCODE_STATUS,
+				       DGFX_CSC_PCIE_DEVICE_STATUS, 0),
+				       &val, NULL);
+	xe_pm_runtime_put(xe);
+
+	return !ret && (val & 0x1U);
+}
+
 /**
  * struct heci_gsc_def - graphics security controller heci interface definitions
  *
@@ -178,7 +201,12 @@ int xe_heci_gsc_init(struct xe_device *xe)
 
 	heci_gsc->irq = -1;
 
-	if (xe->info.platform == XE_BATTLEMAGE) {
+	if (xe->info.platform == XE_CRESCENTISLAND) {
+		if (is_csc_pci_ep(xe))
+			return 0;
+
+		def = &heci_gsc_def_dg2;
+	} else if (xe->info.platform == XE_BATTLEMAGE) {
 		def = &heci_gsc_def_dg2;
 	} else if (xe->info.platform == XE_PVC) {
 		def = &heci_gsc_def_pvc;
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 92bfcba51e199..bd32af0b5a23f 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -35,6 +35,7 @@
 #define     DGFX_GET_INIT_STATUS	0x0
 #define     DGFX_INIT_STATUS_COMPLETE	0x1
 #define     DGFX_LINK_DOWNGRADE_STATUS	REG_BIT(31)
+#define     DGFX_CSC_PCIE_DEVICE_STATUS 0x3
 
 #define   PCODE_POWER_SETUP			0x7C
 #define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4

-- 
2.51.0

[PATCH 06/12] drm/xe/pm: Enable D3cold WAKE# support

[Lucas De Marchi]

From: Raag Jadav <raag.jadav@intel.com>

CRI supports signalling the host through WAKE# pin on smbus alerts while
in D3cold. Enable/disable this feature based on device/host configuration.

Cc: Riana Tauro <riana.tauro@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h |  4 ++++
 drivers/gpu/drm/xe/xe_i2c.c          | 38 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_pcode_api.h    |  5 +++++
 drivers/gpu/drm/xe/xe_pm.c           | 34 ++++++++++++++++++++++++++++++++
 4 files changed, 81 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 02c04ad7296e4..f1e3b16897d1b 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -520,6 +520,10 @@ struct xe_device {
 		 * Default threshold value is 300mb.
 		 */
 		u32 vram_threshold;
+
+		/** @d3cold.wake: Indicates d3cold WAKE# capability of device */
+		u32 wake;
+
 		/** @d3cold.lock: protect vram_threshold */
 		struct mutex lock;
 	} d3cold;
diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c
index 0b5452be0c873..65788c02556ff 100644
--- a/drivers/gpu/drm/xe/xe_i2c.c
+++ b/drivers/gpu/drm/xe/xe_i2c.c
@@ -16,9 +16,11 @@
 #include <linux/notifier.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
+#include <linux/pm_wakeup.h>
 #include <linux/property.h>
 #include <linux/regmap.h>
 #include <linux/sprintf.h>
+#include <linux/string_choices.h>
 #include <linux/string.h>
 #include <linux/types.h>
 #include <linux/workqueue.h>
@@ -30,6 +32,8 @@
 #include "xe_device_types.h"
 #include "xe_i2c.h"
 #include "xe_mmio.h"
+#include "xe_pcode_api.h"
+#include "xe_pcode.h"
 #include "xe_platform_types.h"
 
 /**
@@ -265,6 +269,37 @@ static const struct regmap_config i2c_regmap_config = {
 	.fast_io = true,
 };
 
+static void xe_i2c_d3cold_wake(struct xe_device *xe)
+{
+	struct xe_tile *root_tile = xe_device_get_root_tile(xe);
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	struct pci_dev *root_pdev;
+	bool wakeup;
+	u32 val;
+	int ret;
+
+	/* Check D3cold WAKE# support for I2C */
+	if (!REG_FIELD_GET(I2C_WAKE_ENABLE, xe->d3cold.wake))
+		return;
+
+	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_D3COLD_WAKE, READ_MODE, 0), &val, NULL);
+	if (ret)
+		return;
+
+	root_pdev = pcie_find_root_port(pdev);
+	wakeup = root_pdev && device_may_wakeup(&root_pdev->dev);
+	if (wakeup)
+		val |= I2C_WAKE_ENABLE;
+	else
+		val &= ~I2C_WAKE_ENABLE;
+
+	ret = xe_pcode_write(root_tile, PCODE_MBOX(PCODE_D3COLD_WAKE, WRITE_MODE, 0), val);
+	if (ret)
+		return;
+
+	drm_dbg(&xe->drm, "d3cold: I2C WAKE# %s\n", str_enabled_disabled(wakeup));
+}
+
 void xe_i2c_pm_suspend(struct xe_device *xe)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
@@ -272,6 +307,9 @@ void xe_i2c_pm_suspend(struct xe_device *xe)
 	if (!xe_i2c_present(xe))
 		return;
 
+	if (xe->d3cold.allowed)
+		xe_i2c_d3cold_wake(xe);
+
 	xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D3hot);
 	drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCSR));
 }
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index bd32af0b5a23f..9f4b0d29c4e29 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -51,6 +51,11 @@
 #define	READ_PL_FROM_FW				0x1
 #define	READ_PL_FROM_PCODE			0x0
 
+#define   PCODE_D3COLD_WAKE			0x5A
+#define     READ_MODE				0x0
+#define     WRITE_MODE				0x1
+#define       I2C_WAKE_ENABLE			REG_BIT(1)
+
 #define   PCODE_LATE_BINDING			0x5C
 #define     GET_CAPABILITY_STATUS		0x0
 #define       V1_FAN_SUPPORTED			REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
index 210298c4bcb15..93a19822983ce 100644
--- a/drivers/gpu/drm/xe/xe_pm.c
+++ b/drivers/gpu/drm/xe/xe_pm.c
@@ -7,6 +7,7 @@
 
 #include <linux/fault-inject.h>
 #include <linux/pm_runtime.h>
+#include <linux/pm_wakeup.h>
 #include <linux/suspend.h>
 
 #include <drm/drm_managed.h>
@@ -22,6 +23,7 @@
 #include "xe_i2c.h"
 #include "xe_irq.h"
 #include "xe_late_bind_fw.h"
+#include "xe_pcode_api.h"
 #include "xe_pcode.h"
 #include "xe_pxp.h"
 #include "xe_sriov_vf_ccs.h"
@@ -418,6 +420,35 @@ static int xe_pm_notifier_callback(struct notifier_block *nb,
 	return NOTIFY_DONE;
 }
 
+static void xe_pm_d3cold_wake(struct xe_device *xe)
+{
+	struct xe_tile *root_tile = xe_device_get_root_tile(xe);
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	struct pci_dev *root_pdev;
+	int err;
+
+	err = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_D3COLD_WAKE, READ_MODE, 0),
+			    &xe->d3cold.wake, NULL);
+	if (err || !xe->d3cold.wake) {
+		drm_dbg(&xe->drm, "d3cold: WAKE# not supported by device\n");
+		return;
+	}
+
+	root_pdev = pcie_find_root_port(pdev);
+	if (!root_pdev || !device_can_wakeup(&root_pdev->dev)) {
+		drm_dbg(&xe->drm, "d3cold: WAKE# not supported by host\n");
+		xe->d3cold.wake = 0;
+		goto out;
+	}
+
+	if (!xe_i2c_present(xe))
+		xe->d3cold.wake &= ~I2C_WAKE_ENABLE;
+
+	drm_dbg(&xe->drm, "d3cold: WAKE# configuration 0x%08x\n", xe->d3cold.wake);
+out:
+	xe_pcode_write(root_tile, PCODE_MBOX(PCODE_D3COLD_WAKE, WRITE_MODE, 0), xe->d3cold.wake);
+}
+
 /**
  * xe_pm_init - Initialize Xe Power Management
  * @xe: xe device instance
@@ -455,6 +486,9 @@ int xe_pm_init(struct xe_device *xe)
 			goto err_unregister;
 	}
 
+	if (xe->info.platform == XE_CRESCENTISLAND)
+		xe_pm_d3cold_wake(xe);
+
 	xe_pm_runtime_init(xe);
 	return 0;
 

-- 
2.51.0

Re: [PATCH 6/12] drm/xe/pm: Enable D3cold WAKE# support

[Raag Jadav]

On Tue, Oct 21, 2025 at 10:17:38PM -0700, Raag Jadav wrote:
> CRI supports signalling the host through WAKE# pin on smbus alerts while
> in D3cold. Enable/disable this feature based on device/host configuration.

Thanks for picking this up. Although this made sense when I originally
wrote it, looking at it now I think this can be improved.

Let me spin this out separately if it's okay with you.

Raag

> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---

Re: [PATCH 6/12] drm/xe/pm: Enable D3cold WAKE# support

[Lucas De Marchi]

On Wed, Oct 22, 2025 at 08:35:13AM +0200, Raag Jadav wrote:
>On Tue, Oct 21, 2025 at 10:17:38PM -0700, Raag Jadav wrote:
>> CRI supports signalling the host through WAKE# pin on smbus alerts while
>> in D3cold. Enable/disable this feature based on device/host configuration.
>
>Thanks for picking this up. Although this made sense when I originally
>wrote it, looking at it now I think this can be improved.
>
>Let me spin this out separately if it's okay with you.

yeah, sounds good. Just please Cc me so I can keep track of pending
things.

thanks
Lucas De Marchi

>
>Raag
>
>> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---

[PATCH 07/12] drm/xe: Add device flag to indicate standalone MERT

[Lucas De Marchi]

From: Lukasz Laguna <lukasz.laguna@intel.com>

The MERT subsystem manages memory accesses between host and device. On
the Crescent Island platform, it requires direct management by the
driver.

Introduce a device flag and corresponding helpers to identify platforms
with standalone MERT, enabling proper initialization and handling.

Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_device.h       | 5 +++++
 drivers/gpu/drm/xe/xe_device_types.h | 2 ++
 drivers/gpu/drm/xe/xe_pci.c          | 2 ++
 drivers/gpu/drm/xe/xe_pci_types.h    | 1 +
 4 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 32cc6323b7f64..6604b89330d51 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -172,6 +172,11 @@ static inline bool xe_device_has_lmtt(struct xe_device *xe)
 	return IS_DGFX(xe);
 }
 
+static inline bool xe_device_has_mert(struct xe_device *xe)
+{
+	return xe->info.has_mert;
+}
+
 u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size);
 
 void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p);
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index f1e3b16897d1b..fb401809fae5a 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -305,6 +305,8 @@ struct xe_device {
 		 * pcode mailbox commands.
 		 */
 		u8 has_mbx_power_limits:1;
+		/** @info.has_mert: Device has standalone MERT */
+		u8 has_mert:1;
 		/** @info.has_pxp: Device has PXP support */
 		u8 has_pxp:1;
 		/** @info.has_range_tlb_inval: Has range based TLB invalidations */
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 000bb30b97712..ef27d17d904b8 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -403,6 +403,7 @@ static const struct xe_device_desc cri_desc = {
 	.has_display = false,
 	.has_flat_ccs = false,
 	.has_mbx_power_limits = true,
+	.has_mert = true,
 	.has_sriov = true,
 	.max_gt_per_tile = 2,
 	.require_force_probe = true,
@@ -669,6 +670,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
 	xe->info.has_late_bind = desc->has_late_bind;
 	xe->info.has_llc = desc->has_llc;
+	xe->info.has_mert = desc->has_mert;
 	xe->info.has_pxp = desc->has_pxp;
 	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
 		desc->has_sriov;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index a4451bdc79fb3..3e3bcdd1d1cf1 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -46,6 +46,7 @@ struct xe_device_desc {
 	u8 has_late_bind:1;
 	u8 has_llc:1;
 	u8 has_mbx_power_limits:1;
+	u8 has_mert:1;
 	u8 has_pxp:1;
 	u8 has_sriov:1;
 	u8 needs_scratch:1;

-- 
2.51.0

Re: [PATCH 07/12] drm/xe: Add device flag to indicate standalone MERT

[Dixit, Ashutosh]

On Tue, 21 Oct 2025 22:17:39 -0700, Lucas De Marchi wrote:
>
> From: Lukasz Laguna <lukasz.laguna@intel.com>
>
> The MERT subsystem manages memory accesses between host and device. On
> the Crescent Island platform, it requires direct management by the
> driver.
>
> Introduce a device flag and corresponding helpers to identify platforms
> with standalone MERT, enabling proper initialization and handling.

Looks like all future dGfx products may or may not have this, so we need a
has_mert flag, such as introduced here. So this LGTM:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

>
> Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device.h       | 5 +++++
>  drivers/gpu/drm/xe/xe_device_types.h | 2 ++
>  drivers/gpu/drm/xe/xe_pci.c          | 2 ++
>  drivers/gpu/drm/xe/xe_pci_types.h    | 1 +
>  4 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
> index 32cc6323b7f64..6604b89330d51 100644
> --- a/drivers/gpu/drm/xe/xe_device.h
> +++ b/drivers/gpu/drm/xe/xe_device.h
> @@ -172,6 +172,11 @@ static inline bool xe_device_has_lmtt(struct xe_device *xe)
>	return IS_DGFX(xe);
>  }
>
> +static inline bool xe_device_has_mert(struct xe_device *xe)
> +{
> +	return xe->info.has_mert;
> +}
> +
>  u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size);
>
>  void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p);
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index f1e3b16897d1b..fb401809fae5a 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -305,6 +305,8 @@ struct xe_device {
>		 * pcode mailbox commands.
>		 */
>		u8 has_mbx_power_limits:1;
> +		/** @info.has_mert: Device has standalone MERT */
> +		u8 has_mert:1;
>		/** @info.has_pxp: Device has PXP support */
>		u8 has_pxp:1;
>		/** @info.has_range_tlb_inval: Has range based TLB invalidations */
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 000bb30b97712..ef27d17d904b8 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -403,6 +403,7 @@ static const struct xe_device_desc cri_desc = {
>	.has_display = false,
>	.has_flat_ccs = false,
>	.has_mbx_power_limits = true,
> +	.has_mert = true,
>	.has_sriov = true,
>	.max_gt_per_tile = 2,
>	.require_force_probe = true,
> @@ -669,6 +670,7 @@ static int xe_info_init_early(struct xe_device *xe,
>	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
>	xe->info.has_late_bind = desc->has_late_bind;
>	xe->info.has_llc = desc->has_llc;
> +	xe->info.has_mert = desc->has_mert;
>	xe->info.has_pxp = desc->has_pxp;
>	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
>		desc->has_sriov;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index a4451bdc79fb3..3e3bcdd1d1cf1 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -46,6 +46,7 @@ struct xe_device_desc {
>	u8 has_late_bind:1;
>	u8 has_llc:1;
>	u8 has_mbx_power_limits:1;
> +	u8 has_mert:1;
>	u8 has_pxp:1;
>	u8 has_sriov:1;
>	u8 needs_scratch:1;
>
> --
> 2.51.0
>

[PATCH 08/12] drm/xe/oa/uapi: Expose MERT OA unit

[Lucas De Marchi]

From: Ashutosh Dixit <ashutosh.dixit@intel.com>

A MERT OA unit is available in the SoC on some platforms. Add support
for this OA unit and expose it to userspace. The MERT OA unit does not
have any HW engines attached, but is otherwise similar to an OAM unit.

Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_oa_regs.h |  9 +++++++++
 drivers/gpu/drm/xe/xe_oa.c           | 36 +++++++++++++++++++++++++++++++++---
 include/uapi/drm/xe_drm.h            |  3 +++
 3 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_oa_regs.h b/drivers/gpu/drm/xe/regs/xe_oa_regs.h
index e693a50706f84..72334bd660751 100644
--- a/drivers/gpu/drm/xe/regs/xe_oa_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_oa_regs.h
@@ -100,4 +100,13 @@
 #define OAM_COMPRESSION_T3_CONTROL		XE_REG(0x1c2e00)
 #define  OAM_LAT_MEASURE_ENABLE			REG_BIT(4)
 
+#define OAMERT_CONTROL				XE_REG(0x1453a0)
+#define OAMERT_DEBUG				XE_REG(0x1453a4)
+#define OAMERT_STATUS				XE_REG(0x1453a8)
+#define OAMERT_HEAD_POINTER			XE_REG(0x1453ac)
+#define OAMERT_TAIL_POINTER			XE_REG(0x1453b0)
+#define OAMERT_BUFFER				XE_REG(0x1453b4)
+#define OAMERT_CONTEXT_CONTROL			XE_REG(0x1453c8)
+#define OAMERT_MMIO_TRG				XE_REG(0x1453cc)
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index f901ba52b4032..4aea94d438d40 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -1915,6 +1915,7 @@ static bool oa_unit_supports_oa_format(struct xe_oa_open_param *param, int type)
 			type == DRM_XE_OA_FMT_TYPE_OAC || type == DRM_XE_OA_FMT_TYPE_PEC;
 	case DRM_XE_OA_UNIT_TYPE_OAM:
 	case DRM_XE_OA_UNIT_TYPE_OAM_SAG:
+	case DRM_XE_OA_UNIT_TYPE_MERT:
 		return type == DRM_XE_OA_FMT_TYPE_OAM || type == DRM_XE_OA_FMT_TYPE_OAM_MPEC;
 	default:
 		return false;
@@ -2206,6 +2207,8 @@ static const struct xe_mmio_range xe2_oa_mux_regs[] = {
 	{ .start = 0xE18C, .end = 0xE18C },	/* SAMPLER_MODE */
 	{ .start = 0xE590, .end = 0xE590 },	/* TDL_LSC_LAT_MEASURE_TDL_GFX */
 	{ .start = 0x13000, .end = 0x137FC },	/* PES_0_PESL0 - PES_63_UPPER_PESL3 */
+	{ .start = 0x145194, .end = 0x145194 },	/* SYS_MEM_LAT_MEASURE */
+	{ .start = 0x145340, .end = 0x14537C },	/* MERTSS_PES_0 - MERTSS_PES_7 */
 	{},
 };
 
@@ -2495,7 +2498,12 @@ int xe_oa_register(struct xe_device *xe)
 static u32 num_oa_units_per_gt(struct xe_gt *gt)
 {
 	if (xe_gt_is_main_type(gt) || GRAPHICS_VER(gt_to_xe(gt)) < 20)
-		return 1;
+		/*
+		 * Mert OA unit belongs to the SoC, not a gt, so should be accessed using
+		 * xe_root_tile_mmio(). However, for all known platforms this is the same as
+		 * accessing via xe_root_mmio_gt()->mmio.
+		 */
+		return xe_device_has_mert(gt_to_xe(gt)) ? 2 : 1;
 	else if (!IS_DGFX(gt_to_xe(gt)))
 		return XE_OAM_UNIT_SCMI_0 + 1; /* SAG + SCMI_0 */
 	else
@@ -2577,6 +2585,21 @@ static struct xe_oa_regs __oag_regs(void)
 	};
 }
 
+static struct xe_oa_regs __oamert_regs(void)
+{
+	return (struct xe_oa_regs) {
+		0,
+		OAMERT_HEAD_POINTER,
+		OAMERT_TAIL_POINTER,
+		OAMERT_BUFFER,
+		OAMERT_CONTEXT_CONTROL,
+		OAMERT_CONTROL,
+		OAMERT_DEBUG,
+		OAMERT_STATUS,
+		OAM_CONTROL_COUNTER_SEL_MASK,
+	};
+}
+
 static void __xe_oa_init_oa_units(struct xe_gt *gt)
 {
 	/* Actual address is MEDIA_GT_GSI_OFFSET + oam_base_addr[i] */
@@ -2591,8 +2614,15 @@ static void __xe_oa_init_oa_units(struct xe_gt *gt)
 		struct xe_oa_unit *u = &gt->oa.oa_unit[i];
 
 		if (xe_gt_is_main_type(gt)) {
-			u->regs = __oag_regs();
-			u->type = DRM_XE_OA_UNIT_TYPE_OAG;
+			if (!i) {
+				u->regs = __oag_regs();
+				u->type = DRM_XE_OA_UNIT_TYPE_OAG;
+			} else {
+				xe_gt_assert(gt, xe_device_has_mert(gt_to_xe(gt)));
+				xe_gt_assert(gt, gt == xe_root_mmio_gt(gt_to_xe(gt)));
+				u->regs = __oamert_regs();
+				u->type = DRM_XE_OA_UNIT_TYPE_MERT;
+			}
 		} else {
 			xe_gt_assert(gt, GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270);
 			u->regs = __oam_regs(oam_base_addr[i]);
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 47853659a705e..09599dcc816d6 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -1654,6 +1654,9 @@ enum drm_xe_oa_unit_type {
 
 	/** @DRM_XE_OA_UNIT_TYPE_OAM_SAG: OAM_SAG OA unit */
 	DRM_XE_OA_UNIT_TYPE_OAM_SAG,
+
+	/** @DRM_XE_OA_UNIT_TYPE_MERT: MERT OA unit */
+	DRM_XE_OA_UNIT_TYPE_MERT,
 };
 
 /**

-- 
2.51.0

Re: [PATCH 08/12] drm/xe/oa/uapi: Expose MERT OA unit

[Umesh Nerlige Ramappa]

On Tue, Oct 21, 2025 at 10:17:40PM -0700, Lucas De Marchi wrote:
>From: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
>A MERT OA unit is available in the SoC on some platforms. Add support
>for this OA unit and expose it to userspace. The MERT OA unit does not
>have any HW engines attached, but is otherwise similar to an OAM unit.
>
>Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Looks good,

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Regards,
Umesh

>---
> drivers/gpu/drm/xe/regs/xe_oa_regs.h |  9 +++++++++
> drivers/gpu/drm/xe/xe_oa.c           | 36 +++++++++++++++++++++++++++++++++---
> include/uapi/drm/xe_drm.h            |  3 +++
> 3 files changed, 45 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_oa_regs.h b/drivers/gpu/drm/xe/regs/xe_oa_regs.h
>index e693a50706f84..72334bd660751 100644
>--- a/drivers/gpu/drm/xe/regs/xe_oa_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_oa_regs.h
>@@ -100,4 +100,13 @@
> #define OAM_COMPRESSION_T3_CONTROL		XE_REG(0x1c2e00)
> #define  OAM_LAT_MEASURE_ENABLE			REG_BIT(4)
>
>+#define OAMERT_CONTROL				XE_REG(0x1453a0)
>+#define OAMERT_DEBUG				XE_REG(0x1453a4)
>+#define OAMERT_STATUS				XE_REG(0x1453a8)
>+#define OAMERT_HEAD_POINTER			XE_REG(0x1453ac)
>+#define OAMERT_TAIL_POINTER			XE_REG(0x1453b0)
>+#define OAMERT_BUFFER				XE_REG(0x1453b4)
>+#define OAMERT_CONTEXT_CONTROL			XE_REG(0x1453c8)
>+#define OAMERT_MMIO_TRG				XE_REG(0x1453cc)
>+
> #endif
>diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
>index f901ba52b4032..4aea94d438d40 100644
>--- a/drivers/gpu/drm/xe/xe_oa.c
>+++ b/drivers/gpu/drm/xe/xe_oa.c
>@@ -1915,6 +1915,7 @@ static bool oa_unit_supports_oa_format(struct xe_oa_open_param *param, int type)
> 			type == DRM_XE_OA_FMT_TYPE_OAC || type == DRM_XE_OA_FMT_TYPE_PEC;
> 	case DRM_XE_OA_UNIT_TYPE_OAM:
> 	case DRM_XE_OA_UNIT_TYPE_OAM_SAG:
>+	case DRM_XE_OA_UNIT_TYPE_MERT:
> 		return type == DRM_XE_OA_FMT_TYPE_OAM || type == DRM_XE_OA_FMT_TYPE_OAM_MPEC;
> 	default:
> 		return false;
>@@ -2206,6 +2207,8 @@ static const struct xe_mmio_range xe2_oa_mux_regs[] = {
> 	{ .start = 0xE18C, .end = 0xE18C },	/* SAMPLER_MODE */
> 	{ .start = 0xE590, .end = 0xE590 },	/* TDL_LSC_LAT_MEASURE_TDL_GFX */
> 	{ .start = 0x13000, .end = 0x137FC },	/* PES_0_PESL0 - PES_63_UPPER_PESL3 */
>+	{ .start = 0x145194, .end = 0x145194 },	/* SYS_MEM_LAT_MEASURE */
>+	{ .start = 0x145340, .end = 0x14537C },	/* MERTSS_PES_0 - MERTSS_PES_7 */
> 	{},
> };
>
>@@ -2495,7 +2498,12 @@ int xe_oa_register(struct xe_device *xe)
> static u32 num_oa_units_per_gt(struct xe_gt *gt)
> {
> 	if (xe_gt_is_main_type(gt) || GRAPHICS_VER(gt_to_xe(gt)) < 20)
>-		return 1;
>+		/*
>+		 * Mert OA unit belongs to the SoC, not a gt, so should be accessed using
>+		 * xe_root_tile_mmio(). However, for all known platforms this is the same as
>+		 * accessing via xe_root_mmio_gt()->mmio.
>+		 */
>+		return xe_device_has_mert(gt_to_xe(gt)) ? 2 : 1;
> 	else if (!IS_DGFX(gt_to_xe(gt)))
> 		return XE_OAM_UNIT_SCMI_0 + 1; /* SAG + SCMI_0 */
> 	else
>@@ -2577,6 +2585,21 @@ static struct xe_oa_regs __oag_regs(void)
> 	};
> }
>
>+static struct xe_oa_regs __oamert_regs(void)
>+{
>+	return (struct xe_oa_regs) {
>+		0,
>+		OAMERT_HEAD_POINTER,
>+		OAMERT_TAIL_POINTER,
>+		OAMERT_BUFFER,
>+		OAMERT_CONTEXT_CONTROL,
>+		OAMERT_CONTROL,
>+		OAMERT_DEBUG,
>+		OAMERT_STATUS,
>+		OAM_CONTROL_COUNTER_SEL_MASK,
>+	};
>+}
>+
> static void __xe_oa_init_oa_units(struct xe_gt *gt)
> {
> 	/* Actual address is MEDIA_GT_GSI_OFFSET + oam_base_addr[i] */
>@@ -2591,8 +2614,15 @@ static void __xe_oa_init_oa_units(struct xe_gt *gt)
> 		struct xe_oa_unit *u = &gt->oa.oa_unit[i];
>
> 		if (xe_gt_is_main_type(gt)) {
>-			u->regs = __oag_regs();
>-			u->type = DRM_XE_OA_UNIT_TYPE_OAG;
>+			if (!i) {
>+				u->regs = __oag_regs();
>+				u->type = DRM_XE_OA_UNIT_TYPE_OAG;
>+			} else {
>+				xe_gt_assert(gt, xe_device_has_mert(gt_to_xe(gt)));
>+				xe_gt_assert(gt, gt == xe_root_mmio_gt(gt_to_xe(gt)));
>+				u->regs = __oamert_regs();
>+				u->type = DRM_XE_OA_UNIT_TYPE_MERT;
>+			}
> 		} else {
> 			xe_gt_assert(gt, GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270);
> 			u->regs = __oam_regs(oam_base_addr[i]);
>diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>index 47853659a705e..09599dcc816d6 100644
>--- a/include/uapi/drm/xe_drm.h
>+++ b/include/uapi/drm/xe_drm.h
>@@ -1654,6 +1654,9 @@ enum drm_xe_oa_unit_type {
>
> 	/** @DRM_XE_OA_UNIT_TYPE_OAM_SAG: OAM_SAG OA unit */
> 	DRM_XE_OA_UNIT_TYPE_OAM_SAG,
>+
>+	/** @DRM_XE_OA_UNIT_TYPE_MERT: MERT OA unit */
>+	DRM_XE_OA_UNIT_TYPE_MERT,
> };
>
> /**
>
>-- 
>2.51.0
>

Re: [PATCH 08/12] drm/xe/oa/uapi: Expose MERT OA unit

[Dixit, Ashutosh]

On Wed, 22 Oct 2025 16:09:41 -0700, Umesh Nerlige Ramappa wrote:
>
> On Tue, Oct 21, 2025 at 10:17:40PM -0700, Lucas De Marchi wrote:
> > From: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >
> > A MERT OA unit is available in the SoC on some platforms. Add support
> > for this OA unit and expose it to userspace. The MERT OA unit does not
> > have any HW engines attached, but is otherwise similar to an OAM unit.
> >
> > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Looks good,
>
> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Currently there is some uncertainty about this feature. Because of this I
don't want to merge this patch at present. So please don't merge this
now. I will resend the patch at appropriate time when there is more
clarity. Thanks.

>
> Regards,
> Umesh
>
> > ---
> > drivers/gpu/drm/xe/regs/xe_oa_regs.h |  9 +++++++++
> > drivers/gpu/drm/xe/xe_oa.c           | 36 +++++++++++++++++++++++++++++++++---
> > include/uapi/drm/xe_drm.h            |  3 +++
> > 3 files changed, 45 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/regs/xe_oa_regs.h b/drivers/gpu/drm/xe/regs/xe_oa_regs.h
> > index e693a50706f84..72334bd660751 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_oa_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_oa_regs.h
> > @@ -100,4 +100,13 @@
> > #define OAM_COMPRESSION_T3_CONTROL		XE_REG(0x1c2e00)
> > #define  OAM_LAT_MEASURE_ENABLE			REG_BIT(4)
> >
> > +#define OAMERT_CONTROL				XE_REG(0x1453a0)
> > +#define OAMERT_DEBUG				XE_REG(0x1453a4)
> > +#define OAMERT_STATUS				XE_REG(0x1453a8)
> > +#define OAMERT_HEAD_POINTER			XE_REG(0x1453ac)
> > +#define OAMERT_TAIL_POINTER			XE_REG(0x1453b0)
> > +#define OAMERT_BUFFER				XE_REG(0x1453b4)
> > +#define OAMERT_CONTEXT_CONTROL			XE_REG(0x1453c8)
> > +#define OAMERT_MMIO_TRG				XE_REG(0x1453cc)
> > +
> > #endif
> > diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> > index f901ba52b4032..4aea94d438d40 100644
> > --- a/drivers/gpu/drm/xe/xe_oa.c
> > +++ b/drivers/gpu/drm/xe/xe_oa.c
> > @@ -1915,6 +1915,7 @@ static bool oa_unit_supports_oa_format(struct xe_oa_open_param *param, int type)
> >			type == DRM_XE_OA_FMT_TYPE_OAC || type == DRM_XE_OA_FMT_TYPE_PEC;
> >	case DRM_XE_OA_UNIT_TYPE_OAM:
> >	case DRM_XE_OA_UNIT_TYPE_OAM_SAG:
> > +	case DRM_XE_OA_UNIT_TYPE_MERT:
> >		return type == DRM_XE_OA_FMT_TYPE_OAM || type == DRM_XE_OA_FMT_TYPE_OAM_MPEC;
> >	default:
> >		return false;
> > @@ -2206,6 +2207,8 @@ static const struct xe_mmio_range xe2_oa_mux_regs[] = {
> >	{ .start = 0xE18C, .end = 0xE18C },	/* SAMPLER_MODE */
> >	{ .start = 0xE590, .end = 0xE590 },	/* TDL_LSC_LAT_MEASURE_TDL_GFX */
> >	{ .start = 0x13000, .end = 0x137FC },	/* PES_0_PESL0 - PES_63_UPPER_PESL3 */
> > +	{ .start = 0x145194, .end = 0x145194 },	/* SYS_MEM_LAT_MEASURE */
> > +	{ .start = 0x145340, .end = 0x14537C },	/* MERTSS_PES_0 - MERTSS_PES_7 */
> >	{},
> > };
> >
> > @@ -2495,7 +2498,12 @@ int xe_oa_register(struct xe_device *xe)
> > static u32 num_oa_units_per_gt(struct xe_gt *gt)
> > {
> >	if (xe_gt_is_main_type(gt) || GRAPHICS_VER(gt_to_xe(gt)) < 20)
> > -		return 1;
> > +		/*
> > +		 * Mert OA unit belongs to the SoC, not a gt, so should be accessed using
> > +		 * xe_root_tile_mmio(). However, for all known platforms this is the same as
> > +		 * accessing via xe_root_mmio_gt()->mmio.
> > +		 */
> > +		return xe_device_has_mert(gt_to_xe(gt)) ? 2 : 1;
> >	else if (!IS_DGFX(gt_to_xe(gt)))
> >		return XE_OAM_UNIT_SCMI_0 + 1; /* SAG + SCMI_0 */
> >	else
> > @@ -2577,6 +2585,21 @@ static struct xe_oa_regs __oag_regs(void)
> >	};
> > }
> >
> > +static struct xe_oa_regs __oamert_regs(void)
> > +{
> > +	return (struct xe_oa_regs) {
> > +		0,
> > +		OAMERT_HEAD_POINTER,
> > +		OAMERT_TAIL_POINTER,
> > +		OAMERT_BUFFER,
> > +		OAMERT_CONTEXT_CONTROL,
> > +		OAMERT_CONTROL,
> > +		OAMERT_DEBUG,
> > +		OAMERT_STATUS,
> > +		OAM_CONTROL_COUNTER_SEL_MASK,
> > +	};
> > +}
> > +
> > static void __xe_oa_init_oa_units(struct xe_gt *gt)
> > {
> >	/* Actual address is MEDIA_GT_GSI_OFFSET + oam_base_addr[i] */
> > @@ -2591,8 +2614,15 @@ static void __xe_oa_init_oa_units(struct xe_gt *gt)
> >		struct xe_oa_unit *u = &gt->oa.oa_unit[i];
> >
> >		if (xe_gt_is_main_type(gt)) {
> > -			u->regs = __oag_regs();
> > -			u->type = DRM_XE_OA_UNIT_TYPE_OAG;
> > +			if (!i) {
> > +				u->regs = __oag_regs();
> > +				u->type = DRM_XE_OA_UNIT_TYPE_OAG;
> > +			} else {
> > +				xe_gt_assert(gt, xe_device_has_mert(gt_to_xe(gt)));
> > +				xe_gt_assert(gt, gt == xe_root_mmio_gt(gt_to_xe(gt)));
> > +				u->regs = __oamert_regs();
> > +				u->type = DRM_XE_OA_UNIT_TYPE_MERT;
> > +			}
> >		} else {
> >			xe_gt_assert(gt, GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270);
> >			u->regs = __oam_regs(oam_base_addr[i]);
> > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > index 47853659a705e..09599dcc816d6 100644
> > --- a/include/uapi/drm/xe_drm.h
> > +++ b/include/uapi/drm/xe_drm.h
> > @@ -1654,6 +1654,9 @@ enum drm_xe_oa_unit_type {
> >
> >	/** @DRM_XE_OA_UNIT_TYPE_OAM_SAG: OAM_SAG OA unit */
> >	DRM_XE_OA_UNIT_TYPE_OAM_SAG,
> > +
> > +	/** @DRM_XE_OA_UNIT_TYPE_MERT: MERT OA unit */
> > +	DRM_XE_OA_UNIT_TYPE_MERT,
> > };
> >
> > /**
> >
> > --
> > 2.51.0
> >

[PATCH 09/12] drm/xe/pf: Configure LMTT in MERT

[Lucas De Marchi]

From: Lukasz Laguna <lukasz.laguna@intel.com>

On platforms with standalone MERT, the PF driver needs to program LMTT
in MERT's LMEM_CFG register.

While at it, sort the includes in drivers/gpu/drm/xe/xe_lmtt.c.

Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_mert_regs.h | 13 +++++++++++++
 drivers/gpu/drm/xe/xe_lmtt.c           | 12 ++++++++++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
new file mode 100644
index 0000000000000..5b7c15e08747e
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_MERT_REGS_H_
+#define _XE_MERT_REGS_H_
+
+#include "regs/xe_reg_defs.h"
+
+#define MERT_LMEM_CFG				XE_REG(0x1448b0)
+
+#endif /* _XE_MERT_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_lmtt.c b/drivers/gpu/drm/xe/xe_lmtt.c
index 4dc1de482eeed..e9f19b2a7b5e1 100644
--- a/drivers/gpu/drm/xe/xe_lmtt.c
+++ b/drivers/gpu/drm/xe/xe_lmtt.c
@@ -8,16 +8,18 @@
 #include <drm/drm_managed.h>
 
 #include "regs/xe_gt_regs.h"
+#include "regs/xe_mert_regs.h"
 
 #include "xe_assert.h"
 #include "xe_bo.h"
-#include "xe_tlb_inval.h"
 #include "xe_lmtt.h"
 #include "xe_map.h"
 #include "xe_mmio.h"
 #include "xe_res_cursor.h"
 #include "xe_sriov.h"
+#include "xe_tile.h"
 #include "xe_tile_sriov_printk.h"
+#include "xe_tlb_inval.h"
 
 /**
  * DOC: Local Memory Translation Table
@@ -196,16 +198,22 @@ static void lmtt_setup_dir_ptr(struct xe_lmtt *lmtt)
 	struct xe_device *xe = tile_to_xe(tile);
 	dma_addr_t offset = xe_bo_main_addr(lmtt->pd->bo, XE_PAGE_SIZE);
 	struct xe_gt *gt;
+	u32 config;
 	u8 id;
 
 	lmtt_debug(lmtt, "DIR offset %pad\n", &offset);
 	lmtt_assert(lmtt, xe_bo_is_vram(lmtt->pd->bo));
 	lmtt_assert(lmtt, IS_ALIGNED(offset, SZ_64K));
 
+	config = LMEM_EN | REG_FIELD_PREP(LMTT_DIR_PTR, offset / SZ_64K);
+
 	for_each_gt_on_tile(gt, tile, id)
 		xe_mmio_write32(&gt->mmio,
 				GRAPHICS_VER(xe) >= 20 ? XE2_LMEM_CFG : LMEM_CFG,
-				LMEM_EN | REG_FIELD_PREP(LMTT_DIR_PTR, offset / SZ_64K));
+				config);
+
+	if (xe_device_has_mert(xe) && xe_tile_is_root(tile))
+		xe_mmio_write32(&tile->mmio, MERT_LMEM_CFG, config);
 }
 
 /**

-- 
2.51.0

[PATCH 10/12] drm/xe: Handle MERT interrupts

[Lucas De Marchi]

From: Lukasz Laguna <lukasz.laguna@intel.com>

The MERT interrupts are indicated via bit 13 in the GFX master interrupt
register. Detect these interrupts and start supporting them.

Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
 drivers/gpu/drm/xe/xe_irq.c           | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 2f97662d958de..9d74f454d3ffd 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -20,6 +20,7 @@
 #define   GU_MISC_IRQ				REG_BIT(29)
 #define   ERROR_IRQ(x)				REG_BIT(26 + (x))
 #define   DISPLAY_IRQ				REG_BIT(16)
+#define   SOC_H2DMEMINT_IRQ			REG_BIT(13)
 #define   I2C_IRQ				REG_BIT(12)
 #define   GT_DW_IRQ(x)				REG_BIT(x)
 
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index e5ed0242f7b1d..011b5eb66102f 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -466,6 +466,12 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
 		xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
 }
 
+static void mert_irq_handler(struct xe_device *xe, u32 master_ctl)
+{
+	if (!(master_ctl & SOC_H2DMEMINT_IRQ))
+		return;
+}
+
 /*
  * Top-level interrupt handler for Xe_LP+ and beyond.  These platforms have
  * a "master tile" interrupt register which must be consulted before the
@@ -525,6 +531,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
 				xe_heci_csc_irq_handler(xe, master_ctl);
 			xe_display_irq_handler(xe, master_ctl);
 			xe_i2c_irq_handler(xe, master_ctl);
+			mert_irq_handler(xe, master_ctl);
 			gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
 		}
 	}

-- 
2.51.0

Re: [PATCH 10/12] drm/xe: Handle MERT interrupts

[Matt Roper]

On Tue, Oct 21, 2025 at 10:17:42PM -0700, Lucas De Marchi wrote:
> From: Lukasz Laguna <lukasz.laguna@intel.com>
> 
> The MERT interrupts are indicated via bit 13 in the GFX master interrupt
> register. Detect these interrupts and start supporting them.

This patch doesn't actually do anything yet; I don't think it needs to
exist on its own.  Can we just squash it into patch #12 where the
interrupt starts being handled?


Matt

> 
> Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
>  drivers/gpu/drm/xe/xe_irq.c           | 7 +++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 2f97662d958de..9d74f454d3ffd 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -20,6 +20,7 @@
>  #define   GU_MISC_IRQ				REG_BIT(29)
>  #define   ERROR_IRQ(x)				REG_BIT(26 + (x))
>  #define   DISPLAY_IRQ				REG_BIT(16)
> +#define   SOC_H2DMEMINT_IRQ			REG_BIT(13)
>  #define   I2C_IRQ				REG_BIT(12)
>  #define   GT_DW_IRQ(x)				REG_BIT(x)
>  
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index e5ed0242f7b1d..011b5eb66102f 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -466,6 +466,12 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
>  		xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
>  }
>  
> +static void mert_irq_handler(struct xe_device *xe, u32 master_ctl)
> +{
> +	if (!(master_ctl & SOC_H2DMEMINT_IRQ))
> +		return;
> +}
> +
>  /*
>   * Top-level interrupt handler for Xe_LP+ and beyond.  These platforms have
>   * a "master tile" interrupt register which must be consulted before the
> @@ -525,6 +531,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>  				xe_heci_csc_irq_handler(xe, master_ctl);
>  			xe_display_irq_handler(xe, master_ctl);
>  			xe_i2c_irq_handler(xe, master_ctl);
> +			mert_irq_handler(xe, master_ctl);
>  			gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
>  		}
>  	}
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 10/12] drm/xe: Handle MERT interrupts

[Lucas De Marchi]

On Wed, Oct 22, 2025 at 04:19:12PM -0700, Matt Roper wrote:
>On Tue, Oct 21, 2025 at 10:17:42PM -0700, Lucas De Marchi wrote:
>> From: Lukasz Laguna <lukasz.laguna@intel.com>
>>
>> The MERT interrupts are indicated via bit 13 in the GFX master interrupt
>> register. Detect these interrupts and start supporting them.
>
>This patch doesn't actually do anything yet; I don't think it needs to
>exist on its own.  Can we just squash it into patch #12 where the
>interrupt starts being handled?

yeah... while reviewing this before sending I checked "is this an
interrupt we are actually doing nothing?". Then I noticed the patches on
top build on it and accepted that as separate. But indeed, both are
small enough that could just be one thing.

thanks
Lucas De Marchi

Re: [PATCH 10/12] drm/xe: Handle MERT interrupts

[Laguna, Lukasz]

On 10/23/2025 16:42, Lucas De Marchi wrote:
> On Wed, Oct 22, 2025 at 04:19:12PM -0700, Matt Roper wrote:
>> On Tue, Oct 21, 2025 at 10:17:42PM -0700, Lucas De Marchi wrote:
>>> From: Lukasz Laguna <lukasz.laguna@intel.com>
>>>
>>> The MERT interrupts are indicated via bit 13 in the GFX master 
>>> interrupt
>>> register. Detect these interrupts and start supporting them.
>>
>> This patch doesn't actually do anything yet; I don't think it needs to
>> exist on its own.  Can we just squash it into patch #12 where the
>> interrupt starts being handled?
>
> yeah... while reviewing this before sending I checked "is this an
> interrupt we are actually doing nothing?". Then I noticed the patches on
> top build on it and accepted that as separate. But indeed, both are
> small enough that could just be one thing.
>
> thanks
> Lucas De Marchi

Good point, I'll squash it.

Thanks,
Lukasz

[PATCH 11/12] drm/xe/pf: Add TLB invalidation support for MERT

[Lucas De Marchi]

From: Lukasz Laguna <lukasz.laguna@intel.com>

Trigger MERT's TLB invalidation after LMTT updates ensuring memory
translations remain coherent.

Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_mert_regs.h     |  3 +++
 drivers/gpu/drm/xe/xe_device_types.h       |  6 ++++++
 drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c | 19 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_irq.c                |  8 ++++++++
 drivers/gpu/drm/xe/xe_sriov_pf.c           |  3 +++
 5 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
index 5b7c15e08747e..aef66c04901d2 100644
--- a/drivers/gpu/drm/xe/regs/xe_mert_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
@@ -10,4 +10,7 @@
 
 #define MERT_LMEM_CFG				XE_REG(0x1448b0)
 
+#define MERT_TLB_INV_DESC_A			XE_REG(0x14cf7c)
+#define   MERT_TLB_INV_DESC_A_VALID		REG_BIT(0)
+
 #endif /* _XE_MERT_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index fb401809fae5a..6fcd35bee73b5 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -219,6 +219,12 @@ struct xe_tile {
 
 	/** @debugfs: debugfs directory associated with this tile */
 	struct dentry *debugfs;
+
+	/** @mert: MERT-related data */
+	struct {
+		/** @mert.tlb_inv_done: completion of TLB invalidation */
+		struct completion tlb_inv_done;
+	} mert;
 };
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
index c0c0215c07036..ebe81cb21f5ab 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
@@ -10,6 +10,7 @@
 #include "abi/guc_klvs_abi.h"
 
 #include "regs/xe_guc_regs.h"
+#include "regs/xe_mert_regs.h"
 
 #include "xe_bo.h"
 #include "xe_device.h"
@@ -31,6 +32,7 @@
 #include "xe_lmtt.h"
 #include "xe_map.h"
 #include "xe_migrate.h"
+#include "xe_mmio.h"
 #include "xe_sriov.h"
 #include "xe_ttm_vram_mgr.h"
 #include "xe_vram_types.h"
@@ -1346,6 +1348,20 @@ static int pf_distribute_config_lmem(struct xe_gt *gt, unsigned int vfid, u64 si
 	return 0;
 }
 
+static void invalidate_mert_lmtt(struct xe_device *xe)
+{
+	const long timeout = HZ / 4;
+	struct xe_tile *tile = xe_device_get_root_tile(xe);
+
+	xe_assert(xe, xe_device_has_mert(xe));
+
+	reinit_completion(&tile->mert.tlb_inv_done);
+	xe_mmio_write32(&tile->mmio, MERT_TLB_INV_DESC_A, MERT_TLB_INV_DESC_A_VALID);
+
+	if (!wait_for_completion_timeout(&tile->mert.tlb_inv_done, timeout))
+		drm_err(&xe->drm, "MERT TLB invalidation timeout\n");
+}
+
 static void pf_force_lmtt_invalidate(struct xe_device *xe)
 {
 	struct xe_lmtt *lmtt;
@@ -1359,6 +1375,9 @@ static void pf_force_lmtt_invalidate(struct xe_device *xe)
 		lmtt = &tile->sriov.pf.lmtt;
 		xe_lmtt_invalidate_hw(lmtt);
 	}
+
+	if (xe_device_has_mert(xe))
+		invalidate_mert_lmtt(xe);
 }
 
 static void pf_reset_vf_lmtt(struct xe_device *xe, unsigned int vfid)
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 011b5eb66102f..82bf0d3995dfe 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -12,6 +12,7 @@
 #include "display/xe_display.h"
 #include "regs/xe_guc_regs.h"
 #include "regs/xe_irq_regs.h"
+#include "regs/xe_mert_regs.h"
 #include "xe_device.h"
 #include "xe_drv.h"
 #include "xe_gsc_proxy.h"
@@ -468,8 +469,15 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
 
 static void mert_irq_handler(struct xe_device *xe, u32 master_ctl)
 {
+	struct xe_tile *tile = xe_device_get_root_tile(xe);
+	u32 reg_val;
+
 	if (!(master_ctl & SOC_H2DMEMINT_IRQ))
 		return;
+
+	reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);
+	if (!(reg_val & MERT_TLB_INV_DESC_A_VALID))
+		complete(&tile->mert.tlb_inv_done);
 }
 
 /*
diff --git a/drivers/gpu/drm/xe/xe_sriov_pf.c b/drivers/gpu/drm/xe/xe_sriov_pf.c
index bc1ab9ee31d92..b40701d75dacb 100644
--- a/drivers/gpu/drm/xe/xe_sriov_pf.c
+++ b/drivers/gpu/drm/xe/xe_sriov_pf.c
@@ -88,6 +88,7 @@ bool xe_sriov_pf_readiness(struct xe_device *xe)
  */
 int xe_sriov_pf_init_early(struct xe_device *xe)
 {
+	struct xe_tile *root_tile = xe_device_get_root_tile(xe);
 	int err;
 
 	xe_assert(xe, IS_SRIOV_PF(xe));
@@ -103,6 +104,8 @@ int xe_sriov_pf_init_early(struct xe_device *xe)
 
 	xe_sriov_pf_service_init(xe);
 
+	init_completion(&root_tile->mert.tlb_inv_done);
+
 	return 0;
 }
 

-- 
2.51.0

Re: [PATCH 11/12] drm/xe/pf: Add TLB invalidation support for MERT

[Matthew Brost]

On Tue, Oct 21, 2025 at 10:17:43PM -0700, Lucas De Marchi wrote:
> From: Lukasz Laguna <lukasz.laguna@intel.com>
> 
> Trigger MERT's TLB invalidation after LMTT updates ensuring memory
> translations remain coherent.
> 
> Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_mert_regs.h     |  3 +++
>  drivers/gpu/drm/xe/xe_device_types.h       |  6 ++++++
>  drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c | 19 +++++++++++++++++++
>  drivers/gpu/drm/xe/xe_irq.c                |  8 ++++++++
>  drivers/gpu/drm/xe/xe_sriov_pf.c           |  3 +++
>  5 files changed, 39 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
> index 5b7c15e08747e..aef66c04901d2 100644
> --- a/drivers/gpu/drm/xe/regs/xe_mert_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
> @@ -10,4 +10,7 @@
>  
>  #define MERT_LMEM_CFG				XE_REG(0x1448b0)
>  
> +#define MERT_TLB_INV_DESC_A			XE_REG(0x14cf7c)
> +#define   MERT_TLB_INV_DESC_A_VALID		REG_BIT(0)
> +
>  #endif /* _XE_MERT_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index fb401809fae5a..6fcd35bee73b5 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -219,6 +219,12 @@ struct xe_tile {
>  
>  	/** @debugfs: debugfs directory associated with this tile */
>  	struct dentry *debugfs;
> +
> +	/** @mert: MERT-related data */
> +	struct {
> +		/** @mert.tlb_inv_done: completion of TLB invalidation */
> +		struct completion tlb_inv_done;
> +	} mert;
>  };
>  
>  /**
> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
> index c0c0215c07036..ebe81cb21f5ab 100644
> --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
> @@ -10,6 +10,7 @@
>  #include "abi/guc_klvs_abi.h"
>  
>  #include "regs/xe_guc_regs.h"
> +#include "regs/xe_mert_regs.h"
>  
>  #include "xe_bo.h"
>  #include "xe_device.h"
> @@ -31,6 +32,7 @@
>  #include "xe_lmtt.h"
>  #include "xe_map.h"
>  #include "xe_migrate.h"
> +#include "xe_mmio.h"
>  #include "xe_sriov.h"
>  #include "xe_ttm_vram_mgr.h"
>  #include "xe_vram_types.h"
> @@ -1346,6 +1348,20 @@ static int pf_distribute_config_lmem(struct xe_gt *gt, unsigned int vfid, u64 si
>  	return 0;
>  }
>  
> +static void invalidate_mert_lmtt(struct xe_device *xe)
> +{
> +	const long timeout = HZ / 4;
> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> +
> +	xe_assert(xe, xe_device_has_mert(xe));
> +

It is not obvious how upper layers which call this function get
exclusive access to what appears to be a per device resource.

Is xe_sriov_pf_master_mutex held here? If so, I'd add a lockdep assert
so this is self documenting on how exclusion is achieved and to prevent
misuse. If not, you probably need a lock here.

Matt

> +	reinit_completion(&tile->mert.tlb_inv_done);
> +	xe_mmio_write32(&tile->mmio, MERT_TLB_INV_DESC_A, MERT_TLB_INV_DESC_A_VALID);
> +
> +	if (!wait_for_completion_timeout(&tile->mert.tlb_inv_done, timeout))
> +		drm_err(&xe->drm, "MERT TLB invalidation timeout\n");
> +}
> +
>  static void pf_force_lmtt_invalidate(struct xe_device *xe)
>  {
>  	struct xe_lmtt *lmtt;
> @@ -1359,6 +1375,9 @@ static void pf_force_lmtt_invalidate(struct xe_device *xe)
>  		lmtt = &tile->sriov.pf.lmtt;
>  		xe_lmtt_invalidate_hw(lmtt);
>  	}
> +
> +	if (xe_device_has_mert(xe))
> +		invalidate_mert_lmtt(xe);
>  }
>  
>  static void pf_reset_vf_lmtt(struct xe_device *xe, unsigned int vfid)
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 011b5eb66102f..82bf0d3995dfe 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -12,6 +12,7 @@
>  #include "display/xe_display.h"
>  #include "regs/xe_guc_regs.h"
>  #include "regs/xe_irq_regs.h"
> +#include "regs/xe_mert_regs.h"
>  #include "xe_device.h"
>  #include "xe_drv.h"
>  #include "xe_gsc_proxy.h"
> @@ -468,8 +469,15 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
>  
>  static void mert_irq_handler(struct xe_device *xe, u32 master_ctl)
>  {
> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> +	u32 reg_val;
> +
>  	if (!(master_ctl & SOC_H2DMEMINT_IRQ))
>  		return;
> +
> +	reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);
> +	if (!(reg_val & MERT_TLB_INV_DESC_A_VALID))
> +		complete(&tile->mert.tlb_inv_done);
>  }
>  
>  /*
> diff --git a/drivers/gpu/drm/xe/xe_sriov_pf.c b/drivers/gpu/drm/xe/xe_sriov_pf.c
> index bc1ab9ee31d92..b40701d75dacb 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_pf.c
> +++ b/drivers/gpu/drm/xe/xe_sriov_pf.c
> @@ -88,6 +88,7 @@ bool xe_sriov_pf_readiness(struct xe_device *xe)
>   */
>  int xe_sriov_pf_init_early(struct xe_device *xe)
>  {
> +	struct xe_tile *root_tile = xe_device_get_root_tile(xe);
>  	int err;
>  
>  	xe_assert(xe, IS_SRIOV_PF(xe));
> @@ -103,6 +104,8 @@ int xe_sriov_pf_init_early(struct xe_device *xe)
>  
>  	xe_sriov_pf_service_init(xe);
>  
> +	init_completion(&root_tile->mert.tlb_inv_done);
> +
>  	return 0;
>  }
>  
> 
> -- 
> 2.51.0
> 

Re: [PATCH 11/12] drm/xe/pf: Add TLB invalidation support for MERT

[Lucas De Marchi]

On Wed, Oct 22, 2025 at 11:28:19AM -0700, Matthew Brost wrote:
>On Tue, Oct 21, 2025 at 10:17:43PM -0700, Lucas De Marchi wrote:
>> From: Lukasz Laguna <lukasz.laguna@intel.com>
>>
>> Trigger MERT's TLB invalidation after LMTT updates ensuring memory
>> translations remain coherent.
>>
>> Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/xe/regs/xe_mert_regs.h     |  3 +++
>>  drivers/gpu/drm/xe/xe_device_types.h       |  6 ++++++
>>  drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c | 19 +++++++++++++++++++
>>  drivers/gpu/drm/xe/xe_irq.c                |  8 ++++++++
>>  drivers/gpu/drm/xe/xe_sriov_pf.c           |  3 +++
>>  5 files changed, 39 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
>> index 5b7c15e08747e..aef66c04901d2 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_mert_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
>> @@ -10,4 +10,7 @@
>>
>>  #define MERT_LMEM_CFG				XE_REG(0x1448b0)
>>
>> +#define MERT_TLB_INV_DESC_A			XE_REG(0x14cf7c)
>> +#define   MERT_TLB_INV_DESC_A_VALID		REG_BIT(0)
>> +
>>  #endif /* _XE_MERT_REGS_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index fb401809fae5a..6fcd35bee73b5 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -219,6 +219,12 @@ struct xe_tile {
>>
>>  	/** @debugfs: debugfs directory associated with this tile */
>>  	struct dentry *debugfs;
>> +
>> +	/** @mert: MERT-related data */
>> +	struct {
>> +		/** @mert.tlb_inv_done: completion of TLB invalidation */
>> +		struct completion tlb_inv_done;
>> +	} mert;
>>  };
>>
>>  /**
>> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>> index c0c0215c07036..ebe81cb21f5ab 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>> @@ -10,6 +10,7 @@
>>  #include "abi/guc_klvs_abi.h"
>>
>>  #include "regs/xe_guc_regs.h"
>> +#include "regs/xe_mert_regs.h"
>>
>>  #include "xe_bo.h"
>>  #include "xe_device.h"
>> @@ -31,6 +32,7 @@
>>  #include "xe_lmtt.h"
>>  #include "xe_map.h"
>>  #include "xe_migrate.h"
>> +#include "xe_mmio.h"
>>  #include "xe_sriov.h"
>>  #include "xe_ttm_vram_mgr.h"
>>  #include "xe_vram_types.h"
>> @@ -1346,6 +1348,20 @@ static int pf_distribute_config_lmem(struct xe_gt *gt, unsigned int vfid, u64 si
>>  	return 0;
>>  }
>>
>> +static void invalidate_mert_lmtt(struct xe_device *xe)
>> +{
>> +	const long timeout = HZ / 4;
>> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
>> +
>> +	xe_assert(xe, xe_device_has_mert(xe));
>> +
>
>It is not obvious how upper layers which call this function get
>exclusive access to what appears to be a per device resource.

this is a static function that will only be called by the function
below... I think the lockdep should rather be added in that entrypoint?

>
>Is xe_sriov_pf_master_mutex held here? If so, I'd add a lockdep assert
>so this is self documenting on how exclusion is achieved and to prevent
>misuse. If not, you probably need a lock here.

yep, but another question below for Lukasz or you...

>
>Matt
>
>> +	reinit_completion(&tile->mert.tlb_inv_done);

is that the right thing here? Is xe_sriov_pf_master_mutex preventing 2
waiters?

Lucas De Marchi

>> +	xe_mmio_write32(&tile->mmio, MERT_TLB_INV_DESC_A, MERT_TLB_INV_DESC_A_VALID);
>> +
>> +	if (!wait_for_completion_timeout(&tile->mert.tlb_inv_done, timeout))
>> +		drm_err(&xe->drm, "MERT TLB invalidation timeout\n");
>> +}
>> +
>>  static void pf_force_lmtt_invalidate(struct xe_device *xe)
>>  {
>>  	struct xe_lmtt *lmtt;
>> @@ -1359,6 +1375,9 @@ static void pf_force_lmtt_invalidate(struct xe_device *xe)
>>  		lmtt = &tile->sriov.pf.lmtt;
>>  		xe_lmtt_invalidate_hw(lmtt);
>>  	}
>> +
>> +	if (xe_device_has_mert(xe))
>> +		invalidate_mert_lmtt(xe);
>>  }
>>
>>  static void pf_reset_vf_lmtt(struct xe_device *xe, unsigned int vfid)
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index 011b5eb66102f..82bf0d3995dfe 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -12,6 +12,7 @@
>>  #include "display/xe_display.h"
>>  #include "regs/xe_guc_regs.h"
>>  #include "regs/xe_irq_regs.h"
>> +#include "regs/xe_mert_regs.h"
>>  #include "xe_device.h"
>>  #include "xe_drv.h"
>>  #include "xe_gsc_proxy.h"
>> @@ -468,8 +469,15 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
>>
>>  static void mert_irq_handler(struct xe_device *xe, u32 master_ctl)
>>  {
>> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
>> +	u32 reg_val;
>> +
>>  	if (!(master_ctl & SOC_H2DMEMINT_IRQ))
>>  		return;
>> +
>> +	reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);
>> +	if (!(reg_val & MERT_TLB_INV_DESC_A_VALID))
>> +		complete(&tile->mert.tlb_inv_done);
>>  }
>>
>>  /*
>> diff --git a/drivers/gpu/drm/xe/xe_sriov_pf.c b/drivers/gpu/drm/xe/xe_sriov_pf.c
>> index bc1ab9ee31d92..b40701d75dacb 100644
>> --- a/drivers/gpu/drm/xe/xe_sriov_pf.c
>> +++ b/drivers/gpu/drm/xe/xe_sriov_pf.c
>> @@ -88,6 +88,7 @@ bool xe_sriov_pf_readiness(struct xe_device *xe)
>>   */
>>  int xe_sriov_pf_init_early(struct xe_device *xe)
>>  {
>> +	struct xe_tile *root_tile = xe_device_get_root_tile(xe);
>>  	int err;
>>
>>  	xe_assert(xe, IS_SRIOV_PF(xe));
>> @@ -103,6 +104,8 @@ int xe_sriov_pf_init_early(struct xe_device *xe)
>>
>>  	xe_sriov_pf_service_init(xe);
>>
>> +	init_completion(&root_tile->mert.tlb_inv_done);
>> +
>>  	return 0;
>>  }
>>
>>
>> --
>> 2.51.0
>>

Re: [PATCH 11/12] drm/xe/pf: Add TLB invalidation support for MERT

[Laguna, Lukasz]

On 10/23/2025 17:11, Lucas De Marchi wrote:
> On Wed, Oct 22, 2025 at 11:28:19AM -0700, Matthew Brost wrote:
>> On Tue, Oct 21, 2025 at 10:17:43PM -0700, Lucas De Marchi wrote:
>>> From: Lukasz Laguna <lukasz.laguna@intel.com>
>>>
>>> Trigger MERT's TLB invalidation after LMTT updates ensuring memory
>>> translations remain coherent.
>>>
>>> Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>> ---
>>>  drivers/gpu/drm/xe/regs/xe_mert_regs.h     |  3 +++
>>>  drivers/gpu/drm/xe/xe_device_types.h       |  6 ++++++
>>>  drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c | 19 +++++++++++++++++++
>>>  drivers/gpu/drm/xe/xe_irq.c                |  8 ++++++++
>>>  drivers/gpu/drm/xe/xe_sriov_pf.c           |  3 +++
>>>  5 files changed, 39 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h 
>>> b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
>>> index 5b7c15e08747e..aef66c04901d2 100644
>>> --- a/drivers/gpu/drm/xe/regs/xe_mert_regs.h
>>> +++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
>>> @@ -10,4 +10,7 @@
>>>
>>>  #define MERT_LMEM_CFG                XE_REG(0x1448b0)
>>>
>>> +#define MERT_TLB_INV_DESC_A            XE_REG(0x14cf7c)
>>> +#define   MERT_TLB_INV_DESC_A_VALID        REG_BIT(0)
>>> +
>>>  #endif /* _XE_MERT_REGS_H_ */
>>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h 
>>> b/drivers/gpu/drm/xe/xe_device_types.h
>>> index fb401809fae5a..6fcd35bee73b5 100644
>>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>>> @@ -219,6 +219,12 @@ struct xe_tile {
>>>
>>>      /** @debugfs: debugfs directory associated with this tile */
>>>      struct dentry *debugfs;
>>> +
>>> +    /** @mert: MERT-related data */
>>> +    struct {
>>> +        /** @mert.tlb_inv_done: completion of TLB invalidation */
>>> +        struct completion tlb_inv_done;
>>> +    } mert;
>>>  };
>>>
>>>  /**
>>> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c 
>>> b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>>> index c0c0215c07036..ebe81cb21f5ab 100644
>>> --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>>> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>>> @@ -10,6 +10,7 @@
>>>  #include "abi/guc_klvs_abi.h"
>>>
>>>  #include "regs/xe_guc_regs.h"
>>> +#include "regs/xe_mert_regs.h"
>>>
>>>  #include "xe_bo.h"
>>>  #include "xe_device.h"
>>> @@ -31,6 +32,7 @@
>>>  #include "xe_lmtt.h"
>>>  #include "xe_map.h"
>>>  #include "xe_migrate.h"
>>> +#include "xe_mmio.h"
>>>  #include "xe_sriov.h"
>>>  #include "xe_ttm_vram_mgr.h"
>>>  #include "xe_vram_types.h"
>>> @@ -1346,6 +1348,20 @@ static int pf_distribute_config_lmem(struct 
>>> xe_gt *gt, unsigned int vfid, u64 si
>>>      return 0;
>>>  }
>>>
>>> +static void invalidate_mert_lmtt(struct xe_device *xe)
>>> +{
>>> +    const long timeout = HZ / 4;
>>> +    struct xe_tile *tile = xe_device_get_root_tile(xe);
>>> +
>>> +    xe_assert(xe, xe_device_has_mert(xe));
>>> +
>>
>> It is not obvious how upper layers which call this function get
>> exclusive access to what appears to be a per device resource.
>
> this is a static function that will only be called by the function
> below... I think the lockdep should rather be added in that entrypoint?
>
>>
>> Is xe_sriov_pf_master_mutex held here? If so, I'd add a lockdep assert
>> so this is self documenting on how exclusion is achieved and to prevent
>> misuse. If not, you probably need a lock here.
>

xe_sriov_pf_master_mutex is held here, but there can still be a race 
between reinit_completion() and complete(). I'll prepare a new locking 
approach.

Thanks,
Lukasz

> yep, but another question below for Lukasz or you...
>
>>
>> Matt
>>
>>> + reinit_completion(&tile->mert.tlb_inv_done);
>
> is that the right thing here? Is xe_sriov_pf_master_mutex preventing 2
> waiters?
>
> Lucas De Marchi
>
>>> +    xe_mmio_write32(&tile->mmio, MERT_TLB_INV_DESC_A, 
>>> MERT_TLB_INV_DESC_A_VALID);
>>> +
>>> +    if (!wait_for_completion_timeout(&tile->mert.tlb_inv_done, 
>>> timeout))
>>> +        drm_err(&xe->drm, "MERT TLB invalidation timeout\n");
>>> +}
>>> +
>>>  static void pf_force_lmtt_invalidate(struct xe_device *xe)
>>>  {
>>>      struct xe_lmtt *lmtt;
>>> @@ -1359,6 +1375,9 @@ static void pf_force_lmtt_invalidate(struct 
>>> xe_device *xe)
>>>          lmtt = &tile->sriov.pf.lmtt;
>>>          xe_lmtt_invalidate_hw(lmtt);
>>>      }
>>> +
>>> +    if (xe_device_has_mert(xe))
>>> +        invalidate_mert_lmtt(xe);
>>>  }
>>>
>>>  static void pf_reset_vf_lmtt(struct xe_device *xe, unsigned int vfid)
>>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>>> index 011b5eb66102f..82bf0d3995dfe 100644
>>> --- a/drivers/gpu/drm/xe/xe_irq.c
>>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>>> @@ -12,6 +12,7 @@
>>>  #include "display/xe_display.h"
>>>  #include "regs/xe_guc_regs.h"
>>>  #include "regs/xe_irq_regs.h"
>>> +#include "regs/xe_mert_regs.h"
>>>  #include "xe_device.h"
>>>  #include "xe_drv.h"
>>>  #include "xe_gsc_proxy.h"
>>> @@ -468,8 +469,15 @@ static void dg1_intr_enable(struct xe_device 
>>> *xe, bool stall)
>>>
>>>  static void mert_irq_handler(struct xe_device *xe, u32 master_ctl)
>>>  {
>>> +    struct xe_tile *tile = xe_device_get_root_tile(xe);
>>> +    u32 reg_val;
>>> +
>>>      if (!(master_ctl & SOC_H2DMEMINT_IRQ))
>>>          return;
>>> +
>>> +    reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);
>>> +    if (!(reg_val & MERT_TLB_INV_DESC_A_VALID))
>>> +        complete(&tile->mert.tlb_inv_done);
>>>  }
>>>
>>>  /*
>>> diff --git a/drivers/gpu/drm/xe/xe_sriov_pf.c 
>>> b/drivers/gpu/drm/xe/xe_sriov_pf.c
>>> index bc1ab9ee31d92..b40701d75dacb 100644
>>> --- a/drivers/gpu/drm/xe/xe_sriov_pf.c
>>> +++ b/drivers/gpu/drm/xe/xe_sriov_pf.c
>>> @@ -88,6 +88,7 @@ bool xe_sriov_pf_readiness(struct xe_device *xe)
>>>   */
>>>  int xe_sriov_pf_init_early(struct xe_device *xe)
>>>  {
>>> +    struct xe_tile *root_tile = xe_device_get_root_tile(xe);
>>>      int err;
>>>
>>>      xe_assert(xe, IS_SRIOV_PF(xe));
>>> @@ -103,6 +104,8 @@ int xe_sriov_pf_init_early(struct xe_device *xe)
>>>
>>>      xe_sriov_pf_service_init(xe);
>>>
>>> +    init_completion(&root_tile->mert.tlb_inv_done);
>>> +
>>>      return 0;
>>>  }
>>>
>>>
>>> -- 
>>> 2.51.0
>>>

[PATCH 12/12] drm/xe/pf: Handle MERT catastrophic errors

[Lucas De Marchi]

From: Lukasz Laguna <lukasz.laguna@intel.com>

The MERT block triggers an interrupt when a catastrophic error occurs.
Update the interrupt handler to read the MERT catastrophic error type
and log appropriate debug message.

Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_mert_regs.h |  5 +++++
 drivers/gpu/drm/xe/xe_irq.c            | 11 +++++++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
index aef66c04901d2..7c58b207263c2 100644
--- a/drivers/gpu/drm/xe/regs/xe_mert_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
@@ -10,6 +10,11 @@
 
 #define MERT_LMEM_CFG				XE_REG(0x1448b0)
 
+#define MERT_TLB_CT_INTR_ERR_ID_PORT		XE_REG(0x145190)
+#define   MERT_TLB_CT_VFID_MASK			REG_GENMASK(16, 9)
+#define   MERT_TLB_CT_ERROR_MASK		REG_GENMASK(5, 0)
+#define   MERT_TLB_CT_LMTT_FAULT		0x05
+
 #define MERT_TLB_INV_DESC_A			XE_REG(0x14cf7c)
 #define   MERT_TLB_INV_DESC_A_VALID		REG_BIT(0)
 
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 82bf0d3995dfe..a09abf7bacb33 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -471,10 +471,21 @@ static void mert_irq_handler(struct xe_device *xe, u32 master_ctl)
 {
 	struct xe_tile *tile = xe_device_get_root_tile(xe);
 	u32 reg_val;
+	u8 err;
 
 	if (!(master_ctl & SOC_H2DMEMINT_IRQ))
 		return;
 
+	reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT);
+	xe_mmio_write32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT, 0);
+
+	err = reg_val & MERT_TLB_CT_ERROR_MASK;
+	if (err == MERT_TLB_CT_LMTT_FAULT)
+		drm_dbg(&xe->drm, "MERT catastrophic error: LMTT fault (VF%u)\n",
+			reg_val & MERT_TLB_CT_VFID_MASK);
+	else if (err)
+		drm_dbg(&xe->drm, "MERT catastrophic error: Unexpected fault (0x%x)\n", err);
+
 	reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);
 	if (!(reg_val & MERT_TLB_INV_DESC_A_VALID))
 		complete(&tile->mert.tlb_inv_done);

-- 
2.51.0

✗ CI.checkpatch: warning for drm/xe: Add support for Crescent Island

[Patchwork]

== Series Details ==

Series: drm/xe: Add support for Crescent Island
URL   : https://patchwork.freedesktop.org/series/156297/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
8677d3b99d5fd579c143b22605d99121e2482e8a
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 95ae36d63b69fda12564330e9aa0aa60f194cc1d
Author: Lukasz Laguna <lukasz.laguna@intel.com>
Date:   Tue Oct 21 22:17:44 2025 -0700

    drm/xe/pf: Handle MERT catastrophic errors
    
    The MERT block triggers an interrupt when a catastrophic error occurs.
    Update the interrupt handler to read the MERT catastrophic error type
    and log appropriate debug message.
    
    Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
    Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+ /mt/dim checkpatch fb0f56ad8a2c9953c57c3337a72ccbf9c5050687 drm-intel
2704d1358415 drm/xe/cri: Add CRI platform definition
449396234b92 topic/for-xe-CI: drm/xe/cri: Define GuC firmware for CRI
a4ba0e17a6e5 drm/xe/cri: Setup MOCS table
064459b126cd drm/xe/cri: Add new performance limit reasons bits
-:200: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#200: FILE: drivers/gpu/drm/xe/xe_gt_throttle.c:276:
+}
+static struct kobj_attribute attr_reason_soc_thermal = __ATTR_RO(reason_soc_thermal);

-:218: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#218: FILE: drivers/gpu/drm/xe/xe_gt_throttle.c:320:
+}
+static struct kobj_attribute attr_reason_soc_avg_thermal = __ATTR_RO(reason_soc_avg_thermal);

-:236: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#236: FILE: drivers/gpu/drm/xe/xe_gt_throttle.c:342:
+}
+static struct kobj_attribute attr_reason_fastvmode = __ATTR_RO(reason_fastvmode);

-:247: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#247: FILE: drivers/gpu/drm/xe/xe_gt_throttle.c:353:
+}
+static struct kobj_attribute attr_reason_mem_thermal = __ATTR_RO(reason_mem_thermal);

-:258: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#258: FILE: drivers/gpu/drm/xe/xe_gt_throttle.c:364:
+}
+static struct kobj_attribute attr_reason_vr_thermal = __ATTR_RO(reason_vr_thermal);

-:269: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#269: FILE: drivers/gpu/drm/xe/xe_gt_throttle.c:375:
+}
+static struct kobj_attribute attr_reason_iccmax = __ATTR_RO(reason_iccmax);

-:280: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#280: FILE: drivers/gpu/drm/xe/xe_gt_throttle.c:386:
+}
+static struct kobj_attribute attr_reason_psys_pl1 = __ATTR_RO(reason_psys_pl1);

-:291: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#291: FILE: drivers/gpu/drm/xe/xe_gt_throttle.c:397:
+}
+static struct kobj_attribute attr_reason_psys_pl2 = __ATTR_RO(reason_psys_pl2);

-:302: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#302: FILE: drivers/gpu/drm/xe/xe_gt_throttle.c:408:
+}
+static struct kobj_attribute attr_reason_p0_freq = __ATTR_RO(reason_p0_freq);

-:313: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#313: FILE: drivers/gpu/drm/xe/xe_gt_throttle.c:419:
+}
+static struct kobj_attribute attr_reason_psys_crit = __ATTR_RO(reason_psys_crit);

total: 0 errors, 0 warnings, 10 checks, 352 lines checked
e5cbec3d0ba0 drm/xe/cri: Add check to verify if CSC is a PCIe endpoint
67e422b5353a drm/xe/pm: Enable D3cold WAKE# support
1f793ddbf660 drm/xe: Add device flag to indicate standalone MERT
6a91648287bc drm/xe/oa/uapi: Expose MERT OA unit
bf7a6b6998c9 drm/xe/pf: Configure LMTT in MERT
-:15: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#15: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 55 lines checked
98f06d67fb3a drm/xe: Handle MERT interrupts
08b489ecb4f5 drm/xe/pf: Add TLB invalidation support for MERT
95ae36d63b69 drm/xe/pf: Handle MERT catastrophic errors

✓ CI.KUnit: success for drm/xe: Add support for Crescent Island

[Patchwork]

== Series Details ==

Series: drm/xe: Add support for Crescent Island
URL   : https://patchwork.freedesktop.org/series/156297/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:40:17] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:40:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:40:52] Starting KUnit Kernel (1/1)...
[05:40:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:40:52] ================== guc_buf (11 subtests) ===================
[05:40:52] [PASSED] test_smallest
[05:40:52] [PASSED] test_largest
[05:40:52] [PASSED] test_granular
[05:40:52] [PASSED] test_unique
[05:40:52] [PASSED] test_overlap
[05:40:52] [PASSED] test_reusable
[05:40:52] [PASSED] test_too_big
[05:40:52] [PASSED] test_flush
[05:40:52] [PASSED] test_lookup
[05:40:52] [PASSED] test_data
[05:40:52] [PASSED] test_class
[05:40:52] ===================== [PASSED] guc_buf =====================
[05:40:52] =================== guc_dbm (7 subtests) ===================
[05:40:52] [PASSED] test_empty
[05:40:52] [PASSED] test_default
[05:40:52] ======================== test_size  ========================
[05:40:52] [PASSED] 4
[05:40:52] [PASSED] 8
[05:40:52] [PASSED] 32
[05:40:52] [PASSED] 256
[05:40:52] ==================== [PASSED] test_size ====================
[05:40:52] ======================= test_reuse  ========================
[05:40:52] [PASSED] 4
[05:40:52] [PASSED] 8
[05:40:52] [PASSED] 32
[05:40:52] [PASSED] 256
[05:40:52] =================== [PASSED] test_reuse ====================
[05:40:52] =================== test_range_overlap  ====================
[05:40:52] [PASSED] 4
[05:40:52] [PASSED] 8
[05:40:52] [PASSED] 32
[05:40:52] [PASSED] 256
[05:40:52] =============== [PASSED] test_range_overlap ================
[05:40:52] =================== test_range_compact  ====================
[05:40:52] [PASSED] 4
[05:40:52] [PASSED] 8
[05:40:52] [PASSED] 32
[05:40:52] [PASSED] 256
[05:40:52] =============== [PASSED] test_range_compact ================
[05:40:52] ==================== test_range_spare  =====================
[05:40:52] [PASSED] 4
[05:40:52] [PASSED] 8
[05:40:52] [PASSED] 32
[05:40:52] [PASSED] 256
[05:40:52] ================ [PASSED] test_range_spare =================
[05:40:52] ===================== [PASSED] guc_dbm =====================
[05:40:52] =================== guc_idm (6 subtests) ===================
[05:40:52] [PASSED] bad_init
[05:40:52] [PASSED] no_init
[05:40:52] [PASSED] init_fini
[05:40:52] [PASSED] check_used
[05:40:52] [PASSED] check_quota
[05:40:52] [PASSED] check_all
[05:40:52] ===================== [PASSED] guc_idm =====================
[05:40:52] ================== no_relay (3 subtests) ===================
[05:40:52] [PASSED] xe_drops_guc2pf_if_not_ready
[05:40:52] [PASSED] xe_drops_guc2vf_if_not_ready
[05:40:52] [PASSED] xe_rejects_send_if_not_ready
[05:40:52] ==================== [PASSED] no_relay =====================
[05:40:52] ================== pf_relay (14 subtests) ==================
[05:40:52] [PASSED] pf_rejects_guc2pf_too_short
[05:40:52] [PASSED] pf_rejects_guc2pf_too_long
[05:40:52] [PASSED] pf_rejects_guc2pf_no_payload
[05:40:52] [PASSED] pf_fails_no_payload
[05:40:52] [PASSED] pf_fails_bad_origin
[05:40:52] [PASSED] pf_fails_bad_type
[05:40:52] [PASSED] pf_txn_reports_error
[05:40:52] [PASSED] pf_txn_sends_pf2guc
[05:40:52] [PASSED] pf_sends_pf2guc
[05:40:52] [SKIPPED] pf_loopback_nop
[05:40:52] [SKIPPED] pf_loopback_echo
[05:40:52] [SKIPPED] pf_loopback_fail
[05:40:52] [SKIPPED] pf_loopback_busy
[05:40:52] [SKIPPED] pf_loopback_retry
[05:40:52] ==================== [PASSED] pf_relay =====================
[05:40:52] ================== vf_relay (3 subtests) ===================
[05:40:52] [PASSED] vf_rejects_guc2vf_too_short
[05:40:52] [PASSED] vf_rejects_guc2vf_too_long
[05:40:52] [PASSED] vf_rejects_guc2vf_no_payload
[05:40:52] ==================== [PASSED] vf_relay =====================
[05:40:52] ===================== lmtt (1 subtest) =====================
[05:40:52] ======================== test_ops  =========================
[05:40:52] [PASSED] 2-level
[05:40:52] [PASSED] multi-level
[05:40:52] ==================== [PASSED] test_ops =====================
[05:40:52] ====================== [PASSED] lmtt =======================
[05:40:52] ================= pf_service (11 subtests) =================
[05:40:52] [PASSED] pf_negotiate_any
[05:40:52] [PASSED] pf_negotiate_base_match
[05:40:52] [PASSED] pf_negotiate_base_newer
[05:40:52] [PASSED] pf_negotiate_base_next
[05:40:52] [SKIPPED] pf_negotiate_base_older
[05:40:52] [PASSED] pf_negotiate_base_prev
[05:40:52] [PASSED] pf_negotiate_latest_match
[05:40:52] [PASSED] pf_negotiate_latest_newer
[05:40:52] [PASSED] pf_negotiate_latest_next
[05:40:52] [SKIPPED] pf_negotiate_latest_older
[05:40:52] [SKIPPED] pf_negotiate_latest_prev
[05:40:52] =================== [PASSED] pf_service ====================
[05:40:52] ================= xe_guc_g2g (2 subtests) ==================
[05:40:52] ============== xe_live_guc_g2g_kunit_default  ==============
[05:40:52] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[05:40:52] ============== xe_live_guc_g2g_kunit_allmem  ===============
[05:40:52] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[05:40:52] =================== [SKIPPED] xe_guc_g2g ===================
[05:40:52] =================== xe_mocs (2 subtests) ===================
[05:40:52] ================ xe_live_mocs_kernel_kunit  ================
[05:40:52] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:40:52] ================ xe_live_mocs_reset_kunit  =================
[05:40:52] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:40:52] ==================== [SKIPPED] xe_mocs =====================
[05:40:52] ================= xe_migrate (2 subtests) ==================
[05:40:52] ================= xe_migrate_sanity_kunit  =================
[05:40:52] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:40:52] ================== xe_validate_ccs_kunit  ==================
[05:40:52] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:40:52] =================== [SKIPPED] xe_migrate ===================
[05:40:52] ================== xe_dma_buf (1 subtest) ==================
[05:40:52] ==================== xe_dma_buf_kunit  =====================
[05:40:52] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:40:52] =================== [SKIPPED] xe_dma_buf ===================
[05:40:52] ================= xe_bo_shrink (1 subtest) =================
[05:40:52] =================== xe_bo_shrink_kunit  ====================
[05:40:52] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:40:52] ================== [SKIPPED] xe_bo_shrink ==================
[05:40:52] ==================== xe_bo (2 subtests) ====================
[05:40:52] ================== xe_ccs_migrate_kunit  ===================
[05:40:52] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:40:52] ==================== xe_bo_evict_kunit  ====================
[05:40:52] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:40:52] ===================== [SKIPPED] xe_bo ======================
[05:40:52] ==================== args (11 subtests) ====================
[05:40:52] [PASSED] count_args_test
[05:40:52] [PASSED] call_args_example
[05:40:52] [PASSED] call_args_test
[05:40:52] [PASSED] drop_first_arg_example
[05:40:52] [PASSED] drop_first_arg_test
[05:40:52] [PASSED] first_arg_example
[05:40:52] [PASSED] first_arg_test
[05:40:52] [PASSED] last_arg_example
[05:40:52] [PASSED] last_arg_test
[05:40:52] [PASSED] pick_arg_example
[05:40:52] [PASSED] sep_comma_example
[05:40:52] ====================== [PASSED] args =======================
[05:40:52] =================== xe_pci (3 subtests) ====================
[05:40:52] ==================== check_graphics_ip  ====================
[05:40:52] [PASSED] 12.00 Xe_LP
[05:40:52] [PASSED] 12.10 Xe_LP+
[05:40:52] [PASSED] 12.55 Xe_HPG
[05:40:52] [PASSED] 12.60 Xe_HPC
[05:40:52] [PASSED] 12.70 Xe_LPG
[05:40:52] [PASSED] 12.71 Xe_LPG
[05:40:52] [PASSED] 12.74 Xe_LPG+
[05:40:52] [PASSED] 20.01 Xe2_HPG
[05:40:52] [PASSED] 20.02 Xe2_HPG
[05:40:52] [PASSED] 20.04 Xe2_LPG
[05:40:52] [PASSED] 30.00 Xe3_LPG
[05:40:52] [PASSED] 30.01 Xe3_LPG
[05:40:52] [PASSED] 30.03 Xe3_LPG
[05:40:52] [PASSED] 30.04 Xe3_LPG
[05:40:52] [PASSED] 30.05 Xe3_LPG
[05:40:52] [PASSED] 35.11 Xe3p_XPC
[05:40:52] ================ [PASSED] check_graphics_ip ================
[05:40:52] ===================== check_media_ip  ======================
[05:40:52] [PASSED] 12.00 Xe_M
[05:40:52] [PASSED] 12.55 Xe_HPM
[05:40:52] [PASSED] 13.00 Xe_LPM+
[05:40:52] [PASSED] 13.01 Xe2_HPM
[05:40:52] [PASSED] 20.00 Xe2_LPM
[05:40:52] [PASSED] 30.00 Xe3_LPM
[05:40:52] [PASSED] 30.02 Xe3_LPM
[05:40:52] [PASSED] 35.00 Xe3p_LPM
[05:40:52] [PASSED] 35.03 Xe3p_HPM
[05:40:52] ================= [PASSED] check_media_ip ==================
[05:40:52] ================= check_platform_gt_count  =================
[05:40:52] [PASSED] 0x9A60 (TIGERLAKE)
[05:40:52] [PASSED] 0x9A68 (TIGERLAKE)
[05:40:52] [PASSED] 0x9A70 (TIGERLAKE)
[05:40:52] [PASSED] 0x9A40 (TIGERLAKE)
[05:40:52] [PASSED] 0x9A49 (TIGERLAKE)
[05:40:52] [PASSED] 0x9A59 (TIGERLAKE)
[05:40:52] [PASSED] 0x9A78 (TIGERLAKE)
[05:40:52] [PASSED] 0x9AC0 (TIGERLAKE)
[05:40:52] [PASSED] 0x9AC9 (TIGERLAKE)
[05:40:52] [PASSED] 0x9AD9 (TIGERLAKE)
[05:40:52] [PASSED] 0x9AF8 (TIGERLAKE)
[05:40:52] [PASSED] 0x4C80 (ROCKETLAKE)
[05:40:52] [PASSED] 0x4C8A (ROCKETLAKE)
[05:40:52] [PASSED] 0x4C8B (ROCKETLAKE)
[05:40:52] [PASSED] 0x4C8C (ROCKETLAKE)
[05:40:52] [PASSED] 0x4C90 (ROCKETLAKE)
[05:40:52] [PASSED] 0x4C9A (ROCKETLAKE)
[05:40:52] [PASSED] 0x4680 (ALDERLAKE_S)
[05:40:52] [PASSED] 0x4682 (ALDERLAKE_S)
[05:40:52] [PASSED] 0x4688 (ALDERLAKE_S)
[05:40:52] [PASSED] 0x468A (ALDERLAKE_S)
[05:40:52] [PASSED] 0x468B (ALDERLAKE_S)
[05:40:52] [PASSED] 0x4690 (ALDERLAKE_S)
[05:40:52] [PASSED] 0x4692 (ALDERLAKE_S)
[05:40:52] [PASSED] 0x4693 (ALDERLAKE_S)
[05:40:52] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46AA (ALDERLAKE_P)
[05:40:52] [PASSED] 0x462A (ALDERLAKE_P)
[05:40:52] [PASSED] 0x4626 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x4628 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46B0 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:40:52] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:40:52] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:40:52] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:40:52] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:40:52] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:40:52] [PASSED] 0xA721 (ALDERLAKE_P)
[05:40:52] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:40:52] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:40:52] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:40:52] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:40:52] [PASSED] 0xA720 (ALDERLAKE_P)
[05:40:52] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:40:52] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:40:52] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:40:52] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:40:52] [PASSED] 0xA780 (ALDERLAKE_S)
[05:40:52] [PASSED] 0xA781 (ALDERLAKE_S)
[05:40:52] [PASSED] 0xA782 (ALDERLAKE_S)
[05:40:52] [PASSED] 0xA783 (ALDERLAKE_S)
[05:40:52] [PASSED] 0xA788 (ALDERLAKE_S)
[05:40:52] [PASSED] 0xA789 (ALDERLAKE_S)
[05:40:52] [PASSED] 0xA78A (ALDERLAKE_S)
[05:40:52] [PASSED] 0xA78B (ALDERLAKE_S)
[05:40:52] [PASSED] 0x4905 (DG1)
[05:40:52] [PASSED] 0x4906 (DG1)
[05:40:52] [PASSED] 0x4907 (DG1)
[05:40:52] [PASSED] 0x4908 (DG1)
[05:40:52] [PASSED] 0x4909 (DG1)
[05:40:52] [PASSED] 0x56C0 (DG2)
[05:40:52] [PASSED] 0x56C2 (DG2)
[05:40:52] [PASSED] 0x56C1 (DG2)
[05:40:52] [PASSED] 0x7D51 (METEORLAKE)
[05:40:52] [PASSED] 0x7DD1 (METEORLAKE)
[05:40:52] [PASSED] 0x7D41 (METEORLAKE)
[05:40:52] [PASSED] 0x7D67 (METEORLAKE)
[05:40:52] [PASSED] 0xB640 (METEORLAKE)
[05:40:52] [PASSED] 0x56A0 (DG2)
[05:40:52] [PASSED] 0x56A1 (DG2)
[05:40:52] [PASSED] 0x56A2 (DG2)
[05:40:52] [PASSED] 0x56BE (DG2)
[05:40:52] [PASSED] 0x56BF (DG2)
[05:40:52] [PASSED] 0x5690 (DG2)
[05:40:52] [PASSED] 0x5691 (DG2)
[05:40:52] [PASSED] 0x5692 (DG2)
[05:40:52] [PASSED] 0x56A5 (DG2)
[05:40:52] [PASSED] 0x56A6 (DG2)
[05:40:52] [PASSED] 0x56B0 (DG2)
[05:40:52] [PASSED] 0x56B1 (DG2)
[05:40:52] [PASSED] 0x56BA (DG2)
[05:40:52] [PASSED] 0x56BB (DG2)
[05:40:52] [PASSED] 0x56BC (DG2)
[05:40:52] [PASSED] 0x56BD (DG2)
[05:40:52] [PASSED] 0x5693 (DG2)
[05:40:52] [PASSED] 0x5694 (DG2)
[05:40:52] [PASSED] 0x5695 (DG2)
[05:40:52] [PASSED] 0x56A3 (DG2)
[05:40:52] [PASSED] 0x56A4 (DG2)
[05:40:52] [PASSED] 0x56B2 (DG2)
[05:40:52] [PASSED] 0x56B3 (DG2)
[05:40:52] [PASSED] 0x5696 (DG2)
[05:40:52] [PASSED] 0x5697 (DG2)
[05:40:52] [PASSED] 0xB69 (PVC)
[05:40:52] [PASSED] 0xB6E (PVC)
[05:40:52] [PASSED] 0xBD4 (PVC)
[05:40:52] [PASSED] 0xBD5 (PVC)
[05:40:52] [PASSED] 0xBD6 (PVC)
[05:40:52] [PASSED] 0xBD7 (PVC)
[05:40:52] [PASSED] 0xBD8 (PVC)
[05:40:52] [PASSED] 0xBD9 (PVC)
[05:40:52] [PASSED] 0xBDA (PVC)
[05:40:52] [PASSED] 0xBDB (PVC)
[05:40:52] [PASSED] 0xBE0 (PVC)
[05:40:52] [PASSED] 0xBE1 (PVC)
[05:40:52] [PASSED] 0xBE5 (PVC)
[05:40:52] [PASSED] 0x7D40 (METEORLAKE)
[05:40:52] [PASSED] 0x7D45 (METEORLAKE)
[05:40:52] [PASSED] 0x7D55 (METEORLAKE)
[05:40:52] [PASSED] 0x7D60 (METEORLAKE)
[05:40:52] [PASSED] 0x7DD5 (METEORLAKE)
[05:40:52] [PASSED] 0x6420 (LUNARLAKE)
[05:40:52] [PASSED] 0x64A0 (LUNARLAKE)
[05:40:52] [PASSED] 0x64B0 (LUNARLAKE)
[05:40:52] [PASSED] 0xE202 (BATTLEMAGE)
[05:40:52] [PASSED] 0xE209 (BATTLEMAGE)
[05:40:52] [PASSED] 0xE20B (BATTLEMAGE)
[05:40:52] [PASSED] 0xE20C (BATTLEMAGE)
[05:40:52] [PASSED] 0xE20D (BATTLEMAGE)
[05:40:52] [PASSED] 0xE210 (BATTLEMAGE)
[05:40:52] [PASSED] 0xE211 (BATTLEMAGE)
[05:40:52] [PASSED] 0xE212 (BATTLEMAGE)
[05:40:52] [PASSED] 0xE216 (BATTLEMAGE)
[05:40:52] [PASSED] 0xE220 (BATTLEMAGE)
[05:40:52] [PASSED] 0xE221 (BATTLEMAGE)
[05:40:52] [PASSED] 0xE222 (BATTLEMAGE)
[05:40:52] [PASSED] 0xE223 (BATTLEMAGE)
[05:40:52] [PASSED] 0xB080 (PANTHERLAKE)
[05:40:52] [PASSED] 0xB081 (PANTHERLAKE)
[05:40:52] [PASSED] 0xB082 (PANTHERLAKE)
[05:40:52] [PASSED] 0xB083 (PANTHERLAKE)
[05:40:52] [PASSED] 0xB084 (PANTHERLAKE)
[05:40:52] [PASSED] 0xB085 (PANTHERLAKE)
[05:40:52] [PASSED] 0xB086 (PANTHERLAKE)
[05:40:52] [PASSED] 0xB087 (PANTHERLAKE)
[05:40:52] [PASSED] 0xB08F (PANTHERLAKE)
[05:40:52] [PASSED] 0xB090 (PANTHERLAKE)
[05:40:52] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:40:52] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:40:52] [PASSED] 0xFD80 (PANTHERLAKE)
[05:40:52] [PASSED] 0xFD81 (PANTHERLAKE)
[05:40:52] [PASSED] 0xD740 (NOVALAKE_S)
[05:40:52] [PASSED] 0xD741 (NOVALAKE_S)
[05:40:52] [PASSED] 0xD742 (NOVALAKE_S)
[05:40:52] [PASSED] 0xD743 (NOVALAKE_S)
[05:40:52] [PASSED] 0xD744 (NOVALAKE_S)
[05:40:52] [PASSED] 0xD745 (NOVALAKE_S)
[05:40:52] [PASSED] 0x674C (CRESCENTISLAND)
[05:40:52] ============= [PASSED] check_platform_gt_count =============
[05:40:52] ===================== [PASSED] xe_pci ======================
[05:40:52] =================== xe_rtp (2 subtests) ====================
[05:40:52] =============== xe_rtp_process_to_sr_tests  ================
[05:40:52] [PASSED] coalesce-same-reg
[05:40:52] [PASSED] no-match-no-add
[05:40:52] [PASSED] match-or
[05:40:52] [PASSED] match-or-xfail
[05:40:52] [PASSED] no-match-no-add-multiple-rules
[05:40:52] [PASSED] two-regs-two-entries
[05:40:52] [PASSED] clr-one-set-other
[05:40:52] [PASSED] set-field
[05:40:52] [PASSED] conflict-duplicate
[05:40:52] [PASSED] conflict-not-disjoint
[05:40:52] [PASSED] conflict-reg-type
[05:40:52] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:40:52] ================== xe_rtp_process_tests  ===================
[05:40:52] [PASSED] active1
[05:40:52] [PASSED] active2
[05:40:52] [PASSED] active-inactive
[05:40:52] [PASSED] inactive-active
[05:40:52] [PASSED] inactive-1st_or_active-inactive
[05:40:52] [PASSED] inactive-2nd_or_active-inactive
[05:40:52] [PASSED] inactive-last_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[05:40:52] [PASSED] inactive-no_or_active-inactive
[05:40:52] ============== [PASSED] xe_rtp_process_tests ===============
[05:40:52] ===================== [PASSED] xe_rtp ======================
[05:40:52] ==================== xe_wa (1 subtest) =====================
[05:40:52] ======================== xe_wa_gt  =========================
[05:40:52] [PASSED] TIGERLAKE B0
[05:40:52] [PASSED] DG1 A0
[05:40:52] [PASSED] DG1 B0
[05:40:52] [PASSED] ALDERLAKE_S A0
[05:40:52] [PASSED] ALDERLAKE_S B0
[05:40:52] [PASSED] ALDERLAKE_S C0
[05:40:52] [PASSED] ALDERLAKE_S D0
[05:40:52] [PASSED] ALDERLAKE_P A0
[05:40:52] [PASSED] ALDERLAKE_P B0
[05:40:52] [PASSED] ALDERLAKE_P C0
[05:40:52] [PASSED] ALDERLAKE_S RPLS D0
[05:40:52] [PASSED] ALDERLAKE_P RPLU E0
[05:40:52] [PASSED] DG2 G10 C0
[05:40:52] [PASSED] DG2 G11 B1
[05:40:52] [PASSED] DG2 G12 A1
[05:40:52] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:40:52] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:40:52] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[05:40:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[05:40:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[05:40:52] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[05:40:52] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[05:40:52] ==================== [PASSED] xe_wa_gt =====================
[05:40:52] ====================== [PASSED] xe_wa ======================
[05:40:52] ============================================================
[05:40:52] Testing complete. Ran 318 tests: passed: 300, skipped: 18
[05:40:52] Elapsed time: 35.052s total, 4.223s configuring, 30.462s building, 0.333s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:40:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:40:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:41:19] Starting KUnit Kernel (1/1)...
[05:41:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:41:19] ============ drm_test_pick_cmdline (2 subtests) ============
[05:41:19] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[05:41:19] =============== drm_test_pick_cmdline_named  ===============
[05:41:19] [PASSED] NTSC
[05:41:19] [PASSED] NTSC-J
[05:41:19] [PASSED] PAL
[05:41:19] [PASSED] PAL-M
[05:41:19] =========== [PASSED] drm_test_pick_cmdline_named ===========
[05:41:19] ============== [PASSED] drm_test_pick_cmdline ==============
[05:41:19] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:41:19] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:41:19] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:41:19] =========== drm_validate_clone_mode (2 subtests) ===========
[05:41:19] ============== drm_test_check_in_clone_mode  ===============
[05:41:19] [PASSED] in_clone_mode
[05:41:19] [PASSED] not_in_clone_mode
[05:41:19] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:41:19] =============== drm_test_check_valid_clones  ===============
[05:41:19] [PASSED] not_in_clone_mode
[05:41:19] [PASSED] valid_clone
[05:41:19] [PASSED] invalid_clone
[05:41:19] =========== [PASSED] drm_test_check_valid_clones ===========
[05:41:19] ============= [PASSED] drm_validate_clone_mode =============
[05:41:19] ============= drm_validate_modeset (1 subtest) =============
[05:41:19] [PASSED] drm_test_check_connector_changed_modeset
[05:41:19] ============== [PASSED] drm_validate_modeset ===============
[05:41:19] ====== drm_test_bridge_get_current_state (2 subtests) ======
[05:41:19] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:41:19] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[05:41:19] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:41:19] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:41:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:41:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:41:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[05:41:19] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:41:19] ============== drm_bridge_alloc (2 subtests) ===============
[05:41:19] [PASSED] drm_test_drm_bridge_alloc_basic
[05:41:19] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:41:19] ================ [PASSED] drm_bridge_alloc =================
[05:41:19] ================== drm_buddy (8 subtests) ==================
[05:41:19] [PASSED] drm_test_buddy_alloc_limit
[05:41:19] [PASSED] drm_test_buddy_alloc_optimistic
[05:41:19] [PASSED] drm_test_buddy_alloc_pessimistic
[05:41:19] [PASSED] drm_test_buddy_alloc_pathological
[05:41:19] [PASSED] drm_test_buddy_alloc_contiguous
[05:41:19] [PASSED] drm_test_buddy_alloc_clear
[05:41:19] [PASSED] drm_test_buddy_alloc_range_bias
[05:41:19] [PASSED] drm_test_buddy_fragmentation_performance
[05:41:19] ==================== [PASSED] drm_buddy ====================
[05:41:19] ============= drm_cmdline_parser (40 subtests) =============
[05:41:19] [PASSED] drm_test_cmdline_force_d_only
[05:41:19] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:41:19] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:41:19] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:41:19] [PASSED] drm_test_cmdline_force_e_only
[05:41:19] [PASSED] drm_test_cmdline_res
[05:41:19] [PASSED] drm_test_cmdline_res_vesa
[05:41:19] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:41:19] [PASSED] drm_test_cmdline_res_rblank
[05:41:19] [PASSED] drm_test_cmdline_res_bpp
[05:41:19] [PASSED] drm_test_cmdline_res_refresh
[05:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:41:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:41:19] [PASSED] drm_test_cmdline_res_margins_force_on
[05:41:19] [PASSED] drm_test_cmdline_res_vesa_margins
[05:41:19] [PASSED] drm_test_cmdline_name
[05:41:19] [PASSED] drm_test_cmdline_name_bpp
[05:41:19] [PASSED] drm_test_cmdline_name_option
[05:41:19] [PASSED] drm_test_cmdline_name_bpp_option
[05:41:19] [PASSED] drm_test_cmdline_rotate_0
[05:41:19] [PASSED] drm_test_cmdline_rotate_90
[05:41:19] [PASSED] drm_test_cmdline_rotate_180
[05:41:19] [PASSED] drm_test_cmdline_rotate_270
[05:41:19] [PASSED] drm_test_cmdline_hmirror
[05:41:19] [PASSED] drm_test_cmdline_vmirror
[05:41:19] [PASSED] drm_test_cmdline_margin_options
[05:41:19] [PASSED] drm_test_cmdline_multiple_options
[05:41:19] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:41:19] [PASSED] drm_test_cmdline_extra_and_option
[05:41:19] [PASSED] drm_test_cmdline_freestanding_options
[05:41:19] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:41:19] [PASSED] drm_test_cmdline_panel_orientation
[05:41:19] ================ drm_test_cmdline_invalid  =================
[05:41:19] [PASSED] margin_only
[05:41:19] [PASSED] interlace_only
[05:41:19] [PASSED] res_missing_x
[05:41:19] [PASSED] res_missing_y
[05:41:19] [PASSED] res_bad_y
[05:41:19] [PASSED] res_missing_y_bpp
[05:41:19] [PASSED] res_bad_bpp
[05:41:19] [PASSED] res_bad_refresh
[05:41:19] [PASSED] res_bpp_refresh_force_on_off
[05:41:19] [PASSED] res_invalid_mode
[05:41:19] [PASSED] res_bpp_wrong_place_mode
[05:41:19] [PASSED] name_bpp_refresh
[05:41:19] [PASSED] name_refresh
[05:41:19] [PASSED] name_refresh_wrong_mode
[05:41:19] [PASSED] name_refresh_invalid_mode
[05:41:19] [PASSED] rotate_multiple
[05:41:19] [PASSED] rotate_invalid_val
[05:41:19] [PASSED] rotate_truncated
[05:41:19] [PASSED] invalid_option
[05:41:19] [PASSED] invalid_tv_option
[05:41:19] [PASSED] truncated_tv_option
[05:41:19] ============ [PASSED] drm_test_cmdline_invalid =============
[05:41:19] =============== drm_test_cmdline_tv_options  ===============
[05:41:19] [PASSED] NTSC
[05:41:19] [PASSED] NTSC_443
[05:41:19] [PASSED] NTSC_J
[05:41:19] [PASSED] PAL
[05:41:19] [PASSED] PAL_M
[05:41:19] [PASSED] PAL_N
[05:41:19] [PASSED] SECAM
[05:41:19] [PASSED] MONO_525
[05:41:19] [PASSED] MONO_625
[05:41:19] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:41:19] =============== [PASSED] drm_cmdline_parser ================
[05:41:19] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:41:19] [PASSED] drm_test_connector_hdmi_init_valid
[05:41:19] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:41:19] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:41:19] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:41:19] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:41:19] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:41:19] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:41:19] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:41:19] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[05:41:19] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:41:19] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:41:19] [PASSED] supported_formats=0x3 yuv420_allowed=1
[05:41:19] [PASSED] supported_formats=0x3 yuv420_allowed=0
[05:41:19] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:41:19] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:41:19] [PASSED] drm_test_connector_hdmi_init_null_product
[05:41:19] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:41:19] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:41:19] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:41:19] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:41:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:41:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:41:19] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:41:19] ========= drm_test_connector_hdmi_init_type_valid  =========
[05:41:19] [PASSED] HDMI-A
[05:41:19] [PASSED] HDMI-B
[05:41:19] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:41:19] ======== drm_test_connector_hdmi_init_type_invalid  ========
[05:41:19] [PASSED] Unknown
[05:41:19] [PASSED] VGA
[05:41:19] [PASSED] DVI-I
[05:41:19] [PASSED] DVI-D
[05:41:19] [PASSED] DVI-A
[05:41:19] [PASSED] Composite
[05:41:19] [PASSED] SVIDEO
[05:41:19] [PASSED] LVDS
[05:41:19] [PASSED] Component
[05:41:19] [PASSED] DIN
[05:41:19] [PASSED] DP
[05:41:19] [PASSED] TV
[05:41:19] [PASSED] eDP
[05:41:19] [PASSED] Virtual
[05:41:19] [PASSED] DSI
[05:41:19] [PASSED] DPI
[05:41:19] [PASSED] Writeback
[05:41:19] [PASSED] SPI
[05:41:19] [PASSED] USB
[05:41:19] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:41:19] ============ [PASSED] drmm_connector_hdmi_init =============
[05:41:19] ============= drmm_connector_init (3 subtests) =============
[05:41:19] [PASSED] drm_test_drmm_connector_init
[05:41:19] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:41:19] ========= drm_test_drmm_connector_init_type_valid  =========
[05:41:19] [PASSED] Unknown
[05:41:19] [PASSED] VGA
[05:41:19] [PASSED] DVI-I
[05:41:19] [PASSED] DVI-D
[05:41:19] [PASSED] DVI-A
[05:41:19] [PASSED] Composite
[05:41:19] [PASSED] SVIDEO
[05:41:19] [PASSED] LVDS
[05:41:19] [PASSED] Component
[05:41:19] [PASSED] DIN
[05:41:19] [PASSED] DP
[05:41:19] [PASSED] HDMI-A
[05:41:19] [PASSED] HDMI-B
[05:41:19] [PASSED] TV
[05:41:19] [PASSED] eDP
[05:41:19] [PASSED] Virtual
[05:41:19] [PASSED] DSI
[05:41:19] [PASSED] DPI
[05:41:19] [PASSED] Writeback
[05:41:19] [PASSED] SPI
[05:41:19] [PASSED] USB
[05:41:19] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:41:19] =============== [PASSED] drmm_connector_init ===============
[05:41:19] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_init
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:41:19] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[05:41:19] [PASSED] Unknown
[05:41:19] [PASSED] VGA
[05:41:19] [PASSED] DVI-I
[05:41:19] [PASSED] DVI-D
[05:41:19] [PASSED] DVI-A
[05:41:19] [PASSED] Composite
[05:41:19] [PASSED] SVIDEO
[05:41:19] [PASSED] LVDS
[05:41:19] [PASSED] Component
[05:41:19] [PASSED] DIN
[05:41:19] [PASSED] DP
[05:41:19] [PASSED] HDMI-A
[05:41:19] [PASSED] HDMI-B
[05:41:19] [PASSED] TV
[05:41:19] [PASSED] eDP
[05:41:19] [PASSED] Virtual
[05:41:19] [PASSED] DSI
[05:41:19] [PASSED] DPI
[05:41:19] [PASSED] Writeback
[05:41:19] [PASSED] SPI
[05:41:19] [PASSED] USB
[05:41:19] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:41:19] ======== drm_test_drm_connector_dynamic_init_name  =========
[05:41:19] [PASSED] Unknown
[05:41:19] [PASSED] VGA
[05:41:19] [PASSED] DVI-I
[05:41:19] [PASSED] DVI-D
[05:41:19] [PASSED] DVI-A
[05:41:19] [PASSED] Composite
[05:41:19] [PASSED] SVIDEO
[05:41:19] [PASSED] LVDS
[05:41:19] [PASSED] Component
[05:41:19] [PASSED] DIN
[05:41:19] [PASSED] DP
[05:41:19] [PASSED] HDMI-A
[05:41:19] [PASSED] HDMI-B
[05:41:19] [PASSED] TV
[05:41:19] [PASSED] eDP
[05:41:19] [PASSED] Virtual
[05:41:19] [PASSED] DSI
[05:41:19] [PASSED] DPI
[05:41:19] [PASSED] Writeback
[05:41:19] [PASSED] SPI
[05:41:19] [PASSED] USB
[05:41:19] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:41:19] =========== [PASSED] drm_connector_dynamic_init ============
[05:41:19] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:41:19] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:41:19] ======= drm_connector_dynamic_register (7 subtests) ========
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:41:19] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:41:19] ========= [PASSED] drm_connector_dynamic_register ==========
[05:41:19] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:41:19] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:41:19] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:41:19] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:41:19] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:41:19] ========== drm_test_get_tv_mode_from_name_valid  ===========
[05:41:19] [PASSED] NTSC
[05:41:19] [PASSED] NTSC-443
[05:41:19] [PASSED] NTSC-J
[05:41:19] [PASSED] PAL
[05:41:19] [PASSED] PAL-M
[05:41:19] [PASSED] PAL-N
[05:41:19] [PASSED] SECAM
[05:41:19] [PASSED] Mono
[05:41:19] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:41:19] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:41:19] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:41:19] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:41:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:41:19] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[05:41:19] [PASSED] VIC 96
[05:41:19] [PASSED] VIC 97
[05:41:19] [PASSED] VIC 101
[05:41:19] [PASSED] VIC 102
[05:41:19] [PASSED] VIC 106
[05:41:19] [PASSED] VIC 107
[05:41:19] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:41:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:41:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:41:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:41:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:41:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:41:19] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:41:19] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:41:19] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[05:41:19] [PASSED] Automatic
[05:41:19] [PASSED] Full
[05:41:19] [PASSED] Limited 16:235
[05:41:19] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:41:19] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:41:19] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:41:19] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:41:19] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[05:41:19] [PASSED] RGB
[05:41:19] [PASSED] YUV 4:2:0
[05:41:19] [PASSED] YUV 4:2:2
[05:41:19] [PASSED] YUV 4:4:4
[05:41:19] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:41:19] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:41:19] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:41:19] ============= drm_damage_helper (21 subtests) ==============
[05:41:19] [PASSED] drm_test_damage_iter_no_damage
[05:41:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:41:19] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:41:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:41:19] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:41:19] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:41:19] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:41:19] [PASSED] drm_test_damage_iter_simple_damage
[05:41:19] [PASSED] drm_test_damage_iter_single_damage
[05:41:19] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:41:19] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:41:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:41:19] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:41:19] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:41:19] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:41:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:41:19] [PASSED] drm_test_damage_iter_damage
[05:41:19] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:41:19] [PASSED] drm_test_damage_iter_damage_one_outside
[05:41:19] [PASSED] drm_test_damage_iter_damage_src_moved
[05:41:19] [PASSED] drm_test_damage_iter_damage_not_visible
[05:41:19] ================ [PASSED] drm_damage_helper ================
[05:41:19] ============== drm_dp_mst_helper (3 subtests) ==============
[05:41:19] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[05:41:19] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:41:19] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:41:19] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:41:19] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:41:19] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:41:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:41:19] ============== drm_test_dp_mst_calc_pbn_div  ===============
[05:41:19] [PASSED] Link rate 2000000 lane count 4
[05:41:19] [PASSED] Link rate 2000000 lane count 2
[05:41:19] [PASSED] Link rate 2000000 lane count 1
[05:41:19] [PASSED] Link rate 1350000 lane count 4
[05:41:19] [PASSED] Link rate 1350000 lane count 2
[05:41:19] [PASSED] Link rate 1350000 lane count 1
[05:41:19] [PASSED] Link rate 1000000 lane count 4
[05:41:19] [PASSED] Link rate 1000000 lane count 2
[05:41:19] [PASSED] Link rate 1000000 lane count 1
[05:41:19] [PASSED] Link rate 810000 lane count 4
[05:41:19] [PASSED] Link rate 810000 lane count 2
[05:41:19] [PASSED] Link rate 810000 lane count 1
[05:41:19] [PASSED] Link rate 540000 lane count 4
[05:41:19] [PASSED] Link rate 540000 lane count 2
[05:41:19] [PASSED] Link rate 540000 lane count 1
[05:41:19] [PASSED] Link rate 270000 lane count 4
[05:41:19] [PASSED] Link rate 270000 lane count 2
[05:41:19] [PASSED] Link rate 270000 lane count 1
[05:41:19] [PASSED] Link rate 162000 lane count 4
[05:41:19] [PASSED] Link rate 162000 lane count 2
[05:41:19] [PASSED] Link rate 162000 lane count 1
[05:41:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:41:19] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[05:41:19] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:41:19] [PASSED] DP_POWER_UP_PHY with port number
[05:41:19] [PASSED] DP_POWER_DOWN_PHY with port number
[05:41:19] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:41:19] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:41:19] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:41:19] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:41:19] [PASSED] DP_QUERY_PAYLOAD with port number
[05:41:19] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:41:19] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:41:19] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:41:19] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:41:19] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:41:19] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:41:19] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:41:19] [PASSED] DP_REMOTE_I2C_READ with port number
[05:41:19] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:41:19] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:41:19] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:41:19] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:41:19] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:41:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:41:19] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:41:19] ================ [PASSED] drm_dp_mst_helper ================
[05:41:19] ================== drm_exec (7 subtests) ===================
[05:41:19] [PASSED] sanitycheck
[05:41:19] [PASSED] test_lock
[05:41:19] [PASSED] test_lock_unlock
[05:41:19] [PASSED] test_duplicates
[05:41:19] [PASSED] test_prepare
[05:41:19] [PASSED] test_prepare_array
[05:41:19] [PASSED] test_multiple_loops
[05:41:19] ==================== [PASSED] drm_exec =====================
[05:41:19] =========== drm_format_helper_test (17 subtests) ===========
[05:41:19] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:41:19] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:41:19] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:41:19] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:41:19] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:41:19] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:41:19] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:41:19] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:41:19] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:41:19] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:41:19] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:41:19] ============== drm_test_fb_xrgb8888_to_mono  ===============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:41:19] ==================== drm_test_fb_swab  =====================
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ================ [PASSED] drm_test_fb_swab =================
[05:41:19] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:41:19] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[05:41:19] [PASSED] single_pixel_source_buffer
[05:41:19] [PASSED] single_pixel_clip_rectangle
[05:41:19] [PASSED] well_known_colors
[05:41:19] [PASSED] destination_pitch
[05:41:19] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:41:19] ================= drm_test_fb_clip_offset  =================
[05:41:19] [PASSED] pass through
[05:41:19] [PASSED] horizontal offset
[05:41:19] [PASSED] vertical offset
[05:41:19] [PASSED] horizontal and vertical offset
[05:41:19] [PASSED] horizontal offset (custom pitch)
[05:41:19] [PASSED] vertical offset (custom pitch)
[05:41:19] [PASSED] horizontal and vertical offset (custom pitch)
[05:41:19] ============= [PASSED] drm_test_fb_clip_offset =============
[05:41:19] =================== drm_test_fb_memcpy  ====================
[05:41:19] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:41:19] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:41:19] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:41:19] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:41:19] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:41:19] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:41:19] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:41:19] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:41:19] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:41:19] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:41:19] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:41:19] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:41:19] =============== [PASSED] drm_test_fb_memcpy ================
[05:41:19] ============= [PASSED] drm_format_helper_test ==============
[05:41:19] ================= drm_format (18 subtests) =================
[05:41:19] [PASSED] drm_test_format_block_width_invalid
[05:41:19] [PASSED] drm_test_format_block_width_one_plane
[05:41:19] [PASSED] drm_test_format_block_width_two_plane
[05:41:19] [PASSED] drm_test_format_block_width_three_plane
[05:41:19] [PASSED] drm_test_format_block_width_tiled
[05:41:19] [PASSED] drm_test_format_block_height_invalid
[05:41:19] [PASSED] drm_test_format_block_height_one_plane
[05:41:19] [PASSED] drm_test_format_block_height_two_plane
[05:41:19] [PASSED] drm_test_format_block_height_three_plane
[05:41:19] [PASSED] drm_test_format_block_height_tiled
[05:41:19] [PASSED] drm_test_format_min_pitch_invalid
[05:41:19] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:41:19] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:41:19] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:41:19] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:41:19] [PASSED] drm_test_format_min_pitch_two_plane
[05:41:19] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:41:19] [PASSED] drm_test_format_min_pitch_tiled
[05:41:19] =================== [PASSED] drm_format ====================
[05:41:19] ============== drm_framebuffer (10 subtests) ===============
[05:41:19] ========== drm_test_framebuffer_check_src_coords  ==========
[05:41:19] [PASSED] Success: source fits into fb
[05:41:19] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:41:19] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:41:19] [PASSED] Fail: overflowing fb with source width
[05:41:19] [PASSED] Fail: overflowing fb with source height
[05:41:19] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:41:19] [PASSED] drm_test_framebuffer_cleanup
[05:41:19] =============== drm_test_framebuffer_create  ===============
[05:41:19] [PASSED] ABGR8888 normal sizes
[05:41:19] [PASSED] ABGR8888 max sizes
[05:41:19] [PASSED] ABGR8888 pitch greater than min required
[05:41:19] [PASSED] ABGR8888 pitch less than min required
[05:41:19] [PASSED] ABGR8888 Invalid width
[05:41:19] [PASSED] ABGR8888 Invalid buffer handle
[05:41:19] [PASSED] No pixel format
[05:41:19] [PASSED] ABGR8888 Width 0
[05:41:19] [PASSED] ABGR8888 Height 0
[05:41:19] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:41:19] [PASSED] ABGR8888 Large buffer offset
[05:41:19] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:41:19] [PASSED] ABGR8888 Invalid flag
[05:41:19] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:41:19] [PASSED] ABGR8888 Valid buffer modifier
[05:41:19] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:41:19] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:41:19] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:41:19] [PASSED] NV12 Normal sizes
[05:41:19] [PASSED] NV12 Max sizes
[05:41:19] [PASSED] NV12 Invalid pitch
[05:41:19] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:41:19] [PASSED] NV12 different  modifier per-plane
[05:41:19] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:41:19] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:41:19] [PASSED] NV12 Modifier for inexistent plane
[05:41:19] [PASSED] NV12 Handle for inexistent plane
[05:41:19] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:41:19] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:41:19] [PASSED] YVU420 Normal sizes
[05:41:19] [PASSED] YVU420 Max sizes
[05:41:19] [PASSED] YVU420 Invalid pitch
[05:41:19] [PASSED] YVU420 Different pitches
[05:41:19] [PASSED] YVU420 Different buffer offsets/pitches
[05:41:19] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:41:19] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:41:19] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:41:19] [PASSED] YVU420 Valid modifier
[05:41:19] [PASSED] YVU420 Different modifiers per plane
[05:41:19] [PASSED] YVU420 Modifier for inexistent plane
[05:41:19] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:41:19] [PASSED] X0L2 Normal sizes
[05:41:19] [PASSED] X0L2 Max sizes
[05:41:19] [PASSED] X0L2 Invalid pitch
[05:41:19] [PASSED] X0L2 Pitch greater than minimum required
[05:41:19] [PASSED] X0L2 Handle for inexistent plane
[05:41:19] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:41:19] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:41:19] [PASSED] X0L2 Valid modifier
[05:41:19] [PASSED] X0L2 Modifier for inexistent plane
[05:41:19] =========== [PASSED] drm_test_framebuffer_create ===========
[05:41:19] [PASSED] drm_test_framebuffer_free
[05:41:19] [PASSED] drm_test_framebuffer_init
[05:41:19] [PASSED] drm_test_framebuffer_init_bad_format
[05:41:19] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:41:19] [PASSED] drm_test_framebuffer_lookup
[05:41:19] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:41:19] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:41:19] ================= [PASSED] drm_framebuffer =================
[05:41:19] ================ drm_gem_shmem (8 subtests) ================
[05:41:19] [PASSED] drm_gem_shmem_test_obj_create
[05:41:19] [PASSED] drm_gem_shmem_test_obj_create_private
[05:41:19] [PASSED] drm_gem_shmem_test_pin_pages
[05:41:19] [PASSED] drm_gem_shmem_test_vmap
[05:41:19] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:41:19] [PASSED] drm_gem_shmem_test_get_sg_table
[05:41:19] [PASSED] drm_gem_shmem_test_madvise
[05:41:19] [PASSED] drm_gem_shmem_test_purge
[05:41:19] ================== [PASSED] drm_gem_shmem ==================
[05:41:19] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[05:41:19] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:41:19] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:41:19] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:41:19] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:41:19] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:41:19] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:41:19] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[05:41:19] [PASSED] Automatic
[05:41:19] [PASSED] Full
[05:41:19] [PASSED] Limited 16:235
[05:41:19] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:41:19] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:41:19] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:41:19] [PASSED] drm_test_check_disable_connector
[05:41:19] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:41:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:41:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:41:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:41:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:41:19] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:41:19] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:41:19] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:41:19] [PASSED] drm_test_check_output_bpc_dvi
[05:41:19] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:41:19] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:41:19] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:41:19] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:41:19] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:41:19] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:41:19] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:41:19] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:41:19] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:41:19] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:41:19] [PASSED] drm_test_check_broadcast_rgb_value
[05:41:19] [PASSED] drm_test_check_bpc_8_value
[05:41:19] [PASSED] drm_test_check_bpc_10_value
[05:41:19] [PASSED] drm_test_check_bpc_12_value
[05:41:19] [PASSED] drm_test_check_format_value
[05:41:19] [PASSED] drm_test_check_tmds_char_value
[05:41:19] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:41:19] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[05:41:19] [PASSED] drm_test_check_mode_valid
[05:41:19] [PASSED] drm_test_check_mode_valid_reject
[05:41:19] [PASSED] drm_test_check_mode_valid_reject_rate
[05:41:19] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:41:19] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:41:19] ================= drm_managed (2 subtests) =================
[05:41:19] [PASSED] drm_test_managed_release_action
[05:41:19] [PASSED] drm_test_managed_run_action
[05:41:19] =================== [PASSED] drm_managed ===================
[05:41:19] =================== drm_mm (6 subtests) ====================
[05:41:19] [PASSED] drm_test_mm_init
[05:41:19] [PASSED] drm_test_mm_debug
[05:41:19] [PASSED] drm_test_mm_align32
[05:41:19] [PASSED] drm_test_mm_align64
[05:41:19] [PASSED] drm_test_mm_lowest
[05:41:19] [PASSED] drm_test_mm_highest
[05:41:19] ===================== [PASSED] drm_mm ======================
[05:41:19] ============= drm_modes_analog_tv (5 subtests) =============
[05:41:19] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:41:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:41:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:41:19] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:41:19] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:41:19] =============== [PASSED] drm_modes_analog_tv ===============
[05:41:19] ============== drm_plane_helper (2 subtests) ===============
[05:41:19] =============== drm_test_check_plane_state  ================
[05:41:19] [PASSED] clipping_simple
[05:41:19] [PASSED] clipping_rotate_reflect
[05:41:19] [PASSED] positioning_simple
[05:41:19] [PASSED] upscaling
[05:41:19] [PASSED] downscaling
[05:41:19] [PASSED] rounding1
[05:41:19] [PASSED] rounding2
[05:41:19] [PASSED] rounding3
[05:41:19] [PASSED] rounding4
[05:41:19] =========== [PASSED] drm_test_check_plane_state ============
[05:41:19] =========== drm_test_check_invalid_plane_state  ============
[05:41:19] [PASSED] positioning_invalid
[05:41:19] [PASSED] upscaling_invalid
[05:41:19] [PASSED] downscaling_invalid
[05:41:19] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:41:19] ================ [PASSED] drm_plane_helper =================
[05:41:19] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:41:19] ====== drm_test_connector_helper_tv_get_modes_check  =======
[05:41:19] [PASSED] None
[05:41:19] [PASSED] PAL
[05:41:19] [PASSED] NTSC
[05:41:19] [PASSED] Both, NTSC Default
[05:41:19] [PASSED] Both, PAL Default
[05:41:19] [PASSED] Both, NTSC Default, with PAL on command-line
[05:41:19] [PASSED] Both, PAL Default, with NTSC on command-line
[05:41:19] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:41:19] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:41:19] ================== drm_rect (9 subtests) ===================
[05:41:19] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:41:19] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:41:19] [PASSED] drm_test_rect_clip_scaled_clipped
[05:41:19] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:41:19] ================= drm_test_rect_intersect  =================
[05:41:19] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:41:19] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:41:19] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:41:19] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:41:19] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:41:19] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:41:19] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:41:19] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:41:19] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:41:19] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:41:19] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:41:19] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:41:19] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:41:19] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:41:19] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:41:19] ============= [PASSED] drm_test_rect_intersect =============
[05:41:19] ================ drm_test_rect_calc_hscale  ================
[05:41:19] [PASSED] normal use
[05:41:19] [PASSED] out of max range
[05:41:19] [PASSED] out of min range
[05:41:19] [PASSED] zero dst
[05:41:19] [PASSED] negative src
[05:41:19] [PASSED] negative dst
[05:41:19] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:41:19] ================ drm_test_rect_calc_vscale  ================
[05:41:19] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[05:41:19] [PASSED] out of max range
[05:41:19] [PASSED] out of min range
[05:41:19] [PASSED] zero dst
[05:41:19] [PASSED] negative src
[05:41:19] [PASSED] negative dst
[05:41:19] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:41:19] ================== drm_test_rect_rotate  ===================
[05:41:19] [PASSED] reflect-x
[05:41:19] [PASSED] reflect-y
[05:41:19] [PASSED] rotate-0
[05:41:19] [PASSED] rotate-90
[05:41:19] [PASSED] rotate-180
[05:41:19] [PASSED] rotate-270
[05:41:19] ============== [PASSED] drm_test_rect_rotate ===============
[05:41:19] ================ drm_test_rect_rotate_inv  =================
[05:41:19] [PASSED] reflect-x
[05:41:19] [PASSED] reflect-y
[05:41:19] [PASSED] rotate-0
[05:41:19] [PASSED] rotate-90
[05:41:19] [PASSED] rotate-180
[05:41:19] [PASSED] rotate-270
[05:41:19] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:41:19] ==================== [PASSED] drm_rect =====================
[05:41:19] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:41:19] ============ drm_test_sysfb_build_fourcc_list  =============
[05:41:19] [PASSED] no native formats
[05:41:19] [PASSED] XRGB8888 as native format
[05:41:19] [PASSED] remove duplicates
[05:41:19] [PASSED] convert alpha formats
[05:41:19] [PASSED] random formats
[05:41:19] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:41:19] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:41:19] ============================================================
[05:41:19] Testing complete. Ran 622 tests: passed: 622
[05:41:19] Elapsed time: 26.875s total, 1.693s configuring, 24.712s building, 0.439s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:41:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:41:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:41:30] Starting KUnit Kernel (1/1)...
[05:41:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:41:31] ================= ttm_device (5 subtests) ==================
[05:41:31] [PASSED] ttm_device_init_basic
[05:41:31] [PASSED] ttm_device_init_multiple
[05:41:31] [PASSED] ttm_device_fini_basic
[05:41:31] [PASSED] ttm_device_init_no_vma_man
[05:41:31] ================== ttm_device_init_pools  ==================
[05:41:31] [PASSED] No DMA allocations, no DMA32 required
[05:41:31] [PASSED] DMA allocations, DMA32 required
[05:41:31] [PASSED] No DMA allocations, DMA32 required
[05:41:31] [PASSED] DMA allocations, no DMA32 required
[05:41:31] ============== [PASSED] ttm_device_init_pools ==============
[05:41:31] =================== [PASSED] ttm_device ====================
[05:41:31] ================== ttm_pool (8 subtests) ===================
[05:41:31] ================== ttm_pool_alloc_basic  ===================
[05:41:31] [PASSED] One page
[05:41:31] [PASSED] More than one page
[05:41:31] [PASSED] Above the allocation limit
[05:41:31] [PASSED] One page, with coherent DMA mappings enabled
[05:41:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:41:31] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:41:31] ============== ttm_pool_alloc_basic_dma_addr  ==============
[05:41:31] [PASSED] One page
[05:41:31] [PASSED] More than one page
[05:41:31] [PASSED] Above the allocation limit
[05:41:31] [PASSED] One page, with coherent DMA mappings enabled
[05:41:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:41:31] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:41:31] [PASSED] ttm_pool_alloc_order_caching_match
[05:41:31] [PASSED] ttm_pool_alloc_caching_mismatch
[05:41:31] [PASSED] ttm_pool_alloc_order_mismatch
[05:41:31] [PASSED] ttm_pool_free_dma_alloc
[05:41:31] [PASSED] ttm_pool_free_no_dma_alloc
[05:41:31] [PASSED] ttm_pool_fini_basic
[05:41:31] ==================== [PASSED] ttm_pool =====================
[05:41:31] ================ ttm_resource (8 subtests) =================
[05:41:31] ================= ttm_resource_init_basic  =================
[05:41:31] [PASSED] Init resource in TTM_PL_SYSTEM
[05:41:31] [PASSED] Init resource in TTM_PL_VRAM
[05:41:31] [PASSED] Init resource in a private placement
[05:41:31] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:41:31] ============= [PASSED] ttm_resource_init_basic =============
[05:41:31] [PASSED] ttm_resource_init_pinned
[05:41:31] [PASSED] ttm_resource_fini_basic
[05:41:31] [PASSED] ttm_resource_manager_init_basic
[05:41:31] [PASSED] ttm_resource_manager_usage_basic
[05:41:31] [PASSED] ttm_resource_manager_set_used_basic
[05:41:31] [PASSED] ttm_sys_man_alloc_basic
[05:41:31] [PASSED] ttm_sys_man_free_basic
[05:41:31] ================== [PASSED] ttm_resource ===================
[05:41:31] =================== ttm_tt (15 subtests) ===================
[05:41:31] ==================== ttm_tt_init_basic  ====================
[05:41:31] [PASSED] Page-aligned size
[05:41:31] [PASSED] Extra pages requested
[05:41:31] ================ [PASSED] ttm_tt_init_basic ================
[05:41:31] [PASSED] ttm_tt_init_misaligned
[05:41:31] [PASSED] ttm_tt_fini_basic
[05:41:31] [PASSED] ttm_tt_fini_sg
[05:41:31] [PASSED] ttm_tt_fini_shmem
[05:41:31] [PASSED] ttm_tt_create_basic
[05:41:31] [PASSED] ttm_tt_create_invalid_bo_type
[05:41:31] [PASSED] ttm_tt_create_ttm_exists
[05:41:31] [PASSED] ttm_tt_create_failed
[05:41:31] [PASSED] ttm_tt_destroy_basic
[05:41:31] [PASSED] ttm_tt_populate_null_ttm
[05:41:31] [PASSED] ttm_tt_populate_populated_ttm
[05:41:31] [PASSED] ttm_tt_unpopulate_basic
[05:41:31] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:41:31] [PASSED] ttm_tt_swapin_basic
[05:41:31] ===================== [PASSED] ttm_tt ======================
[05:41:31] =================== ttm_bo (14 subtests) ===================
[05:41:31] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[05:41:31] [PASSED] Cannot be interrupted and sleeps
[05:41:31] [PASSED] Cannot be interrupted, locks straight away
[05:41:31] [PASSED] Can be interrupted, sleeps
[05:41:31] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:41:31] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:41:31] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:41:31] [PASSED] ttm_bo_reserve_double_resv
[05:41:31] [PASSED] ttm_bo_reserve_interrupted
[05:41:31] [PASSED] ttm_bo_reserve_deadlock
[05:41:31] [PASSED] ttm_bo_unreserve_basic
[05:41:31] [PASSED] ttm_bo_unreserve_pinned
[05:41:31] [PASSED] ttm_bo_unreserve_bulk
[05:41:31] [PASSED] ttm_bo_fini_basic
[05:41:31] [PASSED] ttm_bo_fini_shared_resv
[05:41:31] [PASSED] ttm_bo_pin_basic
[05:41:31] [PASSED] ttm_bo_pin_unpin_resource
[05:41:31] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:41:31] ===================== [PASSED] ttm_bo ======================
[05:41:31] ============== ttm_bo_validate (21 subtests) ===============
[05:41:31] ============== ttm_bo_init_reserved_sys_man  ===============
[05:41:31] [PASSED] Buffer object for userspace
[05:41:31] [PASSED] Kernel buffer object
[05:41:31] [PASSED] Shared buffer object
[05:41:31] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:41:31] ============== ttm_bo_init_reserved_mock_man  ==============
[05:41:31] [PASSED] Buffer object for userspace
[05:41:31] [PASSED] Kernel buffer object
[05:41:31] [PASSED] Shared buffer object
[05:41:31] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:41:31] [PASSED] ttm_bo_init_reserved_resv
[05:41:31] ================== ttm_bo_validate_basic  ==================
[05:41:31] [PASSED] Buffer object for userspace
[05:41:31] [PASSED] Kernel buffer object
[05:41:31] [PASSED] Shared buffer object
[05:41:31] ============== [PASSED] ttm_bo_validate_basic ==============
[05:41:31] [PASSED] ttm_bo_validate_invalid_placement
[05:41:31] ============= ttm_bo_validate_same_placement  ==============
[05:41:31] [PASSED] System manager
[05:41:31] [PASSED] VRAM manager
[05:41:31] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:41:31] [PASSED] ttm_bo_validate_failed_alloc
[05:41:31] [PASSED] ttm_bo_validate_pinned
[05:41:31] [PASSED] ttm_bo_validate_busy_placement
[05:41:31] ================ ttm_bo_validate_multihop  =================
[05:41:31] [PASSED] Buffer object for userspace
[05:41:31] [PASSED] Kernel buffer object
[05:41:31] [PASSED] Shared buffer object
[05:41:31] ============ [PASSED] ttm_bo_validate_multihop =============
[05:41:31] ========== ttm_bo_validate_no_placement_signaled  ==========
[05:41:31] [PASSED] Buffer object in system domain, no page vector
[05:41:31] [PASSED] Buffer object in system domain with an existing page vector
[05:41:31] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:41:31] ======== ttm_bo_validate_no_placement_not_signaled  ========
[05:41:31] [PASSED] Buffer object for userspace
[05:41:31] [PASSED] Kernel buffer object
[05:41:31] [PASSED] Shared buffer object
[05:41:31] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:41:31] [PASSED] ttm_bo_validate_move_fence_signaled
[05:41:31] ========= ttm_bo_validate_move_fence_not_signaled  =========
[05:41:31] [PASSED] Waits for GPU
[05:41:31] [PASSED] Tries to lock straight away
[05:41:31] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:41:31] [PASSED] ttm_bo_validate_happy_evict
[05:41:31] [PASSED] ttm_bo_validate_all_pinned_evict
[05:41:31] [PASSED] ttm_bo_validate_allowed_only_evict
[05:41:31] [PASSED] ttm_bo_validate_deleted_evict
[05:41:31] [PASSED] ttm_bo_validate_busy_domain_evict
[05:41:31] [PASSED] ttm_bo_validate_evict_gutting
[05:41:31] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[05:41:31] ================= [PASSED] ttm_bo_validate =================
[05:41:31] ============================================================
[05:41:31] Testing complete. Ran 101 tests: passed: 101
[05:41:31] Elapsed time: 11.140s total, 1.728s configuring, 9.196s building, 0.184s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: Add support for Crescent Island

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1849 bytes --]

== Series Details ==

Series: drm/xe: Add support for Crescent Island
URL   : https://patchwork.freedesktop.org/series/156297/
State : success

== Summary ==

CI Bug Log - changes from xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687_BAT -> xe-pw-156297v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 11)
------------------------------

  Missing    (1): bat-pvc-2 

Known issues
------------

  Here are the changes found in xe-pw-156297v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-plain-flip@b-edp1:
    - bat-adlp-7:         [PASS][1] -> [DMESG-WARN][2] ([Intel XE#4543])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/bat-adlp-7/igt@kms_flip@basic-plain-flip@b-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/bat-adlp-7/igt@kms_flip@basic-plain-flip@b-edp1.html

  
#### Possible fixes ####

  * igt@kms_flip@basic-plain-flip@d-edp1:
    - bat-adlp-7:         [DMESG-WARN][3] ([Intel XE#4543]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/bat-adlp-7/igt@kms_flip@basic-plain-flip@d-edp1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/bat-adlp-7/igt@kms_flip@basic-plain-flip@d-edp1.html

  
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543


Build changes
-------------

  * Linux: xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687 -> xe-pw-156297v1

  IGT_8594: 8594
  xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687: fb0f56ad8a2c9953c57c3337a72ccbf9c5050687
  xe-pw-156297v1: 156297v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/index.html

[-- Attachment #2: Type: text/html, Size: 2512 bytes --]

✗ Xe.CI.Full: failure for drm/xe: Add support for Crescent Island

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 45220 bytes --]

== Series Details ==

Series: drm/xe: Add support for Crescent Island
URL   : https://patchwork.freedesktop.org/series/156297/
State : failure

== Summary ==

CI Bug Log - changes from xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687_FULL -> xe-pw-156297v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-156297v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-156297v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-156297v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-435/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-6.html

  
#### Warnings ####

  * igt@xe_eudebug_sriov@deny-eudebug:
    - shard-adlp:         [SKIP][2] ([Intel XE#4519]) -> [SKIP][3]
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-3/igt@xe_eudebug_sriov@deny-eudebug.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-3/igt@xe_eudebug_sriov@deny-eudebug.html

  
Known issues
------------

  Here are the changes found in xe-pw-156297v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-bmg:          [PASS][4] -> [FAIL][5] ([Intel XE#3718] / [Intel XE#6078])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2:
    - shard-bmg:          [PASS][6] -> [FAIL][7] ([Intel XE#6078])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1:
    - shard-adlp:         [PASS][8] -> [DMESG-WARN][9] ([Intel XE#2953] / [Intel XE#4173]) +6 other tests dmesg-warn
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-2/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-4/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
    - shard-lnl:          [PASS][10] -> [FAIL][11] ([Intel XE#6054]) +3 other tests fail
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-lnl-4/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#316])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#1124])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#619])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#1124]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#367])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2652] / [Intel XE#787]) +12 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][18] ([Intel XE#4345])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-435/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#787]) +6 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2887])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][22] -> [INCOMPLETE][23] ([Intel XE#3862]) +1 other test incomplete
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#2907])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2252]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#373]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          NOTRUN -> [FAIL][27] ([Intel XE#1178]) +2 other tests fail
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_content_protection@atomic.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2320]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_cursor_crc@cursor-onscreen-64x21.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#2291])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][31] -> [FAIL][32] ([Intel XE#1475]) +1 other test fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][33] -> [FAIL][34] ([Intel XE#4633])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2244])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-bmg:          [PASS][36] -> [SKIP][37] ([Intel XE#2316]) +4 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-dg2-set2:     [PASS][38] -> [FAIL][39] ([Intel XE#301])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-lnl:          [PASS][40] -> [FAIL][41] ([Intel XE#301])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
    - shard-adlp:         [PASS][42] -> [DMESG-WARN][43] ([Intel XE#4543]) +11 other tests dmesg-warn
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-4/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-4/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-dp4:
    - shard-dg2-set2:     [PASS][44] -> [FAIL][45] ([Intel XE#301] / [Intel XE#3321])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html

  * igt@kms_flip@flip-vs-rmfb-interruptible:
    - shard-adlp:         [PASS][46] -> [DMESG-WARN][47] ([Intel XE#4543] / [Intel XE#5208]) +1 other test dmesg-warn
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-8/igt@kms_flip@flip-vs-rmfb-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#455]) +4 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y:
    - shard-adlp:         [PASS][49] -> [DMESG-FAIL][50] ([Intel XE#4543])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#6312])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#651]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2311]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#5390]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#2313]) +4 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#653]) +5 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][57] -> [SKIP][58] ([Intel XE#1503])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-3/igt@kms_hdr@invalid-hdr.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-5/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#2927])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-bmg:          [PASS][60] -> [SKIP][61] ([Intel XE#3012])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-7/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#2391])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_psr@fbc-pr-basic:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_psr@fbc-pr-basic.html

  * igt@kms_psr@pr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +4 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_psr@pr-dpms.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][65] ([Intel XE#1127])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#3414] / [Intel XE#3904])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][67] -> [FAIL][68] ([Intel XE#4459]) +1 other test fail
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-lnl-5/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-lnl-7/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_eudebug@basic-exec-queues:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#4837]) +2 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_eudebug@basic-exec-queues.html

  * igt@xe_eudebug@basic-vm-access-userptr-faultable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][70] ([Intel XE#4837]) +2 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@xe_eudebug@basic-vm-access-userptr-faultable.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][71] -> [INCOMPLETE][72] ([Intel XE#6321])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_basic@multigpu-no-exec-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#2322]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_exec_basic@multigpu-no-exec-rebind.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][74] ([Intel XE#288]) +6 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@xe_exec_fault_mode@once-bindexecqueue-imm.html

  * igt@xe_exec_system_allocator@many-stride-malloc-prefetch:
    - shard-bmg:          [PASS][75] -> [WARN][76] ([Intel XE#5786])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_exec_system_allocator@many-stride-malloc-prefetch.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-7/igt@xe_exec_system_allocator@many-stride-malloc-prefetch.html

  * igt@xe_exec_system_allocator@many-stride-malloc-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#4915]) +46 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@xe_exec_system_allocator@many-stride-malloc-race.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [PASS][78] -> [FAIL][79] ([Intel XE#5625])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#4943]) +3 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html

  * igt@xe_module_load@force-load:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#2457])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_module_load@force-load.html

  * igt@xe_pm@d3cold-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][82] ([Intel XE#2284] / [Intel XE#366])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@xe_pm@d3cold-basic.html

  * igt@xe_query@multigpu-query-cs-cycles:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#944])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_query@multigpu-query-cs-cycles.html

  * igt@xe_sriov_auto_provisioning@fair-allocation:
    - shard-dg2-set2:     NOTRUN -> [SKIP][84] ([Intel XE#4130])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-435/igt@xe_sriov_auto_provisioning@fair-allocation.html

  * igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random:
    - shard-adlp:         [PASS][85] -> [DMESG-FAIL][86] ([Intel XE#3868] / [Intel XE#5213] / [Intel XE#5545]) +1 other test dmesg-fail
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-3/igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-3/igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random.html

  
#### Possible fixes ####

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-adlp:         [DMESG-WARN][87] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-9/igt@core_hotunplug@hotrebind-lateclose.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-9/igt@core_hotunplug@hotrebind-lateclose.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-bmg:          [SKIP][89] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][91] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][93] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-bmg:          [SKIP][95] ([Intel XE#2291]) -> [PASS][96] +4 other tests pass
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-7/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-bmg:          [SKIP][97] ([Intel XE#4354]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-7/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [SKIP][99] ([Intel XE#2316]) -> [PASS][100] +6 other tests pass
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][101] ([Intel XE#4543]) -> [PASS][102] +6 other tests pass
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-8/igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a1.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][103] ([Intel XE#301]) -> [PASS][104] +2 other tests pass
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-bmg:          [SKIP][105] ([Intel XE#1503]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [SKIP][107] ([Intel XE#4596]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-4.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][109] ([Intel XE#6321]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-4/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-3/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_exec_balancer@once-parallel-userptr-invalidate:
    - shard-bmg:          [DMESG-FAIL][111] ([Intel XE#3876]) -> [PASS][112] +2 other tests pass
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_exec_balancer@once-parallel-userptr-invalidate.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_exec_balancer@once-parallel-userptr-invalidate.html

  * igt@xe_exec_basic@many-null-defer-bind:
    - shard-bmg:          [DMESG-WARN][113] ([Intel XE#3876]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_exec_basic@many-null-defer-bind.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_exec_basic@many-null-defer-bind.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm:
    - shard-bmg:          [FAIL][115] ([Intel XE#5625]) -> [PASS][116] +3 other tests pass
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-imm.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm:
    - shard-bmg:          [FAIL][117] ([Intel XE#6050]) -> [PASS][118] +1 other test pass
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html

  * igt@xe_exec_reset@cm-gt-reset:
    - shard-bmg:          [FAIL][119] ([Intel XE#6325]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_exec_reset@cm-gt-reset.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_exec_reset@cm-gt-reset.html

  * igt@xe_exec_system_allocator@twice-mmap-new-race-nomemset:
    - shard-bmg:          [FAIL][121] ([Intel XE#4937] / [Intel XE#5625]) -> [PASS][122] +32 other tests pass
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_exec_system_allocator@twice-mmap-new-race-nomemset.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_exec_system_allocator@twice-mmap-new-race-nomemset.html

  * igt@xe_pm@s2idle-exec-after:
    - shard-bmg:          [TIMEOUT][123] ([Intel XE#3876] / [Intel XE#6162]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_pm@s2idle-exec-after.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_pm@s2idle-exec-after.html

  * igt@xe_pm_residency@gt-c6-freeze@gt0:
    - shard-bmg:          [DMESG-FAIL][125] ([Intel XE#5545]) -> [PASS][126] +1 other test pass
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_pm_residency@gt-c6-freeze@gt0.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_pm_residency@gt-c6-freeze@gt0.html

  * igt@xe_pm_residency@gt-c6-freeze@gt1:
    - shard-bmg:          [FAIL][127] ([Intel XE#5545]) -> [PASS][128]
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_pm_residency@gt-c6-freeze@gt1.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_pm_residency@gt-c6-freeze@gt1.html

  * igt@xe_vm@munmap-style-unbind-userptr-inval-front:
    - shard-bmg:          [INCOMPLETE][129] ([Intel XE#4842]) -> [PASS][130]
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-2/igt@xe_vm@munmap-style-unbind-userptr-inval-front.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@xe_vm@munmap-style-unbind-userptr-inval-front.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-adlp:         [DMESG-WARN][131] ([Intel XE#4543]) -> [DMESG-WARN][132] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-2/igt@kms_async_flips@async-flip-suspend-resume.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-4/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [SKIP][133] ([Intel XE#2341]) -> [FAIL][134] ([Intel XE#1178])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_content_protection@srm.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-7/igt@kms_content_protection@srm.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-adlp:         [DMESG-FAIL][135] ([Intel XE#4543] / [Intel XE#4921]) -> [DMESG-FAIL][136] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543] / [Intel XE#4921]) +1 other test dmesg-fail
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y:
    - shard-adlp:         [DMESG-FAIL][137] ([Intel XE#4543]) -> [FAIL][138] ([Intel XE#1874])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][139] ([Intel XE#2311]) -> [SKIP][140] ([Intel XE#2312]) +9 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][141] ([Intel XE#2312]) -> [SKIP][142] ([Intel XE#2311]) +13 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][143] ([Intel XE#2312]) -> [SKIP][144] ([Intel XE#5390]) +6 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move:
    - shard-bmg:          [SKIP][145] ([Intel XE#5390]) -> [SKIP][146] ([Intel XE#2312]) +1 other test skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][147] ([Intel XE#2312]) -> [SKIP][148] ([Intel XE#2313]) +13 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][149] ([Intel XE#2313]) -> [SKIP][150] ([Intel XE#2312]) +9 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][151] ([Intel XE#2426]) -> [FAIL][152] ([Intel XE#1729])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][153] ([Intel XE#362]) -> [SKIP][154] ([Intel XE#1500])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-adlp:         [ABORT][155] ([Intel XE#4917] / [Intel XE#5530]) -> [ABORT][156] ([Intel XE#5530])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687/shard-adlp-3/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/shard-adlp-1/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4519
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4842]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4842
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
  [Intel XE#4921]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4921
  [Intel XE#4937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4937
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
  [Intel XE#6050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6050
  [Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6162
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6325
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687 -> xe-pw-156297v1

  IGT_8594: 8594
  xe-3961-fb0f56ad8a2c9953c57c3337a72ccbf9c5050687: fb0f56ad8a2c9953c57c3337a72ccbf9c5050687
  xe-pw-156297v1: 156297v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156297v1/index.html

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