[PATCH v9 00/17] Enable/Disable DC balance along with VRR DSB

[PATCH v9 00/17] Enable/Disable DC balance along with VRR DSB

[Mitul Golani]

Control DC Balance Adjustment bit to accomodate changes along
with VRR DSB implementation.

Mitul Golani (11):
  drm/i915/display: Add source param for dc balance
  drm/i915/vrr: Add VRR DC balance registers
  drm/i915/vrr: Add DC Balance params to crtc_state
  drm/i915/vrr: Add state dump for DC Balance params
  drm/i915/vrr: Add compute config for DC Balance params
  drm/i915/vrr: Add function to reset DC balance accumulated params
  drm/i915/display: Add DC Balance flip count operations
  drm/i915/vrr: Write DC balance params to hw registers
  drm/i915/display: Wait for VRR PUSH status update
  drm/i915/display: Add function to configure event for dc balance
  drm/i915/vrr: Enable DC Balance

Ville Syrjälä (6):
  drm/i915/dmc: Add pipe dmc registers and bits for DC Balance
  drm/i915/vrr: Add functions to read out vmin/vmax stuff
  drm/i915/vblank: Extract vrr_vblank_start()
  drm/i915/vrr: Implement vblank evasion with DC balancing
  drm/i915/dsb: Add pipedmc dc balance enable/disable
  drm/i915/vrr: Pause DC Balancing for DSB commits

 .../drm/i915/display/intel_crtc_state_dump.c  |   8 +
 drivers/gpu/drm/i915/display/intel_display.c  |  30 ++
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |  11 +
 drivers/gpu/drm/i915/display/intel_dmc.c      |  32 ++
 drivers/gpu/drm/i915/display/intel_dmc.h      |   5 +
 drivers/gpu/drm/i915/display/intel_dmc_regs.h |  60 ++++
 drivers/gpu/drm/i915/display/intel_dsb.c      |  31 +-
 drivers/gpu/drm/i915/display/intel_vblank.c   |  33 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 283 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vrr.h      |  10 +
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  68 +++++
 12 files changed, 565 insertions(+), 7 deletions(-)

-- 
2.48.1

[PATCH v9 01/17] drm/i915/display: Add source param for dc balance

[Mitul Golani]

Add source param for dc balance enablement.

--v2:
- Arrange in alphabetic order. (Ankit)
- Update name. (Ankit)

--v3:
- Commit message update. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index b559ef43d547..7ad49e9529f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -200,6 +200,7 @@ struct intel_display_platforms {
 #define HAS_ULTRAJOINER(__display)	(((__display)->platform.dgfx && \
 					  DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
 #define HAS_VRR(__display)		(DISPLAY_VER(__display) >= 11)
+#define HAS_VRR_DC_BALANCE(__display)	(DISPLAY_VER(__display) >= 30)
 #define INTEL_NUM_PIPES(__display)	(hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
 #define OVERLAY_NEEDS_PHYSICAL(__display)	(DISPLAY_INFO(__display)->overlay_needs_physical)
 #define SUPPORTS_TV(__display)		(DISPLAY_INFO(__display)->supports_tv)
-- 
2.48.1

Re: [PATCH v9 01/17] drm/i915/display: Add source param for dc balance

[Nautiyal, Ankit K]

On 11/27/2025 2:45 PM, Mitul Golani wrote:
> Add source param for dc balance enablement.
>
> --v2:
> - Arrange in alphabetic order. (Ankit)
> - Update name. (Ankit)
>
> --v3:
> - Commit message update. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index b559ef43d547..7ad49e9529f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -200,6 +200,7 @@ struct intel_display_platforms {
>   #define HAS_ULTRAJOINER(__display)	(((__display)->platform.dgfx && \
>   					  DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
>   #define HAS_VRR(__display)		(DISPLAY_VER(__display) >= 11)
> +#define HAS_VRR_DC_BALANCE(__display)	(DISPLAY_VER(__display) >= 30)
>   #define INTEL_NUM_PIPES(__display)	(hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
>   #define OVERLAY_NEEDS_PHYSICAL(__display)	(DISPLAY_INFO(__display)->overlay_needs_physical)
>   #define SUPPORTS_TV(__display)		(DISPLAY_INFO(__display)->supports_tv)

[PATCH v9 02/17] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add pipe dmc registers and  access bits for DC Balance params
configuration and enablement.

--v2:
- Separate register definitions for transcoder and
pipe dmc. (Ankit)
- Use MMIO pipe macros instead of transcoder ones. (Ankit)
- Remove dev_priv use. (Jani, Nikula)

--v3:
- Add all register address, from capital alphabet to small. (Ankit)
- Add EVT CTL registers.
- Add co-author tag.
- Add event flag for Triggering DC Balance.

--v4:
- Add DCB Flip count and balance reset registers.

--v5:
- Correct macro usage for flip count. (Ankit)
- Use register offset in lower case.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index c5aa49921cb9..38e342b45af0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -584,4 +584,64 @@ enum pipedmc_event_id {
 #define PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6b8)
 #define PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6c0)
 
+#define _PIPEDMC_DCB_CTL_A			0x5f1a0
+#define _PIPEDMC_DCB_CTL_B			0x5f5a0
+#define PIPEDMC_DCB_CTL(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A,\
+							   _PIPEDMC_DCB_CTL_B)
+#define  PIPEDMC_ADAPTIVE_DCB_ENABLE		REG_BIT(31)
+
+#define _PIPEDMC_DCB_VBLANK_A			0x5f1bc
+#define _PIPEDMC_DCB_VBLANK_B			0x5f5bc
+#define PIPEDMC_DCB_VBLANK(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A,\
+							   _PIPEDMC_DCB_VBLANK_B)
+
+#define _PIPEDMC_DCB_SLOPE_A			0x5f1b8
+#define _PIPEDMC_DCB_SLOPE_B			0x5f5b8
+#define PIPEDMC_DCB_SLOPE(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A,\
+							   _PIPEDMC_DCB_SLOPE_B)
+
+#define _PIPEDMC_DCB_GUARDBAND_A		0x5f1b4
+#define _PIPEDMC_DCB_GUARDBAND_B		0x5f5b4
+#define PIPEDMC_DCB_GUARDBAND(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A,\
+							   _PIPEDMC_DCB_GUARDBAND_B)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A		0x5f1ac
+#define _PIPEDMC_DCB_MAX_INCREASE_B		0x5f5ac
+#define PIPEDMC_DCB_MAX_INCREASE(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A,\
+							   _PIPEDMC_DCB_MAX_INCREASE_B)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A		0x5f1b0
+#define _PIPEDMC_DCB_MAX_DECREASE_B		0x5f5b0
+#define PIPEDMC_DCB_MAX_DECREASE(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A,\
+							   _PIPEDMC_DCB_MAX_DECREASE_B)
+
+#define _PIPEDMC_DCB_VMIN_A			0x5f1a4
+#define _PIPEDMC_DCB_VMIN_B			0x5f5a4
+#define PIPEDMC_DCB_VMIN(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A,\
+							   _PIPEDMC_DCB_VMIN_B)
+
+#define _PIPEDMC_DCB_VMAX_A			0x5f1a8
+#define _PIPEDMC_DCB_VMAX_B			0x5f5a8
+#define PIPEDMC_DCB_VMAX(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A,\
+							   _PIPEDMC_DCB_VMAX_B)
+
+#define _PIPEDMC_DCB_DEBUG_A			0x5f1c0
+#define _PIPEDMC_DCB_DEBUG_B			0x5f5c0
+#define PIPEDMC_DCB_DEBUG(pipe)			_MMIO_PIPE(pipe, _PIPEDMC_DCB_DEBUG_A,\
+							   _PIPEDMC_DCB_DEBUG_B)
+
+#define _PIPEDMC_EVT_CTL_3_A			0x5f040
+#define _PIPEDMC_EVT_CTL_3_B			0x5f440
+#define PIPEDMC_EVT_CTL_3(pipe)			_MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_3_A,\
+							   _PIPEDMC_EVT_CTL_3_B)
+
+#define _PIPEDMC_DCB_FLIP_COUNT_A		0x906a4
+#define _PIPEDMC_DCB_FLIP_COUNT_B		0x986a4
+#define PIPEDMC_DCB_FLIP_COUNT(pipe)		_MMIO_PIPE(pipe, _PIPEDMC_DCB_FLIP_COUNT_A,\
+							   _PIPEDMC_DCB_FLIP_COUNT_B)
+
+#define _PIPEDMC_DCB_BALANCE_RESET_A		0x906a8
+#define _PIPEDMC_DCB_BALANCE_RESET_B		0x986a8
+#define PIPEDMC_DCB_BALANCE_RESET(pipe)		_MMIO_PIPE(pipe, _PIPEDMC_DCB_BALANCE_RESET_A,\
+							   _PIPEDMC_DCB_BALANCE_RESET_B)
 #endif /* __INTEL_DMC_REGS_H__ */
-- 
2.48.1

[PATCH v9 03/17] drm/i915/vrr: Add VRR DC balance registers

[Mitul Golani]

Add VRR register offsets and bits to access DC Balance configuration.

--v2:
- Separate register definitions. (Ankit)
- Remove usage of dev_priv. (Jani, Nikula)

--v3:
- Convert register address offset, from capital to small. (Ankit)
- Move mask bits near to register offsets. (Ankit)

--v4:
- Use _MMIO_TRANS wherever possible. (Jani)

--v5:
- Added LIVE Value registers for VMAX and FLIPLINE as provided by DMC fw
- For pipe B it is temporary and expected to change later once finalised.

--v6:
- Add live value registers for DCB VMAX/FLIPLINE.

--v7:
- Correct commit message file. (Jani Nikula)
- Add bits in highest to lowest order. (Jani Nikula)

--v8:
- Register/bitfields indentation changes as per i915_reg.h
mentioned format (Jani, Ankit)

--v9:
- Remove comment. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index ba9b9215dc11..427ada0d3973 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -8,6 +8,73 @@
 
 #include "intel_display_reg_defs.h"
 
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A	0x604d4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B	0x614d4
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans)	_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
+							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
+#define  VRR_DCB_ADJ_FLIPLINE_CNT_MASK		REG_GENMASK(31, 24)
+#define  VRR_DCB_ADJ_FLIPLINE_MASK		REG_GENMASK(19, 0)
+#define  VRR_DCB_ADJ_FLIPLINE(flipline)		REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \
+							       (flipline))
+
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A		0x90700
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B		0x98700
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(trans)	_MMIO_TRANS(trans, \
+								    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A, \
+								    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B)
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A		0x604d8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B		0x614d8
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans)	_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
+#define  VRR_DCB_ADJ_VMAX_CNT_MASK		REG_GENMASK(31, 24)
+#define  VRR_DCB_ADJ_VMAX_MASK			REG_GENMASK(19, 0)
+#define  VRR_DCB_ADJ_VMAX(vmax)			REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax))
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A	0x906f8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B	0x986f8
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(trans)	_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B)
+
+#define _TRANS_VRR_DCB_FLIPLINE_A		0x60418
+#define _TRANS_VRR_DCB_FLIPLINE_B		0x61418
+#define TRANS_VRR_DCB_FLIPLINE(trans)		_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_FLIPLINE_A, \
+							    _TRANS_VRR_DCB_FLIPLINE_B)
+#define  VRR_DCB_FLIPLINE_MASK			REG_GENMASK(19, 0)
+#define  VRR_DCB_FLIPLINE(flipline)		REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \
+							       (flipline))
+
+#define _TRANS_VRR_DCB_FLIPLINE_LIVE_A		0x906fc
+#define _TRANS_VRR_DCB_FLIPLINE_LIVE_B		0x986fc
+#define TRANS_VRR_DCB_FLIPLINE_LIVE(trans)	_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_FLIPLINE_LIVE_A, \
+							    _TRANS_VRR_DCB_FLIPLINE_LIVE_B)
+
+#define _TRANS_VRR_DCB_VMAX_A			0x60414
+#define _TRANS_VRR_DCB_VMAX_B			0x61414
+#define TRANS_VRR_DCB_VMAX(trans)		_MMIO_TRANS(trans, \
+							     _TRANS_VRR_DCB_VMAX_A, \
+							     _TRANS_VRR_DCB_VMAX_B)
+#define  VRR_DCB_VMAX_MASK			REG_GENMASK(19, 0)
+#define  VRR_DCB_VMAX(vmax)			REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax))
+
+#define _TRANS_VRR_DCB_VMAX_LIVE_A		0x906f4
+#define _TRANS_VRR_DCB_VMAX_LIVE_B		0x986f4
+#define TRANS_VRR_DCB_VMAX_LIVE(trans)		_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_VMAX_LIVE_A, \
+							    _TRANS_VRR_DCB_VMAX_LIVE_B)
+
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A		0x604c0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B		0x614c0
+#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans)	_MMIO_TRANS(trans, \
+							     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
+							     _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
+#define  ADAPTIVE_SYNC_COUNTER_EN		REG_BIT(31)
+
 #define _TRANS_VRR_CTL_A			0x60420
 #define _TRANS_VRR_CTL_B			0x61420
 #define _TRANS_VRR_CTL_C			0x62420
@@ -19,6 +86,7 @@
 #define   VRR_CTL_CMRR_ENABLE			REG_BIT(27)
 #define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
 #define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
+#define   VRR_CTL_DCB_ADJ_ENABLE		REG_BIT(28)
 #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
 #define   XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
 #define   XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
-- 
2.48.1

[PATCH v9 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.

--v2:
- Correct Author details.

--v3:
- Separate register details from this  patch.

--v4:
- Add mask macros.

--v5:
- As live prefix params indicate timings for current frame,
read just _live prefix values instead of next frame timings as
done previously.
- Squash Refactor vrr params patch.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 56 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  5 +++
 2 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b92c42fde937..7f0ead192777 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -261,6 +261,12 @@ static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
 		return value - crtc_state->set_context_latency;
 }
 
+static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
+				  int vmin_vmax)
+{
+	return intel_vrr_hw_value(crtc_state, vmin_vmax) - crtc_state->vrr.guardband;
+}
+
 /*
  * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
  * Vtotal value.
@@ -898,3 +904,53 @@ int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
 	return intel_vrr_vmin_vblank_start(crtc_state) -
 	       crtc_state->set_context_latency;
 }
+
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index bc9044621635..66fb9ad846f2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -43,4 +43,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
 
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_VRR_H__ */
-- 
2.48.1

Re: [PATCH v9 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff

[Jani Nikula]

On Thu, 27 Nov 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 tmp = 0;
> +
> +	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));
> +
> +	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
> +		return -1;

My pet peeve, using magic -1 as a negative error code.


BR,
Jani.


-- 
Jani Nikula, Intel

RE: [PATCH v9 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: 27 November 2025 16:19
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; ville.syrjala@linux.intel.com
> Subject: Re: [PATCH v9 04/17] drm/i915/vrr: Add functions to read out
> vmin/vmax stuff
> 
> On Thu, 27 Nov 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> wrote:
> > +int intel_vrr_dcb_vmin_vblank_start_next(const struct
> > +intel_crtc_state *crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +	u32 tmp = 0;
> > +
> > +	tmp = intel_de_read(display,
> > +TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));
> > +
> > +	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
> > +		return -1;
> 
> My pet peeve, using magic -1 as a negative error code.

Understood. I will add appropriate error code instead returning -1.

Thanks
> 
> 
> BR,
> Jani.
> 
> 
> --
> Jani Nikula, Intel

[PATCH v9 05/17] drm/i915/vrr: Add DC Balance params to crtc_state

[Mitul Golani]

Add DC Balance params to crtc_state, also add state checker
params for related properties.

--v3:
- Seggregate crtc_state params with this patch. (Ankit)

--v4:
- Update commit message and header. (Ankit)
- Add +1 to VMIN and VMAX only when it is non-zero. (Ankit)

--v5:
- Add headers in sorted order. (Jani Nikula)

--v6:
- Add a separate function to get and check dc_balance params.
- Avoid repeatative use of MMIO read. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  7 ++++
 .../drm/i915/display/intel_display_types.h    |  7 ++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 32 +++++++++++++++++++
 3 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 04f5c488f399..db4f84cb8762 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5467,6 +5467,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
 		PIPE_CONF_CHECK_BOOL(cmrr.enable);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
 	}
 
 	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 38702a9e0f50..8eb0ace7d918 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1357,6 +1357,13 @@ struct intel_crtc_state {
 		u8 pipeline_full;
 		u16 flipline, vmin, vmax, guardband;
 		u32 vsync_end, vsync_start;
+		struct {
+			bool enable;
+			u16 vmin, vmax;
+			u16 guardband, slope;
+			u16 max_increase, max_decrease;
+			u16 vblank_target;
+		} dc_balance;
 	} vrr;
 
 	/* Content Match Refresh Rate state */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 7f0ead192777..650077eb280f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_dmc_regs.h"
 #include "intel_dp.h"
 #include "intel_psr.h"
 #include "intel_vrr.h"
@@ -785,6 +786,35 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
 	       crtc_state->vrr.flipline == crtc_state->vrr.vmin;
 }
 
+static
+void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
+{
+	u32 reg_val;
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+
+	if (!HAS_VRR_DC_BALANCE(display))
+		return;
+
+	reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
+	crtc_state->vrr.dc_balance.vmin = reg_val ? reg_val + 1 : 0;
+
+	reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe));
+	crtc_state->vrr.dc_balance.vmax = reg_val ? reg_val + 1 : 0;
+
+	crtc_state->vrr.dc_balance.guardband =
+		intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
+	crtc_state->vrr.dc_balance.max_increase =
+		intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
+	crtc_state->vrr.dc_balance.max_decrease =
+		intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
+	crtc_state->vrr.dc_balance.slope =
+		intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
+	crtc_state->vrr.dc_balance.vblank_target =
+		intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
+}
+
 void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -866,6 +896,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	else
 		crtc_state->vrr.enable = vrr_enable;
 
+	intel_vrr_get_dc_balance_config(crtc_state);
+
 	/*
 	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
 	 * Since CMRR is currently disabled, set this flag for VRR for now.
-- 
2.48.1

[PATCH v9 06/17] drm/i915/vrr: Add state dump for DC Balance params

[Mitul Golani]

Add state dump for dc balance params to track DC Balance
crtc state config.

-v1:
-- nitpick: s/Vblank target/vblank target. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index c2a6217c2262..234843b8f83a 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -303,6 +303,14 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 	drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n",
 		   intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config),
 		   intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config));
+	drm_printf(&p, "vrr: dc balance: %s, vmin: %d vmax: %d guardband: %d, slope: %d max increase: %d max decrease: %d vblank target: %d\n",
+		   str_yes_no(pipe_config->vrr.dc_balance.enable),
+		   pipe_config->vrr.dc_balance.vmin, pipe_config->vrr.dc_balance.vmax,
+		   pipe_config->vrr.dc_balance.guardband,
+		   pipe_config->vrr.dc_balance.slope,
+		   pipe_config->vrr.dc_balance.max_increase,
+		   pipe_config->vrr.dc_balance.max_decrease,
+		   pipe_config->vrr.dc_balance.vblank_target);
 
 	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&pipe_config->hw.mode));
-- 
2.48.1

[PATCH v9 07/17] drm/i915/vrr: Add compute config for DC Balance params

[Mitul Golani]

Compute DC Balance parameters and tunable params based on
experiments.

--v2:
- Document tunable params. (Ankit)

--v3:
- Add line spaces to compute config. (Ankit)
- Remove redundancy checks.

--v4:
- Separate out conpute config to separate function.
- As all the valuse are being computed in scanlines, and slope
is still in usec, convert and store it to scanlines.

--v5:
- Update and add comments for slope calculation. (Ankit)
- Update early return conditions for dc balance compute. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 46 ++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 650077eb280f..45e632e8a981 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -6,6 +6,7 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
@@ -20,6 +21,14 @@
 #define FIXED_POINT_PRECISION		100
 #define CMRR_PRECISION_TOLERANCE	10
 
+/*
+ * Tunable parameters for DC Balance correction.
+ * These are captured based on experimentations.
+ */
+#define DCB_CORRECTION_SENSITIVITY	30
+#define DCB_CORRECTION_AGGRESSIVENESS	1000
+#define DCB_BLANK_TARGET		50
+
 bool intel_vrr_is_capable(struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(connector);
@@ -342,6 +351,41 @@ int intel_vrr_compute_vmax(struct intel_connector *connector,
 	return vmax;
 }
 
+static void
+intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
+{
+	int guardband_usec, adjustment_usec;
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+	if (!(HAS_VRR_DC_BALANCE(display) && crtc_state->vrr.enable))
+		return;
+
+	crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
+	crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
+	crtc_state->vrr.dc_balance.max_increase =
+		crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+	crtc_state->vrr.dc_balance.max_decrease =
+		crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+	crtc_state->vrr.dc_balance.guardband =
+		DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
+			     DCB_CORRECTION_SENSITIVITY, 100);
+	guardband_usec =
+		intel_scanlines_to_usecs(adjusted_mode,
+					 crtc_state->vrr.dc_balance.guardband);
+	/*
+	 *  The correction_aggressiveness/100 is the number of milliseconds to
+	 *  adjust by when the balance is at twice the guardband.
+	 *  guardband_slope = correction_aggressiveness / (guardband * 100)
+	 */
+	adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS * 10;
+	crtc_state->vrr.dc_balance.slope =
+		DIV_ROUND_UP(adjustment_usec, guardband_usec);
+	crtc_state->vrr.dc_balance.vblank_target =
+		DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
+			     DCB_BLANK_TARGET, 100);
+}
+
 void
 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			 struct drm_connector_state *conn_state)
@@ -399,6 +443,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
 			 crtc_state->hw.adjusted_mode.crtc_vsync_end);
 	}
+
+	intel_vrr_dc_balance_compute_config(crtc_state);
 }
 
 static int
-- 
2.48.1

Re: [PATCH v9 07/17] drm/i915/vrr: Add compute config for DC Balance params

[Nautiyal, Ankit K]

On 11/27/2025 2:46 PM, Mitul Golani wrote:
> Compute DC Balance parameters and tunable params based on
> experiments.
>
> --v2:
> - Document tunable params. (Ankit)
>
> --v3:
> - Add line spaces to compute config. (Ankit)
> - Remove redundancy checks.
>
> --v4:
> - Separate out conpute config to separate function.
> - As all the valuse are being computed in scanlines, and slope
> is still in usec, convert and store it to scanlines.
>
> --v5:
> - Update and add comments for slope calculation. (Ankit)
> - Update early return conditions for dc balance compute. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 46 ++++++++++++++++++++++++
>   1 file changed, 46 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 650077eb280f..45e632e8a981 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -6,6 +6,7 @@
>   
>   #include <drm/drm_print.h>
>   
> +#include "intel_crtc.h"
>   #include "intel_de.h"
>   #include "intel_display_regs.h"
>   #include "intel_display_types.h"
> @@ -20,6 +21,14 @@
>   #define FIXED_POINT_PRECISION		100
>   #define CMRR_PRECISION_TOLERANCE	10
>   
> +/*
> + * Tunable parameters for DC Balance correction.
> + * These are captured based on experimentations.
> + */
> +#define DCB_CORRECTION_SENSITIVITY	30
> +#define DCB_CORRECTION_AGGRESSIVENESS	1000
> +#define DCB_BLANK_TARGET		50
> +
>   bool intel_vrr_is_capable(struct intel_connector *connector)
>   {
>   	struct intel_display *display = to_intel_display(connector);
> @@ -342,6 +351,41 @@ int intel_vrr_compute_vmax(struct intel_connector *connector,
>   	return vmax;
>   }
>   
> +static void
> +intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
> +{
> +	int guardband_usec, adjustment_usec;
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> +	if (!(HAS_VRR_DC_BALANCE(display) && crtc_state->vrr.enable))
> +		return;

Can simplify to:

if (!HAS_VRR_DC_BALANCE(display) || !crtc_state->vrr.enable)

     return;

IMO, if (notA or not B) is more readable than: if not (A and B)


> +
> +	crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
> +	crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
> +	crtc_state->vrr.dc_balance.max_increase =
> +		crtc_state->vrr.vmax - crtc_state->vrr.vmin;
> +	crtc_state->vrr.dc_balance.max_decrease =
> +		crtc_state->vrr.vmax - crtc_state->vrr.vmin;
> +	crtc_state->vrr.dc_balance.guardband =
> +		DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
> +			     DCB_CORRECTION_SENSITIVITY, 100);
> +	guardband_usec =
> +		intel_scanlines_to_usecs(adjusted_mode,
> +					 crtc_state->vrr.dc_balance.guardband);
> +	/*
> +	 *  The correction_aggressiveness/100 is the number of milliseconds to
> +	 *  adjust by when the balance is at twice the guardband.
> +	 *  guardband_slope = correction_aggressiveness / (guardband * 100)
> +	 */
> +	adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS * 10;

The current value represents milliseconds x 100, so 10 msecs becomes 1000.
This scaling can be confusing compared to working directly with 
microseconds or milliseconds.
IMO ideally we could define the correction aggressiveness in either 
usecs or msecs for clarity, but that might make it harder to match 
values from the spec.
If this factor changes in the future (e.g., to 400 or 1400 based on 
experimentation), we might need to recalculate if we switch to pure 
msecs or usecs.

However, I think it would still be clearer if we rename the macro to:
#define DCB_CORRECTION_AGGRESSIVENESS_msecs_X100 1000

Then, when we use:
adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS_msecs_X100 * 10;

it becomes more intuitive because we can see the conversion: msecs x 100 
x 10 -> usecs


Regards,

Ankit

> +	crtc_state->vrr.dc_balance.slope =
> +		DIV_ROUND_UP(adjustment_usec, guardband_usec);
> +	crtc_state->vrr.dc_balance.vblank_target =
> +		DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
> +			     DCB_BLANK_TARGET, 100);
> +}
> +
>   void
>   intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   			 struct drm_connector_state *conn_state)
> @@ -399,6 +443,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   			(crtc_state->hw.adjusted_mode.crtc_vtotal -
>   			 crtc_state->hw.adjusted_mode.crtc_vsync_end);
>   	}
> +
> +	intel_vrr_dc_balance_compute_config(crtc_state);
>   }
>   
>   static int

Re: [PATCH v9 07/17] drm/i915/vrr: Add compute config for DC Balance params

[Nautiyal, Ankit K]

On 11/28/2025 6:40 PM, Nautiyal, Ankit K wrote:
>
> On 11/27/2025 2:46 PM, Mitul Golani wrote:
>> Compute DC Balance parameters and tunable params based on
>> experiments.
>>
>> --v2:
>> - Document tunable params. (Ankit)
>>
>> --v3:
>> - Add line spaces to compute config. (Ankit)
>> - Remove redundancy checks.
>>
>> --v4:
>> - Separate out conpute config to separate function.
>> - As all the valuse are being computed in scanlines, and slope
>> is still in usec, convert and store it to scanlines.
>>
>> --v5:
>> - Update and add comments for slope calculation. (Ankit)
>> - Update early return conditions for dc balance compute. (Ankit)
>>
>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 46 ++++++++++++++++++++++++
>>   1 file changed, 46 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 650077eb280f..45e632e8a981 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -6,6 +6,7 @@
>>     #include <drm/drm_print.h>
>>   +#include "intel_crtc.h"
>>   #include "intel_de.h"
>>   #include "intel_display_regs.h"
>>   #include "intel_display_types.h"
>> @@ -20,6 +21,14 @@
>>   #define FIXED_POINT_PRECISION        100
>>   #define CMRR_PRECISION_TOLERANCE    10
>>   +/*
>> + * Tunable parameters for DC Balance correction.
>> + * These are captured based on experimentations.
>> + */
>> +#define DCB_CORRECTION_SENSITIVITY    30
>> +#define DCB_CORRECTION_AGGRESSIVENESS    1000
>> +#define DCB_BLANK_TARGET        50
>> +
>>   bool intel_vrr_is_capable(struct intel_connector *connector)
>>   {
>>       struct intel_display *display = to_intel_display(connector);
>> @@ -342,6 +351,41 @@ int intel_vrr_compute_vmax(struct 
>> intel_connector *connector,
>>       return vmax;
>>   }
>>   +static void
>> +intel_vrr_dc_balance_compute_config(struct intel_crtc_state 
>> *crtc_state)
>> +{
>> +    int guardband_usec, adjustment_usec;
>> +    struct intel_display *display = to_intel_display(crtc_state);
>> +    struct drm_display_mode *adjusted_mode = 
>> &crtc_state->hw.adjusted_mode;
>> +
>> +    if (!(HAS_VRR_DC_BALANCE(display) && crtc_state->vrr.enable))
>> +        return;
>
> Can simplify to:
>
> if (!HAS_VRR_DC_BALANCE(display) || !crtc_state->vrr.enable)
>
>     return;


I think we can introduce intel_vrr_dc_balance_possible() here itself, 
rather than later.

So:

if (!intel_vrr_dc_balance_possible() || !crtc_state->vrr.enable)

     return;


Regards,

Ankit

>
> IMO, if (notA or not B) is more readable than: if not (A and B)
>
>
>> +
>> +    crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
>> +    crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
>> +    crtc_state->vrr.dc_balance.max_increase =
>> +        crtc_state->vrr.vmax - crtc_state->vrr.vmin;
>> +    crtc_state->vrr.dc_balance.max_decrease =
>> +        crtc_state->vrr.vmax - crtc_state->vrr.vmin;
>> +    crtc_state->vrr.dc_balance.guardband =
>> +        DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
>> +                 DCB_CORRECTION_SENSITIVITY, 100);
>> +    guardband_usec =
>> +        intel_scanlines_to_usecs(adjusted_mode,
>> +                     crtc_state->vrr.dc_balance.guardband);
>> +    /*
>> +     *  The correction_aggressiveness/100 is the number of 
>> milliseconds to
>> +     *  adjust by when the balance is at twice the guardband.
>> +     *  guardband_slope = correction_aggressiveness / (guardband * 100)
>> +     */
>> +    adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS * 10;
>
> The current value represents milliseconds x 100, so 10 msecs becomes 
> 1000.
> This scaling can be confusing compared to working directly with 
> microseconds or milliseconds.
> IMO ideally we could define the correction aggressiveness in either 
> usecs or msecs for clarity, but that might make it harder to match 
> values from the spec.
> If this factor changes in the future (e.g., to 400 or 1400 based on 
> experimentation), we might need to recalculate if we switch to pure 
> msecs or usecs.
>
> However, I think it would still be clearer if we rename the macro to:
> #define DCB_CORRECTION_AGGRESSIVENESS_msecs_X100 1000
>
> Then, when we use:
> adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS_msecs_X100 * 10;
>
> it becomes more intuitive because we can see the conversion: msecs x 
> 100 x 10 -> usecs
>
>
> Regards,
>
> Ankit
>
>> +    crtc_state->vrr.dc_balance.slope =
>> +        DIV_ROUND_UP(adjustment_usec, guardband_usec);
>> +    crtc_state->vrr.dc_balance.vblank_target =
>> +        DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
>> +                 DCB_BLANK_TARGET, 100);
>> +}
>> +
>>   void
>>   intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>>                struct drm_connector_state *conn_state)
>> @@ -399,6 +443,8 @@ intel_vrr_compute_config(struct intel_crtc_state 
>> *crtc_state,
>>               (crtc_state->hw.adjusted_mode.crtc_vtotal -
>>                crtc_state->hw.adjusted_mode.crtc_vsync_end);
>>       }
>> +
>> +    intel_vrr_dc_balance_compute_config(crtc_state);
>>   }
>>     static int

RE: [PATCH v9 07/17] drm/i915/vrr: Add compute config for DC Balance params

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: 28 November 2025 19:00
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; ville.syrjala@linux.intel.com
> Subject: Re: [PATCH v9 07/17] drm/i915/vrr: Add compute config for DC
> Balance params
> 
> 
> On 11/28/2025 6:40 PM, Nautiyal, Ankit K wrote:
> >
> > On 11/27/2025 2:46 PM, Mitul Golani wrote:
> >> Compute DC Balance parameters and tunable params based on
> >> experiments.
> >>
> >> --v2:
> >> - Document tunable params. (Ankit)
> >>
> >> --v3:
> >> - Add line spaces to compute config. (Ankit)
> >> - Remove redundancy checks.
> >>
> >> --v4:
> >> - Separate out conpute config to separate function.
> >> - As all the valuse are being computed in scanlines, and slope is
> >> still in usec, convert and store it to scanlines.
> >>
> >> --v5:
> >> - Update and add comments for slope calculation. (Ankit)
> >> - Update early return conditions for dc balance compute. (Ankit)
> >>
> >> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_vrr.c | 46
> >> ++++++++++++++++++++++++
> >>   1 file changed, 46 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> >> b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> index 650077eb280f..45e632e8a981 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> @@ -6,6 +6,7 @@
> >>     #include <drm/drm_print.h>
> >>   +#include "intel_crtc.h"
> >>   #include "intel_de.h"
> >>   #include "intel_display_regs.h"
> >>   #include "intel_display_types.h"
> >> @@ -20,6 +21,14 @@
> >>   #define FIXED_POINT_PRECISION        100
> >>   #define CMRR_PRECISION_TOLERANCE    10
> >>   +/*
> >> + * Tunable parameters for DC Balance correction.
> >> + * These are captured based on experimentations.
> >> + */
> >> +#define DCB_CORRECTION_SENSITIVITY    30 #define
> >> +DCB_CORRECTION_AGGRESSIVENESS    1000 #define
> DCB_BLANK_TARGET
> >> +50
> >> +
> >>   bool intel_vrr_is_capable(struct intel_connector *connector)
> >>   {
> >>       struct intel_display *display = to_intel_display(connector); @@
> >> -342,6 +351,41 @@ int intel_vrr_compute_vmax(struct intel_connector
> >> *connector,
> >>       return vmax;
> >>   }
> >>   +static void
> >> +intel_vrr_dc_balance_compute_config(struct intel_crtc_state
> >> *crtc_state)
> >> +{
> >> +    int guardband_usec, adjustment_usec;
> >> +    struct intel_display *display = to_intel_display(crtc_state);
> >> +    struct drm_display_mode *adjusted_mode =
> >> &crtc_state->hw.adjusted_mode;
> >> +
> >> +    if (!(HAS_VRR_DC_BALANCE(display) && crtc_state->vrr.enable))
> >> +        return;
> >
> > Can simplify to:
> >
> > if (!HAS_VRR_DC_BALANCE(display) || !crtc_state->vrr.enable)
> >
> >     return;
> 
> 
> I think we can introduce intel_vrr_dc_balance_possible() here itself, rather
> than later.
> 
> So:
> 
> if (!intel_vrr_dc_balance_possible() || !crtc_state->vrr.enable)
> 
>      return;
> 
> 
> Regards,
> 
> Ankit
> 
> >
> > IMO, if (notA or not B) is more readable than: if not (A and B)

Sure, I will add in next revision.

Thanks.


> >
> >
> >> +
> >> +    crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
> >> +    crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
> >> +    crtc_state->vrr.dc_balance.max_increase =
> >> +        crtc_state->vrr.vmax - crtc_state->vrr.vmin;
> >> +    crtc_state->vrr.dc_balance.max_decrease =
> >> +        crtc_state->vrr.vmax - crtc_state->vrr.vmin;
> >> +    crtc_state->vrr.dc_balance.guardband =
> >> +        DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
> >> +                 DCB_CORRECTION_SENSITIVITY, 100);
> >> +    guardband_usec =
> >> +        intel_scanlines_to_usecs(adjusted_mode,
> >> +                     crtc_state->vrr.dc_balance.guardband);
> >> +    /*
> >> +     *  The correction_aggressiveness/100 is the number of
> >> milliseconds to
> >> +     *  adjust by when the balance is at twice the guardband.
> >> +     *  guardband_slope = correction_aggressiveness / (guardband *
> >> +100)
> >> +     */
> >> +    adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS * 10;
> >
> > The current value represents milliseconds x 100, so 10 msecs becomes
> > 1000.
> > This scaling can be confusing compared to working directly with
> > microseconds or milliseconds.
> > IMO ideally we could define the correction aggressiveness in either
> > usecs or msecs for clarity, but that might make it harder to match
> > values from the spec.
> > If this factor changes in the future (e.g., to 400 or 1400 based on
> > experimentation), we might need to recalculate if we switch to pure
> > msecs or usecs.
> >
> > However, I think it would still be clearer if we rename the macro to:
> > #define DCB_CORRECTION_AGGRESSIVENESS_msecs_X100 1000
> >
> > Then, when we use:
> > adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS_msecs_X100 * 10;
> >
> > it becomes more intuitive because we can see the conversion: msecs x
> > 100 x 10 -> usecs

Thanks for the suggestion. I agree that clarifying the units helps readability.
I’ve kept the macro name as DCB_CORRECTION_AGGRESSIVENESS and added a clear unit comment (/* ms × 100; 10 ms */) instead of renaming it to include _msecs_X100, this keeps the name consistent with surrounding defines while still making the unit explicit.

> >
> >
> > Regards,
> >
> > Ankit
> >
> >> +    crtc_state->vrr.dc_balance.slope =
> >> +        DIV_ROUND_UP(adjustment_usec, guardband_usec);
> >> +    crtc_state->vrr.dc_balance.vblank_target =
> >> +        DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
> >> +                 DCB_BLANK_TARGET, 100); }
> >> +
> >>   void
> >>   intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> >>                struct drm_connector_state *conn_state) @@ -399,6
> >> +443,8 @@ intel_vrr_compute_config(struct intel_crtc_state
> >> *crtc_state,
> >>               (crtc_state->hw.adjusted_mode.crtc_vtotal -
> >>                crtc_state->hw.adjusted_mode.crtc_vsync_end);
> >>       }
> >> +
> >> +    intel_vrr_dc_balance_compute_config(crtc_state);
> >>   }
> >>     static int

[PATCH v9 08/17] drm/i915/vrr: Add function to reset DC balance accumulated params

[Mitul Golani]

Add function which resets all accumulated DC Balance parameters
whenever adaptive mode of VRR goes off. This helps to give a
fresh start when VRR is re-enabled.

--v2:
- Typo, change crtc_state to old_crtc_state. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c     | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h     |  3 +++
 3 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index db4f84cb8762..d41ab965c013 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1158,6 +1158,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 
 	if (intel_crtc_vrr_disabling(state, crtc)) {
 		intel_vrr_disable(old_crtc_state);
+		intel_vrr_dcb_reset(old_crtc_state, crtc);
 		intel_crtc_update_active_timings(old_crtc_state, false);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 45e632e8a981..ff65c1167e1b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -632,6 +632,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
 }
 
+void
+intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
+		    struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(old_crtc_state);
+	enum pipe pipe = crtc->pipe;
+
+	if (!old_crtc_state->vrr.dc_balance.enable)
+		return;
+
+	intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
+}
+
 void intel_vrr_send_push(struct intel_dsb *dsb,
 			 const struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 66fb9ad846f2..d40ed5504180 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -11,6 +11,7 @@
 struct drm_connector_state;
 struct intel_atomic_state;
 struct intel_connector;
+struct intel_crtc;
 struct intel_crtc_state;
 struct intel_dsb;
 struct intel_display;
@@ -39,6 +40,8 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
+void intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
+			 struct intel_crtc *crtc);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
-- 
2.48.1

Re: [PATCH v9 08/17] drm/i915/vrr: Add function to reset DC balance accumulated params

[Nautiyal, Ankit K]

On 11/27/2025 2:46 PM, Mitul Golani wrote:
> Add function which resets all accumulated DC Balance parameters
> whenever adaptive mode of VRR goes off. This helps to give a
> fresh start when VRR is re-enabled.
>
> --v2:
> - Typo, change crtc_state to old_crtc_state. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_display.c |  1 +
>   drivers/gpu/drm/i915/display/intel_vrr.c     | 13 +++++++++++++
>   drivers/gpu/drm/i915/display/intel_vrr.h     |  3 +++
>   3 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index db4f84cb8762..d41ab965c013 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1158,6 +1158,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>   
>   	if (intel_crtc_vrr_disabling(state, crtc)) {
>   		intel_vrr_disable(old_crtc_state);
> +		intel_vrr_dcb_reset(old_crtc_state, crtc);
>   		intel_crtc_update_active_timings(old_crtc_state, false);
>   	}
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 45e632e8a981..ff65c1167e1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -632,6 +632,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>   }
>   
> +void
> +intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
> +		    struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(old_crtc_state);
> +	enum pipe pipe = crtc->pipe;
> +
> +	if (!old_crtc_state->vrr.dc_balance.enable)
> +		return;
> +
> +	intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
> +}
> +
>   void intel_vrr_send_push(struct intel_dsb *dsb,
>   			 const struct intel_crtc_state *crtc_state)
>   {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 66fb9ad846f2..d40ed5504180 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -11,6 +11,7 @@
>   struct drm_connector_state;
>   struct intel_atomic_state;
>   struct intel_connector;
> +struct intel_crtc;
>   struct intel_crtc_state;
>   struct intel_dsb;
>   struct intel_display;
> @@ -39,6 +40,8 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
>   void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
>   void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
>   void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
> +void intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
> +			 struct intel_crtc *crtc);
>   bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
>   int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
>   int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);

[PATCH v9 09/17] drm/i915/display: Add DC Balance flip count operations

[Mitul Golani]

Track dc balance flip count with params per crtc. Increment
DC Balance Flip count before every flip to indicate DMC
firmware about new flip occurrence which needs to be adjusted
for dc balancing. This is tracked separately from legacy
FLIP_COUNT register also Reset DC balance flip count value
while disabling VRR adaptive mode, this is to start with
fresh counts when VRR adaptive refresh mode is triggered again.

--v2:
- Call during intel_update_crtc.(Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c      |  3 +++
 .../gpu/drm/i915/display/intel_display_types.h    |  4 ++++
 drivers/gpu/drm/i915/display/intel_vrr.c          | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h          |  2 ++
 4 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d41ab965c013..1269f841d48b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6863,6 +6863,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 		intel_crtc_update_active_timings(new_crtc_state,
 						 new_crtc_state->vrr.enable);
 
+	if (new_crtc_state->vrr.dc_balance.enable)
+		intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
+
 	/*
 	 * We usually enable FIFO underrun interrupts as part of the
 	 * CRTC enable sequence during modesets.  But when we inherit a
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8eb0ace7d918..740c5fc9fe1e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1501,6 +1501,10 @@ struct intel_crtc {
 		struct intel_link_m_n m_n, m2_n2;
 	} drrs;
 
+	struct {
+		u64 flip_count;
+	} dc_balance;
+
 	int scanline_offset;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index ff65c1167e1b..411ae5da3824 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -632,6 +632,20 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
 }
 
+void
+intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
+				   struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum pipe pipe = crtc->pipe;
+
+	if (!crtc_state->vrr.dc_balance.enable)
+		return;
+
+	intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe),
+		       ++crtc->dc_balance.flip_count);
+}
+
 void
 intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
 		    struct intel_crtc *crtc)
@@ -642,6 +656,7 @@ intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
 	if (!old_crtc_state->vrr.dc_balance.enable)
 		return;
 
+	intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);
 	intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index d40ed5504180..bedcc8c4bff2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -29,6 +29,8 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
 			 const struct intel_crtc_state *crtc_state);
 void intel_vrr_check_push_sent(struct intel_dsb *dsb,
 			       const struct intel_crtc_state *crtc_state);
+void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
+					struct intel_crtc *crtc);
 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
 void intel_vrr_get_config(struct intel_crtc_state *crtc_state);
-- 
2.48.1

Re: [PATCH v9 09/17] drm/i915/display: Add DC Balance flip count operations

[Nautiyal, Ankit K]

On 11/27/2025 2:46 PM, Mitul Golani wrote:
> Track dc balance flip count with params per crtc. Increment
> DC Balance Flip count before every flip to indicate DMC
> firmware about new flip occurrence which needs to be adjusted
> for dc balancing. This is tracked separately from legacy
> FLIP_COUNT register also Reset DC balance flip count value
> while disabling VRR adaptive mode, this is to start with
> fresh counts when VRR adaptive refresh mode is triggered again.
>
> --v2:
> - Call during intel_update_crtc.(Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_display.c      |  3 +++
>   .../gpu/drm/i915/display/intel_display_types.h    |  4 ++++
>   drivers/gpu/drm/i915/display/intel_vrr.c          | 15 +++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vrr.h          |  2 ++
>   4 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d41ab965c013..1269f841d48b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6863,6 +6863,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>   		intel_crtc_update_active_timings(new_crtc_state,
>   						 new_crtc_state->vrr.enable);
>   
> +	if (new_crtc_state->vrr.dc_balance.enable)
> +		intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
> +
>   	/*
>   	 * We usually enable FIFO underrun interrupts as part of the
>   	 * CRTC enable sequence during modesets.  But when we inherit a
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8eb0ace7d918..740c5fc9fe1e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1501,6 +1501,10 @@ struct intel_crtc {
>   		struct intel_link_m_n m_n, m2_n2;
>   	} drrs;
>   
> +	struct {
> +		u64 flip_count;
> +	} dc_balance;
> +
>   	int scanline_offset;
>   
>   	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index ff65c1167e1b..411ae5da3824 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -632,6 +632,20 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>   }
>   
> +void
> +intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
> +				   struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum pipe pipe = crtc->pipe;
> +
> +	if (!crtc_state->vrr.dc_balance.enable)
> +		return;
> +
> +	intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe),
> +		       ++crtc->dc_balance.flip_count);
> +}
> +
>   void
>   intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
>   		    struct intel_crtc *crtc)
> @@ -642,6 +656,7 @@ intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
>   	if (!old_crtc_state->vrr.dc_balance.enable)
>   		return;
>   
> +	intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);
>   	intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
>   }
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index d40ed5504180..bedcc8c4bff2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -29,6 +29,8 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
>   			 const struct intel_crtc_state *crtc_state);
>   void intel_vrr_check_push_sent(struct intel_dsb *dsb,
>   			       const struct intel_crtc_state *crtc_state);
> +void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
> +					struct intel_crtc *crtc);
>   bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
>   void intel_vrr_get_config(struct intel_crtc_state *crtc_state);

[PATCH v9 10/17] drm/i915/vrr: Write DC balance params to hw registers

[Mitul Golani]

Write DC Balance parameters to hw registers.

--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)

--v3:
- Write registers at compute config.
- Update condition for write.

--v4:
- Address issue with state checker.

--v5:
- Initialise some more dc balance register while enabling VRR.

--v6:
- FLIPLINE_CFG need to be configure at last, as it is double buffer
arming point.

--v7:
- Initialise and reset live value of vmax and vmin as well.

--v8:
- Add separate functions while writing hw registers. (Ankit)

--v9:
- Add DC Balance counter enable bit to this patch. (Ankit)

--v10:
- Add rigister writes to vrr_enable/disable. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 76 ++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 411ae5da3824..11f06a5b854a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -767,6 +767,80 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_hw_flipline(crtc_state) - 1);
 }
 
+static void
+intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+
+	if (!crtc_state->vrr.dc_balance.enable)
+		return;
+
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
+		       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder),
+		       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+	intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
+		       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+	intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder),
+		       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
+		       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder),
+		       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),
+		       VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
+		       VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
+	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
+		       crtc_state->vrr.dc_balance.vmin - 1);
+	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
+		       crtc_state->vrr.dc_balance.vmax - 1);
+	intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
+		       crtc_state->vrr.dc_balance.max_increase);
+	intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
+		       crtc_state->vrr.dc_balance.max_decrease);
+	intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
+		       crtc_state->vrr.dc_balance.guardband);
+	intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
+		       crtc_state->vrr.dc_balance.slope);
+	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
+		       crtc_state->vrr.dc_balance.vblank_target);
+	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
+		       ADAPTIVE_SYNC_COUNTER_EN);
+}
+
+static void
+intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_display *display = to_intel_display(old_crtc_state);
+	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+
+	if (!old_crtc_state->vrr.dc_balance.enable)
+		return;
+
+	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
+	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
+}
+
 static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 				bool cmrr_enable)
 {
@@ -813,6 +887,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 		return;
 
 	intel_vrr_set_vrr_timings(crtc_state);
+	intel_vrr_enable_dc_balancing(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
 		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
@@ -828,6 +903,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	if (!intel_vrr_always_use_vrr_tg(display))
 		intel_vrr_tg_disable(old_crtc_state);
 
+	intel_vrr_disable_dc_balancing(old_crtc_state);
 	intel_vrr_set_fixed_rr_timings(old_crtc_state);
 }
 
-- 
2.48.1

Re: [PATCH v9 10/17] drm/i915/vrr: Write DC balance params to hw registers

[Nautiyal, Ankit K]

On 11/27/2025 2:46 PM, Mitul Golani wrote:
> Write DC Balance parameters to hw registers.
>
> --v2:
> - Update commit header.
> - Separate crtc_state params from this patch. (Ankit)
>
> --v3:
> - Write registers at compute config.
> - Update condition for write.
>
> --v4:
> - Address issue with state checker.
>
> --v5:
> - Initialise some more dc balance register while enabling VRR.
>
> --v6:
> - FLIPLINE_CFG need to be configure at last, as it is double buffer
> arming point.
>
> --v7:
> - Initialise and reset live value of vmax and vmin as well.
>
> --v8:
> - Add separate functions while writing hw registers. (Ankit)
>
> --v9:
> - Add DC Balance counter enable bit to this patch. (Ankit)
>
> --v10:
> - Add rigister writes to vrr_enable/disable. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 76 ++++++++++++++++++++++++
>   1 file changed, 76 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 411ae5da3824..11f06a5b854a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -767,6 +767,80 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
>   		       intel_vrr_hw_flipline(crtc_state) - 1);
>   }
>   
> +static void
> +intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	if (!crtc_state->vrr.dc_balance.enable)
> +		return;
> +
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
> +		       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder),
> +		       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
> +		       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder),
> +		       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
> +		       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder),
> +		       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),
> +		       VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
> +		       VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
> +	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
> +		       crtc_state->vrr.dc_balance.vmin - 1);
> +	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
> +		       crtc_state->vrr.dc_balance.vmax - 1);
> +	intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
> +		       crtc_state->vrr.dc_balance.max_increase);
> +	intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
> +		       crtc_state->vrr.dc_balance.max_decrease);
> +	intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
> +		       crtc_state->vrr.dc_balance.guardband);
> +	intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
> +		       crtc_state->vrr.dc_balance.slope);
> +	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
> +		       crtc_state->vrr.dc_balance.vblank_target);
> +	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> +		       ADAPTIVE_SYNC_COUNTER_EN);
> +}
> +
> +static void
> +intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(old_crtc_state);
> +	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	if (!old_crtc_state->vrr.dc_balance.enable)
> +		return;
> +
> +	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
> +	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
> +}
> +
>   static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
>   				bool cmrr_enable)
>   {
> @@ -813,6 +887,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   		return;
>   
>   	intel_vrr_set_vrr_timings(crtc_state);
> +	intel_vrr_enable_dc_balancing(crtc_state);
>   
>   	if (!intel_vrr_always_use_vrr_tg(display))
>   		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
> @@ -828,6 +903,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   	if (!intel_vrr_always_use_vrr_tg(display))
>   		intel_vrr_tg_disable(old_crtc_state);
>   
> +	intel_vrr_disable_dc_balancing(old_crtc_state);
>   	intel_vrr_set_fixed_rr_timings(old_crtc_state);
>   }
>   

Re: [PATCH v9 10/17] drm/i915/vrr: Write DC balance params to hw registers

[Nautiyal, Ankit K]

On 11/27/2025 2:46 PM, Mitul Golani wrote:
> Write DC Balance parameters to hw registers.
>
> --v2:
> - Update commit header.
> - Separate crtc_state params from this patch. (Ankit)
>
> --v3:
> - Write registers at compute config.
> - Update condition for write.
>
> --v4:
> - Address issue with state checker.
>
> --v5:
> - Initialise some more dc balance register while enabling VRR.
>
> --v6:
> - FLIPLINE_CFG need to be configure at last, as it is double buffer
> arming point.
>
> --v7:
> - Initialise and reset live value of vmax and vmin as well.
>
> --v8:
> - Add separate functions while writing hw registers. (Ankit)
>
> --v9:
> - Add DC Balance counter enable bit to this patch. (Ankit)
>
> --v10:
> - Add rigister writes to vrr_enable/disable. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 76 ++++++++++++++++++++++++
>   1 file changed, 76 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 411ae5da3824..11f06a5b854a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -767,6 +767,80 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
>   		       intel_vrr_hw_flipline(crtc_state) - 1);
>   }
>   
> +static void
> +intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	if (!crtc_state->vrr.dc_balance.enable)
> +		return;
> +
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
> +		       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder),
> +		       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
> +		       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder),
> +		       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
> +		       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder),
> +		       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),
> +		       VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
> +		       VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
> +	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
> +		       crtc_state->vrr.dc_balance.vmin - 1);
> +	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
> +		       crtc_state->vrr.dc_balance.vmax - 1);
> +	intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
> +		       crtc_state->vrr.dc_balance.max_increase);
> +	intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
> +		       crtc_state->vrr.dc_balance.max_decrease);
> +	intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
> +		       crtc_state->vrr.dc_balance.guardband);
> +	intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
> +		       crtc_state->vrr.dc_balance.slope);
> +	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
> +		       crtc_state->vrr.dc_balance.vblank_target);
> +	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> +		       ADAPTIVE_SYNC_COUNTER_EN);
> +}
> +
> +static void
> +intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(old_crtc_state);
> +	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	if (!old_crtc_state->vrr.dc_balance.enable)
> +		return;
> +
> +	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
> +	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
> +	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
> +}
> +
>   static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
>   				bool cmrr_enable)
>   {
> @@ -813,6 +887,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   		return;
>   
>   	intel_vrr_set_vrr_timings(crtc_state);
> +	intel_vrr_enable_dc_balancing(crtc_state);
>   
>   	if (!intel_vrr_always_use_vrr_tg(display))
>   		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
> @@ -828,6 +903,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   	if (!intel_vrr_always_use_vrr_tg(display))
>   		intel_vrr_tg_disable(old_crtc_state);
>   
> +	intel_vrr_disable_dc_balancing(old_crtc_state);
>   	intel_vrr_set_fixed_rr_timings(old_crtc_state);
>   }
>   

[PATCH v9 11/17] drm/i915/vblank: Extract vrr_vblank_start()

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Initialise delayed vblank position for evasion logic.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 671f357c6563..de20baeb9d99 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -652,6 +652,14 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 	return pre_commit_crtc_state(old_crtc_state, new_crtc_state);
 }
 
+static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	if (intel_vrr_is_push_sent(crtc_state))
+		return intel_vrr_vmin_vblank_start(crtc_state);
+	else
+		return intel_vrr_vmax_vblank_start(crtc_state);
+}
+
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 			     const struct intel_crtc_state *new_crtc_state,
 			     struct intel_vblank_evade_ctx *evade)
@@ -678,10 +686,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
 			    new_crtc_state->update_m_n || new_crtc_state->update_lrr);
 
-		if (intel_vrr_is_push_sent(crtc_state))
-			evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
-		else
-			evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
+		evade->vblank_start = vrr_vblank_start(crtc_state);
 
 		vblank_delay = crtc_state->set_context_latency;
 	} else {
-- 
2.48.1

[PATCH v9 12/17] drm/i915/vrr: Implement vblank evasion with DC balancing

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add vblank evasion logic when vrr is already enabled along with
dc balance is computed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c    | 31 ++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 26 +++++++++++++++--
 2 files changed, 53 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 4ad4efbf9253..83130bb74aa9 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -704,7 +704,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
 	if (crtc_state->has_psr)
 		intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
 
-	if (pre_commit_is_vrr_active(state, crtc)) {
+	if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
+		int vblank_delay = crtc_state->set_context_latency;
+		int vmin_vblank_start, vmax_vblank_start;
+
+		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+
+		if (vmin_vblank_start >= 0) {
+			end = vmin_vblank_start;
+			start = end - vblank_delay - latency;
+			intel_dsb_wait_scanline_out(state, dsb, start, end);
+		}
+
+		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+		if (vmax_vblank_start >= 0) {
+			end = vmax_vblank_start;
+			start = end - vblank_delay - latency;
+			intel_dsb_wait_scanline_out(state, dsb, start, end);
+		}
+
+		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+		end = vmin_vblank_start;
+		start = end - vblank_delay - latency;
+		intel_dsb_wait_scanline_out(state, dsb, start, end);
+
+		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+		end = vmax_vblank_start;
+		start = end - vblank_delay - latency;
+		intel_dsb_wait_scanline_out(state, dsb, start, end);
+	} else if (pre_commit_is_vrr_active(state, crtc)) {
 		int vblank_delay = crtc_state->set_context_latency;
 
 		end = intel_vrr_vmin_vblank_start(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index de20baeb9d99..df5879489963 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -654,10 +654,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 
 static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	if (intel_vrr_is_push_sent(crtc_state))
-		return intel_vrr_vmin_vblank_start(crtc_state);
+	bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
+	int vblank_start;
+
+	if (!crtc_state->vrr.dc_balance.enable) {
+		if (is_push_sent)
+			return intel_vrr_vmin_vblank_start(crtc_state);
+		else
+			return intel_vrr_vmax_vblank_start(crtc_state);
+	}
+
+	if (is_push_sent)
+		vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
 	else
-		return intel_vrr_vmax_vblank_start(crtc_state);
+		vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+	if (vblank_start >= 0)
+		return vblank_start;
+
+	if (is_push_sent)
+		vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+	else
+		vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+
+	return vblank_start;
 }
 
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
-- 
2.48.1

[PATCH v9 13/17] drm/i915/display: Wait for VRR PUSH status update

[Mitul Golani]

After VRR Push is sent, need to wait till flipline decision boundary
to get Push bit to get cleared.

--v2:
- Adjust delays to vrr vmin vblank delays. (Ankit)

--v3:
- Change intel_vrr_vmin_safe_window_end() so that
intel_dsb_wait_for_delayed_vblank() uses correct delay. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 11f06a5b854a..e5cff3892cb1 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -1081,10 +1081,23 @@ int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
 		return crtc_state->hw.adjusted_mode.crtc_vdisplay;
 }
 
+static int
+intel_vrr_dcb_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	return (intel_vrr_dcb_vmin_vblank_start_next(crtc_state) < 0) ?
+		intel_vrr_dcb_vmin_vblank_start_final(crtc_state) :
+		intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+}
+
 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
 {
-	return intel_vrr_vmin_vblank_start(crtc_state) -
-	       crtc_state->set_context_latency;
+	if (crtc_state->vrr.dc_balance.enable) {
+		return intel_vrr_dcb_vmin_vblank_start(crtc_state) -
+			crtc_state->set_context_latency;
+	} else {
+		return intel_vrr_vmin_vblank_start(crtc_state) -
+			crtc_state->set_context_latency;
+	}
 }
 
 int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
-- 
2.48.1

Re: [PATCH v9 13/17] drm/i915/display: Wait for VRR PUSH status update

[Nautiyal, Ankit K]

On 11/27/2025 2:46 PM, Mitul Golani wrote:
> After VRR Push is sent, need to wait till flipline decision boundary
> to get Push bit to get cleared.
>
> --v2:
> - Adjust delays to vrr vmin vblank delays. (Ankit)
>
> --v3:
> - Change intel_vrr_vmin_safe_window_end() so that
> intel_dsb_wait_for_delayed_vblank() uses correct delay. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++++++++--
>   1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 11f06a5b854a..e5cff3892cb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -1081,10 +1081,23 @@ int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
>   		return crtc_state->hw.adjusted_mode.crtc_vdisplay;
>   }
>   
> +static int
> +intel_vrr_dcb_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
> +{
> +	return (intel_vrr_dcb_vmin_vblank_start_next(crtc_state) < 0) ?
> +		intel_vrr_dcb_vmin_vblank_start_final(crtc_state) :
> +		intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
> +}
> +
>   int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
>   {
> -	return intel_vrr_vmin_vblank_start(crtc_state) -
> -	       crtc_state->set_context_latency;
> +	if (crtc_state->vrr.dc_balance.enable) {
> +		return intel_vrr_dcb_vmin_vblank_start(crtc_state) -
> +			crtc_state->set_context_latency;
> +	} else {
> +		return intel_vrr_vmin_vblank_start(crtc_state) -
> +			crtc_state->set_context_latency;
> +	}
>   }


This can be simplified to:

  int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state 
*crtc_state)
  {
     int vmin_vblank_start = crtc_state->vrr.dc_balance.enable ?
                 intel_vrr_dcb_vmin_vblank_start(crtc_state) :
                 intel_vrr_vmin_vblank_start(crtc_state);

     return vmin_vblank_start - crtc_state->set_context_latency;
  }

Regards,

Ankit

>   
>   int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)

RE: [PATCH v9 13/17] drm/i915/display: Wait for VRR PUSH status update

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: 28 November 2025 18:52
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; ville.syrjala@linux.intel.com
> Subject: Re: [PATCH v9 13/17] drm/i915/display: Wait for VRR PUSH status
> update
> 
> 
> On 11/27/2025 2:46 PM, Mitul Golani wrote:
> > After VRR Push is sent, need to wait till flipline decision boundary
> > to get Push bit to get cleared.
> >
> > --v2:
> > - Adjust delays to vrr vmin vblank delays. (Ankit)
> >
> > --v3:
> > - Change intel_vrr_vmin_safe_window_end() so that
> > intel_dsb_wait_for_delayed_vblank() uses correct delay. (Ankit)
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++++++++--
> >   1 file changed, 15 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 11f06a5b854a..e5cff3892cb1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -1081,10 +1081,23 @@ int intel_vrr_safe_window_start(const struct
> intel_crtc_state *crtc_state)
> >   		return crtc_state->hw.adjusted_mode.crtc_vdisplay;
> >   }
> >
> > +static int
> > +intel_vrr_dcb_vmin_vblank_start(const struct intel_crtc_state
> > +*crtc_state) {
> > +	return (intel_vrr_dcb_vmin_vblank_start_next(crtc_state) < 0) ?
> > +		intel_vrr_dcb_vmin_vblank_start_final(crtc_state) :
> > +		intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
> > +}
> > +
> >   int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state
> *crtc_state)
> >   {
> > -	return intel_vrr_vmin_vblank_start(crtc_state) -
> > -	       crtc_state->set_context_latency;
> > +	if (crtc_state->vrr.dc_balance.enable) {
> > +		return intel_vrr_dcb_vmin_vblank_start(crtc_state) -
> > +			crtc_state->set_context_latency;
> > +	} else {
> > +		return intel_vrr_vmin_vblank_start(crtc_state) -
> > +			crtc_state->set_context_latency;
> > +	}
> >   }
> 
> 
> This can be simplified to:
> 
>   int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state
> *crtc_state)
>   {
>      int vmin_vblank_start = crtc_state->vrr.dc_balance.enable ?
>                  intel_vrr_dcb_vmin_vblank_start(crtc_state) :
>                  intel_vrr_vmin_vblank_start(crtc_state);
> 
>      return vmin_vblank_start - crtc_state->set_context_latency;
>   }

Sure, I will simplify this function in next revision based on suggestion.

Thanks
> 
> Regards,
> 
> Ankit
> 
> >
> >   int intel_vrr_dcb_vmin_vblank_start_next(const struct
> > intel_crtc_state *crtc_state)

[PATCH v9 14/17] drm/i915/dsb: Add pipedmc dc balance enable/disable

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add function to control DC balance enable/disable bit via DSB.

--v2:
Remove redundant forward declaration.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dmc.h |  3 +++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 6ebbd97e6351..147adcd18320 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1755,3 +1755,20 @@ u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc)
 
 	return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0;
 }
+
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum pipe pipe = crtc->pipe;
+
+	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
+			   PIPEDMC_ADAPTIVE_DCB_ENABLE);
+}
+
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum pipe pipe = crtc->pipe;
+
+	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 40e9dcb033cc..9c6a42fc820e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -15,6 +15,7 @@ struct intel_crtc;
 struct intel_crtc_state;
 struct intel_display;
 struct intel_dmc_snapshot;
+struct intel_dsb;
 
 void intel_dmc_init(struct intel_display *display);
 void intel_dmc_load_program(struct intel_display *display);
@@ -39,6 +40,8 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
 void assert_main_dmc_loaded(struct intel_display *display);
 
 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
 
 u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc);
 void intel_pipedmc_enable_event(struct intel_crtc *crtc,
-- 
2.48.1

[PATCH v9 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pause the DMC DC Balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.

--v2:
- Remove typo. (Ankit)
- Separate vrr enable structuring. (Ankit)

--v3:
- Add gaurd before accessing DC balance bits.
- Remove redundancy checks.

--v4:
- Move events to separate function.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c     |  3 +++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1269f841d48b..63cf337e1086 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7326,6 +7326,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		if (new_crtc_state->use_flipq)
 			intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc);
 
+		if (new_crtc_state->vrr.dc_balance.enable) {
+			/*
+			 * Pause the DMC DC balancing for the remainder of
+			 * the commit so that vmin/vmax won't change after
+			 * we've baked them into the DSB vblank evasion
+			 * commands.
+			 *
+			 * FIXME maybe need a small delay here to make sure
+			 * DMC has finished updating the values? Or we need
+			 * a better DMC<->driver protocol that gives is real
+			 * guarantees about that...
+			 */
+			intel_pipedmc_dcb_disable(NULL, crtc);
+		}
+
 		if (intel_crtc_needs_color_update(new_crtc_state))
 			intel_color_commit_noarm(new_crtc_state->dsb_commit,
 						 new_crtc_state);
@@ -7379,6 +7394,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit);
 		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
 					  new_crtc_state);
+
+		if (new_crtc_state->vrr.dc_balance.enable)
+			intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
+
 		intel_dsb_interrupt(new_crtc_state->dsb_commit);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e5cff3892cb1..286ffa35107b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -10,6 +10,7 @@
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_dmc.h"
 #include "intel_dmc_regs.h"
 #include "intel_dp.h"
 #include "intel_psr.h"
@@ -810,6 +811,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
 		       crtc_state->vrr.dc_balance.vblank_target);
 	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
 		       ADAPTIVE_SYNC_COUNTER_EN);
+	intel_pipedmc_dcb_enable(NULL, crtc);
 }
 
 static void
@@ -823,6 +825,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 	if (!old_crtc_state->vrr.dc_balance.enable)
 		return;
 
+	intel_pipedmc_dcb_disable(NULL, crtc);
 	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
 	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
 	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
-- 
2.48.1

[PATCH v9 16/17] drm/i915/display: Add function to configure event for dc balance

[Mitul Golani]

Configure pipe dmc event for dc balance enable/disable.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/intel_dmc.h |  2 ++
 drivers/gpu/drm/i915/display/intel_vrr.c |  2 ++
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 147adcd18320..8de8e69780fa 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -859,6 +859,21 @@ static void dmc_configure_event(struct intel_display *display,
 		      dmc_id, num_handlers, event_id);
 }
 
+/*
+ * intel_dmc_configure_dc_balance_event() - Configure event
+ * for dc balance enable/disable
+ * @display: display instance
+ * @pipe: pipe which register use to block
+ * @enable: enable/disable
+ */
+void intel_dmc_configure_dc_balance_event(struct intel_display *display,
+					  enum pipe pipe, bool enable)
+{
+	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
+
+	dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable);
+}
+
 /**
  * intel_dmc_block_pkgc() - block PKG C-state
  * @display: display instance
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 9c6a42fc820e..3d8a9a593319 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -25,6 +25,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state);
 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state);
 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
 			  bool block);
+void intel_dmc_configure_dc_balance_event(struct intel_display *display,
+					  enum pipe pipe, bool enable);
 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
 							    enum pipe pipe, bool enable);
 void intel_dmc_fini(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 286ffa35107b..ec2e5a94a99e 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -809,6 +809,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
 		       crtc_state->vrr.dc_balance.slope);
 	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
 		       crtc_state->vrr.dc_balance.vblank_target);
+	intel_dmc_configure_dc_balance_event(display, pipe, true);
 	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
 		       ADAPTIVE_SYNC_COUNTER_EN);
 	intel_pipedmc_dcb_enable(NULL, crtc);
@@ -826,6 +827,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 		return;
 
 	intel_pipedmc_dcb_disable(NULL, crtc);
+	intel_dmc_configure_dc_balance_event(display, pipe, false);
 	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
 	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
 	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
-- 
2.48.1

Re: [PATCH v9 16/17] drm/i915/display: Add function to configure event for dc balance

[Jani Nikula]

On Thu, 27 Nov 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Configure pipe dmc event for dc balance enable/disable.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dmc.h |  2 ++
>  drivers/gpu/drm/i915/display/intel_vrr.c |  2 ++
>  3 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 147adcd18320..8de8e69780fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -859,6 +859,21 @@ static void dmc_configure_event(struct intel_display *display,
>  		      dmc_id, num_handlers, event_id);
>  }
>  
> +/*
> + * intel_dmc_configure_dc_balance_event() - Configure event
> + * for dc balance enable/disable
> + * @display: display instance
> + * @pipe: pipe which register use to block
> + * @enable: enable/disable
> + */

How is this comment helpful?

> +void intel_dmc_configure_dc_balance_event(struct intel_display *display,
> +					  enum pipe pipe, bool enable)
> +{
> +	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
> +
> +	dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable);
> +}
> +
>  /**
>   * intel_dmc_block_pkgc() - block PKG C-state
>   * @display: display instance
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 9c6a42fc820e..3d8a9a593319 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -25,6 +25,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state);
>  void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state);
>  void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
>  			  bool block);
> +void intel_dmc_configure_dc_balance_event(struct intel_display *display,
> +					  enum pipe pipe, bool enable);
>  void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
>  							    enum pipe pipe, bool enable);
>  void intel_dmc_fini(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 286ffa35107b..ec2e5a94a99e 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -809,6 +809,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
>  		       crtc_state->vrr.dc_balance.slope);
>  	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
>  		       crtc_state->vrr.dc_balance.vblank_target);
> +	intel_dmc_configure_dc_balance_event(display, pipe, true);
>  	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
>  		       ADAPTIVE_SYNC_COUNTER_EN);
>  	intel_pipedmc_dcb_enable(NULL, crtc);
> @@ -826,6 +827,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
>  		return;
>  
>  	intel_pipedmc_dcb_disable(NULL, crtc);
> +	intel_dmc_configure_dc_balance_event(display, pipe, false);
>  	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
>  	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
>  	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);

-- 
Jani Nikula, Intel

RE: [PATCH v9 16/17] drm/i915/display: Add function to configure event for dc balance

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: 27 November 2025 16:27
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; ville.syrjala@linux.intel.com
> Subject: Re: [PATCH v9 16/17] drm/i915/display: Add function to configure
> event for dc balance
> 
> On Thu, 27 Nov 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> wrote:
> > Configure pipe dmc event for dc balance enable/disable.
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dmc.c | 15 +++++++++++++++
> > drivers/gpu/drm/i915/display/intel_dmc.h |  2 ++
> > drivers/gpu/drm/i915/display/intel_vrr.c |  2 ++
> >  3 files changed, 19 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> > b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index 147adcd18320..8de8e69780fa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -859,6 +859,21 @@ static void dmc_configure_event(struct
> intel_display *display,
> >  		      dmc_id, num_handlers, event_id);  }
> >
> > +/*
> > + * intel_dmc_configure_dc_balance_event() - Configure event
> > + * for dc balance enable/disable
> > + * @display: display instance
> > + * @pipe: pipe which register use to block
> > + * @enable: enable/disable
> > + */
> 
> How is this comment helpful?

Just added this comment to make it look consistent with other surrounding functions added, But I will remove them in next revision as it doesn't change original outcome.

Thanks

> 
> > +void intel_dmc_configure_dc_balance_event(struct intel_display *display,
> > +					  enum pipe pipe, bool enable)
> > +{
> > +	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
> > +
> > +	dmc_configure_event(display, dmc_id,
> > +PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); }
> > +
> >  /**
> >   * intel_dmc_block_pkgc() - block PKG C-state
> >   * @display: display instance
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
> > b/drivers/gpu/drm/i915/display/intel_dmc.h
> > index 9c6a42fc820e..3d8a9a593319 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> > @@ -25,6 +25,8 @@ void intel_dmc_enable_pipe(const struct
> > intel_crtc_state *crtc_state);  void intel_dmc_disable_pipe(const
> > struct intel_crtc_state *crtc_state);  void intel_dmc_block_pkgc(struct
> intel_display *display, enum pipe pipe,
> >  			  bool block);
> > +void intel_dmc_configure_dc_balance_event(struct intel_display *display,
> > +					  enum pipe pipe, bool enable);
> >  void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct
> intel_display *display,
> >  							    enum pipe pipe,
> bool enable);  void intel_dmc_fini(struct
> > intel_display *display); diff --git
> > a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 286ffa35107b..ec2e5a94a99e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -809,6 +809,7 @@ intel_vrr_enable_dc_balancing(const struct
> intel_crtc_state *crtc_state)
> >  		       crtc_state->vrr.dc_balance.slope);
> >  	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
> >  		       crtc_state->vrr.dc_balance.vblank_target);
> > +	intel_dmc_configure_dc_balance_event(display, pipe, true);
> >  	intel_de_write(display,
> TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> >  		       ADAPTIVE_SYNC_COUNTER_EN);
> >  	intel_pipedmc_dcb_enable(NULL, crtc); @@ -826,6 +827,7 @@
> > intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
> >  		return;
> >
> >  	intel_pipedmc_dcb_disable(NULL, crtc);
> > +	intel_dmc_configure_dc_balance_event(display, pipe, false);
> >  	intel_de_write(display,
> TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
> >  	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
> >  	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
> 
> --
> Jani Nikula, Intel

[PATCH v9 17/17] drm/i915/vrr: Enable DC Balance

[Mitul Golani]

Enable DC Balance from vrr compute config and related hw flag.
Also to add pipe restrictions along with this.

--v2:
- Use dc balance check instead of source restriction.
--v3:
- Club pipe restriction check with dc balance enablement. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 29 +++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index ec2e5a94a99e..425bd83aebfc 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -352,14 +352,28 @@ int intel_vrr_compute_vmax(struct intel_connector *connector,
 	return vmax;
 }
 
+static bool intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+
+	/*
+	 * FIXME: Currently Firmware supports DC Balancing on PIPE A
+	 * and PIPE B. Account those limitation while computing DC
+	 * Balance parameters.
+	 */
+	return (HAS_VRR_DC_BALANCE(display) &&
+		((pipe == PIPE_A) || (pipe == PIPE_B)));
+}
+
 static void
 intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
 {
 	int guardband_usec, adjustment_usec;
-	struct intel_display *display = to_intel_display(crtc_state);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 
-	if (!(HAS_VRR_DC_BALANCE(display) && crtc_state->vrr.enable))
+	if (!(intel_vrr_dc_balance_possible(crtc_state) && crtc_state->vrr.enable))
 		return;
 
 	crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
@@ -385,6 +399,7 @@ intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
 	crtc_state->vrr.dc_balance.vblank_target =
 		DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
 			     DCB_BLANK_TARGET, 100);
+	crtc_state->vrr.dc_balance.enable = true;
 }
 
 void
@@ -775,6 +790,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
+	u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
 
 	if (!crtc_state->vrr.dc_balance.enable)
 		return;
@@ -813,6 +829,9 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
 		       ADAPTIVE_SYNC_COUNTER_EN);
 	intel_pipedmc_dcb_enable(NULL, crtc);
+
+	vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE;
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
 static void
@@ -822,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
+	u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
 
 	if (!old_crtc_state->vrr.dc_balance.enable)
 		return;
@@ -844,6 +864,9 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
 	intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
 	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
+
+	vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE;
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
 static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
@@ -949,7 +972,7 @@ void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 
-	if (!HAS_VRR_DC_BALANCE(display))
+	if (!intel_vrr_dc_balance_possible(crtc_state))
 		return;
 
 	reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
-- 
2.48.1

✗ CI.checkpatch: warning for Enable/Disable DC balance along with VRR DSB

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/158157/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 97639065529bb0a4b0cd4cb3901628ecabe693a0
Author: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Date:   Thu Nov 27 14:46:14 2025 +0530

    drm/i915/vrr: Enable DC Balance
    
    Enable DC Balance from vrr compute config and related hw flag.
    Also to add pipe restrictions along with this.
    
    --v2:
    - Use dc balance check instead of source restriction.
    --v3:
    - Club pipe restriction check with dc balance enablement. (Ankit)
    
    Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
+ /mt/dim checkpatch e7a767430515c3a6e8aee91c2a68cba8b06fe884 drm-intel
041ede64a8b8 drm/i915/display: Add source param for dc balance
145f177f236a drm/i915/dmc: Add pipe dmc registers and bits for DC Balance
ba061eb01683 drm/i915/vrr: Add VRR DC balance registers
-:61: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#61: FILE: drivers/gpu/drm/i915/display/intel_vrr_regs.h:24:
+								    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A, \

-:62: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#62: FILE: drivers/gpu/drm/i915/display/intel_vrr_regs.h:25:
+								    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B)

total: 0 errors, 2 warnings, 0 checks, 80 lines checked
738b670f6ff3 drm/i915/vrr: Add functions to read out vmin/vmax stuff
5e78c1242224 drm/i915/vrr: Add DC Balance params to crtc_state
d6cf9c01b06d drm/i915/vrr: Add state dump for DC Balance params
8cb94cdc651d drm/i915/vrr: Add compute config for DC Balance params
62da285b3064 drm/i915/vrr: Add function to reset DC balance accumulated params
7097aaa10ee2 drm/i915/display: Add DC Balance flip count operations
3b132fdafd95 drm/i915/vrr: Write DC balance params to hw registers
458e73e57083 drm/i915/vblank: Extract vrr_vblank_start()
b36229ce499b drm/i915/vrr: Implement vblank evasion with DC balancing
82065a937522 drm/i915/display: Wait for VRR PUSH status update
6f71e755ef0b drm/i915/dsb: Add pipedmc dc balance enable/disable
72798d8ea6c0 drm/i915/vrr: Pause DC Balancing for DSB commits
f6f614eb03f0 drm/i915/display: Add function to configure event for dc balance
97639065529b drm/i915/vrr: Enable DC Balance

✓ CI.KUnit: success for Enable/Disable DC balance along with VRR DSB

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/158157/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[09:22:13] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:22:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:22:48] Starting KUnit Kernel (1/1)...
[09:22:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:22:48] ================== guc_buf (11 subtests) ===================
[09:22:48] [PASSED] test_smallest
[09:22:48] [PASSED] test_largest
[09:22:48] [PASSED] test_granular
[09:22:48] [PASSED] test_unique
[09:22:48] [PASSED] test_overlap
[09:22:48] [PASSED] test_reusable
[09:22:48] [PASSED] test_too_big
[09:22:48] [PASSED] test_flush
[09:22:48] [PASSED] test_lookup
[09:22:48] [PASSED] test_data
[09:22:48] [PASSED] test_class
[09:22:48] ===================== [PASSED] guc_buf =====================
[09:22:48] =================== guc_dbm (7 subtests) ===================
[09:22:48] [PASSED] test_empty
[09:22:48] [PASSED] test_default
[09:22:48] ======================== test_size  ========================
[09:22:48] [PASSED] 4
[09:22:48] [PASSED] 8
[09:22:48] [PASSED] 32
[09:22:48] [PASSED] 256
[09:22:48] ==================== [PASSED] test_size ====================
[09:22:48] ======================= test_reuse  ========================
[09:22:48] [PASSED] 4
[09:22:48] [PASSED] 8
[09:22:48] [PASSED] 32
[09:22:48] [PASSED] 256
[09:22:48] =================== [PASSED] test_reuse ====================
[09:22:48] =================== test_range_overlap  ====================
[09:22:48] [PASSED] 4
[09:22:48] [PASSED] 8
[09:22:48] [PASSED] 32
[09:22:48] [PASSED] 256
[09:22:48] =============== [PASSED] test_range_overlap ================
[09:22:48] =================== test_range_compact  ====================
[09:22:48] [PASSED] 4
[09:22:48] [PASSED] 8
[09:22:48] [PASSED] 32
[09:22:48] [PASSED] 256
[09:22:48] =============== [PASSED] test_range_compact ================
[09:22:48] ==================== test_range_spare  =====================
[09:22:48] [PASSED] 4
[09:22:48] [PASSED] 8
[09:22:48] [PASSED] 32
[09:22:48] [PASSED] 256
[09:22:48] ================ [PASSED] test_range_spare =================
[09:22:48] ===================== [PASSED] guc_dbm =====================
[09:22:48] =================== guc_idm (6 subtests) ===================
[09:22:48] [PASSED] bad_init
[09:22:48] [PASSED] no_init
[09:22:48] [PASSED] init_fini
[09:22:48] [PASSED] check_used
[09:22:48] [PASSED] check_quota
[09:22:48] [PASSED] check_all
[09:22:48] ===================== [PASSED] guc_idm =====================
[09:22:48] ================== no_relay (3 subtests) ===================
[09:22:48] [PASSED] xe_drops_guc2pf_if_not_ready
[09:22:48] [PASSED] xe_drops_guc2vf_if_not_ready
[09:22:48] [PASSED] xe_rejects_send_if_not_ready
[09:22:48] ==================== [PASSED] no_relay =====================
[09:22:48] ================== pf_relay (14 subtests) ==================
[09:22:48] [PASSED] pf_rejects_guc2pf_too_short
[09:22:48] [PASSED] pf_rejects_guc2pf_too_long
[09:22:48] [PASSED] pf_rejects_guc2pf_no_payload
[09:22:48] [PASSED] pf_fails_no_payload
[09:22:48] [PASSED] pf_fails_bad_origin
[09:22:48] [PASSED] pf_fails_bad_type
[09:22:48] [PASSED] pf_txn_reports_error
[09:22:48] [PASSED] pf_txn_sends_pf2guc
[09:22:48] [PASSED] pf_sends_pf2guc
[09:22:48] [SKIPPED] pf_loopback_nop
[09:22:48] [SKIPPED] pf_loopback_echo
[09:22:48] [SKIPPED] pf_loopback_fail
[09:22:48] [SKIPPED] pf_loopback_busy
[09:22:48] [SKIPPED] pf_loopback_retry
[09:22:48] ==================== [PASSED] pf_relay =====================
[09:22:48] ================== vf_relay (3 subtests) ===================
[09:22:48] [PASSED] vf_rejects_guc2vf_too_short
[09:22:48] [PASSED] vf_rejects_guc2vf_too_long
[09:22:48] [PASSED] vf_rejects_guc2vf_no_payload
[09:22:48] ==================== [PASSED] vf_relay =====================
[09:22:48] ================ pf_gt_config (6 subtests) =================
[09:22:48] [PASSED] fair_contexts_1vf
[09:22:48] [PASSED] fair_doorbells_1vf
[09:22:48] [PASSED] fair_ggtt_1vf
[09:22:48] ====================== fair_contexts  ======================
[09:22:48] [PASSED] 1 VF
[09:22:48] [PASSED] 2 VFs
[09:22:48] [PASSED] 3 VFs
[09:22:48] [PASSED] 4 VFs
[09:22:48] [PASSED] 5 VFs
[09:22:48] [PASSED] 6 VFs
[09:22:48] [PASSED] 7 VFs
[09:22:48] [PASSED] 8 VFs
[09:22:48] [PASSED] 9 VFs
[09:22:48] [PASSED] 10 VFs
[09:22:48] [PASSED] 11 VFs
[09:22:48] [PASSED] 12 VFs
[09:22:48] [PASSED] 13 VFs
[09:22:48] [PASSED] 14 VFs
[09:22:48] [PASSED] 15 VFs
[09:22:48] [PASSED] 16 VFs
[09:22:48] [PASSED] 17 VFs
[09:22:48] [PASSED] 18 VFs
[09:22:48] [PASSED] 19 VFs
[09:22:48] [PASSED] 20 VFs
[09:22:48] [PASSED] 21 VFs
[09:22:48] [PASSED] 22 VFs
[09:22:48] [PASSED] 23 VFs
[09:22:48] [PASSED] 24 VFs
[09:22:48] [PASSED] 25 VFs
[09:22:48] [PASSED] 26 VFs
[09:22:48] [PASSED] 27 VFs
[09:22:48] [PASSED] 28 VFs
[09:22:48] [PASSED] 29 VFs
[09:22:48] [PASSED] 30 VFs
[09:22:48] [PASSED] 31 VFs
[09:22:48] [PASSED] 32 VFs
[09:22:48] [PASSED] 33 VFs
[09:22:48] [PASSED] 34 VFs
[09:22:48] [PASSED] 35 VFs
[09:22:48] [PASSED] 36 VFs
[09:22:48] [PASSED] 37 VFs
[09:22:48] [PASSED] 38 VFs
[09:22:48] [PASSED] 39 VFs
[09:22:48] [PASSED] 40 VFs
[09:22:48] [PASSED] 41 VFs
[09:22:48] [PASSED] 42 VFs
[09:22:48] [PASSED] 43 VFs
[09:22:48] [PASSED] 44 VFs
[09:22:48] [PASSED] 45 VFs
[09:22:48] [PASSED] 46 VFs
[09:22:48] [PASSED] 47 VFs
[09:22:48] [PASSED] 48 VFs
[09:22:48] [PASSED] 49 VFs
[09:22:48] [PASSED] 50 VFs
[09:22:48] [PASSED] 51 VFs
[09:22:48] [PASSED] 52 VFs
[09:22:48] [PASSED] 53 VFs
[09:22:48] [PASSED] 54 VFs
[09:22:48] [PASSED] 55 VFs
[09:22:48] [PASSED] 56 VFs
[09:22:48] [PASSED] 57 VFs
[09:22:48] [PASSED] 58 VFs
[09:22:48] [PASSED] 59 VFs
[09:22:48] [PASSED] 60 VFs
[09:22:48] [PASSED] 61 VFs
[09:22:48] [PASSED] 62 VFs
[09:22:48] [PASSED] 63 VFs
[09:22:48] ================== [PASSED] fair_contexts ==================
[09:22:48] ===================== fair_doorbells  ======================
[09:22:48] [PASSED] 1 VF
[09:22:48] [PASSED] 2 VFs
[09:22:48] [PASSED] 3 VFs
[09:22:48] [PASSED] 4 VFs
[09:22:48] [PASSED] 5 VFs
[09:22:48] [PASSED] 6 VFs
[09:22:48] [PASSED] 7 VFs
[09:22:48] [PASSED] 8 VFs
[09:22:48] [PASSED] 9 VFs
[09:22:48] [PASSED] 10 VFs
[09:22:48] [PASSED] 11 VFs
[09:22:48] [PASSED] 12 VFs
[09:22:48] [PASSED] 13 VFs
[09:22:48] [PASSED] 14 VFs
[09:22:48] [PASSED] 15 VFs
[09:22:48] [PASSED] 16 VFs
[09:22:48] [PASSED] 17 VFs
[09:22:48] [PASSED] 18 VFs
[09:22:48] [PASSED] 19 VFs
[09:22:48] [PASSED] 20 VFs
[09:22:48] [PASSED] 21 VFs
[09:22:48] [PASSED] 22 VFs
[09:22:48] [PASSED] 23 VFs
[09:22:48] [PASSED] 24 VFs
[09:22:48] [PASSED] 25 VFs
[09:22:48] [PASSED] 26 VFs
[09:22:48] [PASSED] 27 VFs
[09:22:48] [PASSED] 28 VFs
[09:22:48] [PASSED] 29 VFs
[09:22:48] [PASSED] 30 VFs
[09:22:48] [PASSED] 31 VFs
[09:22:48] [PASSED] 32 VFs
[09:22:48] [PASSED] 33 VFs
[09:22:48] [PASSED] 34 VFs
[09:22:48] [PASSED] 35 VFs
[09:22:48] [PASSED] 36 VFs
[09:22:48] [PASSED] 37 VFs
[09:22:48] [PASSED] 38 VFs
[09:22:48] [PASSED] 39 VFs
[09:22:48] [PASSED] 40 VFs
[09:22:48] [PASSED] 41 VFs
[09:22:48] [PASSED] 42 VFs
[09:22:48] [PASSED] 43 VFs
[09:22:48] [PASSED] 44 VFs
[09:22:48] [PASSED] 45 VFs
[09:22:48] [PASSED] 46 VFs
[09:22:48] [PASSED] 47 VFs
[09:22:48] [PASSED] 48 VFs
[09:22:48] [PASSED] 49 VFs
[09:22:48] [PASSED] 50 VFs
[09:22:48] [PASSED] 51 VFs
[09:22:48] [PASSED] 52 VFs
[09:22:48] [PASSED] 53 VFs
[09:22:48] [PASSED] 54 VFs
[09:22:48] [PASSED] 55 VFs
[09:22:48] [PASSED] 56 VFs
[09:22:48] [PASSED] 57 VFs
[09:22:48] [PASSED] 58 VFs
[09:22:48] [PASSED] 59 VFs
[09:22:48] [PASSED] 60 VFs
[09:22:48] [PASSED] 61 VFs
[09:22:48] [PASSED] 62 VFs
[09:22:48] [PASSED] 63 VFs
[09:22:48] ================= [PASSED] fair_doorbells ==================
[09:22:48] ======================== fair_ggtt  ========================
[09:22:48] [PASSED] 1 VF
[09:22:48] [PASSED] 2 VFs
[09:22:48] [PASSED] 3 VFs
[09:22:48] [PASSED] 4 VFs
[09:22:48] [PASSED] 5 VFs
[09:22:48] [PASSED] 6 VFs
[09:22:48] [PASSED] 7 VFs
[09:22:48] [PASSED] 8 VFs
[09:22:48] [PASSED] 9 VFs
[09:22:48] [PASSED] 10 VFs
[09:22:48] [PASSED] 11 VFs
[09:22:48] [PASSED] 12 VFs
[09:22:48] [PASSED] 13 VFs
[09:22:48] [PASSED] 14 VFs
[09:22:48] [PASSED] 15 VFs
[09:22:48] [PASSED] 16 VFs
[09:22:48] [PASSED] 17 VFs
[09:22:48] [PASSED] 18 VFs
[09:22:48] [PASSED] 19 VFs
[09:22:48] [PASSED] 20 VFs
[09:22:48] [PASSED] 21 VFs
[09:22:48] [PASSED] 22 VFs
[09:22:48] [PASSED] 23 VFs
[09:22:48] [PASSED] 24 VFs
[09:22:48] [PASSED] 25 VFs
[09:22:48] [PASSED] 26 VFs
[09:22:48] [PASSED] 27 VFs
[09:22:48] [PASSED] 28 VFs
[09:22:48] [PASSED] 29 VFs
[09:22:48] [PASSED] 30 VFs
[09:22:48] [PASSED] 31 VFs
[09:22:48] [PASSED] 32 VFs
[09:22:48] [PASSED] 33 VFs
[09:22:48] [PASSED] 34 VFs
[09:22:48] [PASSED] 35 VFs
[09:22:48] [PASSED] 36 VFs
[09:22:48] [PASSED] 37 VFs
[09:22:48] [PASSED] 38 VFs
[09:22:48] [PASSED] 39 VFs
[09:22:48] [PASSED] 40 VFs
[09:22:48] [PASSED] 41 VFs
[09:22:48] [PASSED] 42 VFs
[09:22:48] [PASSED] 43 VFs
[09:22:48] [PASSED] 44 VFs
[09:22:48] [PASSED] 45 VFs
[09:22:48] [PASSED] 46 VFs
[09:22:48] [PASSED] 47 VFs
[09:22:48] [PASSED] 48 VFs
[09:22:48] [PASSED] 49 VFs
[09:22:48] [PASSED] 50 VFs
[09:22:48] [PASSED] 51 VFs
[09:22:48] [PASSED] 52 VFs
[09:22:48] [PASSED] 53 VFs
[09:22:48] [PASSED] 54 VFs
[09:22:48] [PASSED] 55 VFs
[09:22:48] [PASSED] 56 VFs
[09:22:48] [PASSED] 57 VFs
[09:22:48] [PASSED] 58 VFs
[09:22:48] [PASSED] 59 VFs
[09:22:48] [PASSED] 60 VFs
[09:22:48] [PASSED] 61 VFs
[09:22:48] [PASSED] 62 VFs
[09:22:48] [PASSED] 63 VFs
[09:22:48] ==================== [PASSED] fair_ggtt ====================
[09:22:48] ================== [PASSED] pf_gt_config ===================
[09:22:48] ===================== lmtt (1 subtest) =====================
[09:22:48] ======================== test_ops  =========================
[09:22:48] [PASSED] 2-level
[09:22:48] [PASSED] multi-level
[09:22:48] ==================== [PASSED] test_ops =====================
[09:22:48] ====================== [PASSED] lmtt =======================
[09:22:48] ================= pf_service (11 subtests) =================
[09:22:48] [PASSED] pf_negotiate_any
[09:22:48] [PASSED] pf_negotiate_base_match
[09:22:48] [PASSED] pf_negotiate_base_newer
[09:22:48] [PASSED] pf_negotiate_base_next
[09:22:48] [SKIPPED] pf_negotiate_base_older
[09:22:48] [PASSED] pf_negotiate_base_prev
[09:22:48] [PASSED] pf_negotiate_latest_match
[09:22:48] [PASSED] pf_negotiate_latest_newer
[09:22:48] [PASSED] pf_negotiate_latest_next
[09:22:48] [SKIPPED] pf_negotiate_latest_older
[09:22:48] [SKIPPED] pf_negotiate_latest_prev
[09:22:48] =================== [PASSED] pf_service ====================
[09:22:48] ================= xe_guc_g2g (2 subtests) ==================
[09:22:48] ============== xe_live_guc_g2g_kunit_default  ==============
[09:22:48] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[09:22:48] ============== xe_live_guc_g2g_kunit_allmem  ===============
[09:22:48] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[09:22:48] =================== [SKIPPED] xe_guc_g2g ===================
[09:22:48] =================== xe_mocs (2 subtests) ===================
[09:22:48] ================ xe_live_mocs_kernel_kunit  ================
[09:22:48] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[09:22:48] ================ xe_live_mocs_reset_kunit  =================
[09:22:48] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[09:22:48] ==================== [SKIPPED] xe_mocs =====================
[09:22:48] ================= xe_migrate (2 subtests) ==================
[09:22:48] ================= xe_migrate_sanity_kunit  =================
[09:22:48] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[09:22:48] ================== xe_validate_ccs_kunit  ==================
[09:22:48] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[09:22:48] =================== [SKIPPED] xe_migrate ===================
[09:22:48] ================== xe_dma_buf (1 subtest) ==================
[09:22:48] ==================== xe_dma_buf_kunit  =====================
[09:22:48] ================ [SKIPPED] xe_dma_buf_kunit ================
[09:22:48] =================== [SKIPPED] xe_dma_buf ===================
[09:22:48] ================= xe_bo_shrink (1 subtest) =================
[09:22:48] =================== xe_bo_shrink_kunit  ====================
[09:22:48] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[09:22:48] ================== [SKIPPED] xe_bo_shrink ==================
[09:22:48] ==================== xe_bo (2 subtests) ====================
[09:22:48] ================== xe_ccs_migrate_kunit  ===================
[09:22:48] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[09:22:48] ==================== xe_bo_evict_kunit  ====================
[09:22:48] =============== [SKIPPED] xe_bo_evict_kunit ================
[09:22:48] ===================== [SKIPPED] xe_bo ======================
[09:22:48] ==================== args (11 subtests) ====================
[09:22:48] [PASSED] count_args_test
[09:22:48] [PASSED] call_args_example
[09:22:48] [PASSED] call_args_test
[09:22:48] [PASSED] drop_first_arg_example
[09:22:48] [PASSED] drop_first_arg_test
[09:22:48] [PASSED] first_arg_example
[09:22:48] [PASSED] first_arg_test
[09:22:48] [PASSED] last_arg_example
[09:22:48] [PASSED] last_arg_test
[09:22:48] [PASSED] pick_arg_example
[09:22:48] [PASSED] sep_comma_example
[09:22:48] ====================== [PASSED] args =======================
[09:22:48] =================== xe_pci (3 subtests) ====================
[09:22:48] ==================== check_graphics_ip  ====================
[09:22:48] [PASSED] 12.00 Xe_LP
[09:22:48] [PASSED] 12.10 Xe_LP+
[09:22:48] [PASSED] 12.55 Xe_HPG
[09:22:48] [PASSED] 12.60 Xe_HPC
[09:22:48] [PASSED] 12.70 Xe_LPG
[09:22:48] [PASSED] 12.71 Xe_LPG
[09:22:48] [PASSED] 12.74 Xe_LPG+
[09:22:48] [PASSED] 20.01 Xe2_HPG
[09:22:48] [PASSED] 20.02 Xe2_HPG
[09:22:48] [PASSED] 20.04 Xe2_LPG
[09:22:48] [PASSED] 30.00 Xe3_LPG
[09:22:48] [PASSED] 30.01 Xe3_LPG
[09:22:48] [PASSED] 30.03 Xe3_LPG
[09:22:48] [PASSED] 30.04 Xe3_LPG
[09:22:48] [PASSED] 30.05 Xe3_LPG
[09:22:48] [PASSED] 35.11 Xe3p_XPC
[09:22:48] ================ [PASSED] check_graphics_ip ================
[09:22:48] ===================== check_media_ip  ======================
[09:22:48] [PASSED] 12.00 Xe_M
[09:22:48] [PASSED] 12.55 Xe_HPM
[09:22:48] [PASSED] 13.00 Xe_LPM+
[09:22:48] [PASSED] 13.01 Xe2_HPM
[09:22:48] [PASSED] 20.00 Xe2_LPM
[09:22:48] [PASSED] 30.00 Xe3_LPM
[09:22:48] [PASSED] 30.02 Xe3_LPM
[09:22:48] [PASSED] 35.00 Xe3p_LPM
[09:22:48] [PASSED] 35.03 Xe3p_HPM
[09:22:48] ================= [PASSED] check_media_ip ==================
[09:22:48] =================== check_platform_desc  ===================
[09:22:48] [PASSED] 0x9A60 (TIGERLAKE)
[09:22:48] [PASSED] 0x9A68 (TIGERLAKE)
[09:22:48] [PASSED] 0x9A70 (TIGERLAKE)
[09:22:48] [PASSED] 0x9A40 (TIGERLAKE)
[09:22:48] [PASSED] 0x9A49 (TIGERLAKE)
[09:22:48] [PASSED] 0x9A59 (TIGERLAKE)
[09:22:48] [PASSED] 0x9A78 (TIGERLAKE)
[09:22:48] [PASSED] 0x9AC0 (TIGERLAKE)
[09:22:48] [PASSED] 0x9AC9 (TIGERLAKE)
[09:22:48] [PASSED] 0x9AD9 (TIGERLAKE)
[09:22:48] [PASSED] 0x9AF8 (TIGERLAKE)
[09:22:48] [PASSED] 0x4C80 (ROCKETLAKE)
[09:22:48] [PASSED] 0x4C8A (ROCKETLAKE)
[09:22:48] [PASSED] 0x4C8B (ROCKETLAKE)
[09:22:48] [PASSED] 0x4C8C (ROCKETLAKE)
[09:22:48] [PASSED] 0x4C90 (ROCKETLAKE)
[09:22:48] [PASSED] 0x4C9A (ROCKETLAKE)
[09:22:48] [PASSED] 0x4680 (ALDERLAKE_S)
[09:22:48] [PASSED] 0x4682 (ALDERLAKE_S)
[09:22:48] [PASSED] 0x4688 (ALDERLAKE_S)
[09:22:48] [PASSED] 0x468A (ALDERLAKE_S)
[09:22:48] [PASSED] 0x468B (ALDERLAKE_S)
[09:22:48] [PASSED] 0x4690 (ALDERLAKE_S)
[09:22:48] [PASSED] 0x4692 (ALDERLAKE_S)
[09:22:48] [PASSED] 0x4693 (ALDERLAKE_S)
[09:22:48] [PASSED] 0x46A0 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46A1 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46A2 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46A3 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46A6 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46A8 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46AA (ALDERLAKE_P)
[09:22:48] [PASSED] 0x462A (ALDERLAKE_P)
[09:22:48] [PASSED] 0x4626 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x4628 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[09:22:48] [PASSED] 0x46B1 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46B2 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46B3 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46C0 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46C1 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46C2 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46C3 (ALDERLAKE_P)
[09:22:48] [PASSED] 0x46D0 (ALDERLAKE_N)
[09:22:48] [PASSED] 0x46D1 (ALDERLAKE_N)
[09:22:48] [PASSED] 0x46D2 (ALDERLAKE_N)
[09:22:48] [PASSED] 0x46D3 (ALDERLAKE_N)
[09:22:48] [PASSED] 0x46D4 (ALDERLAKE_N)
[09:22:48] [PASSED] 0xA721 (ALDERLAKE_P)
[09:22:48] [PASSED] 0xA7A1 (ALDERLAKE_P)
[09:22:48] [PASSED] 0xA7A9 (ALDERLAKE_P)
[09:22:48] [PASSED] 0xA7AC (ALDERLAKE_P)
[09:22:48] [PASSED] 0xA7AD (ALDERLAKE_P)
[09:22:48] [PASSED] 0xA720 (ALDERLAKE_P)
[09:22:48] [PASSED] 0xA7A0 (ALDERLAKE_P)
[09:22:48] [PASSED] 0xA7A8 (ALDERLAKE_P)
[09:22:48] [PASSED] 0xA7AA (ALDERLAKE_P)
[09:22:48] [PASSED] 0xA7AB (ALDERLAKE_P)
[09:22:48] [PASSED] 0xA780 (ALDERLAKE_S)
[09:22:48] [PASSED] 0xA781 (ALDERLAKE_S)
[09:22:48] [PASSED] 0xA782 (ALDERLAKE_S)
[09:22:48] [PASSED] 0xA783 (ALDERLAKE_S)
[09:22:48] [PASSED] 0xA788 (ALDERLAKE_S)
[09:22:48] [PASSED] 0xA789 (ALDERLAKE_S)
[09:22:48] [PASSED] 0xA78A (ALDERLAKE_S)
[09:22:48] [PASSED] 0xA78B (ALDERLAKE_S)
[09:22:48] [PASSED] 0x4905 (DG1)
[09:22:48] [PASSED] 0x4906 (DG1)
[09:22:48] [PASSED] 0x4907 (DG1)
[09:22:48] [PASSED] 0x4908 (DG1)
[09:22:48] [PASSED] 0x4909 (DG1)
[09:22:48] [PASSED] 0x56C0 (DG2)
[09:22:48] [PASSED] 0x56C2 (DG2)
[09:22:48] [PASSED] 0x56C1 (DG2)
[09:22:48] [PASSED] 0x7D51 (METEORLAKE)
[09:22:48] [PASSED] 0x7DD1 (METEORLAKE)
[09:22:48] [PASSED] 0x7D41 (METEORLAKE)
[09:22:48] [PASSED] 0x7D67 (METEORLAKE)
[09:22:48] [PASSED] 0xB640 (METEORLAKE)
[09:22:48] [PASSED] 0x56A0 (DG2)
[09:22:48] [PASSED] 0x56A1 (DG2)
[09:22:48] [PASSED] 0x56A2 (DG2)
[09:22:48] [PASSED] 0x56BE (DG2)
[09:22:48] [PASSED] 0x56BF (DG2)
[09:22:48] [PASSED] 0x5690 (DG2)
[09:22:48] [PASSED] 0x5691 (DG2)
[09:22:48] [PASSED] 0x5692 (DG2)
[09:22:48] [PASSED] 0x56A5 (DG2)
[09:22:48] [PASSED] 0x56A6 (DG2)
[09:22:48] [PASSED] 0x56B0 (DG2)
[09:22:48] [PASSED] 0x56B1 (DG2)
[09:22:48] [PASSED] 0x56BA (DG2)
[09:22:48] [PASSED] 0x56BB (DG2)
[09:22:48] [PASSED] 0x56BC (DG2)
[09:22:48] [PASSED] 0x56BD (DG2)
[09:22:48] [PASSED] 0x5693 (DG2)
[09:22:48] [PASSED] 0x5694 (DG2)
[09:22:48] [PASSED] 0x5695 (DG2)
[09:22:48] [PASSED] 0x56A3 (DG2)
[09:22:48] [PASSED] 0x56A4 (DG2)
[09:22:48] [PASSED] 0x56B2 (DG2)
[09:22:48] [PASSED] 0x56B3 (DG2)
[09:22:48] [PASSED] 0x5696 (DG2)
[09:22:48] [PASSED] 0x5697 (DG2)
[09:22:48] [PASSED] 0xB69 (PVC)
[09:22:48] [PASSED] 0xB6E (PVC)
[09:22:48] [PASSED] 0xBD4 (PVC)
[09:22:48] [PASSED] 0xBD5 (PVC)
[09:22:48] [PASSED] 0xBD6 (PVC)
[09:22:48] [PASSED] 0xBD7 (PVC)
[09:22:48] [PASSED] 0xBD8 (PVC)
[09:22:48] [PASSED] 0xBD9 (PVC)
[09:22:48] [PASSED] 0xBDA (PVC)
[09:22:48] [PASSED] 0xBDB (PVC)
[09:22:48] [PASSED] 0xBE0 (PVC)
[09:22:48] [PASSED] 0xBE1 (PVC)
[09:22:48] [PASSED] 0xBE5 (PVC)
[09:22:48] [PASSED] 0x7D40 (METEORLAKE)
[09:22:48] [PASSED] 0x7D45 (METEORLAKE)
[09:22:48] [PASSED] 0x7D55 (METEORLAKE)
[09:22:48] [PASSED] 0x7D60 (METEORLAKE)
[09:22:48] [PASSED] 0x7DD5 (METEORLAKE)
[09:22:48] [PASSED] 0x6420 (LUNARLAKE)
[09:22:48] [PASSED] 0x64A0 (LUNARLAKE)
[09:22:48] [PASSED] 0x64B0 (LUNARLAKE)
[09:22:48] [PASSED] 0xE202 (BATTLEMAGE)
[09:22:48] [PASSED] 0xE209 (BATTLEMAGE)
[09:22:48] [PASSED] 0xE20B (BATTLEMAGE)
[09:22:48] [PASSED] 0xE20C (BATTLEMAGE)
[09:22:48] [PASSED] 0xE20D (BATTLEMAGE)
[09:22:48] [PASSED] 0xE210 (BATTLEMAGE)
[09:22:48] [PASSED] 0xE211 (BATTLEMAGE)
[09:22:48] [PASSED] 0xE212 (BATTLEMAGE)
[09:22:48] [PASSED] 0xE216 (BATTLEMAGE)
[09:22:48] [PASSED] 0xE220 (BATTLEMAGE)
[09:22:48] [PASSED] 0xE221 (BATTLEMAGE)
[09:22:48] [PASSED] 0xE222 (BATTLEMAGE)
[09:22:48] [PASSED] 0xE223 (BATTLEMAGE)
[09:22:48] [PASSED] 0xB080 (PANTHERLAKE)
[09:22:48] [PASSED] 0xB081 (PANTHERLAKE)
[09:22:48] [PASSED] 0xB082 (PANTHERLAKE)
[09:22:48] [PASSED] 0xB083 (PANTHERLAKE)
[09:22:48] [PASSED] 0xB084 (PANTHERLAKE)
[09:22:48] [PASSED] 0xB085 (PANTHERLAKE)
[09:22:48] [PASSED] 0xB086 (PANTHERLAKE)
[09:22:48] [PASSED] 0xB087 (PANTHERLAKE)
[09:22:48] [PASSED] 0xB08F (PANTHERLAKE)
[09:22:48] [PASSED] 0xB090 (PANTHERLAKE)
[09:22:48] [PASSED] 0xB0A0 (PANTHERLAKE)
[09:22:48] [PASSED] 0xB0B0 (PANTHERLAKE)
[09:22:48] [PASSED] 0xD740 (NOVALAKE_S)
[09:22:48] [PASSED] 0xD741 (NOVALAKE_S)
[09:22:48] [PASSED] 0xD742 (NOVALAKE_S)
[09:22:48] [PASSED] 0xD743 (NOVALAKE_S)
[09:22:48] [PASSED] 0xD744 (NOVALAKE_S)
[09:22:48] [PASSED] 0xD745 (NOVALAKE_S)
[09:22:48] [PASSED] 0x674C (CRESCENTISLAND)
[09:22:48] [PASSED] 0xFD80 (PANTHERLAKE)
[09:22:48] [PASSED] 0xFD81 (PANTHERLAKE)
[09:22:48] =============== [PASSED] check_platform_desc ===============
[09:22:48] ===================== [PASSED] xe_pci ======================
[09:22:48] =================== xe_rtp (2 subtests) ====================
[09:22:48] =============== xe_rtp_process_to_sr_tests  ================
[09:22:48] [PASSED] coalesce-same-reg
[09:22:48] [PASSED] no-match-no-add
[09:22:48] [PASSED] match-or
[09:22:48] [PASSED] match-or-xfail
[09:22:48] [PASSED] no-match-no-add-multiple-rules
[09:22:48] [PASSED] two-regs-two-entries
[09:22:48] [PASSED] clr-one-set-other
[09:22:48] [PASSED] set-field
[09:22:48] [PASSED] conflict-duplicate
[09:22:48] [PASSED] conflict-not-disjoint
[09:22:48] [PASSED] conflict-reg-type
[09:22:48] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[09:22:48] ================== xe_rtp_process_tests  ===================
[09:22:48] [PASSED] active1
[09:22:48] [PASSED] active2
[09:22:48] [PASSED] active-inactive
[09:22:48] [PASSED] inactive-active
[09:22:48] [PASSED] inactive-1st_or_active-inactive
[09:22:48] [PASSED] inactive-2nd_or_active-inactive
[09:22:48] [PASSED] inactive-last_or_active-inactive
[09:22:48] [PASSED] inactive-no_or_active-inactive
[09:22:48] ============== [PASSED] xe_rtp_process_tests ===============
[09:22:48] ===================== [PASSED] xe_rtp ======================
[09:22:48] ==================== xe_wa (1 subtest) =====================
[09:22:48] ======================== xe_wa_gt  =========================
[09:22:48] [PASSED] TIGERLAKE B0
[09:22:48] [PASSED] DG1 A0
[09:22:48] [PASSED] DG1 B0
[09:22:48] [PASSED] ALDERLAKE_S A0
[09:22:48] [PASSED] ALDERLAKE_S B0
[09:22:48] [PASSED] ALDERLAKE_S C0
[09:22:48] [PASSED] ALDERLAKE_S D0
[09:22:48] [PASSED] ALDERLAKE_P A0
[09:22:48] [PASSED] ALDERLAKE_P B0
[09:22:48] [PASSED] ALDERLAKE_P C0
[09:22:48] [PASSED] ALDERLAKE_S RPLS D0
[09:22:48] [PASSED] ALDERLAKE_P RPLU E0
[09:22:48] [PASSED] DG2 G10 C0
[09:22:48] [PASSED] DG2 G11 B1
[09:22:48] [PASSED] DG2 G12 A1
[09:22:48] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[09:22:48] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[09:22:48] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[09:22:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[09:22:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[09:22:48] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[09:22:48] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[09:22:48] ==================== [PASSED] xe_wa_gt =====================
[09:22:48] ====================== [PASSED] xe_wa ======================
[09:22:48] ============================================================
[09:22:48] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[09:22:49] Elapsed time: 35.752s total, 4.230s configuring, 31.005s building, 0.494s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[09:22:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:22:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:23:16] Starting KUnit Kernel (1/1)...
[09:23:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:23:16] ============ drm_test_pick_cmdline (2 subtests) ============
[09:23:16] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[09:23:16] =============== drm_test_pick_cmdline_named  ===============
[09:23:16] [PASSED] NTSC
[09:23:16] [PASSED] NTSC-J
[09:23:16] [PASSED] PAL
[09:23:16] [PASSED] PAL-M
[09:23:16] =========== [PASSED] drm_test_pick_cmdline_named ===========
[09:23:16] ============== [PASSED] drm_test_pick_cmdline ==============
[09:23:16] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[09:23:16] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[09:23:16] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[09:23:16] =========== drm_validate_clone_mode (2 subtests) ===========
[09:23:16] ============== drm_test_check_in_clone_mode  ===============
[09:23:16] [PASSED] in_clone_mode
[09:23:16] [PASSED] not_in_clone_mode
[09:23:16] ========== [PASSED] drm_test_check_in_clone_mode ===========
[09:23:16] =============== drm_test_check_valid_clones  ===============
[09:23:16] [PASSED] not_in_clone_mode
[09:23:16] [PASSED] valid_clone
[09:23:16] [PASSED] invalid_clone
[09:23:16] =========== [PASSED] drm_test_check_valid_clones ===========
[09:23:16] ============= [PASSED] drm_validate_clone_mode =============
[09:23:16] ============= drm_validate_modeset (1 subtest) =============
[09:23:16] [PASSED] drm_test_check_connector_changed_modeset
[09:23:16] ============== [PASSED] drm_validate_modeset ===============
[09:23:16] ====== drm_test_bridge_get_current_state (2 subtests) ======
[09:23:16] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[09:23:16] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[09:23:16] ======== [PASSED] drm_test_bridge_get_current_state ========
[09:23:16] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[09:23:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[09:23:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[09:23:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[09:23:16] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[09:23:16] ============== drm_bridge_alloc (2 subtests) ===============
[09:23:16] [PASSED] drm_test_drm_bridge_alloc_basic
[09:23:16] [PASSED] drm_test_drm_bridge_alloc_get_put
[09:23:16] ================ [PASSED] drm_bridge_alloc =================
[09:23:16] ================== drm_buddy (8 subtests) ==================
[09:23:16] [PASSED] drm_test_buddy_alloc_limit
[09:23:16] [PASSED] drm_test_buddy_alloc_optimistic
[09:23:16] [PASSED] drm_test_buddy_alloc_pessimistic
[09:23:16] [PASSED] drm_test_buddy_alloc_pathological
[09:23:16] [PASSED] drm_test_buddy_alloc_contiguous
[09:23:16] [PASSED] drm_test_buddy_alloc_clear
[09:23:16] [PASSED] drm_test_buddy_alloc_range_bias
[09:23:16] [PASSED] drm_test_buddy_fragmentation_performance
[09:23:16] ==================== [PASSED] drm_buddy ====================
[09:23:16] ============= drm_cmdline_parser (40 subtests) =============
[09:23:16] [PASSED] drm_test_cmdline_force_d_only
[09:23:16] [PASSED] drm_test_cmdline_force_D_only_dvi
[09:23:16] [PASSED] drm_test_cmdline_force_D_only_hdmi
[09:23:16] [PASSED] drm_test_cmdline_force_D_only_not_digital
[09:23:16] [PASSED] drm_test_cmdline_force_e_only
[09:23:16] [PASSED] drm_test_cmdline_res
[09:23:16] [PASSED] drm_test_cmdline_res_vesa
[09:23:16] [PASSED] drm_test_cmdline_res_vesa_rblank
[09:23:16] [PASSED] drm_test_cmdline_res_rblank
[09:23:16] [PASSED] drm_test_cmdline_res_bpp
[09:23:16] [PASSED] drm_test_cmdline_res_refresh
[09:23:16] [PASSED] drm_test_cmdline_res_bpp_refresh
[09:23:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[09:23:16] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[09:23:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[09:23:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[09:23:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[09:23:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[09:23:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[09:23:16] [PASSED] drm_test_cmdline_res_margins_force_on
[09:23:16] [PASSED] drm_test_cmdline_res_vesa_margins
[09:23:16] [PASSED] drm_test_cmdline_name
[09:23:16] [PASSED] drm_test_cmdline_name_bpp
[09:23:16] [PASSED] drm_test_cmdline_name_option
[09:23:16] [PASSED] drm_test_cmdline_name_bpp_option
[09:23:16] [PASSED] drm_test_cmdline_rotate_0
[09:23:16] [PASSED] drm_test_cmdline_rotate_90
[09:23:16] [PASSED] drm_test_cmdline_rotate_180
[09:23:16] [PASSED] drm_test_cmdline_rotate_270
[09:23:16] [PASSED] drm_test_cmdline_hmirror
[09:23:16] [PASSED] drm_test_cmdline_vmirror
[09:23:16] [PASSED] drm_test_cmdline_margin_options
[09:23:16] [PASSED] drm_test_cmdline_multiple_options
[09:23:16] [PASSED] drm_test_cmdline_bpp_extra_and_option
[09:23:16] [PASSED] drm_test_cmdline_extra_and_option
[09:23:16] [PASSED] drm_test_cmdline_freestanding_options
[09:23:16] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[09:23:16] [PASSED] drm_test_cmdline_panel_orientation
[09:23:16] ================ drm_test_cmdline_invalid  =================
[09:23:16] [PASSED] margin_only
[09:23:16] [PASSED] interlace_only
[09:23:16] [PASSED] res_missing_x
[09:23:16] [PASSED] res_missing_y
[09:23:16] [PASSED] res_bad_y
[09:23:16] [PASSED] res_missing_y_bpp
[09:23:16] [PASSED] res_bad_bpp
[09:23:16] [PASSED] res_bad_refresh
[09:23:16] [PASSED] res_bpp_refresh_force_on_off
[09:23:16] [PASSED] res_invalid_mode
[09:23:16] [PASSED] res_bpp_wrong_place_mode
[09:23:16] [PASSED] name_bpp_refresh
[09:23:16] [PASSED] name_refresh
[09:23:16] [PASSED] name_refresh_wrong_mode
[09:23:16] [PASSED] name_refresh_invalid_mode
[09:23:16] [PASSED] rotate_multiple
[09:23:16] [PASSED] rotate_invalid_val
[09:23:16] [PASSED] rotate_truncated
[09:23:16] [PASSED] invalid_option
[09:23:16] [PASSED] invalid_tv_option
[09:23:16] [PASSED] truncated_tv_option
[09:23:16] ============ [PASSED] drm_test_cmdline_invalid =============
[09:23:16] =============== drm_test_cmdline_tv_options  ===============
[09:23:16] [PASSED] NTSC
[09:23:16] [PASSED] NTSC_443
[09:23:16] [PASSED] NTSC_J
[09:23:16] [PASSED] PAL
[09:23:16] [PASSED] PAL_M
[09:23:16] [PASSED] PAL_N
[09:23:16] [PASSED] SECAM
[09:23:16] [PASSED] MONO_525
[09:23:16] [PASSED] MONO_625
[09:23:16] =========== [PASSED] drm_test_cmdline_tv_options ===========
[09:23:16] =============== [PASSED] drm_cmdline_parser ================
[09:23:16] ========== drmm_connector_hdmi_init (20 subtests) ==========
[09:23:16] [PASSED] drm_test_connector_hdmi_init_valid
[09:23:16] [PASSED] drm_test_connector_hdmi_init_bpc_8
[09:23:16] [PASSED] drm_test_connector_hdmi_init_bpc_10
[09:23:16] [PASSED] drm_test_connector_hdmi_init_bpc_12
[09:23:16] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[09:23:16] [PASSED] drm_test_connector_hdmi_init_bpc_null
[09:23:16] [PASSED] drm_test_connector_hdmi_init_formats_empty
[09:23:16] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[09:23:16] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[09:23:16] [PASSED] supported_formats=0x9 yuv420_allowed=1
[09:23:16] [PASSED] supported_formats=0x9 yuv420_allowed=0
[09:23:16] [PASSED] supported_formats=0x3 yuv420_allowed=1
[09:23:16] [PASSED] supported_formats=0x3 yuv420_allowed=0
[09:23:16] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[09:23:16] [PASSED] drm_test_connector_hdmi_init_null_ddc
[09:23:16] [PASSED] drm_test_connector_hdmi_init_null_product
[09:23:16] [PASSED] drm_test_connector_hdmi_init_null_vendor
[09:23:16] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[09:23:16] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[09:23:16] [PASSED] drm_test_connector_hdmi_init_product_valid
[09:23:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[09:23:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[09:23:16] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[09:23:16] ========= drm_test_connector_hdmi_init_type_valid  =========
[09:23:16] [PASSED] HDMI-A
[09:23:16] [PASSED] HDMI-B
[09:23:16] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[09:23:16] ======== drm_test_connector_hdmi_init_type_invalid  ========
[09:23:16] [PASSED] Unknown
[09:23:16] [PASSED] VGA
[09:23:16] [PASSED] DVI-I
[09:23:16] [PASSED] DVI-D
[09:23:16] [PASSED] DVI-A
[09:23:16] [PASSED] Composite
[09:23:16] [PASSED] SVIDEO
[09:23:16] [PASSED] LVDS
[09:23:16] [PASSED] Component
[09:23:16] [PASSED] DIN
[09:23:16] [PASSED] DP
[09:23:16] [PASSED] TV
[09:23:16] [PASSED] eDP
[09:23:16] [PASSED] Virtual
[09:23:16] [PASSED] DSI
[09:23:16] [PASSED] DPI
[09:23:16] [PASSED] Writeback
[09:23:16] [PASSED] SPI
[09:23:16] [PASSED] USB
[09:23:16] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[09:23:16] ============ [PASSED] drmm_connector_hdmi_init =============
[09:23:16] ============= drmm_connector_init (3 subtests) =============
[09:23:16] [PASSED] drm_test_drmm_connector_init
[09:23:16] [PASSED] drm_test_drmm_connector_init_null_ddc
[09:23:16] ========= drm_test_drmm_connector_init_type_valid  =========
[09:23:16] [PASSED] Unknown
[09:23:16] [PASSED] VGA
[09:23:16] [PASSED] DVI-I
[09:23:16] [PASSED] DVI-D
[09:23:16] [PASSED] DVI-A
[09:23:16] [PASSED] Composite
[09:23:16] [PASSED] SVIDEO
[09:23:16] [PASSED] LVDS
[09:23:16] [PASSED] Component
[09:23:16] [PASSED] DIN
[09:23:16] [PASSED] DP
[09:23:16] [PASSED] HDMI-A
[09:23:16] [PASSED] HDMI-B
[09:23:16] [PASSED] TV
[09:23:16] [PASSED] eDP
[09:23:16] [PASSED] Virtual
[09:23:16] [PASSED] DSI
[09:23:16] [PASSED] DPI
[09:23:16] [PASSED] Writeback
[09:23:16] [PASSED] SPI
[09:23:16] [PASSED] USB
[09:23:16] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[09:23:16] =============== [PASSED] drmm_connector_init ===============
[09:23:16] ========= drm_connector_dynamic_init (6 subtests) ==========
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_init
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_init_properties
[09:23:16] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[09:23:16] [PASSED] Unknown
[09:23:16] [PASSED] VGA
[09:23:16] [PASSED] DVI-I
[09:23:16] [PASSED] DVI-D
[09:23:16] [PASSED] DVI-A
[09:23:16] [PASSED] Composite
[09:23:16] [PASSED] SVIDEO
[09:23:16] [PASSED] LVDS
[09:23:16] [PASSED] Component
[09:23:16] [PASSED] DIN
[09:23:16] [PASSED] DP
[09:23:16] [PASSED] HDMI-A
[09:23:16] [PASSED] HDMI-B
[09:23:16] [PASSED] TV
[09:23:16] [PASSED] eDP
[09:23:16] [PASSED] Virtual
[09:23:16] [PASSED] DSI
[09:23:16] [PASSED] DPI
[09:23:16] [PASSED] Writeback
[09:23:16] [PASSED] SPI
[09:23:16] [PASSED] USB
[09:23:16] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[09:23:16] ======== drm_test_drm_connector_dynamic_init_name  =========
[09:23:16] [PASSED] Unknown
[09:23:16] [PASSED] VGA
[09:23:16] [PASSED] DVI-I
[09:23:16] [PASSED] DVI-D
[09:23:16] [PASSED] DVI-A
[09:23:16] [PASSED] Composite
[09:23:16] [PASSED] SVIDEO
[09:23:16] [PASSED] LVDS
[09:23:16] [PASSED] Component
[09:23:16] [PASSED] DIN
[09:23:16] [PASSED] DP
[09:23:16] [PASSED] HDMI-A
[09:23:16] [PASSED] HDMI-B
[09:23:16] [PASSED] TV
[09:23:16] [PASSED] eDP
[09:23:16] [PASSED] Virtual
[09:23:16] [PASSED] DSI
[09:23:16] [PASSED] DPI
[09:23:16] [PASSED] Writeback
[09:23:16] [PASSED] SPI
[09:23:16] [PASSED] USB
[09:23:16] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[09:23:16] =========== [PASSED] drm_connector_dynamic_init ============
[09:23:16] ==== drm_connector_dynamic_register_early (4 subtests) =====
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[09:23:16] ====== [PASSED] drm_connector_dynamic_register_early =======
[09:23:16] ======= drm_connector_dynamic_register (7 subtests) ========
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[09:23:16] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[09:23:16] ========= [PASSED] drm_connector_dynamic_register ==========
[09:23:16] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[09:23:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[09:23:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[09:23:16] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[09:23:16] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[09:23:16] ========== drm_test_get_tv_mode_from_name_valid  ===========
[09:23:16] [PASSED] NTSC
[09:23:16] [PASSED] NTSC-443
[09:23:16] [PASSED] NTSC-J
[09:23:16] [PASSED] PAL
[09:23:16] [PASSED] PAL-M
[09:23:16] [PASSED] PAL-N
[09:23:16] [PASSED] SECAM
[09:23:16] [PASSED] Mono
[09:23:16] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[09:23:16] [PASSED] drm_test_get_tv_mode_from_name_truncated
[09:23:16] ============ [PASSED] drm_get_tv_mode_from_name ============
[09:23:16] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[09:23:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[09:23:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[09:23:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[09:23:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[09:23:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[09:23:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[09:23:16] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[09:23:16] [PASSED] VIC 96
[09:23:16] [PASSED] VIC 97
[09:23:16] [PASSED] VIC 101
[09:23:16] [PASSED] VIC 102
[09:23:16] [PASSED] VIC 106
[09:23:16] [PASSED] VIC 107
[09:23:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[09:23:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[09:23:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[09:23:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[09:23:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[09:23:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[09:23:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[09:23:16] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[09:23:16] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[09:23:16] [PASSED] Automatic
[09:23:16] [PASSED] Full
[09:23:16] [PASSED] Limited 16:235
[09:23:16] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[09:23:16] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[09:23:16] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[09:23:16] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[09:23:16] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[09:23:16] [PASSED] RGB
[09:23:16] [PASSED] YUV 4:2:0
[09:23:16] [PASSED] YUV 4:2:2
[09:23:16] [PASSED] YUV 4:4:4
[09:23:16] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[09:23:16] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[09:23:16] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[09:23:16] ============= drm_damage_helper (21 subtests) ==============
[09:23:16] [PASSED] drm_test_damage_iter_no_damage
[09:23:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[09:23:16] [PASSED] drm_test_damage_iter_no_damage_src_moved
[09:23:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[09:23:16] [PASSED] drm_test_damage_iter_no_damage_not_visible
[09:23:16] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[09:23:16] [PASSED] drm_test_damage_iter_no_damage_no_fb
[09:23:16] [PASSED] drm_test_damage_iter_simple_damage
[09:23:16] [PASSED] drm_test_damage_iter_single_damage
[09:23:16] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[09:23:16] [PASSED] drm_test_damage_iter_single_damage_outside_src
[09:23:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[09:23:16] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[09:23:16] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[09:23:16] [PASSED] drm_test_damage_iter_single_damage_src_moved
[09:23:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[09:23:16] [PASSED] drm_test_damage_iter_damage
[09:23:16] [PASSED] drm_test_damage_iter_damage_one_intersect
[09:23:16] [PASSED] drm_test_damage_iter_damage_one_outside
[09:23:16] [PASSED] drm_test_damage_iter_damage_src_moved
[09:23:16] [PASSED] drm_test_damage_iter_damage_not_visible
[09:23:16] ================ [PASSED] drm_damage_helper ================
[09:23:16] ============== drm_dp_mst_helper (3 subtests) ==============
[09:23:16] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[09:23:16] [PASSED] Clock 154000 BPP 30 DSC disabled
[09:23:16] [PASSED] Clock 234000 BPP 30 DSC disabled
[09:23:16] [PASSED] Clock 297000 BPP 24 DSC disabled
[09:23:16] [PASSED] Clock 332880 BPP 24 DSC enabled
[09:23:16] [PASSED] Clock 324540 BPP 24 DSC enabled
[09:23:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[09:23:16] ============== drm_test_dp_mst_calc_pbn_div  ===============
[09:23:16] [PASSED] Link rate 2000000 lane count 4
[09:23:16] [PASSED] Link rate 2000000 lane count 2
[09:23:16] [PASSED] Link rate 2000000 lane count 1
[09:23:16] [PASSED] Link rate 1350000 lane count 4
[09:23:16] [PASSED] Link rate 1350000 lane count 2
[09:23:16] [PASSED] Link rate 1350000 lane count 1
[09:23:16] [PASSED] Link rate 1000000 lane count 4
[09:23:16] [PASSED] Link rate 1000000 lane count 2
[09:23:16] [PASSED] Link rate 1000000 lane count 1
[09:23:16] [PASSED] Link rate 810000 lane count 4
[09:23:16] [PASSED] Link rate 810000 lane count 2
[09:23:16] [PASSED] Link rate 810000 lane count 1
[09:23:16] [PASSED] Link rate 540000 lane count 4
[09:23:16] [PASSED] Link rate 540000 lane count 2
[09:23:16] [PASSED] Link rate 540000 lane count 1
[09:23:16] [PASSED] Link rate 270000 lane count 4
[09:23:16] [PASSED] Link rate 270000 lane count 2
[09:23:16] [PASSED] Link rate 270000 lane count 1
[09:23:16] [PASSED] Link rate 162000 lane count 4
[09:23:16] [PASSED] Link rate 162000 lane count 2
[09:23:16] [PASSED] Link rate 162000 lane count 1
[09:23:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[09:23:16] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[09:23:16] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[09:23:16] [PASSED] DP_POWER_UP_PHY with port number
[09:23:16] [PASSED] DP_POWER_DOWN_PHY with port number
[09:23:16] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[09:23:16] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[09:23:16] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[09:23:16] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[09:23:16] [PASSED] DP_QUERY_PAYLOAD with port number
[09:23:16] [PASSED] DP_QUERY_PAYLOAD with VCPI
[09:23:16] [PASSED] DP_REMOTE_DPCD_READ with port number
[09:23:16] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[09:23:16] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[09:23:16] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[09:23:16] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[09:23:16] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[09:23:16] [PASSED] DP_REMOTE_I2C_READ with port number
[09:23:16] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[09:23:16] [PASSED] DP_REMOTE_I2C_READ with transactions array
[09:23:16] [PASSED] DP_REMOTE_I2C_WRITE with port number
[09:23:16] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[09:23:16] [PASSED] DP_REMOTE_I2C_WRITE with data array
[09:23:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[09:23:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[09:23:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[09:23:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[09:23:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[09:23:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[09:23:16] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[09:23:16] ================ [PASSED] drm_dp_mst_helper ================
[09:23:16] ================== drm_exec (7 subtests) ===================
[09:23:16] [PASSED] sanitycheck
[09:23:16] [PASSED] test_lock
[09:23:16] [PASSED] test_lock_unlock
[09:23:16] [PASSED] test_duplicates
[09:23:16] [PASSED] test_prepare
[09:23:16] [PASSED] test_prepare_array
[09:23:16] [PASSED] test_multiple_loops
[09:23:16] ==================== [PASSED] drm_exec =====================
[09:23:16] =========== drm_format_helper_test (17 subtests) ===========
[09:23:16] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[09:23:16] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[09:23:16] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[09:23:16] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[09:23:16] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[09:23:16] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[09:23:16] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[09:23:16] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[09:23:16] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[09:23:16] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[09:23:16] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[09:23:16] ============== drm_test_fb_xrgb8888_to_mono  ===============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[09:23:16] ==================== drm_test_fb_swab  =====================
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ================ [PASSED] drm_test_fb_swab =================
[09:23:16] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[09:23:16] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[09:23:16] [PASSED] single_pixel_source_buffer
[09:23:16] [PASSED] single_pixel_clip_rectangle
[09:23:16] [PASSED] well_known_colors
[09:23:16] [PASSED] destination_pitch
[09:23:16] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[09:23:16] ================= drm_test_fb_clip_offset  =================
[09:23:16] [PASSED] pass through
[09:23:16] [PASSED] horizontal offset
[09:23:16] [PASSED] vertical offset
[09:23:16] [PASSED] horizontal and vertical offset
[09:23:16] [PASSED] horizontal offset (custom pitch)
[09:23:16] [PASSED] vertical offset (custom pitch)
[09:23:16] [PASSED] horizontal and vertical offset (custom pitch)
[09:23:16] ============= [PASSED] drm_test_fb_clip_offset =============
[09:23:16] =================== drm_test_fb_memcpy  ====================
[09:23:16] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[09:23:16] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[09:23:16] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[09:23:16] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[09:23:16] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[09:23:16] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[09:23:16] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[09:23:16] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[09:23:16] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[09:23:16] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[09:23:16] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[09:23:16] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[09:23:16] =============== [PASSED] drm_test_fb_memcpy ================
[09:23:16] ============= [PASSED] drm_format_helper_test ==============
[09:23:16] ================= drm_format (18 subtests) =================
[09:23:16] [PASSED] drm_test_format_block_width_invalid
[09:23:16] [PASSED] drm_test_format_block_width_one_plane
[09:23:16] [PASSED] drm_test_format_block_width_two_plane
[09:23:16] [PASSED] drm_test_format_block_width_three_plane
[09:23:16] [PASSED] drm_test_format_block_width_tiled
[09:23:16] [PASSED] drm_test_format_block_height_invalid
[09:23:16] [PASSED] drm_test_format_block_height_one_plane
[09:23:16] [PASSED] drm_test_format_block_height_two_plane
[09:23:16] [PASSED] drm_test_format_block_height_three_plane
[09:23:16] [PASSED] drm_test_format_block_height_tiled
[09:23:16] [PASSED] drm_test_format_min_pitch_invalid
[09:23:16] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[09:23:16] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[09:23:16] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[09:23:16] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[09:23:16] [PASSED] drm_test_format_min_pitch_two_plane
[09:23:16] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[09:23:16] [PASSED] drm_test_format_min_pitch_tiled
[09:23:16] =================== [PASSED] drm_format ====================
[09:23:16] ============== drm_framebuffer (10 subtests) ===============
[09:23:16] ========== drm_test_framebuffer_check_src_coords  ==========
[09:23:16] [PASSED] Success: source fits into fb
[09:23:16] [PASSED] Fail: overflowing fb with x-axis coordinate
[09:23:16] [PASSED] Fail: overflowing fb with y-axis coordinate
[09:23:16] [PASSED] Fail: overflowing fb with source width
[09:23:16] [PASSED] Fail: overflowing fb with source height
[09:23:16] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[09:23:16] [PASSED] drm_test_framebuffer_cleanup
[09:23:16] =============== drm_test_framebuffer_create  ===============
[09:23:16] [PASSED] ABGR8888 normal sizes
[09:23:16] [PASSED] ABGR8888 max sizes
[09:23:16] [PASSED] ABGR8888 pitch greater than min required
[09:23:16] [PASSED] ABGR8888 pitch less than min required
[09:23:16] [PASSED] ABGR8888 Invalid width
[09:23:16] [PASSED] ABGR8888 Invalid buffer handle
[09:23:16] [PASSED] No pixel format
[09:23:16] [PASSED] ABGR8888 Width 0
[09:23:16] [PASSED] ABGR8888 Height 0
[09:23:16] [PASSED] ABGR8888 Out of bound height * pitch combination
[09:23:16] [PASSED] ABGR8888 Large buffer offset
[09:23:16] [PASSED] ABGR8888 Buffer offset for inexistent plane
[09:23:16] [PASSED] ABGR8888 Invalid flag
[09:23:16] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[09:23:16] [PASSED] ABGR8888 Valid buffer modifier
[09:23:16] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[09:23:16] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[09:23:16] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[09:23:16] [PASSED] NV12 Normal sizes
[09:23:16] [PASSED] NV12 Max sizes
[09:23:16] [PASSED] NV12 Invalid pitch
[09:23:16] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[09:23:16] [PASSED] NV12 different  modifier per-plane
[09:23:16] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[09:23:16] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[09:23:16] [PASSED] NV12 Modifier for inexistent plane
[09:23:16] [PASSED] NV12 Handle for inexistent plane
[09:23:16] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[09:23:16] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[09:23:16] [PASSED] YVU420 Normal sizes
[09:23:16] [PASSED] YVU420 Max sizes
[09:23:16] [PASSED] YVU420 Invalid pitch
[09:23:16] [PASSED] YVU420 Different pitches
[09:23:16] [PASSED] YVU420 Different buffer offsets/pitches
[09:23:16] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[09:23:16] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[09:23:16] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[09:23:16] [PASSED] YVU420 Valid modifier
[09:23:16] [PASSED] YVU420 Different modifiers per plane
[09:23:16] [PASSED] YVU420 Modifier for inexistent plane
[09:23:16] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[09:23:16] [PASSED] X0L2 Normal sizes
[09:23:16] [PASSED] X0L2 Max sizes
[09:23:16] [PASSED] X0L2 Invalid pitch
[09:23:16] [PASSED] X0L2 Pitch greater than minimum required
[09:23:16] [PASSED] X0L2 Handle for inexistent plane
[09:23:16] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[09:23:16] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[09:23:16] [PASSED] X0L2 Valid modifier
[09:23:16] [PASSED] X0L2 Modifier for inexistent plane
[09:23:16] =========== [PASSED] drm_test_framebuffer_create ===========
[09:23:16] [PASSED] drm_test_framebuffer_free
[09:23:16] [PASSED] drm_test_framebuffer_init
[09:23:16] [PASSED] drm_test_framebuffer_init_bad_format
[09:23:16] [PASSED] drm_test_framebuffer_init_dev_mismatch
[09:23:16] [PASSED] drm_test_framebuffer_lookup
[09:23:16] [PASSED] drm_test_framebuffer_lookup_inexistent
[09:23:16] [PASSED] drm_test_framebuffer_modifiers_not_supported
[09:23:16] ================= [PASSED] drm_framebuffer =================
[09:23:16] ================ drm_gem_shmem (8 subtests) ================
[09:23:16] [PASSED] drm_gem_shmem_test_obj_create
[09:23:16] [PASSED] drm_gem_shmem_test_obj_create_private
[09:23:16] [PASSED] drm_gem_shmem_test_pin_pages
[09:23:16] [PASSED] drm_gem_shmem_test_vmap
[09:23:16] [PASSED] drm_gem_shmem_test_get_pages_sgt
[09:23:16] [PASSED] drm_gem_shmem_test_get_sg_table
[09:23:16] [PASSED] drm_gem_shmem_test_madvise
[09:23:16] [PASSED] drm_gem_shmem_test_purge
[09:23:16] ================== [PASSED] drm_gem_shmem ==================
[09:23:16] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[09:23:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[09:23:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[09:23:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[09:23:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[09:23:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[09:23:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[09:23:16] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[09:23:16] [PASSED] Automatic
[09:23:16] [PASSED] Full
[09:23:16] [PASSED] Limited 16:235
[09:23:16] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[09:23:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[09:23:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[09:23:16] [PASSED] drm_test_check_disable_connector
[09:23:16] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[09:23:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[09:23:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[09:23:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[09:23:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[09:23:16] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[09:23:16] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[09:23:16] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[09:23:16] [PASSED] drm_test_check_output_bpc_dvi
[09:23:16] [PASSED] drm_test_check_output_bpc_format_vic_1
[09:23:16] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[09:23:16] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[09:23:16] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[09:23:16] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[09:23:16] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[09:23:16] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[09:23:16] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[09:23:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[09:23:16] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[09:23:16] [PASSED] drm_test_check_broadcast_rgb_value
[09:23:16] [PASSED] drm_test_check_bpc_8_value
[09:23:16] [PASSED] drm_test_check_bpc_10_value
[09:23:16] [PASSED] drm_test_check_bpc_12_value
[09:23:16] [PASSED] drm_test_check_format_value
[09:23:16] [PASSED] drm_test_check_tmds_char_value
[09:23:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[09:23:16] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[09:23:16] [PASSED] drm_test_check_mode_valid
[09:23:16] [PASSED] drm_test_check_mode_valid_reject
[09:23:16] [PASSED] drm_test_check_mode_valid_reject_rate
[09:23:16] [PASSED] drm_test_check_mode_valid_reject_max_clock
[09:23:16] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[09:23:16] ================= drm_managed (2 subtests) =================
[09:23:16] [PASSED] drm_test_managed_release_action
[09:23:16] [PASSED] drm_test_managed_run_action
[09:23:16] =================== [PASSED] drm_managed ===================
[09:23:16] =================== drm_mm (6 subtests) ====================
[09:23:16] [PASSED] drm_test_mm_init
[09:23:16] [PASSED] drm_test_mm_debug
[09:23:16] [PASSED] drm_test_mm_align32
[09:23:16] [PASSED] drm_test_mm_align64
[09:23:16] [PASSED] drm_test_mm_lowest
[09:23:16] [PASSED] drm_test_mm_highest
[09:23:16] ===================== [PASSED] drm_mm ======================
[09:23:16] ============= drm_modes_analog_tv (5 subtests) =============
[09:23:16] [PASSED] drm_test_modes_analog_tv_mono_576i
[09:23:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[09:23:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[09:23:16] [PASSED] drm_test_modes_analog_tv_pal_576i
[09:23:16] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[09:23:16] =============== [PASSED] drm_modes_analog_tv ===============
[09:23:16] ============== drm_plane_helper (2 subtests) ===============
[09:23:16] =============== drm_test_check_plane_state  ================
[09:23:16] [PASSED] clipping_simple
[09:23:16] [PASSED] clipping_rotate_reflect
[09:23:16] [PASSED] positioning_simple
[09:23:16] [PASSED] upscaling
[09:23:16] [PASSED] downscaling
[09:23:16] [PASSED] rounding1
[09:23:16] [PASSED] rounding2
[09:23:16] [PASSED] rounding3
[09:23:16] [PASSED] rounding4
[09:23:16] =========== [PASSED] drm_test_check_plane_state ============
[09:23:16] =========== drm_test_check_invalid_plane_state  ============
[09:23:16] [PASSED] positioning_invalid
[09:23:16] [PASSED] upscaling_invalid
[09:23:16] [PASSED] downscaling_invalid
[09:23:16] ======= [PASSED] drm_test_check_invalid_plane_state ========
[09:23:16] ================ [PASSED] drm_plane_helper =================
[09:23:16] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[09:23:16] ====== drm_test_connector_helper_tv_get_modes_check  =======
[09:23:16] [PASSED] None
[09:23:16] [PASSED] PAL
[09:23:16] [PASSED] NTSC
[09:23:16] [PASSED] Both, NTSC Default
[09:23:16] [PASSED] Both, PAL Default
[09:23:16] [PASSED] Both, NTSC Default, with PAL on command-line
[09:23:16] [PASSED] Both, PAL Default, with NTSC on command-line
[09:23:16] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[09:23:16] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[09:23:16] ================== drm_rect (9 subtests) ===================
[09:23:16] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[09:23:16] [PASSED] drm_test_rect_clip_scaled_not_clipped
[09:23:16] [PASSED] drm_test_rect_clip_scaled_clipped
[09:23:16] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[09:23:16] ================= drm_test_rect_intersect  =================
[09:23:16] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[09:23:16] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[09:23:16] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[09:23:16] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[09:23:16] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[09:23:16] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[09:23:16] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[09:23:16] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[09:23:16] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[09:23:16] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[09:23:16] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[09:23:16] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[09:23:16] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[09:23:16] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[09:23:16] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[09:23:16] ============= [PASSED] drm_test_rect_intersect =============
[09:23:16] ================ drm_test_rect_calc_hscale  ================
[09:23:16] [PASSED] normal use
[09:23:16] [PASSED] out of max range
[09:23:16] [PASSED] out of min range
[09:23:16] [PASSED] zero dst
[09:23:16] [PASSED] negative src
[09:23:16] [PASSED] negative dst
[09:23:16] ============ [PASSED] drm_test_rect_calc_hscale ============
[09:23:16] ================ drm_test_rect_calc_vscale  ================
[09:23:16] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[09:23:16] [PASSED] out of max range
[09:23:16] [PASSED] out of min range
[09:23:16] [PASSED] zero dst
[09:23:16] [PASSED] negative src
[09:23:16] [PASSED] negative dst
[09:23:16] ============ [PASSED] drm_test_rect_calc_vscale ============
[09:23:16] ================== drm_test_rect_rotate  ===================
[09:23:16] [PASSED] reflect-x
[09:23:16] [PASSED] reflect-y
[09:23:16] [PASSED] rotate-0
[09:23:16] [PASSED] rotate-90
[09:23:16] [PASSED] rotate-180
[09:23:16] [PASSED] rotate-270
[09:23:16] ============== [PASSED] drm_test_rect_rotate ===============
[09:23:16] ================ drm_test_rect_rotate_inv  =================
[09:23:16] [PASSED] reflect-x
[09:23:16] [PASSED] reflect-y
[09:23:16] [PASSED] rotate-0
[09:23:16] [PASSED] rotate-90
[09:23:16] [PASSED] rotate-180
[09:23:16] [PASSED] rotate-270
[09:23:16] ============ [PASSED] drm_test_rect_rotate_inv =============
[09:23:16] ==================== [PASSED] drm_rect =====================
[09:23:16] ============ drm_sysfb_modeset_test (1 subtest) ============
[09:23:16] ============ drm_test_sysfb_build_fourcc_list  =============
[09:23:16] [PASSED] no native formats
[09:23:16] [PASSED] XRGB8888 as native format
[09:23:16] [PASSED] remove duplicates
[09:23:16] [PASSED] convert alpha formats
[09:23:16] [PASSED] random formats
[09:23:16] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[09:23:16] ============= [PASSED] drm_sysfb_modeset_test ==============
[09:23:16] ================== drm_fixp (2 subtests) ===================
[09:23:16] [PASSED] drm_test_int2fixp
[09:23:16] [PASSED] drm_test_sm2fixp
[09:23:16] ==================== [PASSED] drm_fixp =====================
[09:23:16] ============================================================
[09:23:16] Testing complete. Ran 624 tests: passed: 624
[09:23:16] Elapsed time: 27.353s total, 1.613s configuring, 25.322s building, 0.397s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[09:23:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:23:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:23:27] Starting KUnit Kernel (1/1)...
[09:23:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:23:27] ================= ttm_device (5 subtests) ==================
[09:23:27] [PASSED] ttm_device_init_basic
[09:23:27] [PASSED] ttm_device_init_multiple
[09:23:27] [PASSED] ttm_device_fini_basic
[09:23:27] [PASSED] ttm_device_init_no_vma_man
[09:23:27] ================== ttm_device_init_pools  ==================
[09:23:27] [PASSED] No DMA allocations, no DMA32 required
[09:23:27] [PASSED] DMA allocations, DMA32 required
[09:23:27] [PASSED] No DMA allocations, DMA32 required
[09:23:27] [PASSED] DMA allocations, no DMA32 required
[09:23:27] ============== [PASSED] ttm_device_init_pools ==============
[09:23:27] =================== [PASSED] ttm_device ====================
[09:23:27] ================== ttm_pool (8 subtests) ===================
[09:23:27] ================== ttm_pool_alloc_basic  ===================
[09:23:27] [PASSED] One page
[09:23:27] [PASSED] More than one page
[09:23:27] [PASSED] Above the allocation limit
[09:23:27] [PASSED] One page, with coherent DMA mappings enabled
[09:23:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:23:27] ============== [PASSED] ttm_pool_alloc_basic ===============
[09:23:27] ============== ttm_pool_alloc_basic_dma_addr  ==============
[09:23:27] [PASSED] One page
[09:23:27] [PASSED] More than one page
[09:23:27] [PASSED] Above the allocation limit
[09:23:27] [PASSED] One page, with coherent DMA mappings enabled
[09:23:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:23:27] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[09:23:27] [PASSED] ttm_pool_alloc_order_caching_match
[09:23:27] [PASSED] ttm_pool_alloc_caching_mismatch
[09:23:27] [PASSED] ttm_pool_alloc_order_mismatch
[09:23:27] [PASSED] ttm_pool_free_dma_alloc
[09:23:27] [PASSED] ttm_pool_free_no_dma_alloc
[09:23:27] [PASSED] ttm_pool_fini_basic
[09:23:27] ==================== [PASSED] ttm_pool =====================
[09:23:27] ================ ttm_resource (8 subtests) =================
[09:23:27] ================= ttm_resource_init_basic  =================
[09:23:27] [PASSED] Init resource in TTM_PL_SYSTEM
[09:23:27] [PASSED] Init resource in TTM_PL_VRAM
[09:23:27] [PASSED] Init resource in a private placement
[09:23:27] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[09:23:27] ============= [PASSED] ttm_resource_init_basic =============
[09:23:27] [PASSED] ttm_resource_init_pinned
[09:23:27] [PASSED] ttm_resource_fini_basic
[09:23:27] [PASSED] ttm_resource_manager_init_basic
[09:23:27] [PASSED] ttm_resource_manager_usage_basic
[09:23:27] [PASSED] ttm_resource_manager_set_used_basic
[09:23:27] [PASSED] ttm_sys_man_alloc_basic
[09:23:27] [PASSED] ttm_sys_man_free_basic
[09:23:27] ================== [PASSED] ttm_resource ===================
[09:23:27] =================== ttm_tt (15 subtests) ===================
[09:23:27] ==================== ttm_tt_init_basic  ====================
[09:23:27] [PASSED] Page-aligned size
[09:23:27] [PASSED] Extra pages requested
[09:23:27] ================ [PASSED] ttm_tt_init_basic ================
[09:23:27] [PASSED] ttm_tt_init_misaligned
[09:23:27] [PASSED] ttm_tt_fini_basic
[09:23:27] [PASSED] ttm_tt_fini_sg
[09:23:27] [PASSED] ttm_tt_fini_shmem
[09:23:27] [PASSED] ttm_tt_create_basic
[09:23:27] [PASSED] ttm_tt_create_invalid_bo_type
[09:23:27] [PASSED] ttm_tt_create_ttm_exists
[09:23:27] [PASSED] ttm_tt_create_failed
[09:23:27] [PASSED] ttm_tt_destroy_basic
[09:23:27] [PASSED] ttm_tt_populate_null_ttm
[09:23:27] [PASSED] ttm_tt_populate_populated_ttm
[09:23:27] [PASSED] ttm_tt_unpopulate_basic
[09:23:27] [PASSED] ttm_tt_unpopulate_empty_ttm
[09:23:27] [PASSED] ttm_tt_swapin_basic
[09:23:27] ===================== [PASSED] ttm_tt ======================
[09:23:27] =================== ttm_bo (14 subtests) ===================
[09:23:27] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[09:23:27] [PASSED] Cannot be interrupted and sleeps
[09:23:27] [PASSED] Cannot be interrupted, locks straight away
[09:23:27] [PASSED] Can be interrupted, sleeps
[09:23:27] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[09:23:27] [PASSED] ttm_bo_reserve_locked_no_sleep
[09:23:27] [PASSED] ttm_bo_reserve_no_wait_ticket
[09:23:27] [PASSED] ttm_bo_reserve_double_resv
[09:23:27] [PASSED] ttm_bo_reserve_interrupted
[09:23:27] [PASSED] ttm_bo_reserve_deadlock
[09:23:27] [PASSED] ttm_bo_unreserve_basic
[09:23:27] [PASSED] ttm_bo_unreserve_pinned
[09:23:27] [PASSED] ttm_bo_unreserve_bulk
[09:23:27] [PASSED] ttm_bo_fini_basic
[09:23:27] [PASSED] ttm_bo_fini_shared_resv
[09:23:27] [PASSED] ttm_bo_pin_basic
[09:23:27] [PASSED] ttm_bo_pin_unpin_resource
[09:23:27] [PASSED] ttm_bo_multiple_pin_one_unpin
[09:23:27] ===================== [PASSED] ttm_bo ======================
[09:23:27] ============== ttm_bo_validate (21 subtests) ===============
[09:23:27] ============== ttm_bo_init_reserved_sys_man  ===============
[09:23:27] [PASSED] Buffer object for userspace
[09:23:27] [PASSED] Kernel buffer object
[09:23:27] [PASSED] Shared buffer object
[09:23:27] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[09:23:27] ============== ttm_bo_init_reserved_mock_man  ==============
[09:23:27] [PASSED] Buffer object for userspace
[09:23:27] [PASSED] Kernel buffer object
[09:23:27] [PASSED] Shared buffer object
[09:23:27] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[09:23:27] [PASSED] ttm_bo_init_reserved_resv
[09:23:27] ================== ttm_bo_validate_basic  ==================
[09:23:27] [PASSED] Buffer object for userspace
[09:23:27] [PASSED] Kernel buffer object
[09:23:27] [PASSED] Shared buffer object
[09:23:27] ============== [PASSED] ttm_bo_validate_basic ==============
[09:23:27] [PASSED] ttm_bo_validate_invalid_placement
[09:23:27] ============= ttm_bo_validate_same_placement  ==============
[09:23:27] [PASSED] System manager
[09:23:27] [PASSED] VRAM manager
[09:23:27] ========= [PASSED] ttm_bo_validate_same_placement ==========
[09:23:27] [PASSED] ttm_bo_validate_failed_alloc
[09:23:27] [PASSED] ttm_bo_validate_pinned
[09:23:27] [PASSED] ttm_bo_validate_busy_placement
[09:23:27] ================ ttm_bo_validate_multihop  =================
[09:23:27] [PASSED] Buffer object for userspace
[09:23:27] [PASSED] Kernel buffer object
[09:23:27] [PASSED] Shared buffer object
[09:23:27] ============ [PASSED] ttm_bo_validate_multihop =============
[09:23:27] ========== ttm_bo_validate_no_placement_signaled  ==========
[09:23:27] [PASSED] Buffer object in system domain, no page vector
[09:23:27] [PASSED] Buffer object in system domain with an existing page vector
[09:23:27] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[09:23:27] ======== ttm_bo_validate_no_placement_not_signaled  ========
[09:23:27] [PASSED] Buffer object for userspace
[09:23:27] [PASSED] Kernel buffer object
[09:23:27] [PASSED] Shared buffer object
[09:23:27] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[09:23:27] [PASSED] ttm_bo_validate_move_fence_signaled
[09:23:27] ========= ttm_bo_validate_move_fence_not_signaled  =========
[09:23:27] [PASSED] Waits for GPU
[09:23:27] [PASSED] Tries to lock straight away
[09:23:27] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[09:23:27] [PASSED] ttm_bo_validate_happy_evict
[09:23:27] [PASSED] ttm_bo_validate_all_pinned_evict
[09:23:27] [PASSED] ttm_bo_validate_allowed_only_evict
[09:23:27] [PASSED] ttm_bo_validate_deleted_evict
[09:23:27] [PASSED] ttm_bo_validate_busy_domain_evict
[09:23:27] [PASSED] ttm_bo_validate_evict_gutting
[09:23:27] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[09:23:27] ================= [PASSED] ttm_bo_validate =================
[09:23:27] ============================================================
[09:23:27] Testing complete. Ran 101 tests: passed: 101
[09:23:27] Elapsed time: 11.398s total, 1.691s configuring, 9.490s building, 0.180s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Enable/Disable DC balance along with VRR DSB

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/158157/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast e7a767430515c3a6e8aee91c2a68cba8b06fe884
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_casf.c:147:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2083:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2096:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2096:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2096:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_lt_phy.c:1935:35: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable/Disable DC balance along with VRR DSB

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1952 bytes --]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/158157/
State : success

== Summary ==

CI Bug Log - changes from xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884_BAT -> xe-pw-158157v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-158157v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@abstime:
    - bat-dg2-oem2:       [PASS][1] -> [TIMEOUT][2] ([Intel XE#6506])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/bat-dg2-oem2/igt@xe_waitfence@abstime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/bat-dg2-oem2/igt@xe_waitfence@abstime.html

  
#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [FAIL][3] ([Intel XE#6519]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519


Build changes
-------------

  * Linux: xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884 -> xe-pw-158157v1

  IGT_8639: 2ce563031e6b2ec91479f6af8c326d25c15bdb26 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884: e7a767430515c3a6e8aee91c2a68cba8b06fe884
  xe-pw-158157v1: 158157v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/index.html

[-- Attachment #2: Type: text/html, Size: 2539 bytes --]

✓ Xe.CI.Full: success for Enable/Disable DC balance along with VRR DSB

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 56419 bytes --]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/158157/
State : success

== Summary ==

CI Bug Log - changes from xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884_FULL -> xe-pw-158157v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-158157v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][1] ([Intel XE#1407]) +1 other test skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-adlp:         NOTRUN -> [SKIP][2] ([Intel XE#1124]) +6 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-adlp:         NOTRUN -> [FAIL][3] ([Intel XE#1231])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-adlp:         [PASS][4] -> [FAIL][5] ([Intel XE#1231])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-180:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#1124])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-adlp:         NOTRUN -> [FAIL][7] ([Intel XE#1874])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#1124])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#2191])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
    - shard-adlp:         NOTRUN -> [SKIP][11] ([Intel XE#2191])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][12] ([Intel XE#455] / [Intel XE#787]) +9 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#2887]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_ccs@bad-aux-stride-y-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][14] ([Intel XE#3442])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#3432])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][17] ([Intel XE#787]) +6 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][18] ([Intel XE#787]) +14 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2724])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-adlp:         NOTRUN -> [SKIP][20] ([Intel XE#306])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@kms_chamelium_color@ctm-red-to-blue.html
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#306])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-adlp:         NOTRUN -> [SKIP][22] ([Intel XE#373]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#373]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2252])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#307])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@suspend-resume@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][26] ([Intel XE#1178]) +1 other test fail
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@kms_content_protection@suspend-resume@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-rapid-movement-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#1424])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-2:
    - shard-bmg:          [PASS][28] -> [ABORT][29] ([Intel XE#6675])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-1/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-2.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-8/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-2.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#309]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-adlp:         NOTRUN -> [SKIP][31] ([Intel XE#309]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#2244])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-adlp:         NOTRUN -> [SKIP][33] ([Intel XE#4422])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          [PASS][34] -> [SKIP][35] ([Intel XE#2373])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-5/igt@kms_feature_discovery@display-2x.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2316])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-bmg:          [PASS][37] -> [SKIP][38] ([Intel XE#2316]) +6 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-8/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-adlp:         NOTRUN -> [SKIP][39] ([Intel XE#310]) +4 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#1421]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-lnl:          [PASS][41] -> [FAIL][42] ([Intel XE#301])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#1397] / [Intel XE#1745])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#1397])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][45] ([Intel XE#455]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x:
    - shard-adlp:         [PASS][46] -> [FAIL][47] ([Intel XE#1874]) +1 other test fail
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#651]) +2 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][49] ([Intel XE#656]) +11 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
    - shard-adlp:         NOTRUN -> [FAIL][50] ([Intel XE#5671])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-dg2-set2:     NOTRUN -> [ABORT][51] ([Intel XE#6675])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-pgflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#651])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][53] ([Intel XE#651]) +5 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#656]) +8 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-adlp:         NOTRUN -> [SKIP][55] ([Intel XE#653]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#1469])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][57] ([Intel XE#6312])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2312]) +2 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_hdmi_inject@inject-4k:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#1470])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_hdmi_inject@inject-4k.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-bmg:          [PASS][60] -> [ABORT][61] ([Intel XE#6662]) +2 other tests abort
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-4/igt@kms_hdr@bpc-switch-dpms.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-7/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@bpc-switch@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [ABORT][62] ([Intel XE#6662])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-7/igt@kms_hdr@bpc-switch@pipe-a-dp-2.html

  * igt@kms_hdr@static-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#1503])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#3012])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-adlp:         NOTRUN -> [SKIP][65] ([Intel XE#455]) +10 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [PASS][66] -> [SKIP][67] ([Intel XE#4596])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-8/igt@kms_plane_multiple@2x-tiling-4.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@tiling-4:
    - shard-adlp:         NOTRUN -> [SKIP][68] ([Intel XE#5020])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-1/igt@kms_plane_multiple@tiling-4.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#6691]) +3 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-adlp:         NOTRUN -> [FAIL][70] ([Intel XE#718])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@legacy-planes@plane-43:
    - shard-adlp:         [PASS][71] -> [DMESG-WARN][72] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-8/igt@kms_pm_rpm@legacy-planes@plane-43.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@kms_pm_rpm@legacy-planes@plane-43.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#1406] / [Intel XE#2893]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
    - shard-adlp:         NOTRUN -> [SKIP][75] ([Intel XE#1406] / [Intel XE#1489])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-psr-primary-page-flip:
    - shard-adlp:         NOTRUN -> [SKIP][77] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_psr@fbc-psr-primary-page-flip.html

  * igt@kms_psr@fbc-psr2-no-drrs:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#1406]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_psr@fbc-psr2-no-drrs.html

  * igt@kms_psr@fbc-psr2-no-drrs@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#1406] / [Intel XE#4609])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_psr@fbc-psr2-no-drrs@edp-1.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-adlp:         NOTRUN -> [SKIP][80] ([Intel XE#3414])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-bmg:          [PASS][81] -> [SKIP][82] ([Intel XE#1435])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-8/igt@kms_setmode@clone-exclusive-crtc.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-6/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#1435])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-adlp:         [PASS][84] -> [ABORT][85] ([Intel XE#6675]) +2 other tests abort
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-1/igt@kms_vblank@ts-continuation-dpms-suspend.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-1/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][86] ([Intel XE#4488])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-436/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-dp-4.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-bmg:          NOTRUN -> [ABORT][87] ([Intel XE#6675]) +3 other tests abort
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@kms_vblank@ts-continuation-suspend.html

  * igt@kms_vrr@lobf:
    - shard-adlp:         NOTRUN -> [SKIP][88] ([Intel XE#2168])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@kms_vrr@lobf.html

  * igt@xe_ccs@suspend-resume:
    - shard-adlp:         NOTRUN -> [SKIP][89] ([Intel XE#455] / [Intel XE#488] / [Intel XE#5607])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_ccs@suspend-resume.html

  * igt@xe_compute_preempt@compute-preempt-many:
    - shard-dg2-set2:     NOTRUN -> [SKIP][90] ([Intel XE#6360])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@xe_compute_preempt@compute-preempt-many.html

  * igt@xe_copy_basic@mem-page-copy-17:
    - shard-adlp:         NOTRUN -> [SKIP][91] ([Intel XE#5300])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-1/igt@xe_copy_basic@mem-page-copy-17.html

  * igt@xe_eu_stall@invalid-gt-id:
    - shard-adlp:         NOTRUN -> [SKIP][92] ([Intel XE#5626])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@xe_eu_stall@invalid-gt-id.html

  * igt@xe_eudebug@attach-debug-metadata:
    - shard-adlp:         NOTRUN -> [SKIP][93] ([Intel XE#4837] / [Intel XE#5565]) +3 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_eudebug@attach-debug-metadata.html

  * igt@xe_eudebug_online@resume-one:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#4837]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_eudebug_online@resume-one.html

  * igt@xe_eudebug_online@set-breakpoint-faultable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][95] ([Intel XE#4837])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@xe_eudebug_online@set-breakpoint-faultable.html

  * igt@xe_evict@evict-cm-threads-large-multi-vm:
    - shard-adlp:         NOTRUN -> [SKIP][96] ([Intel XE#261])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_evict@evict-cm-threads-large-multi-vm.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd:
    - shard-adlp:         NOTRUN -> [SKIP][97] ([Intel XE#688]) +1 other test skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#688]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd.html

  * igt@xe_exec_basic@multigpu-no-exec-rebind:
    - shard-adlp:         NOTRUN -> [SKIP][99] ([Intel XE#1392] / [Intel XE#5575]) +3 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@xe_exec_basic@multigpu-no-exec-rebind.html

  * igt@xe_exec_basic@multigpu-once-null:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#1392]) +2 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_exec_basic@multigpu-once-null.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-prefetch:
    - shard-adlp:         NOTRUN -> [SKIP][101] ([Intel XE#288] / [Intel XE#5561]) +10 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-prefetch.html

  * igt@xe_exec_system_allocator@many-stride-mmap-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][102] ([Intel XE#4943]) +4 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_exec_system_allocator@many-stride-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
    - shard-lnl:          NOTRUN -> [FAIL][103] ([Intel XE#5625])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html

  * igt@xe_exec_system_allocator@process-many-execqueues-free-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][104] ([Intel XE#4915]) +28 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@xe_exec_system_allocator@process-many-execqueues-free-race.html

  * igt@xe_exec_system_allocator@process-many-execqueues-mmap-nomemset:
    - shard-adlp:         NOTRUN -> [SKIP][105] ([Intel XE#4915]) +105 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@xe_exec_system_allocator@process-many-execqueues-mmap-nomemset.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-lnl:          NOTRUN -> [ABORT][106] ([Intel XE#5466])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_gt_freq@freq_suspend:
    - shard-adlp:         NOTRUN -> [ABORT][107] ([Intel XE#6675])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@xe_gt_freq@freq_suspend.html
    - shard-lnl:          NOTRUN -> [SKIP][108] ([Intel XE#584])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_gt_freq@freq_suspend.html

  * igt@xe_mmap@pci-membarrier-bad-pagesize:
    - shard-lnl:          NOTRUN -> [SKIP][109] ([Intel XE#5100])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_mmap@pci-membarrier-bad-pagesize.html

  * igt@xe_module_load@load:
    - shard-adlp:         ([PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134]) -> ([PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [SKIP][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160]) ([Intel XE#378] / [Intel XE#5612])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-4/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-4/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-4/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-3/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-4/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-1/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-1/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-1/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-1/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-9/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-6/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-9/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-8/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-8/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-6/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-8/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-9/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-9/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-6/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-2/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-2/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-2/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-3/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-3/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-2/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-6/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-1/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-9/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-6/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-9/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-4/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-4/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-8/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-1/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-6/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-9/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-6/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-4/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-2/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-2/igt@xe_module_load@load.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-2/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-1/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-1/igt@xe_module_load@load.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_module_load@load.html

  * igt@xe_oa@mmio-triggered-reports-read:
    - shard-adlp:         NOTRUN -> [SKIP][161] ([Intel XE#6032])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_oa@mmio-triggered-reports-read.html

  * igt@xe_oa@oa-tlb-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][162] ([Intel XE#2248])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_oa@oa-tlb-invalidate.html

  * igt@xe_oa@syncs-syncobj-wait-cfg:
    - shard-adlp:         NOTRUN -> [SKIP][163] ([Intel XE#3573])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_oa@syncs-syncobj-wait-cfg.html

  * igt@xe_pm@d3hot-mmap-vram:
    - shard-bmg:          [PASS][164] -> [FAIL][165] ([Intel XE#6548])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-5/igt@xe_pm@d3hot-mmap-vram.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-6/igt@xe_pm@d3hot-mmap-vram.html

  * igt@xe_pmu@engine-activity-accuracy-50:
    - shard-lnl:          [PASS][166] -> [FAIL][167] ([Intel XE#6251]) +1 other test fail
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-50.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-4/igt@xe_pmu@engine-activity-accuracy-50.html

  * igt@xe_pmu@fn-engine-activity-load:
    - shard-dg2-set2:     NOTRUN -> [SKIP][168] ([Intel XE#4650])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@xe_pmu@fn-engine-activity-load.html

  * igt@xe_pxp@pxp-optout:
    - shard-adlp:         NOTRUN -> [SKIP][169] ([Intel XE#4733] / [Intel XE#5594])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-3/igt@xe_pxp@pxp-optout.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-rpm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][170] ([Intel XE#4733])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@xe_pxp@pxp-stale-bo-bind-post-rpm.html

  * igt@xe_sriov_auto_provisioning@selfconfig-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][171] ([Intel XE#4130])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-463/igt@xe_sriov_auto_provisioning@selfconfig-basic.html

  * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs:
    - shard-lnl:          NOTRUN -> [SKIP][172] ([Intel XE#4130])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs.html

  
#### Possible fixes ####

  * igt@kms_cursor_edge_walk@256x256-left-edge:
    - shard-bmg:          [FAIL][173] -> [PASS][174]
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-2/igt@kms_cursor_edge_walk@256x256-left-edge.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-1/igt@kms_cursor_edge_walk@256x256-left-edge.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-bmg:          [SKIP][175] ([Intel XE#2291]) -> [PASS][176] +3 other tests pass
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][177] ([Intel XE#5299]) -> [PASS][178]
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-bmg:          [SKIP][179] ([Intel XE#2316]) -> [PASS][180] +1 other test pass
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-1/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][181] ([Intel XE#301]) -> [PASS][182]
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [FAIL][183] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][184]
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y:
    - shard-adlp:         [FAIL][185] ([Intel XE#1874]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1:
    - shard-adlp:         [ABORT][187] ([Intel XE#6675]) -> [PASS][188] +3 other tests pass
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-6/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-2/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1.html

  * igt@xe_exec_system_allocator@processes-evict-malloc:
    - shard-bmg:          [ABORT][189] ([Intel XE#3970]) -> [PASS][190]
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-5/igt@xe_exec_system_allocator@processes-evict-malloc.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@xe_exec_system_allocator@processes-evict-malloc.html

  * igt@xe_pm@s3-multiple-execs:
    - shard-bmg:          [ABORT][191] ([Intel XE#6675]) -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-6/igt@xe_pm@s3-multiple-execs.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-1/igt@xe_pm@s3-multiple-execs.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-lnl:          [ABORT][193] ([Intel XE#6675]) -> [PASS][194]
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-lnl-4/igt@xe_pm@s4-vm-bind-userptr.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-2/igt@xe_pm@s4-vm-bind-userptr.html

  
#### Warnings ####

  * igt@kms_content_protection@legacy:
    - shard-bmg:          [FAIL][195] ([Intel XE#1178]) -> [SKIP][196] ([Intel XE#2341])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-5/igt@kms_content_protection@legacy.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-6/igt@kms_content_protection@legacy.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][197] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][198] ([Intel XE#301])
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][199] ([Intel XE#2311]) -> [SKIP][200] ([Intel XE#2312]) +7 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][201] ([Intel XE#4141]) -> [SKIP][202] ([Intel XE#2312]) +3 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt:
    - shard-bmg:          [SKIP][203] ([Intel XE#2312]) -> [SKIP][204] ([Intel XE#4141])
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt:
    - shard-bmg:          [SKIP][205] ([Intel XE#2312]) -> [SKIP][206] ([Intel XE#2311]) +6 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][207] ([Intel XE#2313]) -> [SKIP][208] ([Intel XE#2312]) +11 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][209] ([Intel XE#2312]) -> [SKIP][210] ([Intel XE#2313]) +7 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-adlp:         [ABORT][211] ([Intel XE#6675]) -> [ABORT][212] ([Intel XE#2953] / [Intel XE#6675]) +1 other test abort
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-adlp-6/igt@kms_plane@plane-panning-bottom-right-suspend.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-adlp-2/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][213] ([Intel XE#2426]) -> [FAIL][214] ([Intel XE#1729])
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
    - shard-dg2-set2:     [SKIP][215] ([Intel XE#362]) -> [FAIL][216] ([Intel XE#1729])
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][217] ([Intel XE#2509]) -> [SKIP][218] ([Intel XE#2426])
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2248]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2248
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4488
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
  [Intel XE#5607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5607
  [Intel XE#5612]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5612
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#5671]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5671
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#6548]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6548
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6662]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6662
  [Intel XE#6675]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6675
  [Intel XE#6691]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6691
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929


Build changes
-------------

  * Linux: xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884 -> xe-pw-158157v1

  IGT_8639: 2ce563031e6b2ec91479f6af8c326d25c15bdb26 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4156-e7a767430515c3a6e8aee91c2a68cba8b06fe884: e7a767430515c3a6e8aee91c2a68cba8b06fe884
  xe-pw-158157v1: 158157v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158157v1/index.html

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