[PATCH v3 00/24] drm/xe: Add Xe3p support

[PATCH v3 00/24] drm/xe: Add Xe3p support

[Lucas De Marchi]

This begins the support for the Xe3p arch - it contains generic support
for graphics version 35 and the Xe3p_xpc IP, the Xe3p_LPM IP for media
and support for Nova Lake S (NVL-S), that uses a mix of IPs - the
display side for NVL-S will be submitted separately.

Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Changes in v3:
- Add more patches for irq refactors as discussed in v2
- Fix vecs irqs from v2
- s/Xe3p_LPM/Xe3p_HPM/ where appropriate
- Some other changes, mentioned in the individual commits
- Link to v2: https://lore.kernel.org/r/20251015-xe3p-v2-0-b9189b3056a2@intel.com

Changes in v2:
- Rebase on latest drm-tip as some interfaces changed like the device
  flags location and RTP helper signature
- Drop patches to handle app transient and additional flushes as they
  are not currently used
- Drop patches to handle main gam control - they are actually correct,
  but having a spec reference to embed in the commit message is
  preferred
- Add 2 patches to refactor irq enabling on hw engines so we don blindly
  set bits intended for one engine class in another.
- Some other changes, mentioned in the individual commits
- Link to v1: https://lore.kernel.org/r/20251013-xe3p-v1-0-bfb74f038215@intel.com
---
Balasubramani Vivekanandan (3):
      drm/xe: Drop CTC_MODE register read
      drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs
      drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

Dnyaneshwar Bhadane (1):
      drm/xe/nvls: Attach MOCS table for NVL-S

Fei Yang (1):
      drm/xe/xe3p_xpc: Add L3 bank mask

Harish Chegondi (1):
      drm/xe/xe3p: Add xe3p EU stall data format

Lucas De Marchi (6):
      drm/xe: Add GT_VER() to check version specific to gt type
      drm/xe/irq: Rename fuse mask variables
      drm/xe/irq: Split irq mask per engine class
      drm/xe/irq: Rename bits used with all engines
      drm/xe/irq: Check fuse mask for media engines
      drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

Matt Roper (8):
      drm/xe/xe3p_lpm: Handle MCR steering
      drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting
      drm/xe/xe3p: Determine service copy availability from fuse
      drm/xe/nvl: Define NVL-S platform
      drm/xe/nvls: Define GuC firmware for NVL-S
      drm/xe/xe3p_xpc: Add MCR steering
      drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs
      drm/xe/xe3p_xpc: Setup PAT table

Shekhar Chauhan (2):
      drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05
      drm/xe/xe3p: Add support for media IP versions 35.00 & 35.03

Wang Xin (2):
      drm/xe: Dump CURRENT_LRCA register
      drm/xe/xe3p: Dump CSMQDEBUG register

 drivers/gpu/drm/xe/regs/xe_engine_regs.h |   4 ++
 drivers/gpu/drm/xe/regs/xe_gt_regs.h     |   7 +-
 drivers/gpu/drm/xe/regs/xe_irq_regs.h    |   8 ++-
 drivers/gpu/drm/xe/xe_eu_stall.c         |  28 +++++++-
 drivers/gpu/drm/xe/xe_gt.h               |   6 ++
 drivers/gpu/drm/xe/xe_gt_clock.c         |  19 -----
 drivers/gpu/drm/xe/xe_gt_mcr.c           |  67 +++++++++++++++--
 drivers/gpu/drm/xe/xe_gt_topology.c      |   6 +-
 drivers/gpu/drm/xe/xe_gt_types.h         |  15 ++++
 drivers/gpu/drm/xe/xe_guc_capture.c      |  29 +++++++-
 drivers/gpu/drm/xe/xe_hw_engine.c        |  52 +++++++++++---
 drivers/gpu/drm/xe/xe_irq.c              | 120 +++++++++++++++++++++----------
 drivers/gpu/drm/xe/xe_memirq.c           |   4 +-
 drivers/gpu/drm/xe/xe_mocs.c             |   1 +
 drivers/gpu/drm/xe/xe_oa.c               |   3 +-
 drivers/gpu/drm/xe/xe_pat.c              |  96 ++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_pci.c              |  24 +++++++
 drivers/gpu/drm/xe/xe_platform_types.h   |   1 +
 drivers/gpu/drm/xe/xe_rtp.c              |   7 ++
 drivers/gpu/drm/xe/xe_rtp.h              |  12 ++++
 drivers/gpu/drm/xe/xe_tuning.c           |   9 ++-
 drivers/gpu/drm/xe/xe_uc_fw.c            |   1 +
 drivers/gpu/drm/xe/xe_wa.c               |   6 +-
 drivers/gpu/drm/xe/xe_wa_oob.rules       |   9 +--
 include/drm/intel/pciids.h               |   9 +++
 25 files changed, 448 insertions(+), 95 deletions(-)

base-commit: e919806d9a23ee1c2611792492289a170be4cf9d
change-id: 20251013-xe3p-81bb749e9de0

Lucas De Marchi

[PATCH v3 01/24] drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05

[Lucas De Marchi]

From: Shekhar Chauhan <shekhar.chauhan@intel.com>

Add graphics IP versions 30.04 & 30.05 and initial workarounds for these
IP versions.

BSpec: 74201
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Merge graphics range together (Shekhar, Matt Roper)
---
 drivers/gpu/drm/xe/xe_pci.c        | 2 ++
 drivers/gpu/drm/xe/xe_wa.c         | 6 +++---
 drivers/gpu/drm/xe/xe_wa_oob.rules | 9 +++++----
 3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 24a38904bb508..3ea8ccfcbca55 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -136,6 +136,8 @@ static const struct xe_ip graphics_ips[] = {
 	{ 3000, "Xe3_LPG", &graphics_xe2 },
 	{ 3001, "Xe3_LPG", &graphics_xe2 },
 	{ 3003, "Xe3_LPG", &graphics_xe2 },
+	{ 3004, "Xe3_LPG", &graphics_xe2 },
+	{ 3005, "Xe3_LPG", &graphics_xe2 },
 };
 
 /* Pre-GMDID Media IPs */
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index aa1b69f48f6f9..b6dcd9827354d 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -684,7 +684,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	},
 	{ XE_RTP_NAME("13012615864"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR,
-		       GRAPHICS_VERSION(3003),
+		       GRAPHICS_VERSION_RANGE(3003, 3005),
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
 	},
@@ -695,7 +695,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 	},
 	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(3003), FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
 	},
 	{ XE_RTP_NAME("18041344222"),
@@ -913,7 +913,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 			     DIS_AUTOSTRIP))
 	},
 	{ XE_RTP_NAME("22021007897"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3003), ENGINE_CLASS(RENDER)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
 	},
 };
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 4bb94e5799ed6..fb38eb3d6e9a3 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -33,14 +33,15 @@
 13011645652	GRAPHICS_VERSION(2004)
 		GRAPHICS_VERSION_RANGE(3000, 3001)
 		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3004, 3005)
 14022293748	GRAPHICS_VERSION_RANGE(2001, 2002)
 		GRAPHICS_VERSION(2004)
-		GRAPHICS_VERSION_RANGE(3000, 3001)
-		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3000, 3005)
 22019794406	GRAPHICS_VERSION_RANGE(2001, 2002)
 		GRAPHICS_VERSION(2004)
 		GRAPHICS_VERSION_RANGE(3000, 3001)
 		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3004, 3005)
 22019338487	MEDIA_VERSION(2000)
 		GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_not_sriov_vf)
 		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_not_sriov_vf)
@@ -61,11 +62,11 @@
 16023105232	GRAPHICS_VERSION_RANGE(2001, 3001)
 		MEDIA_VERSION_RANGE(1301, 3000)
 		MEDIA_VERSION(3002)
-		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3003, 3005)
 16026508708	GRAPHICS_VERSION_RANGE(1200, 3001)
 		MEDIA_VERSION_RANGE(1300, 3000)
 		MEDIA_VERSION(3002)
-		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3003, 3005)
 14020001231	GRAPHICS_VERSION_RANGE(2001,2004), FUNC(xe_rtp_match_psmi_enabled)
 		MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
 		MEDIA_VERSION(3000), FUNC(xe_rtp_match_psmi_enabled)

-- 
2.51.0

[PATCH v3 02/24] drm/xe/xe3p: Add support for media IP versions 35.00 & 35.03

[Lucas De Marchi]

From: Shekhar Chauhan <shekhar.chauhan@intel.com>

Xe3p_LPM/Xe3p_HPM are very similar to Xe3_LPM on the kmd interface, so it can use
the same descriptor structure. Add both 35.00 and 35.03 IP versions.

BSpec: 74201, 74202, 77977, 77979
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Fix 35.03 IP name (Gustavo)
---
 drivers/gpu/drm/xe/xe_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 3ea8ccfcbca55..fac46178cebba 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -151,6 +151,8 @@ static const struct xe_ip media_ips[] = {
 	{ 2000, "Xe2_LPM", &media_xelpmp },
 	{ 3000, "Xe3_LPM", &media_xelpmp },
 	{ 3002, "Xe3_LPM", &media_xelpmp },
+	{ 3500, "Xe3p_LPM", &media_xelpmp },
+	{ 3503, "Xe3p_HPM", &media_xelpmp },
 };
 
 static const struct xe_device_desc tgl_desc = {

-- 
2.51.0

[PATCH v3 03/24] drm/xe: Drop CTC_MODE register read

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

The warning was added for a condition that never triggered even for
platforms prior to Xe2. It's not supported in Xe2 and in Xe3p the
register is removed from the main GT. Just drop the entire function as
it doesn't bring any benefit.

Bspec: 62395
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
[ Drop the entire check for CTC_MODE ]
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h |  4 ----
 drivers/gpu/drm/xe/xe_gt_clock.c     | 19 -------------------
 2 files changed, 23 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 51f2a03847f9d..21c15441c4537 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -346,10 +346,6 @@
 #define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
 #define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))
 
-#define CTC_MODE				XE_REG(0xa26c)
-#define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
-#define   CTC_SOURCE_DIVIDE_LOGIC		REG_BIT(0)
-
 #define FORCEWAKE_RENDER			XE_REG(0xa278)
 
 #define POWERGATE_DOMAIN_STATUS			XE_REG(0xa2a0)
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index 4f011d1573c65..00f5972c14dc5 100644
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -55,30 +55,11 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
 	}
 }
 
-static void check_ctc_mode(struct xe_gt *gt)
-{
-	/*
-	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
-	 * platforms.  In theory it could be a valid setting for pre-Xe2
-	 * platforms, but there's no documentation on how to properly handle
-	 * this case.  Reading TIMESTAMP_OVERRIDE, as the driver attempted in
-	 * the past has been confirmed as incorrect by the hardware architects.
-	 *
-	 * For now just warn if we ever encounter hardware in the wild that
-	 * has this setting and move on as if it hadn't been set.
-	 */
-	if (xe_mmio_read32(&gt->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC)
-		xe_gt_warn(gt, "CTC_MODE[0] is set; this is unexpected and undocumented\n");
-}
-
 int xe_gt_clock_init(struct xe_gt *gt)
 {
 	u32 freq;
 	u32 c0;
 
-	if (!IS_SRIOV_VF(gt_to_xe(gt)))
-		check_ctc_mode(gt);
-
 	c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);
 	read_crystal_clock(gt, c0, &freq, &gt->info.timestamp_base);
 

-- 
2.51.0

[PATCH v3 04/24] drm/xe: Add GT_VER() to check version specific to gt type

[Lucas De Marchi]

In some situations we will need to check the version of the specific gt
being passed as argument, not if the device has a certain graphics/media
version.

This is extracted from a patch by Balasubramani Vivekanandan that
may need some rework, but this helper is still useful for other enabling
parts of Xe3p.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
index 5df2ffe3ff838..9d710049da455 100644
--- a/drivers/gpu/drm/xe/xe_gt.h
+++ b/drivers/gpu/drm/xe/xe_gt.h
@@ -22,6 +22,12 @@
 
 #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
 
+#define GT_VER(gt) ({ \
+	typeof(gt) gt_ = (gt); \
+	struct xe_device *xe = gt_to_xe(gt_); \
+	xe_gt_is_media_type(gt_) ? MEDIA_VER(xe) : GRAPHICS_VER(xe); \
+})
+
 extern struct fault_attr gt_reset_failure;
 static inline bool xe_fault_inject_gt_reset(void)
 {

-- 
2.51.0

[PATCH v3 05/24] drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

IP version 35 has removed "NOA Enable Signal" bit from RPM_CONFIG1
register. Skip clearing that bit on unsupported IPs.

Bspec: 62391
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index a4894eb0d7f3f..f901ba52b4032 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -837,7 +837,8 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
 		xe_oa_configure_oa_context(stream, false);
 
 	/* Make sure we disable noa to save power. */
-	xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);
+	if (GT_VER(stream->gt) < 35)
+		xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);
 
 	sqcnt1 = SQCNT1_PMON_ENABLE |
 		 (HAS_OA_BPC_REPORTING(stream->oa->xe) ? SQCNT1_OABPC : 0);

-- 
2.51.0

[PATCH v3 06/24] drm/xe/xe3p_lpm: Handle MCR steering

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_LPM's MCR steering has the same ranges and behavior as Xe3_LPM.
However one register range that was reserved on Xe3_LPM has now become a
unicast range (0x384200-0x38427F), so we need to stop consolidating the
adjacent MCR ranges into a single table entry in the table.  With this
change to the Xe3_LPM table, we can continue to use the same table for
both IP families.

While we're touching this table, take the opportunity to fix a
whitespace mistake and clarify that one of the other consolidated range
entries includes a reserved range.

Bspec: 76445
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_mcr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 8fb1cae917244..e1a2b38fc2a86 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -236,12 +236,13 @@ static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {
 };
 
 static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
-	{ 0x384000, 0x3847DF },         /* GAM, rsvd, GAM */
+	{ 0x384000, 0x3841FF },         /* GAM */
+	{ 0x384400, 0x3847DF },         /* GAM */
 	{ 0x384900, 0x384AFF },         /* GAM */
 	{ 0x389560, 0x3895FF },         /* MEDIAINF */
 	{ 0x38B600, 0x38B8FF },         /* L3BANK */
 	{ 0x38C800, 0x38D07F },         /* GAM, MEDIAINF */
-	{ 0x38D0D0, 0x38F0FF },		/* MEDIAINF, GAM */
+	{ 0x38D0D0, 0x38F0FF },         /* MEDIAINF, rsvd, GAM */
 	{ 0x393C00, 0x393C7F },         /* MEDIAINF */
 	{},
 };

-- 
2.51.0

[PATCH v3 07/24] drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Since the hardware load balancing is no longer supported, the
programming in RCU_MODE is no longer necessary.

Bspec: 60382
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index cba4375525c7e..b08a6d42c8ffc 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -350,6 +350,13 @@ static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_device *xe,
 						 const struct xe_gt *gt,
 						 const struct xe_hw_engine *hwe)
 {
+	/*
+	 * Xe3p no longer supports load balance mode, so "fixed cslice" mode
+	 * is automatic and no RCU_MODE programming is required.
+	 */
+	if (GRAPHICS_VER(gt_to_xe(gt)) >= 35)
+		return false;
+
 	return xe_gt_ccs_mode_enabled(gt) &&
 	       xe_rtp_match_first_render_or_compute(xe, gt, hwe);
 }

-- 
2.51.0

[PATCH v3 08/24] drm/xe/xe3p: Determine service copy availability from fuse

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p introduces a dedicated SERVICE_COPY_ENABLE fuse register to reflect
the availability of the service copy engines (BCS1-BCS8).

Bspec: 74624
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
 drivers/gpu/drm/xe/xe_hw_engine.c    | 43 ++++++++++++++++++++++++++++--------
 2 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 21c15441c4537..228de47c0f3f5 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -239,6 +239,9 @@
 #define XE2_GT_GEOMETRY_DSS_1			XE_REG(0x9150)
 #define XE2_GT_GEOMETRY_DSS_2			XE_REG(0x9154)
 
+#define SERVICE_COPY_ENABLE			XE_REG(0x9170)
+#define   FUSE_SERVICE_COPY_ENABLE_MASK		REG_GENMASK(7, 0)
+
 #define GDRST					XE_REG(0x941c)
 #define   GRDOM_GUC				REG_BIT(3)
 #define   GRDOM_FULL				REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index b08a6d42c8ffc..073ecd263e543 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -718,27 +718,52 @@ static void read_media_fuses(struct xe_gt *gt)
 	}
 }
 
+static u32 infer_svccopy_from_meml3(struct xe_gt *gt)
+{
+	u32 meml3 = REG_FIELD_GET(MEML3_EN_MASK,
+				  xe_mmio_read32(&gt->mmio, MIRROR_FUSE3));
+	u32 svccopy_mask = 0;
+
+	/*
+	 * Each of the four meml3 bits determines the fusing of two service
+	 * copy engines.
+	 */
+	for (int i = 0; i < 4; i++)
+		svccopy_mask |= (meml3 & BIT(i)) ? 0b11 << 2 * i : 0;
+
+	return svccopy_mask;
+}
+
+static u32 read_svccopy_fuses(struct xe_gt *gt)
+{
+	return REG_FIELD_GET(FUSE_SERVICE_COPY_ENABLE_MASK,
+			     xe_mmio_read32(&gt->mmio, SERVICE_COPY_ENABLE));
+}
+
 static void read_copy_fuses(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
 	u32 bcs_mask;
 
-	if (GRAPHICS_VERx100(xe) < 1260 || GRAPHICS_VERx100(xe) >= 1270)
-		return;
-
 	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
 
-	bcs_mask = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3);
-	bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
+	if (GRAPHICS_VER(xe) >= 35)
+		bcs_mask = read_svccopy_fuses(gt);
+	else if (GRAPHICS_VERx100(xe) == 1260)
+		bcs_mask = infer_svccopy_from_meml3(gt);
+	else
+		return;
 
-	/* BCS0 is always present; only BCS1-BCS8 may be fused off */
-	for (int i = XE_HW_ENGINE_BCS1, j = 0; i <= XE_HW_ENGINE_BCS8; ++i, ++j) {
+	/* Only BCS1-BCS8 may be fused off */
+	bcs_mask <<= XE_HW_ENGINE_BCS1;
+	for (int i = XE_HW_ENGINE_BCS1; i <= XE_HW_ENGINE_BCS8; ++i) {
 		if (!(gt->info.engine_mask & BIT(i)))
 			continue;
 
-		if (!(BIT(j / 2) & bcs_mask)) {
+		if (!(bcs_mask & BIT(i))) {
 			gt->info.engine_mask &= ~BIT(i);
-			xe_gt_info(gt, "bcs%u fused off\n", j);
+			xe_gt_info(gt, "bcs%u fused off\n",
+				   i - XE_HW_ENGINE_BCS0);
 		}
 	}
 }

-- 
2.51.0

[PATCH v3 09/24] drm/xe: Dump CURRENT_LRCA register

[Lucas De Marchi]

From: Wang Xin <x.wang@intel.com>

Add CURRENT_LRCA to register dump to help debugging.

Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Wang Xin <x.wang@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Extract CURRENT_LRCA from other patch dumping xe3p-specific register
    (Matt Roper)
v3: Drop bit definition that is not used now (Matt Roper)
---
 drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 ++
 drivers/gpu/drm/xe/xe_guc_capture.c      | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index f4c3e1187a00a..0c02d0fe55315 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -141,6 +141,8 @@
 #define   INHIBIT_SWITCH_UNTIL_PREEMPTED	REG_BIT(31)
 #define   IDLE_DELAY				REG_GENMASK(20, 0)
 
+#define RING_CURRENT_LRCA(base)			XE_REG((base) + 0x240)
+
 #define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
 #define	  CTX_CTRL_PXP_ENABLE			REG_BIT(10)
 #define	  CTX_CTRL_OAC_CONTEXT_ENABLE		REG_BIT(8)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 243dad3e24185..8d1bfa2cdb151 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -122,6 +122,7 @@ struct __guc_capture_parsed_output {
 	{ RING_IPEHR(0),		REG_32BIT,	0,	0,	0,	"IPEHR"}, \
 	{ RING_INSTDONE(0),		REG_32BIT,	0,	0,	0,	"RING_INSTDONE"}, \
 	{ INDIRECT_RING_STATE(0),	REG_32BIT,	0,	0,	0,	"INDIRECT_RING_STATE"}, \
+	{ RING_CURRENT_LRCA(0),		REG_32BIT,	0,	0,	0,	"CURRENT_LRCA"}, \
 	{ RING_ACTHD(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
 	{ RING_ACTHD_UDW(0),		REG_64BIT_HI_DW, 0,	0,	0,	"ACTHD"}, \
 	{ RING_BBADDR(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \

-- 
2.51.0

[PATCH v3 10/24] drm/xe/xe3p: Dump CSMQDEBUG register

[Lucas De Marchi]

From: Wang Xin <x.wang@intel.com>

The CSMQDEBUG is useful for the development of MQ feature. Start dumping
the debug register.

Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Wang Xin <x.wang@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2:
 - Extract CSMQDEBUG from other patch dumping multiple register (Matt
   Roper)
 - Simplify version check (Matt Roper)
 - Do not dump CSMQDEBUG for engines that do not support MQ (Matt Roper)
v3:
 - Drop desc structs not needed anymore, just use the one for previous
   platform (Matt Roper)
---
 drivers/gpu/drm/xe/regs/xe_engine_regs.h |  2 ++
 drivers/gpu/drm/xe/xe_guc_capture.c      | 28 +++++++++++++++++++++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 0c02d0fe55315..68172b0248a6e 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -155,6 +155,8 @@
 #define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)
 #define   GFX_MSIX_INTERRUPT_ENABLE		REG_BIT(13)
 
+#define RING_CSMQDEBUG(base)			XE_REG((base) + 0x2b0)
+
 #define RING_TIMESTAMP(base)			XE_REG((base) + 0x358)
 
 #define RING_TIMESTAMP_UDW(base)		XE_REG((base) + 0x358 + 4)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 8d1bfa2cdb151..0c1fbe97b8bf2 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -150,6 +150,9 @@ struct __guc_capture_parsed_output {
 	{ SFC_DONE(2),			0,	0,	0,	0,	"SFC_DONE[2]"}, \
 	{ SFC_DONE(3),			0,	0,	0,	0,	"SFC_DONE[3]"}
 
+#define XE3P_BASE_ENGINE_INSTANCE \
+	{ RING_CSMQDEBUG(0),		REG_32BIT,	0,	0,	0,	"CSMQDEBUG"}
+
 /* XE_LP Global */
 static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
 	COMMON_XELP_BASE_GLOBAL,
@@ -196,6 +199,12 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
 	COMMON_BASE_ENGINE_INSTANCE,
 };
 
+/* Render / Compute Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+	XE3P_BASE_ENGINE_INSTANCE,
+};
+
 /*
  * Empty list to prevent warnings about unknown class/instance types
  * as not all class/instance types have entries on all platforms.
@@ -246,6 +255,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = {
 	{}
 };
 
+ /* List of lists for Xe3p and beyond */
+static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
+	MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
+	MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
+	MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
+	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
+	MAKE_REGLIST(xe_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
+	MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
+	MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
+	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
+	MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
+	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+	MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+	{}
+};
 static const char * const capture_list_type_names[] = {
 	"Global",
 	"Class",
@@ -293,7 +317,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc,
 static const struct __guc_mmio_reg_descr_group *
 guc_capture_get_device_reglist(struct xe_device *xe)
 {
-	if (GRAPHICS_VERx100(xe) >= 1255)
+	if (GRAPHICS_VER(xe) >= 35)
+		return xe3p_lists;
+	else if (GRAPHICS_VERx100(xe) >= 1255)
 		return xe_hpg_lists;
 	else
 		return xe_lp_lists;

-- 
2.51.0

Re: [PATCH v3 10/24] drm/xe/xe3p: Dump CSMQDEBUG register

[Matt Roper]

On Thu, Oct 16, 2025 at 07:26:29PM -0700, Lucas De Marchi wrote:
> From: Wang Xin <x.wang@intel.com>
> 
> The CSMQDEBUG is useful for the development of MQ feature. Start dumping
> the debug register.
> 
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Wang Xin <x.wang@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
> v2:
>  - Extract CSMQDEBUG from other patch dumping multiple register (Matt
>    Roper)
>  - Simplify version check (Matt Roper)
>  - Do not dump CSMQDEBUG for engines that do not support MQ (Matt Roper)
> v3:
>  - Drop desc structs not needed anymore, just use the one for previous
>    platform (Matt Roper)
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  2 ++
>  drivers/gpu/drm/xe/xe_guc_capture.c      | 28 +++++++++++++++++++++++++++-
>  2 files changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 0c02d0fe55315..68172b0248a6e 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -155,6 +155,8 @@
>  #define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)
>  #define   GFX_MSIX_INTERRUPT_ENABLE		REG_BIT(13)
>  
> +#define RING_CSMQDEBUG(base)			XE_REG((base) + 0x2b0)
> +
>  #define RING_TIMESTAMP(base)			XE_REG((base) + 0x358)
>  
>  #define RING_TIMESTAMP_UDW(base)		XE_REG((base) + 0x358 + 4)
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 8d1bfa2cdb151..0c1fbe97b8bf2 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -150,6 +150,9 @@ struct __guc_capture_parsed_output {
>  	{ SFC_DONE(2),			0,	0,	0,	0,	"SFC_DONE[2]"}, \
>  	{ SFC_DONE(3),			0,	0,	0,	0,	"SFC_DONE[3]"}
>  
> +#define XE3P_BASE_ENGINE_INSTANCE \
> +	{ RING_CSMQDEBUG(0),		REG_32BIT,	0,	0,	0,	"CSMQDEBUG"}
> +
>  /* XE_LP Global */
>  static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
>  	COMMON_XELP_BASE_GLOBAL,
> @@ -196,6 +199,12 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
>  	COMMON_BASE_ENGINE_INSTANCE,
>  };
>  
> +/* Render / Compute Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +	XE3P_BASE_ENGINE_INSTANCE,
> +};
> +
>  /*
>   * Empty list to prevent warnings about unknown class/instance types
>   * as not all class/instance types have entries on all platforms.
> @@ -246,6 +255,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = {
>  	{}
>  };
>  
> + /* List of lists for Xe3p and beyond */
> +static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
> +	MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
> +	MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
> +	MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
> +	MAKE_REGLIST(xe_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
> +	MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> +	MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
> +	MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> +	MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> +	{}
> +};
>  static const char * const capture_list_type_names[] = {
>  	"Global",
>  	"Class",
> @@ -293,7 +317,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc,
>  static const struct __guc_mmio_reg_descr_group *
>  guc_capture_get_device_reglist(struct xe_device *xe)
>  {
> -	if (GRAPHICS_VERx100(xe) >= 1255)
> +	if (GRAPHICS_VER(xe) >= 35)
> +		return xe3p_lists;
> +	else if (GRAPHICS_VERx100(xe) >= 1255)
>  		return xe_hpg_lists;
>  	else
>  		return xe_lp_lists;
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v3 10/24] drm/xe/xe3p: Dump CSMQDEBUG register

[Summers, Stuart]

On Thu, 2025-10-16 at 19:26 -0700, Lucas De Marchi wrote:
> From: Wang Xin <x.wang@intel.com>
> 
> The CSMQDEBUG is useful for the development of MQ feature. Start
> dumping
> the debug register.
> 
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Wang Xin <x.wang@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> v2:
>  - Extract CSMQDEBUG from other patch dumping multiple register (Matt
>    Roper)
>  - Simplify version check (Matt Roper)
>  - Do not dump CSMQDEBUG for engines that do not support MQ (Matt
> Roper)
> v3:
>  - Drop desc structs not needed anymore, just use the one for
> previous
>    platform (Matt Roper)
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  2 ++
>  drivers/gpu/drm/xe/xe_guc_capture.c      | 28
> +++++++++++++++++++++++++++-
>  2 files changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 0c02d0fe55315..68172b0248a6e 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -155,6 +155,8 @@
>  #define   GFX_DISABLE_LEGACY_MODE              REG_BIT(3)
>  #define   GFX_MSIX_INTERRUPT_ENABLE            REG_BIT(13)
>  
> +#define RING_CSMQDEBUG(base)                   XE_REG((base) +
> 0x2b0)
> +
>  #define RING_TIMESTAMP(base)                   XE_REG((base) +
> 0x358)
>  
>  #define RING_TIMESTAMP_UDW(base)               XE_REG((base) + 0x358
> + 4)
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c
> b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 8d1bfa2cdb151..0c1fbe97b8bf2 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -150,6 +150,9 @@ struct __guc_capture_parsed_output {
>         {
> SFC_DONE(2),                  0,      0,      0,      0,      "SFC_DO
> NE[2]"}, \
>         {
> SFC_DONE(3),                  0,      0,      0,      0,      "SFC_DO
> NE[3]"}
>  
> +#define XE3P_BASE_ENGINE_INSTANCE \
> +       {
> RING_CSMQDEBUG(0),            REG_32BIT,      0,      0,      0,     
>  "CSMQDEBUG"}
> +
>  /* XE_LP Global */
>  static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
>         COMMON_XELP_BASE_GLOBAL,
> @@ -196,6 +199,12 @@ static const struct __guc_mmio_reg_descr
> xe_lp_gsc_inst_regs[] = {
>         COMMON_BASE_ENGINE_INSTANCE,
>  };
>  
> +/* Render / Compute Per-Engine-Instance */

Maybe I'm misreading your patch here, but MQ should be supported also
on blitter. Why are we only dumping this for render/compute?

Thanks,
Stuart

> +static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
> +       COMMON_BASE_ENGINE_INSTANCE,
> +       XE3P_BASE_ENGINE_INSTANCE,
> +};
> +
>  /*
>   * Empty list to prevent warnings about unknown class/instance types
>   * as not all class/instance types have entries on all platforms.
> @@ -246,6 +255,21 @@ static const struct __guc_mmio_reg_descr_group
> xe_hpg_lists[] = {
>         {}
>  };
>  
> + /* List of lists for Xe3p and beyond */
> +static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
> +       MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
> +       MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS,
> GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
> +       MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE,
> GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
> +       MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
> GUC_CAPTURE_LIST_CLASS_VIDEO),
> +       MAKE_REGLIST(xe_vd_inst_regs, PF, ENGINE_INSTANCE,
> GUC_CAPTURE_LIST_CLASS_VIDEO),
> +       MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS,
> GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> +       MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE,
> GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> +       MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
> GUC_CAPTURE_LIST_CLASS_BLITTER),
> +       MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE,
> GUC_CAPTURE_LIST_CLASS_BLITTER),
> +       MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
> GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> +       MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE,
> GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> +       {}
> +};
>  static const char * const capture_list_type_names[] = {
>         "Global",
>         "Class",
> @@ -293,7 +317,9 @@ guc_capture_remove_stale_matches_from_list(struct
> xe_guc_state_capture *gc,
>  static const struct __guc_mmio_reg_descr_group *
>  guc_capture_get_device_reglist(struct xe_device *xe)
>  {
> -       if (GRAPHICS_VERx100(xe) >= 1255)
> +       if (GRAPHICS_VER(xe) >= 35)
> +               return xe3p_lists;
> +       else if (GRAPHICS_VERx100(xe) >= 1255)
>                 return xe_hpg_lists;
>         else
>                 return xe_lp_lists;
> 

[PATCH v3 11/24] drm/xe/nvl: Define NVL-S platform

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Provide the basic platform definitions and PCI IDs for NVL-S.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Fix rebase on flags moving to the device descriptor (Gustavo)
---
 drivers/gpu/drm/xe/xe_pci.c            | 12 ++++++++++++
 drivers/gpu/drm/xe/xe_platform_types.h |  1 +
 include/drm/intel/pciids.h             |  9 +++++++++
 3 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index fac46178cebba..0546442e2a631 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -377,6 +377,17 @@ static const struct xe_device_desc ptl_desc = {
 	.vm_max_level = 4,
 };
 
+static const struct xe_device_desc nvls_desc = {
+	PLATFORM(NOVALAKE_S),
+	.dma_mask_size = 46,
+	.has_display = true,
+	.has_flat_ccs = 1,
+	.max_gt_per_tile = 2,
+	.require_force_probe = true,
+	.va_bits = 48,
+	.vm_max_level = 4,
+};
+
 #undef PLATFORM
 __diag_pop();
 
@@ -405,6 +416,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
 	INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
 	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
+	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index 3e332214c7bb4..78286285c2495 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -24,6 +24,7 @@ enum xe_platform {
 	XE_LUNARLAKE,
 	XE_BATTLEMAGE,
 	XE_PANTHERLAKE,
+	XE_NOVALAKE_S,
 };
 
 enum xe_subplatform {
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index 452c1de606ff2..13c592e1a28c7 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -887,4 +887,13 @@
 	MACRO__(0xFD80, ## __VA_ARGS__), \
 	MACRO__(0xFD81, ## __VA_ARGS__)
 
+/* NVL-S */
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+	MACRO__(0xD740, ## __VA_ARGS__), \
+	MACRO__(0xD741, ## __VA_ARGS__), \
+	MACRO__(0xD742, ## __VA_ARGS__), \
+	MACRO__(0xD743, ## __VA_ARGS__), \
+	MACRO__(0xD744, ## __VA_ARGS__), \
+	MACRO__(0xD745, ## __VA_ARGS__)
+
 #endif /* __PCIIDS_H__ */

-- 
2.51.0

Re: [PATCH v3 11/24] drm/xe/nvl: Define NVL-S platform

[Gustavo Sousa]

Quoting Lucas De Marchi (2025-10-16 23:26:30-03:00)
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Provide the basic platform definitions and PCI IDs for NVL-S.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
>v2: Fix rebase on flags moving to the device descriptor (Gustavo)
>---
> drivers/gpu/drm/xe/xe_pci.c            | 12 ++++++++++++
> drivers/gpu/drm/xe/xe_platform_types.h |  1 +
> include/drm/intel/pciids.h             |  9 +++++++++
> 3 files changed, 22 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index fac46178cebba..0546442e2a631 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -377,6 +377,17 @@ static const struct xe_device_desc ptl_desc = {
>         .vm_max_level = 4,
> };
> 
>+static const struct xe_device_desc nvls_desc = {
>+        PLATFORM(NOVALAKE_S),
>+        .dma_mask_size = 46,
>+        .has_display = true,
>+        .has_flat_ccs = 1,
>+        .max_gt_per_tile = 2,
>+        .require_force_probe = true,
>+        .va_bits = 48,
>+        .vm_max_level = 4,
>+};
>+
> #undef PLATFORM
> __diag_pop();
> 
>@@ -405,6 +416,7 @@ static const struct pci_device_id pciidlist[] = {
>         INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
>         INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>         INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>+        INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
>         { }
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
>diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
>index 3e332214c7bb4..78286285c2495 100644
>--- a/drivers/gpu/drm/xe/xe_platform_types.h
>+++ b/drivers/gpu/drm/xe/xe_platform_types.h
>@@ -24,6 +24,7 @@ enum xe_platform {
>         XE_LUNARLAKE,
>         XE_BATTLEMAGE,
>         XE_PANTHERLAKE,
>+        XE_NOVALAKE_S,
> };
> 
> enum xe_subplatform {
>diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
>index 452c1de606ff2..13c592e1a28c7 100644
>--- a/include/drm/intel/pciids.h
>+++ b/include/drm/intel/pciids.h
>@@ -887,4 +887,13 @@
>         MACRO__(0xFD80, ## __VA_ARGS__), \
>         MACRO__(0xFD81, ## __VA_ARGS__)
> 
>+/* NVL-S */
>+#define INTEL_NVLS_IDS(MACRO__, ...) \
>+        MACRO__(0xD740, ## __VA_ARGS__), \
>+        MACRO__(0xD741, ## __VA_ARGS__), \
>+        MACRO__(0xD742, ## __VA_ARGS__), \
>+        MACRO__(0xD743, ## __VA_ARGS__), \
>+        MACRO__(0xD744, ## __VA_ARGS__), \
>+        MACRO__(0xD745, ## __VA_ARGS__)
>+
> #endif /* __PCIIDS_H__ */
>
>-- 
>2.51.0
>

[PATCH v3 12/24] drm/xe/nvls: Define GuC firmware for NVL-S

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Although NVL-S has a similar Xe3 to PTL/WCL, it requires a unique GuC
firmware.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_uc_fw.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 6056ecd0b92f5..e589c7e38f125 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -115,6 +115,7 @@ struct fw_blobs_by_type {
 #define XE_GT_TYPE_ANY XE_GT_TYPE_UNINITIALIZED
 
 #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver)					\
+	fw_def(NOVALAKE_S,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	nvl,	70, 49, 4))	\
 	fw_def(PANTHERLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	ptl,	70, 49, 4))	\
 	fw_def(BATTLEMAGE,	GT_TYPE_ANY,	major_ver(xe,	guc,	bmg,	70, 49, 4))	\
 	fw_def(LUNARLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	lnl,	70, 45, 2))	\

-- 
2.51.0

[PATCH v3 13/24] drm/xe/nvls: Attach MOCS table for NVL-S

[Lucas De Marchi]

From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>

The MOCS table for NVL-S is the same as that of
Xe2.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_mocs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 7b68c22ff7bbc..e8ec4114302e5 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -576,6 +576,7 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
 	memset(info, 0, sizeof(struct xe_mocs_info));
 
 	switch (xe->info.platform) {
+	case XE_NOVALAKE_S:
 	case XE_PANTHERLAKE:
 	case XE_LUNARLAKE:
 	case XE_BATTLEMAGE:

-- 
2.51.0

[PATCH v3 14/24] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Add support for graphics IP Xe3p_XPC having IP version 35.11.

Bspec: 77979, 77975
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 0546442e2a631..c3136141a9536 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -106,6 +106,13 @@ static const struct xe_graphics_desc graphics_xe2 = {
 	XE2_GFX_FEATURES,
 };
 
+static const struct xe_graphics_desc graphics_xe3p_xpc = {
+	XE2_GFX_FEATURES,
+	.hw_engine_mask =
+		GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
+		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
+};
+
 static const struct xe_media_desc media_xem = {
 	.hw_engine_mask =
 		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
@@ -138,6 +145,7 @@ static const struct xe_ip graphics_ips[] = {
 	{ 3003, "Xe3_LPG", &graphics_xe2 },
 	{ 3004, "Xe3_LPG", &graphics_xe2 },
 	{ 3005, "Xe3_LPG", &graphics_xe2 },
+	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
 };
 
 /* Pre-GMDID Media IPs */

-- 
2.51.0

[PATCH v3 15/24] drm/xe/xe3p_xpc: Add L3 bank mask

[Lucas De Marchi]

From: Fei Yang <fei.yang@intel.com>

Expose L3 bank mask through topology query interface.

In Xe3p_XPC, MIRROR_L3BANK_ENABLE represents the full L3 bank mask (not
just a per-node mask), and each bit represents a single bank. With that
there's no extra complexity to calculate the L3 bank mask like there was
in previous platforms.

Bspec: 73439
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Better commit message (Matt Roper)
---
 drivers/gpu/drm/xe/xe_gt_topology.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
index 80ef3a6e0a3b5..14af073783ad3 100644
--- a/drivers/gpu/drm/xe/xe_gt_topology.c
+++ b/drivers/gpu/drm/xe/xe_gt_topology.c
@@ -148,7 +148,11 @@ load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
 	if (!xe_gt_topology_report_l3(gt))
 		return;
 
-	if (GRAPHICS_VER(xe) >= 30) {
+	if (GRAPHICS_VERx100(xe) == 3511) {
+		u32 fuse_val = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);
+
+		bitmap_from_arr32(l3_bank_mask, &fuse_val, 32);
+	} else if (GRAPHICS_VER(xe) >= 30) {
 		xe_l3_bank_mask_t per_node = {};
 		u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3);
 		u32 mirror_l3bank_enable = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);

-- 
2.51.0

Re: [PATCH v3 15/24] drm/xe/xe3p_xpc: Add L3 bank mask

[Matt Roper]

On Thu, Oct 16, 2025 at 07:26:34PM -0700, Lucas De Marchi wrote:
> From: Fei Yang <fei.yang@intel.com>
> 
> Expose L3 bank mask through topology query interface.
> 
> In Xe3p_XPC, MIRROR_L3BANK_ENABLE represents the full L3 bank mask (not
> just a per-node mask), and each bit represents a single bank. With that
> there's no extra complexity to calculate the L3 bank mask like there was
> in previous platforms.
> 
> Bspec: 73439
> Signed-off-by: Fei Yang <fei.yang@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Actually, although this patch is correct, I don't think it needs to be
specific to Xe3p_XPC / 35.11.  It should be equally correct (and more
future-proof) to make it a general Xe3p patch:

        if (GRAPHICS_VER(xe) >= 35)


Matt

> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> v2: Better commit message (Matt Roper)
> ---
>  drivers/gpu/drm/xe/xe_gt_topology.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
> index 80ef3a6e0a3b5..14af073783ad3 100644
> --- a/drivers/gpu/drm/xe/xe_gt_topology.c
> +++ b/drivers/gpu/drm/xe/xe_gt_topology.c
> @@ -148,7 +148,11 @@ load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
>  	if (!xe_gt_topology_report_l3(gt))
>  		return;
>  
> -	if (GRAPHICS_VER(xe) >= 30) {
> +	if (GRAPHICS_VERx100(xe) == 3511) {
> +		u32 fuse_val = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);
> +
> +		bitmap_from_arr32(l3_bank_mask, &fuse_val, 32);
> +	} else if (GRAPHICS_VER(xe) >= 30) {
>  		xe_l3_bank_mask_t per_node = {};
>  		u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3);
>  		u32 mirror_l3bank_enable = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v3 15/24] drm/xe/xe3p_xpc: Add L3 bank mask

[Lucas De Marchi]

On Fri, Oct 17, 2025 at 10:51:55AM -0700, Matt Roper wrote:
>On Thu, Oct 16, 2025 at 07:26:34PM -0700, Lucas De Marchi wrote:
>> From: Fei Yang <fei.yang@intel.com>
>>
>> Expose L3 bank mask through topology query interface.
>>
>> In Xe3p_XPC, MIRROR_L3BANK_ENABLE represents the full L3 bank mask (not
>> just a per-node mask), and each bit represents a single bank. With that
>> there's no extra complexity to calculate the L3 bank mask like there was
>> in previous platforms.
>>
>> Bspec: 73439
>> Signed-off-by: Fei Yang <fei.yang@intel.com>
>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>Actually, although this patch is correct, I don't think it needs to be
>specific to Xe3p_XPC / 35.11.  It should be equally correct (and more
>future-proof) to make it a general Xe3p patch:
>
>        if (GRAPHICS_VER(xe) >= 35)

changed, thanks.

Lucas De Marchi

[PATCH v3 16/24] drm/xe/xe3p_xpc: Add MCR steering

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_XPC's steering has a few changes from Xe3.  Aside from
minor changes to the XeCore (the new name for what used to be "DSS") and
INSTANCE0 tables, different rules apply to different subranges of type
"GAM."  Certain GAM subranges require steering to grp/instance (0,0)
(and thus use the INSTANCE0 table), while others require special
steering to (1,0) instead.  Similarly, there are multiple classes of
"PSMI" steering, with some requiring steering to (0,0) while others
require (19,0).

There are some ranges in Bspec missing the termination. Add a TODO
comment so they can eventually be updated.

Bspec: 74418
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Move TODO to a comment in the code so it can be revisited later,
    before force_probe removal (Gustavo)
---
 drivers/gpu/drm/xe/xe_gt_mcr.c   | 62 ++++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_gt_types.h | 15 ++++++++++
 2 files changed, 75 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index e1a2b38fc2a86..81ecd93826350 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -169,6 +169,15 @@ static const struct xe_mmio_range xelpg_dss_steering_table[] = {
 	{},
 };
 
+static const struct xe_mmio_range xe3p_xpc_xecore_steering_table[] = {
+	{ 0x008140, 0x00817F },         /* SLICE, XeCore, SLICE */
+	{ 0x009480, 0x00955F },         /* SLICE, XeCore */
+	{ 0x00D800, 0x00D87F },		/* SLICE */
+	{ 0x00DC00, 0x00E9FF },         /* SLICE, rsvd, XeCore, rsvd, XeCore, rsvd, XeCore */
+	{ 0x013000, 0x0135FF },         /* XeCore, SLICE */
+	{},
+};
+
 static const struct xe_mmio_range xelpmp_oaddrm_steering_table[] = {
 	{ 0x393200, 0x39323F },
 	{ 0x393400, 0x3934FF },
@@ -247,6 +256,30 @@ static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
 	{},
 };
 
+/*
+ * Different "GAM" ranges have different rules; GAMWKRS, STLB, and GAMREQSTRM
+ * range subtypes need to be steered to (1,0), while all other GAM subtypes
+ * are steered to (0,0) and are included in the "INSTANCE0" table farther
+ * down.
+ */
+static const struct xe_mmio_range xe3p_xpc_gam_grp1_steering_table[] = {
+	{ 0x004000, 0x004AFF },		/* GAMREQSTRM, rsvd, STLB, GAMWKRS, GAMREQSTRM */
+	{ 0x00F100, 0x00FFFF },		/* GAMWKRS */
+	{},
+};
+
+static const struct xe_mmio_range xe3p_xpc_psmi_grp19_steering_table[] = {
+	{ 0x00B500, 0x00B5FF },
+	{},
+};
+
+static const struct xe_mmio_range xe3p_xpc_instance0_steering_table[] = {
+	{ 0x00B600, 0x00B6FF },		/* PSMI0 */
+	{ 0x00C800, 0x00CFFF },		/* GAMCTRL */
+	{ 0x00F000, 0x00F0FF },		/* GAMCTRL */
+	{},
+};
+
 static void init_steering_l3bank(struct xe_gt *gt)
 {
 	struct xe_mmio *mmio = &gt->mmio;
@@ -419,6 +452,18 @@ static void init_steering_sqidi_psmi(struct xe_gt *gt)
 	gt->steering[SQIDI_PSMI].instance_target = select & 0x1;
 }
 
+static void init_steering_psmi(struct xe_gt *gt)
+{
+	gt->steering[PSMI19].group_target = 19;
+	gt->steering[PSMI19].instance_target = 0;
+}
+
+static void init_steering_gam1(struct xe_gt *gt)
+{
+	gt->steering[GAM1].group_target = 1;
+	gt->steering[GAM1].instance_target = 0;
+}
+
 static const struct {
 	const char *name;
 	void (*init)(struct xe_gt *gt);
@@ -426,9 +471,11 @@ static const struct {
 	[L3BANK] =	{ "L3BANK",	init_steering_l3bank },
 	[MSLICE] =	{ "MSLICE",	init_steering_mslice },
 	[LNCF] =	{ "LNCF",	NULL }, /* initialized by mslice init */
-	[DSS] =		{ "DSS",	init_steering_dss },
+	[DSS] =		{ "DSS / XeCore", init_steering_dss },
 	[OADDRM] =	{ "OADDRM / GPMXMT", init_steering_oaddrm },
 	[SQIDI_PSMI] =  { "SQIDI_PSMI", init_steering_sqidi_psmi },
+	[PSMI19] =	{ "PSMI[19]",	init_steering_psmi },
+	[GAM1] =	{ "GAMWKRS / STLB / GAMREQSTRM", init_steering_gam1 },
 	[INSTANCE0] =	{ "INSTANCE 0",	NULL },
 	[IMPLICIT_STEERING] = { "IMPLICIT", NULL },
 };
@@ -467,7 +514,18 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
 			gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;
 		}
 	} else {
-		if (GRAPHICS_VER(xe) >= 20) {
+		if (GRAPHICS_VERx100(xe) == 3511) {
+			/*
+			 * TODO: there are some ranges in bspec with missing
+			 * termination: [0x00B000, 0x00B0FF] and
+			 * [0x00D880, 0x00D8FF] (NODE); [0x00B100, 0x00B3FF]
+			 * (L3BANK). Update them here once bspec is updated.
+			 */
+			gt->steering[DSS].ranges = xe3p_xpc_xecore_steering_table;
+			gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table;
+			gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;
+			gt->steering[PSMI19].ranges = xe3p_xpc_psmi_grp19_steering_table;
+		} else if (GRAPHICS_VER(xe) >= 20) {
 			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
 			gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;
 			gt->steering[INSTANCE0].ranges = xe2lpg_instance0_steering_table;
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 8b5f604d7883a..d93faa1eedef8 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -72,6 +72,21 @@ enum xe_steering_type {
 	OADDRM,
 	SQIDI_PSMI,
 
+	/*
+	 * The bspec lists multiple ranges as "PSMI," but the different
+	 * ranges with that label have different grpid steering values so we
+	 * treat them independently in code.  Note that the ranges with grpid=0
+	 * are included in the INSTANCE0 group above.
+	 */
+	PSMI19,
+
+	/*
+	 * Although most GAM ranges must be steered to (0,0) and thus use the
+	 * INSTANCE0 type farther down, some platforms have special rules
+	 * for specific subtypes that require steering to (1,0) instead.
+	 */
+	GAM1,
+
 	/*
 	 * On some platforms there are multiple types of MCR registers that
 	 * will always return a non-terminated value at instance (0, 0).  We'll

-- 
2.51.0

[PATCH v3 17/24] drm/xe/irq: Rename fuse mask variables

[Lucas De Marchi]

It's confusing to refer to some masks as the interrupt masks and others
as the fuse masks. Rename the fuse one to make it clearer.

Note that the most important role they play here is that the call
to xe_hw_engine_mask_per_class() will not only limit the engines
according to the fuses, but also by what is available in the specific
architecture - the latter is more important information to know what
interrupts should be enabled. Add a comment about that.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_irq.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 838fb512b7779..9c3a85c4585ed 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -139,7 +139,6 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
 	struct xe_mmio *mmio = &gt->mmio;
-	u32 ccs_mask, bcs_mask;
 	u32 irqs, dmask, smask;
 	u32 gsc_mask = 0;
 	u32 heci_mask = 0;
@@ -157,36 +156,43 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 		       GT_WAIT_SEMAPHORE_INTERRUPT;
 	}
 
-	ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
-	bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
-
 	dmask = irqs << 16 | irqs;
 	smask = irqs << 16;
 
 	if (xe_gt_is_main_type(gt)) {
+		/*
+		 * For enabling the interrupts, the information about fused off
+		 * engines doesn't matter much, but this also allows to check if
+		 * the engine is available architecturally in the platform
+		 */
+		u32 ccs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
+		u32 bcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
+
 		/* Enable interrupts for each engine class */
 		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
-		if (ccs_mask)
+		if (ccs_fuse_mask)
 			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
 
 		/* Unmask interrupts for each engine instance */
 		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
 		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
-		if (bcs_mask & (BIT(1)|BIT(2)))
+		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
 			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
-		if (bcs_mask & (BIT(3)|BIT(4)))
+		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
 			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
-		if (bcs_mask & (BIT(5)|BIT(6)))
+		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
 			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
-		if (bcs_mask & (BIT(7)|BIT(8)))
+		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
 			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
-		if (ccs_mask & (BIT(0)|BIT(1)))
+		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
 			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
-		if (ccs_mask & (BIT(2)|BIT(3)))
+		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
 			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
 	}
 
 	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
+		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
+
 		/* Enable interrupts for each engine class */
 		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
 
@@ -199,7 +205,7 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 		 * the heci2 interrupt is enabled via the same register as the
 		 * GSCCS interrupts, but it has its own mask register.
 		 */
-		if (xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER)) {
+		if (other_fuse_mask) {
 			gsc_mask = irqs | GSC_ER_COMPLETE;
 			heci_mask = GSC_IRQ_INTF(1);
 		} else if (xe->info.has_heci_gscfi) {

-- 
2.51.0

[PATCH v3 18/24] drm/xe/irq: Split irq mask per engine class

[Lucas De Marchi]

Each engine class has a different bitfield structure in the hw. We've
been just using a common mask for all of them, but this means that we
could inadvertently set a wrong bit in one class while enabling
something in another. Split them to make it more future proof.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Fix copy paste mistake: s/vcs/vecs/ (Matt Roper)
---
 drivers/gpu/drm/xe/xe_irq.c | 73 +++++++++++++++++++++++++++++----------------
 1 file changed, 47 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 9c3a85c4585ed..142f422a5d97e 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -139,25 +139,28 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
 	struct xe_mmio *mmio = &gt->mmio;
-	u32 irqs, dmask, smask;
-	u32 gsc_mask = 0;
-	u32 heci_mask = 0;
+	u32 common_mask, val, gsc_mask = 0, heci_mask = 0,
+	    rcs_mask = 0, bcs_mask = 0, vcs_mask = 0, vecs_mask = 0,
+	    ccs_mask = 0;
 
 	if (xe_device_uses_memirq(xe))
 		return;
 
 	if (xe_device_uc_enabled(xe)) {
-		irqs = GT_RENDER_USER_INTERRUPT |
-			GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
+		common_mask = GT_RENDER_USER_INTERRUPT |
+			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
 	} else {
-		irqs = GT_RENDER_USER_INTERRUPT |
-		       GT_CS_MASTER_ERROR_INTERRUPT |
-		       GT_CONTEXT_SWITCH_INTERRUPT |
-		       GT_WAIT_SEMAPHORE_INTERRUPT;
+		common_mask = GT_RENDER_USER_INTERRUPT |
+			      GT_CS_MASTER_ERROR_INTERRUPT |
+			      GT_CONTEXT_SWITCH_INTERRUPT |
+			      GT_WAIT_SEMAPHORE_INTERRUPT;
 	}
 
-	dmask = irqs << 16 | irqs;
-	smask = irqs << 16;
+	rcs_mask |= common_mask;
+	bcs_mask |= common_mask;
+	vcs_mask |= common_mask;
+	vecs_mask |= common_mask;
+	ccs_mask |= common_mask;
 
 	if (xe_gt_is_main_type(gt)) {
 		/*
@@ -169,44 +172,62 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 		u32 bcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
 
 		/* Enable interrupts for each engine class */
-		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
+		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE,
+				REG_FIELD_PREP(ENGINE1_MASK, rcs_mask) |
+				REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
 		if (ccs_fuse_mask)
-			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
+			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE,
+					REG_FIELD_PREP(ENGINE1_MASK, ccs_mask));
 
 		/* Unmask interrupts for each engine instance */
-		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
-		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
+		val = ~REG_FIELD_PREP(ENGINE1_MASK, rcs_mask);
+		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, val);
+		val = ~REG_FIELD_PREP(ENGINE1_MASK, bcs_mask);
+		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, val);
+
+		val = ~(REG_FIELD_PREP(ENGINE1_MASK, bcs_mask) |
+			REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
 		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
-			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, val);
 		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
-			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, val);
 		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
-			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, val);
 		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
-			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, val);
+
+		val = ~(REG_FIELD_PREP(ENGINE1_MASK, ccs_mask) |
+			REG_FIELD_PREP(ENGINE0_MASK, ccs_mask));
 		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
-			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, val);
 		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
-			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, val);
 	}
 
 	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
 		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
 
 		/* Enable interrupts for each engine class */
-		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
+		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE,
+				REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
+				REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));
 
 		/* Unmask interrupts for each engine instance */
-		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
-		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
-		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
+		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
+			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
+		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
+		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
+
+		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vecs_mask) |
+			REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));
+		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
 
 		/*
 		 * the heci2 interrupt is enabled via the same register as the
 		 * GSCCS interrupts, but it has its own mask register.
 		 */
 		if (other_fuse_mask) {
-			gsc_mask = irqs | GSC_ER_COMPLETE;
+			gsc_mask = common_mask | GSC_ER_COMPLETE;
 			heci_mask = GSC_IRQ_INTF(1);
 		} else if (xe->info.has_heci_gscfi) {
 			gsc_mask = GSC_IRQ_INTF(1);

-- 
2.51.0

Re: [PATCH v3 18/24] drm/xe/irq: Split irq mask per engine class

[Matt Roper]

On Thu, Oct 16, 2025 at 07:26:37PM -0700, Lucas De Marchi wrote:
> Each engine class has a different bitfield structure in the hw. We've
> been just using a common mask for all of them, but this means that we
> could inadvertently set a wrong bit in one class while enabling
> something in another. Split them to make it more future proof.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
> v2: Fix copy paste mistake: s/vcs/vecs/ (Matt Roper)
> ---
>  drivers/gpu/drm/xe/xe_irq.c | 73 +++++++++++++++++++++++++++++----------------
>  1 file changed, 47 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 9c3a85c4585ed..142f422a5d97e 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -139,25 +139,28 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  {
>  	struct xe_device *xe = gt_to_xe(gt);
>  	struct xe_mmio *mmio = &gt->mmio;
> -	u32 irqs, dmask, smask;
> -	u32 gsc_mask = 0;
> -	u32 heci_mask = 0;
> +	u32 common_mask, val, gsc_mask = 0, heci_mask = 0,
> +	    rcs_mask = 0, bcs_mask = 0, vcs_mask = 0, vecs_mask = 0,
> +	    ccs_mask = 0;
>  
>  	if (xe_device_uses_memirq(xe))
>  		return;
>  
>  	if (xe_device_uc_enabled(xe)) {
> -		irqs = GT_RENDER_USER_INTERRUPT |
> -			GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> +		common_mask = GT_RENDER_USER_INTERRUPT |
> +			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
>  	} else {
> -		irqs = GT_RENDER_USER_INTERRUPT |
> -		       GT_CS_MASTER_ERROR_INTERRUPT |
> -		       GT_CONTEXT_SWITCH_INTERRUPT |
> -		       GT_WAIT_SEMAPHORE_INTERRUPT;
> +		common_mask = GT_RENDER_USER_INTERRUPT |
> +			      GT_CS_MASTER_ERROR_INTERRUPT |
> +			      GT_CONTEXT_SWITCH_INTERRUPT |
> +			      GT_WAIT_SEMAPHORE_INTERRUPT;
>  	}
>  
> -	dmask = irqs << 16 | irqs;
> -	smask = irqs << 16;
> +	rcs_mask |= common_mask;
> +	bcs_mask |= common_mask;
> +	vcs_mask |= common_mask;
> +	vecs_mask |= common_mask;
> +	ccs_mask |= common_mask;
>  
>  	if (xe_gt_is_main_type(gt)) {
>  		/*
> @@ -169,44 +172,62 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  		u32 bcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
>  
>  		/* Enable interrupts for each engine class */
> -		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
> +		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE,
> +				REG_FIELD_PREP(ENGINE1_MASK, rcs_mask) |
> +				REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
>  		if (ccs_fuse_mask)
> -			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
> +			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE,
> +					REG_FIELD_PREP(ENGINE1_MASK, ccs_mask));
>  
>  		/* Unmask interrupts for each engine instance */
> -		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
> -		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
> +		val = ~REG_FIELD_PREP(ENGINE1_MASK, rcs_mask);
> +		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, val);
> +		val = ~REG_FIELD_PREP(ENGINE1_MASK, bcs_mask);
> +		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, val);
> +
> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, bcs_mask) |
> +			REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
>  		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
> -			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, val);
>  		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
> -			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, val);
>  		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
> -			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, val);
>  		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
> -			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, val);
> +
> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, ccs_mask) |
> +			REG_FIELD_PREP(ENGINE0_MASK, ccs_mask));
>  		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
> -			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, val);
>  		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
> -			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, val);
>  	}
>  
>  	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
>  		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
>  
>  		/* Enable interrupts for each engine class */
> -		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
> +		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE,
> +				REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
> +				REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));
>  
>  		/* Unmask interrupts for each engine instance */
> -		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
> -		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
> -		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
> +			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
> +		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
> +		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
> +
> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vecs_mask) |
> +			REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));
> +		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
>  
>  		/*
>  		 * the heci2 interrupt is enabled via the same register as the
>  		 * GSCCS interrupts, but it has its own mask register.
>  		 */
>  		if (other_fuse_mask) {
> -			gsc_mask = irqs | GSC_ER_COMPLETE;
> +			gsc_mask = common_mask | GSC_ER_COMPLETE;
>  			heci_mask = GSC_IRQ_INTF(1);
>  		} else if (xe->info.has_heci_gscfi) {
>  			gsc_mask = GSC_IRQ_INTF(1);
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v3 19/24] drm/xe/irq: Rename bits used with all engines

[Lucas De Marchi]

Two bit fields have similar functionality across the interrupt vectors
but are named "RENDER". Rename them to follow the bspec more closely and
clear any confusion when using them for other engines.

Bspec: 62353, 62354, 62355, 62346, 62345, 63341
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_irq_regs.h | 4 ++--
 drivers/gpu/drm/xe/xe_hw_engine.c     | 2 +-
 drivers/gpu/drm/xe/xe_irq.c           | 6 +++---
 drivers/gpu/drm/xe/xe_memirq.c        | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 7c2a3a1401424..f6117720963b6 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -80,9 +80,9 @@
 #define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)
 #define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)
 #define   GSC_ER_COMPLETE			REG_BIT(5)
-#define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
+#define   GT_FLUSH_COMPLETE_INTERRUPT	REG_BIT(4)
 #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
-#define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
+#define   GT_MI_USER_INTERRUPT			REG_BIT(0)
 
 /* irqs for OTHER_KCR_INSTANCE */
 #define   KCR_PXP_STATE_TERMINATED_INTERRUPT		REG_BIT(1)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 073ecd263e543..6a9e2a4272dde 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -904,7 +904,7 @@ void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec)
 	if (hwe->irq_handler)
 		hwe->irq_handler(hwe, intr_vec);
 
-	if (intr_vec & GT_RENDER_USER_INTERRUPT)
+	if (intr_vec & GT_MI_USER_INTERRUPT)
 		xe_hw_fence_irq_run(hwe->fence_irq);
 }
 
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 142f422a5d97e..2108c86ed478d 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -147,10 +147,10 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 		return;
 
 	if (xe_device_uc_enabled(xe)) {
-		common_mask = GT_RENDER_USER_INTERRUPT |
-			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
+		common_mask = GT_MI_USER_INTERRUPT |
+			      GT_FLUSH_COMPLETE_INTERRUPT;
 	} else {
-		common_mask = GT_RENDER_USER_INTERRUPT |
+		common_mask = GT_MI_USER_INTERRUPT |
 			      GT_CS_MASTER_ERROR_INTERRUPT |
 			      GT_CONTEXT_SWITCH_INTERRUPT |
 			      GT_WAIT_SEMAPHORE_INTERRUPT;
diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index 2ef9d9aab2649..b0c7ce0a5d1eb 100644
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -434,8 +434,8 @@ static void memirq_dispatch_engine(struct xe_memirq *memirq, struct iosys_map *s
 {
 	memirq_debug(memirq, "STATUS %s %*ph\n", hwe->name, 16, status->vaddr);
 
-	if (memirq_received(memirq, status, ilog2(GT_RENDER_USER_INTERRUPT), hwe->name))
-		xe_hw_engine_handle_irq(hwe, GT_RENDER_USER_INTERRUPT);
+	if (memirq_received(memirq, status, ilog2(GT_MI_USER_INTERRUPT), hwe->name))
+		xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
 }
 
 static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *status,

-- 
2.51.0

Re: [PATCH v3 19/24] drm/xe/irq: Rename bits used with all engines

[Matt Roper]

On Thu, Oct 16, 2025 at 07:26:38PM -0700, Lucas De Marchi wrote:
> Two bit fields have similar functionality across the interrupt vectors
> but are named "RENDER". Rename them to follow the bspec more closely and
> clear any confusion when using them for other engines.
> 
> Bspec: 62353, 62354, 62355, 62346, 62345, 63341
> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 4 ++--
>  drivers/gpu/drm/xe/xe_hw_engine.c     | 2 +-
>  drivers/gpu/drm/xe/xe_irq.c           | 6 +++---
>  drivers/gpu/drm/xe/xe_memirq.c        | 4 ++--
>  4 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 7c2a3a1401424..f6117720963b6 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -80,9 +80,9 @@
>  #define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)
>  #define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)
>  #define   GSC_ER_COMPLETE			REG_BIT(5)
> -#define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
> +#define   GT_FLUSH_COMPLETE_INTERRUPT	REG_BIT(4)
>  #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
> -#define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
> +#define   GT_MI_USER_INTERRUPT			REG_BIT(0)
>  
>  /* irqs for OTHER_KCR_INSTANCE */
>  #define   KCR_PXP_STATE_TERMINATED_INTERRUPT		REG_BIT(1)
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 073ecd263e543..6a9e2a4272dde 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -904,7 +904,7 @@ void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec)
>  	if (hwe->irq_handler)
>  		hwe->irq_handler(hwe, intr_vec);
>  
> -	if (intr_vec & GT_RENDER_USER_INTERRUPT)
> +	if (intr_vec & GT_MI_USER_INTERRUPT)
>  		xe_hw_fence_irq_run(hwe->fence_irq);
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 142f422a5d97e..2108c86ed478d 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -147,10 +147,10 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  		return;
>  
>  	if (xe_device_uc_enabled(xe)) {
> -		common_mask = GT_RENDER_USER_INTERRUPT |
> -			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> +		common_mask = GT_MI_USER_INTERRUPT |
> +			      GT_FLUSH_COMPLETE_INTERRUPT;
>  	} else {
> -		common_mask = GT_RENDER_USER_INTERRUPT |
> +		common_mask = GT_MI_USER_INTERRUPT |
>  			      GT_CS_MASTER_ERROR_INTERRUPT |
>  			      GT_CONTEXT_SWITCH_INTERRUPT |
>  			      GT_WAIT_SEMAPHORE_INTERRUPT;
> diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
> index 2ef9d9aab2649..b0c7ce0a5d1eb 100644
> --- a/drivers/gpu/drm/xe/xe_memirq.c
> +++ b/drivers/gpu/drm/xe/xe_memirq.c
> @@ -434,8 +434,8 @@ static void memirq_dispatch_engine(struct xe_memirq *memirq, struct iosys_map *s
>  {
>  	memirq_debug(memirq, "STATUS %s %*ph\n", hwe->name, 16, status->vaddr);
>  
> -	if (memirq_received(memirq, status, ilog2(GT_RENDER_USER_INTERRUPT), hwe->name))
> -		xe_hw_engine_handle_irq(hwe, GT_RENDER_USER_INTERRUPT);
> +	if (memirq_received(memirq, status, ilog2(GT_MI_USER_INTERRUPT), hwe->name))
> +		xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
>  }
>  
>  static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *status,
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v3 20/24] drm/xe/irq: Check fuse mask for media engines

[Lucas De Marchi]

Just like the other engines, check xe_hw_engine_mask_per_class() for VCS
and VECS to account for architectural availability of those registers.
With that, all the possibly available media engines can have their
interrupts enabled.

Bspec: 54030
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_irq_regs.h |  3 +++
 drivers/gpu/drm/xe/xe_irq.c           | 17 ++++++++++++++---
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index f6117720963b6..815d5e3d22099 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -65,7 +65,10 @@
 #define BCS_RSVD_INTR_MASK			XE_REG(0x1900a0, XE_REG_OPTION_VF)
 #define VCS0_VCS1_INTR_MASK			XE_REG(0x1900a8, XE_REG_OPTION_VF)
 #define VCS2_VCS3_INTR_MASK			XE_REG(0x1900ac, XE_REG_OPTION_VF)
+#define VCS4_VCS5_INTR_MASK			XE_REG(0x1900b0, XE_REG_OPTION_VF)
+#define VCS6_VCS7_INTR_MASK			XE_REG(0x1900b4, XE_REG_OPTION_VF)
 #define VECS0_VECS1_INTR_MASK			XE_REG(0x1900d0, XE_REG_OPTION_VF)
+#define VECS2_VECS3_INTR_MASK			XE_REG(0x1900d4, XE_REG_OPTION_VF)
 #define HECI2_RSVD_INTR_MASK			XE_REG(0x1900e4)
 #define GUC_SG_INTR_MASK			XE_REG(0x1900e8, XE_REG_OPTION_VF)
 #define GPM_WGBOXPERF_INTR_MASK			XE_REG(0x1900ec, XE_REG_OPTION_VF)
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 2108c86ed478d..8f2c8d3ae5f8a 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -205,6 +205,8 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 	}
 
 	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
+		u32 vcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_DECODE);
+		u32 vecs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE);
 		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
 
 		/* Enable interrupts for each engine class */
@@ -215,12 +217,21 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 		/* Unmask interrupts for each engine instance */
 		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
 			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
-		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
-		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
+		if (vcs_fuse_mask & (BIT(0) | BIT(1)))
+			xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
+		if (vcs_fuse_mask & (BIT(2) | BIT(3)))
+			xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
+		if (vcs_fuse_mask & (BIT(4) | BIT(5)))
+			xe_mmio_write32(mmio, VCS4_VCS5_INTR_MASK, val);
+		if (vcs_fuse_mask & (BIT(6) | BIT(7)))
+			xe_mmio_write32(mmio, VCS6_VCS7_INTR_MASK, val);
 
 		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vecs_mask) |
 			REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));
-		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
+		if (vecs_fuse_mask & (BIT(0) | BIT(1)))
+			xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
+		if (vecs_fuse_mask & (BIT(2) | BIT(3)))
+			xe_mmio_write32(mmio, VECS2_VECS3_INTR_MASK, val);
 
 		/*
 		 * the heci2 interrupt is enabled via the same register as the

-- 
2.51.0

Re: [PATCH v3 20/24] drm/xe/irq: Check fuse mask for media engines

[Matt Roper]

On Thu, Oct 16, 2025 at 07:26:39PM -0700, Lucas De Marchi wrote:
> Just like the other engines, check xe_hw_engine_mask_per_class() for VCS
> and VECS to account for architectural availability of those registers.
> With that, all the possibly available media engines can have their
> interrupts enabled.
> 
> Bspec: 54030
> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_irq_regs.h |  3 +++
>  drivers/gpu/drm/xe/xe_irq.c           | 17 ++++++++++++++---
>  2 files changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index f6117720963b6..815d5e3d22099 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -65,7 +65,10 @@
>  #define BCS_RSVD_INTR_MASK			XE_REG(0x1900a0, XE_REG_OPTION_VF)
>  #define VCS0_VCS1_INTR_MASK			XE_REG(0x1900a8, XE_REG_OPTION_VF)
>  #define VCS2_VCS3_INTR_MASK			XE_REG(0x1900ac, XE_REG_OPTION_VF)
> +#define VCS4_VCS5_INTR_MASK			XE_REG(0x1900b0, XE_REG_OPTION_VF)
> +#define VCS6_VCS7_INTR_MASK			XE_REG(0x1900b4, XE_REG_OPTION_VF)
>  #define VECS0_VECS1_INTR_MASK			XE_REG(0x1900d0, XE_REG_OPTION_VF)
> +#define VECS2_VECS3_INTR_MASK			XE_REG(0x1900d4, XE_REG_OPTION_VF)
>  #define HECI2_RSVD_INTR_MASK			XE_REG(0x1900e4)
>  #define GUC_SG_INTR_MASK			XE_REG(0x1900e8, XE_REG_OPTION_VF)
>  #define GPM_WGBOXPERF_INTR_MASK			XE_REG(0x1900ec, XE_REG_OPTION_VF)
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 2108c86ed478d..8f2c8d3ae5f8a 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -205,6 +205,8 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  	}
>  
>  	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
> +		u32 vcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_DECODE);
> +		u32 vecs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE);
>  		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
>  
>  		/* Enable interrupts for each engine class */
> @@ -215,12 +217,21 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  		/* Unmask interrupts for each engine instance */
>  		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
>  			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
> -		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
> -		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
> +		if (vcs_fuse_mask & (BIT(0) | BIT(1)))
> +			xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
> +		if (vcs_fuse_mask & (BIT(2) | BIT(3)))
> +			xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
> +		if (vcs_fuse_mask & (BIT(4) | BIT(5)))
> +			xe_mmio_write32(mmio, VCS4_VCS5_INTR_MASK, val);
> +		if (vcs_fuse_mask & (BIT(6) | BIT(7)))
> +			xe_mmio_write32(mmio, VCS6_VCS7_INTR_MASK, val);
>  
>  		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vecs_mask) |
>  			REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));
> -		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
> +		if (vecs_fuse_mask & (BIT(0) | BIT(1)))
> +			xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
> +		if (vecs_fuse_mask & (BIT(2) | BIT(3)))
> +			xe_mmio_write32(mmio, VECS2_VECS3_INTR_MASK, val);
>  
>  		/*
>  		 * the heci2 interrupt is enabled via the same register as the
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v3 21/24] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Lucas De Marchi]

Current implementation of compute walker has dependency on GPU/SW Stack
which requires SW/UMD to wait for event from KMD to indicate
PIPE_CONTROL interrupt was done. This created latency on SW stack.

This feature adds support to generate completion interrupt from GPGPU
walker which does not support MSIx and avoid software using Pipe control
drain/idle latency.

The only thing needed for the kernel driver to do here is to wakeup the
thread waiting on the ufence, which is already handled by the irq
handler.

Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Rebase on split mask per engine class
---
 drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
 drivers/gpu/drm/xe/xe_irq.c           | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 815d5e3d22099..2f97662d958de 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -85,6 +85,7 @@
 #define   GSC_ER_COMPLETE			REG_BIT(5)
 #define   GT_FLUSH_COMPLETE_INTERRUPT	REG_BIT(4)
 #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
+#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
 #define   GT_MI_USER_INTERRUPT			REG_BIT(0)
 
 /* irqs for OTHER_KCR_INSTANCE */
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 8f2c8d3ae5f8a..e5ed0242f7b1d 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -149,6 +149,12 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 	if (xe_device_uc_enabled(xe)) {
 		common_mask = GT_MI_USER_INTERRUPT |
 			      GT_FLUSH_COMPLETE_INTERRUPT;
+
+		/* Enable Compute Walker Interrupt for non-MSIX platforms */
+		if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe)) {
+			rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
+			ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
+		}
 	} else {
 		common_mask = GT_MI_USER_INTERRUPT |
 			      GT_CS_MASTER_ERROR_INTERRUPT |

-- 
2.51.0

Re: [PATCH v3 21/24] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Matt Roper]

On Thu, Oct 16, 2025 at 07:26:40PM -0700, Lucas De Marchi wrote:
> Current implementation of compute walker has dependency on GPU/SW Stack
> which requires SW/UMD to wait for event from KMD to indicate
> PIPE_CONTROL interrupt was done. This created latency on SW stack.
> 
> This feature adds support to generate completion interrupt from GPGPU
> walker which does not support MSIx and avoid software using Pipe control
> drain/idle latency.
> 
> The only thing needed for the kernel driver to do here is to wakeup the
> thread waiting on the ufence, which is already handled by the irq
> handler.
> 
> Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> Signed-off-by: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Digging into this more, I think the implementation is correct, but I
think we could still expand the commit message a little bit more to
explain how/when this winds up getting used.  The description above left
me uncertain whether these new interrupts are opt-in on a per-walker
basis, or whether the hardware was going to start unconditionally
generating interrupts for every walker's completion.  After looking
through the bspec, it looks like the interrupts here are only generated
for COMPUTE_WALKER_2 instructions (not COMPUTE_WALKER) if specifically
requested via the flag in the POST_SYNC_DATA_2 substructure's dw0[3].

So with a minor clarification to the commit message that the interrupts
we're enabling here are something userspace can opt into on a per-walker
basis,

        Bspec: 62346, 74334
        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


Matt

> ---
> v2: Rebase on split mask per engine class
> ---
>  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
>  drivers/gpu/drm/xe/xe_irq.c           | 6 ++++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 815d5e3d22099..2f97662d958de 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -85,6 +85,7 @@
>  #define   GSC_ER_COMPLETE			REG_BIT(5)
>  #define   GT_FLUSH_COMPLETE_INTERRUPT	REG_BIT(4)
>  #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
> +#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
>  #define   GT_MI_USER_INTERRUPT			REG_BIT(0)
>  
>  /* irqs for OTHER_KCR_INSTANCE */
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 8f2c8d3ae5f8a..e5ed0242f7b1d 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -149,6 +149,12 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  	if (xe_device_uc_enabled(xe)) {
>  		common_mask = GT_MI_USER_INTERRUPT |
>  			      GT_FLUSH_COMPLETE_INTERRUPT;
> +
> +		/* Enable Compute Walker Interrupt for non-MSIX platforms */
> +		if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe)) {
> +			rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
> +			ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
> +		}
>  	} else {
>  		common_mask = GT_MI_USER_INTERRUPT |
>  			      GT_CS_MASTER_ERROR_INTERRUPT |
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v3 22/24] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

The compression overfetch tuning settings only apply to platforms that
support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
compression) some of the registers being adjusted by this tuning will
not exist or may have been repurposed for something else, so we should
take care not to try to program them.

Note that our xe_rtp_match_has_flatccs() function will also return false
on platforms that do have FlatCCS in the hardware design, but have
compression manually disabled in the BIOS.  On such platforms the
registers still exist (and it would be fine to continue programming
them), but they would have no effect, so skipping that tuning is also
safe.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_rtp.c    |  7 +++++++
 drivers/gpu/drm/xe/xe_rtp.h    | 12 ++++++++++++
 drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
 3 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 66707cc89ec97..ed509b1c8cfcd 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -378,3 +378,10 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
 {
 	return xe_gt_has_discontiguous_dss_groups(gt);
 }
+
+bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe,
+			       const struct xe_gt *gt,
+			       const struct xe_hw_engine *hwe)
+{
+	return xe->info.has_flat_ccs;
+}
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index e5b8a9452e29e..ba5f940c0a961 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -491,4 +491,16 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
 						  const struct xe_gt *gt,
 						  const struct xe_hw_engine *hwe);
 
+/**
+ * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS compression
+ * @xe: Device structure
+ * @gt: GT structure
+ * @hwe: Engine instance
+ *
+ * Returns: true if platform has FlatCCS compression, false otherwise
+ */
+bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe,
+			       const struct xe_gt *gt,
+			       const struct xe_hw_engine *hwe);
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index fd58ea5e78bf6..7c140d8cb1e07 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
 	},
 	{ XE_RTP_NAME("Tuning: Compression Overfetch"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
+		       FUNC(xe_rtp_match_has_flat_ccs)),
 	  XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
 			 SET(CCCHKNREG1, L3CMPCTRL))
 	},
@@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
 	},
 	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
+		       FUNC(xe_rtp_match_has_flat_ccs)),
 	  XE_RTP_ACTIONS(SET(L3SQCREG2,
 			     COMPMEMRD256BOVRFETCHEN))
 	},
 	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
-	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
+		       FUNC(xe_rtp_match_has_flat_ccs)),
 	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
 			     COMPMEMRD256BOVRFETCHEN))
 	},

-- 
2.51.0

[PATCH v3 23/24] drm/xe/xe3p_xpc: Setup PAT table

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_XPC IP requires a new PAT table; note that this table has one fewer
column than the Xe2/Xe3 tables since compression is not supported.
There's also no "WT" entry (which we wouldn't have used on a platform
without display anyway).

Bspec: 71582
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pat.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 95 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 6e48ff84ad0a0..7649b554942aa 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -154,6 +154,41 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
 static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
 static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );
 
+/*
+ * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no
+ * option for compression.  Also note that the "L3" and "L4" register fields
+ * actually control L2 and L3 cache respectively on this platform.
+ */
+#define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \
+	XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode)
+
+static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );
+static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );
+
+static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),
+	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),
+	/* 11..22 are reserved; leave set to all 0's */
+	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),
+	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),
+	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),
+	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),
+	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),
+	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),
+	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),
+	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),
+	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
+};
+
 u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
 {
 	WARN_ON(pat_index >= xe->pat.n_entries);
@@ -380,9 +415,68 @@ static const struct xe_pat_ops xe2_pat_ops = {
 	.dump = xe2_dump,
 };
 
+static int xe3p_xpc_dump(struct xe_gt *gt, struct drm_printer *p)
+{
+	struct xe_device *xe = gt_to_xe(gt);
+	unsigned int fw_ref;
+	u32 pat;
+	int i;
+
+	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+	if (!fw_ref)
+		return -ETIMEDOUT;
+
+	drm_printf(p, "PAT table:\n");
+
+	for (i = 0; i < xe->pat.n_entries; i++) {
+		pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
+
+		drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u ]  (%#8x)\n", i,
+			   !!(pat & XE2_NO_PROMOTE),
+			   REG_FIELD_GET(XE2_L3_CLOS, pat),
+			   REG_FIELD_GET(XE2_L3_POLICY, pat),
+			   REG_FIELD_GET(XE2_L4_POLICY, pat),
+			   REG_FIELD_GET(XE2_COH_MODE, pat),
+			   pat);
+	}
+
+	/*
+	 * Also print PTA_MODE, which describes how the hardware accesses
+	 * PPGTT entries.
+	 */
+	pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
+
+	drm_printf(p, "Page Table Access:\n");
+	drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u ]  (%#8x)\n",
+		   !!(pat & XE2_NO_PROMOTE),
+		   REG_FIELD_GET(XE2_L3_CLOS, pat),
+		   REG_FIELD_GET(XE2_L3_POLICY, pat),
+		   REG_FIELD_GET(XE2_L4_POLICY, pat),
+		   REG_FIELD_GET(XE2_COH_MODE, pat),
+		   pat);
+
+	xe_force_wake_put(gt_to_fw(gt), fw_ref);
+	return 0;
+}
+
+static const struct xe_pat_ops xe3p_xpc_pat_ops = {
+	.program_graphics = program_pat_mcr,
+	.program_media = program_pat,
+	.dump = xe3p_xpc_dump,
+};
+
 void xe_pat_init_early(struct xe_device *xe)
 {
-	if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
+	if (GRAPHICS_VERx100(xe) == 3511) {
+		xe->pat.ops = &xe3p_xpc_pat_ops;
+		xe->pat.table = xe3p_xpc_pat_table;
+		xe->pat.pat_ats = &xe3p_xpc_pat_ats;
+		xe->pat.pat_pta = &xe3p_xpc_pat_pta;
+		xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
+		xe->pat.idx[XE_CACHE_NONE] = 3;
+		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
+		xe->pat.idx[XE_CACHE_WB] = 2;
+	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
 		xe->pat.ops = &xe2_pat_ops;
 		xe->pat.table = xe2_pat_table;
 		xe->pat.pat_ats = &xe2_pat_ats;

-- 
2.51.0

Re: [PATCH v3 23/24] drm/xe/xe3p_xpc: Setup PAT table

[Ville Syrjälä]

On Thu, Oct 16, 2025 at 07:26:42PM -0700, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe3p_XPC IP requires a new PAT table; note that this table has one fewer
> column than the Xe2/Xe3 tables since compression is not supported.
> There's also no "WT" entry (which we wouldn't have used on a platform
> without display anyway).
> 
> Bspec: 71582
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pat.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 95 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 6e48ff84ad0a0..7649b554942aa 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -154,6 +154,41 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
>  static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
>  static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );
>  
> +/*
> + * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no
> + * option for compression.  Also note that the "L3" and "L4" register fields
> + * actually control L2 and L3 cache respectively on this platform.
> + */
> +#define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \
> +	XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode)
> +
> +static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );
> +static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );
> +
> +static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
> +	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),
> +	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),
> +	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),
> +	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),
> +	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),
> +	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),
> +	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),
> +	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),
> +	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),
> +	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),
> +	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),
> +	/* 11..22 are reserved; leave set to all 0's */
> +	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),
> +	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),
> +	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),
> +	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),
> +	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),
> +	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),
> +	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),
> +	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),
> +	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),

Why did we go from human readable names to raw magic numbers?
This is now completely illegible.

> +};
> +
>  u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
>  {
>  	WARN_ON(pat_index >= xe->pat.n_entries);
> @@ -380,9 +415,68 @@ static const struct xe_pat_ops xe2_pat_ops = {
>  	.dump = xe2_dump,
>  };
>  
> +static int xe3p_xpc_dump(struct xe_gt *gt, struct drm_printer *p)
> +{
> +	struct xe_device *xe = gt_to_xe(gt);
> +	unsigned int fw_ref;
> +	u32 pat;
> +	int i;
> +
> +	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> +	if (!fw_ref)
> +		return -ETIMEDOUT;
> +
> +	drm_printf(p, "PAT table:\n");
> +
> +	for (i = 0; i < xe->pat.n_entries; i++) {
> +		pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
> +
> +		drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u ]  (%#8x)\n", i,
> +			   !!(pat & XE2_NO_PROMOTE),
> +			   REG_FIELD_GET(XE2_L3_CLOS, pat),
> +			   REG_FIELD_GET(XE2_L3_POLICY, pat),
> +			   REG_FIELD_GET(XE2_L4_POLICY, pat),
> +			   REG_FIELD_GET(XE2_COH_MODE, pat),
> +			   pat);
> +	}
> +
> +	/*
> +	 * Also print PTA_MODE, which describes how the hardware accesses
> +	 * PPGTT entries.
> +	 */
> +	pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
> +
> +	drm_printf(p, "Page Table Access:\n");
> +	drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u ]  (%#8x)\n",
> +		   !!(pat & XE2_NO_PROMOTE),
> +		   REG_FIELD_GET(XE2_L3_CLOS, pat),
> +		   REG_FIELD_GET(XE2_L3_POLICY, pat),
> +		   REG_FIELD_GET(XE2_L4_POLICY, pat),
> +		   REG_FIELD_GET(XE2_COH_MODE, pat),
> +		   pat);
> +
> +	xe_force_wake_put(gt_to_fw(gt), fw_ref);
> +	return 0;
> +}
> +
> +static const struct xe_pat_ops xe3p_xpc_pat_ops = {
> +	.program_graphics = program_pat_mcr,
> +	.program_media = program_pat,
> +	.dump = xe3p_xpc_dump,
> +};
> +
>  void xe_pat_init_early(struct xe_device *xe)
>  {
> -	if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
> +	if (GRAPHICS_VERx100(xe) == 3511) {
> +		xe->pat.ops = &xe3p_xpc_pat_ops;
> +		xe->pat.table = xe3p_xpc_pat_table;
> +		xe->pat.pat_ats = &xe3p_xpc_pat_ats;
> +		xe->pat.pat_pta = &xe3p_xpc_pat_pta;
> +		xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
> +		xe->pat.idx[XE_CACHE_NONE] = 3;
> +		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
> +		xe->pat.idx[XE_CACHE_WB] = 2;
> +	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
>  		xe->pat.ops = &xe2_pat_ops;
>  		xe->pat.table = xe2_pat_table;
>  		xe->pat.pat_ats = &xe2_pat_ats;
> 
> -- 
> 2.51.0

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 23/24] drm/xe/xe3p_xpc: Setup PAT table

[Matt Roper]

On Fri, Oct 17, 2025 at 02:05:53PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 16, 2025 at 07:26:42PM -0700, Lucas De Marchi wrote:
> > From: Matt Roper <matthew.d.roper@intel.com>
> > 
> > Xe3p_XPC IP requires a new PAT table; note that this table has one fewer
> > column than the Xe2/Xe3 tables since compression is not supported.
> > There's also no "WT" entry (which we wouldn't have used on a platform
> > without display anyway).
> > 
> > Bspec: 71582
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_pat.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 95 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> > index 6e48ff84ad0a0..7649b554942aa 100644
> > --- a/drivers/gpu/drm/xe/xe_pat.c
> > +++ b/drivers/gpu/drm/xe/xe_pat.c
> > @@ -154,6 +154,41 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
> >  static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
> >  static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );
> >  
> > +/*
> > + * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no
> > + * option for compression.  Also note that the "L3" and "L4" register fields
> > + * actually control L2 and L3 cache respectively on this platform.
> > + */
> > +#define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \
> > +	XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode)
> > +
> > +static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );
> > +static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );
> > +
> > +static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
> > +	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),
> > +	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),
> > +	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),
> > +	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),
> > +	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),
> > +	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),
> > +	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),
> > +	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),
> > +	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),
> > +	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),
> > +	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),
> > +	/* 11..22 are reserved; leave set to all 0's */
> > +	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),
> > +	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),
> > +	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),
> > +	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),
> > +	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),
> > +	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),
> > +	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),
> > +	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),
> > +	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
> 
> Why did we go from human readable names to raw magic numbers?
> This is now completely illegible.

For Xe2/Xe3 I think it's actually a lot easier to read since we have a
kerneldoc right above the tables explaining exactly what each column
represents:

 """
 * The Xe2 table is getting large/complicated so it's easier to review if
 * provided in a form that exactly matches the bspec's formatting.  The meaning
 * of the fields here are:
 *   - no_promote:  0=promotable, 1=no promote
 *   - comp_en:     0=disable, 1=enable
 *   - l3clos:      L3 class of service (0-3)
 *   - l3_policy:   0=WB, 1=XD ("WB - Transient Display"), 3=UC
 *   - l4_policy:   0=WB, 1=WT, 3=UC
 *   - coh_mode:    0=no snoop, 2=1-way coherent, 3=2-way coherent
 """

Trying to write out symbolic names like we did on i915 became pretty
illegible due to the long/wrapping lines since we have so many fields
now.  It also became a nightmare to maintain since it was easy to make
mistakes (and also easy to overlook them in code review).  This approach
gives us something that exactly matches the presentation of the table in
the bspec (so easier to add/modify without making mistakes, easier to
review for correctness), and a key in the comments that makes it really
easy to quickly understand the specific characteristics that relate to
each row.

For Xe3p_XPC, we should probably duplicate that comment block (minus the
"comp_en" field that's not relevant here) since we lost a field compared
to the Xe2/Xe3 tables.


Matt

> 
> > +};
> > +
> >  u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
> >  {
> >  	WARN_ON(pat_index >= xe->pat.n_entries);
> > @@ -380,9 +415,68 @@ static const struct xe_pat_ops xe2_pat_ops = {
> >  	.dump = xe2_dump,
> >  };
> >  
> > +static int xe3p_xpc_dump(struct xe_gt *gt, struct drm_printer *p)
> > +{
> > +	struct xe_device *xe = gt_to_xe(gt);
> > +	unsigned int fw_ref;
> > +	u32 pat;
> > +	int i;
> > +
> > +	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> > +	if (!fw_ref)
> > +		return -ETIMEDOUT;
> > +
> > +	drm_printf(p, "PAT table:\n");
> > +
> > +	for (i = 0; i < xe->pat.n_entries; i++) {
> > +		pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
> > +
> > +		drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u ]  (%#8x)\n", i,
> > +			   !!(pat & XE2_NO_PROMOTE),
> > +			   REG_FIELD_GET(XE2_L3_CLOS, pat),
> > +			   REG_FIELD_GET(XE2_L3_POLICY, pat),
> > +			   REG_FIELD_GET(XE2_L4_POLICY, pat),
> > +			   REG_FIELD_GET(XE2_COH_MODE, pat),
> > +			   pat);
> > +	}
> > +
> > +	/*
> > +	 * Also print PTA_MODE, which describes how the hardware accesses
> > +	 * PPGTT entries.
> > +	 */
> > +	pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
> > +
> > +	drm_printf(p, "Page Table Access:\n");
> > +	drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u ]  (%#8x)\n",
> > +		   !!(pat & XE2_NO_PROMOTE),
> > +		   REG_FIELD_GET(XE2_L3_CLOS, pat),
> > +		   REG_FIELD_GET(XE2_L3_POLICY, pat),
> > +		   REG_FIELD_GET(XE2_L4_POLICY, pat),
> > +		   REG_FIELD_GET(XE2_COH_MODE, pat),
> > +		   pat);
> > +
> > +	xe_force_wake_put(gt_to_fw(gt), fw_ref);
> > +	return 0;
> > +}
> > +
> > +static const struct xe_pat_ops xe3p_xpc_pat_ops = {
> > +	.program_graphics = program_pat_mcr,
> > +	.program_media = program_pat,
> > +	.dump = xe3p_xpc_dump,
> > +};
> > +
> >  void xe_pat_init_early(struct xe_device *xe)
> >  {
> > -	if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
> > +	if (GRAPHICS_VERx100(xe) == 3511) {
> > +		xe->pat.ops = &xe3p_xpc_pat_ops;
> > +		xe->pat.table = xe3p_xpc_pat_table;
> > +		xe->pat.pat_ats = &xe3p_xpc_pat_ats;
> > +		xe->pat.pat_pta = &xe3p_xpc_pat_pta;
> > +		xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
> > +		xe->pat.idx[XE_CACHE_NONE] = 3;
> > +		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
> > +		xe->pat.idx[XE_CACHE_WB] = 2;
> > +	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
> >  		xe->pat.ops = &xe2_pat_ops;
> >  		xe->pat.table = xe2_pat_table;
> >  		xe->pat.pat_ats = &xe2_pat_ats;
> > 
> > -- 
> > 2.51.0
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v3 23/24] drm/xe/xe3p_xpc: Setup PAT table

[Ville Syrjälä]

On Fri, Oct 17, 2025 at 10:18:11AM -0700, Matt Roper wrote:
> On Fri, Oct 17, 2025 at 02:05:53PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 16, 2025 at 07:26:42PM -0700, Lucas De Marchi wrote:
> > > From: Matt Roper <matthew.d.roper@intel.com>
> > > 
> > > Xe3p_XPC IP requires a new PAT table; note that this table has one fewer
> > > column than the Xe2/Xe3 tables since compression is not supported.
> > > There's also no "WT" entry (which we wouldn't have used on a platform
> > > without display anyway).
> > > 
> > > Bspec: 71582
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_pat.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-
> > >  1 file changed, 95 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> > > index 6e48ff84ad0a0..7649b554942aa 100644
> > > --- a/drivers/gpu/drm/xe/xe_pat.c
> > > +++ b/drivers/gpu/drm/xe/xe_pat.c
> > > @@ -154,6 +154,41 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
> > >  static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
> > >  static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );
> > >  
> > > +/*
> > > + * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no
> > > + * option for compression.  Also note that the "L3" and "L4" register fields
> > > + * actually control L2 and L3 cache respectively on this platform.
> > > + */
> > > +#define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \
> > > +	XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode)
> > > +
> > > +static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );
> > > +static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );
> > > +
> > > +static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
> > > +	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),
> > > +	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),
> > > +	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),
> > > +	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),
> > > +	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),
> > > +	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),
> > > +	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),
> > > +	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),
> > > +	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),
> > > +	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),
> > > +	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),
> > > +	/* 11..22 are reserved; leave set to all 0's */
> > > +	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),
> > > +	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),
> > > +	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),
> > > +	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),
> > > +	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),
> > > +	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),
> > > +	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),
> > > +	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),
> > > +	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
> > 
> > Why did we go from human readable names to raw magic numbers?
> > This is now completely illegible.
> 
> For Xe2/Xe3 I think it's actually a lot easier to read since we have a
> kerneldoc right above the tables explaining exactly what each column
> represents:
> 
>  """
>  * The Xe2 table is getting large/complicated so it's easier to review if
>  * provided in a form that exactly matches the bspec's formatting.  The meaning
>  * of the fields here are:
>  *   - no_promote:  0=promotable, 1=no promote
>  *   - comp_en:     0=disable, 1=enable
>  *   - l3clos:      L3 class of service (0-3)
>  *   - l3_policy:   0=WB, 1=XD ("WB - Transient Display"), 3=UC
>  *   - l4_policy:   0=WB, 1=WT, 3=UC
>  *   - coh_mode:    0=no snoop, 2=1-way coherent, 3=2-way coherent
>  """

I don't like counting colums by hand. I would just like to look
at a row and understand what it means. With this thing that is
not possible without taking notes.

> 
> Trying to write out symbolic names like we did on i915 became pretty
> illegible due to the long/wrapping lines since we have so many fields
> now.

If wrapping is making a mess then don't wrap. I think people have big
enough screens that we can tolerate longs lines for something like this.

> It also became a nightmare to maintain since it was easy to make
> mistakes (and also easy to overlook them in code review).  This approach
> gives us something that exactly matches the presentation of the table in
> the bspec (so easier to add/modify without making mistakes, easier to
> review for correctness),

Except when the tables in the bspec are wrong you have to actually
debug this, like I did recently wrt. the CCS AUX screwups. 

Though even i915 wasn't fully using human reaadable names (eg.
some 0 values were basically just omitted). I have patch to 
also give those proper names, which I should probably clean
up and send out.

> and a key in the comments that makes it really
> easy to quickly understand the specific characteristics that relate to
> each row.
> 
> For Xe3p_XPC, we should probably duplicate that comment block (minus the
> "comp_en" field that's not relevant here) since we lost a field compared
> to the Xe2/Xe3 tables.

I think the only way the comment would actually help if it would
be directly above the table, and the comments would line up
properly with the colums of the table. Now the comment is too
far away (it's documenting the macro, not the table). And the
comment is using rows rather than the columns the actual table
is using, so there is a 90 degree rotation you have to perform
in your head all the time which is a pain.

Though even with the comments lining up with the colums you'd still
have to jump through extra hoops to figure out what eg. a magic '3'
means in a specific column. So still not the best solution IMO.

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 23/24] drm/xe/xe3p_xpc: Setup PAT table

[Matt Roper]

On Fri, Oct 17, 2025 at 09:09:34PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 17, 2025 at 10:18:11AM -0700, Matt Roper wrote:
> > On Fri, Oct 17, 2025 at 02:05:53PM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 16, 2025 at 07:26:42PM -0700, Lucas De Marchi wrote:
> > > > From: Matt Roper <matthew.d.roper@intel.com>
> > > > 
> > > > Xe3p_XPC IP requires a new PAT table; note that this table has one fewer
> > > > column than the Xe2/Xe3 tables since compression is not supported.
> > > > There's also no "WT" entry (which we wouldn't have used on a platform
> > > > without display anyway).
> > > > 
> > > > Bspec: 71582
> > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/xe/xe_pat.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-
> > > >  1 file changed, 95 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> > > > index 6e48ff84ad0a0..7649b554942aa 100644
> > > > --- a/drivers/gpu/drm/xe/xe_pat.c
> > > > +++ b/drivers/gpu/drm/xe/xe_pat.c
> > > > @@ -154,6 +154,41 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
> > > >  static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
> > > >  static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );
> > > >  
> > > > +/*
> > > > + * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no
> > > > + * option for compression.  Also note that the "L3" and "L4" register fields
> > > > + * actually control L2 and L3 cache respectively on this platform.
> > > > + */
> > > > +#define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \
> > > > +	XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode)
> > > > +
> > > > +static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );
> > > > +static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );
> > > > +
> > > > +static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
> > > > +	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),
> > > > +	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),
> > > > +	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),
> > > > +	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),
> > > > +	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),
> > > > +	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),
> > > > +	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),
> > > > +	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),
> > > > +	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),
> > > > +	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),
> > > > +	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),
> > > > +	/* 11..22 are reserved; leave set to all 0's */
> > > > +	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),
> > > > +	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),
> > > > +	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),
> > > > +	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),
> > > > +	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),
> > > > +	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),
> > > > +	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),
> > > > +	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),
> > > > +	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
> > > 
> > > Why did we go from human readable names to raw magic numbers?
> > > This is now completely illegible.
> > 
> > For Xe2/Xe3 I think it's actually a lot easier to read since we have a
> > kerneldoc right above the tables explaining exactly what each column
> > represents:
> > 
> >  """
> >  * The Xe2 table is getting large/complicated so it's easier to review if
> >  * provided in a form that exactly matches the bspec's formatting.  The meaning
> >  * of the fields here are:
> >  *   - no_promote:  0=promotable, 1=no promote
> >  *   - comp_en:     0=disable, 1=enable
> >  *   - l3clos:      L3 class of service (0-3)
> >  *   - l3_policy:   0=WB, 1=XD ("WB - Transient Display"), 3=UC
> >  *   - l4_policy:   0=WB, 1=WT, 3=UC
> >  *   - coh_mode:    0=no snoop, 2=1-way coherent, 3=2-way coherent
> >  """
> 
> I don't like counting colums by hand. I would just like to look
> at a row and understand what it means. With this thing that is
> not possible without taking notes.

I don't know, personally I disagree here.  The preferred reference is
always the bspec itself (or the PRMs once they eventually get released
for the platform), and looking up / understanding PAT settings there has
always been very quick and easy.  I think the most important thing is to
keep the code in exactly the same presentation format at the spec itself
so that it's easy to confirm that our code table actually matches the
bspec and doesn't accidentally deviate.  If someone doesn't want to fire
up their web browser to look at the authoritative data in the bspec/prm,
the necessary information is still easily available here.

If we want to make it even more readable in the code itself, then I'd
rather add comments at the end of the line, similar to the "use" column
in the bspec, rather than trying to change the numbers into ugly macro
names.  E.g.,

   ...
   [28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),  /* CLOS2: L2 + L3 (2-way coh) */
   [29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),  /* CLOS3: L2 + L3 */
   ...

> 
> > 
> > Trying to write out symbolic names like we did on i915 became pretty
> > illegible due to the long/wrapping lines since we have so many fields
> > now.
> 
> If wrapping is making a mess then don't wrap. I think people have big
> enough screens that we can tolerate longs lines for something like this.
> 
> > It also became a nightmare to maintain since it was easy to make
> > mistakes (and also easy to overlook them in code review).  This approach
> > gives us something that exactly matches the presentation of the table in
> > the bspec (so easier to add/modify without making mistakes, easier to
> > review for correctness),
> 
> Except when the tables in the bspec are wrong you have to actually
> debug this, like I did recently wrt. the CCS AUX screwups. 

I think the i915 stuff you're referring to was with MOCS rather than
PAT, right?  That's slightly different since there are/were a lot of
places where the hardware itself implicitly uses some fixed MOCS index
to control certain types of operations (and sometimes that usage isn't
documented).  So in those cases if a documented MOCS entry suggests
values that don't work properly with the way hardware is implicitly
trying to use the entry it can cause problems.  I think that kind of
problem has been becoming less common with MOCS over time since there's
been a clear effort by the hardware guys to start adding explicit "mocs
index" values into the various instructions and registers where things
used to pick some special index implicitly; Xe_LP platforms were bad,
Xe_HP got better, Xe_HPC/Xe_LPG got better still, etc.

For PAT, I don't believe there's ever that kind of undocumented usage or
an entry.  With the exception of the "PAT_ATS" and "PTA_MODE" special
cases that control the behavior for Address Translation Services and
PPGTT page tables themselves, the regular 0..31 PAT entries are only
used when the index is referenced from a PTE.  That also means that
aside from PAT_ATS and PTA_MODE, there isn't really anything we can
consider absolutely "right" or "wrong" --- problems just arise if
software binds a buffer with a PAT index that has incompatible settings
with the buffer's usage, or if some piece of software tried to implement
its own PAT settings table that doesn't match the one from the bspec
that all the other software components are using.


Matt

> 
> Though even i915 wasn't fully using human reaadable names (eg.
> some 0 values were basically just omitted). I have patch to 
> also give those proper names, which I should probably clean
> up and send out.
> 
> > and a key in the comments that makes it really
> > easy to quickly understand the specific characteristics that relate to
> > each row.
> > 
> > For Xe3p_XPC, we should probably duplicate that comment block (minus the
> > "comp_en" field that's not relevant here) since we lost a field compared
> > to the Xe2/Xe3 tables.
> 
> I think the only way the comment would actually help if it would
> be directly above the table, and the comments would line up
> properly with the colums of the table. Now the comment is too
> far away (it's documenting the macro, not the table). And the
> comment is using rows rather than the columns the actual table
> is using, so there is a 90 degree rotation you have to perform
> in your head all the time which is a pain.
> 
> Though even with the comments lining up with the colums you'd still
> have to jump through extra hoops to figure out what eg. a magic '3'
> means in a specific column. So still not the best solution IMO.
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v3 24/24] drm/xe/xe3p: Add xe3p EU stall data format

[Lucas De Marchi]

From: Harish Chegondi <harish.chegondi@intel.com>

Starting with Xe3p, IP address in EU stall data increases to 61 bits.
While at it, re-order the if-else ladder so the officially supported
platforms come before PVC.

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: reorder the if-else ladder so PVC is the last (Lucas)
---
 drivers/gpu/drm/xe/xe_eu_stall.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index f5cfdf29fde34..650e45f6a7c7e 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -124,6 +124,27 @@ struct xe_eu_stall_data_xe2 {
 	__u64 unused[6];
 } __packed;
 
+/*
+ * EU stall data format for Xe3p arch GPUs.
+ */
+struct xe_eu_stall_data_xe3p {
+	__u64 ip_addr:61;	  /* Bits 0  to 60  */
+	__u64 tdr_count:8;	  /* Bits 61 to 68  */
+	__u64 other_count:8;	  /* Bits 69 to 76  */
+	__u64 control_count:8;	  /* Bits 77 to 84  */
+	__u64 pipestall_count:8;  /* Bits 85 to 92  */
+	__u64 send_count:8;	  /* Bits 93 to 100 */
+	__u64 dist_acc_count:8;   /* Bits 101 to 108 */
+	__u64 sbid_count:8;	  /* Bits 109 to 116 */
+	__u64 sync_count:8;	  /* Bits 117 to 124 */
+	__u64 inst_fetch_count:8; /* Bits 125 to 132 */
+	__u64 active_count:8;	  /* Bits 133 to 140 */
+	__u64 ex_id:3;		  /* Bits 141 to 143 */
+	__u64 end_flag:1;	  /* Bit  144 */
+	__u64 unused_bits:47;
+	__u64 unused[5];
+} __packed;
+
 const u64 eu_stall_sampling_rates[] = {251, 251 * 2, 251 * 3, 251 * 4, 251 * 5, 251 * 6, 251 * 7};
 
 /**
@@ -167,10 +188,13 @@ size_t xe_eu_stall_data_record_size(struct xe_device *xe)
 {
 	size_t record_size = 0;
 
-	if (xe->info.platform == XE_PVC)
-		record_size = sizeof(struct xe_eu_stall_data_pvc);
+	if (GRAPHICS_VER(xe) >= 35)
+		record_size = sizeof(struct xe_eu_stall_data_xe3p);
 	else if (GRAPHICS_VER(xe) >= 20)
 		record_size = sizeof(struct xe_eu_stall_data_xe2);
+	else if (xe->info.platform == XE_PVC)
+		record_size = sizeof(struct xe_eu_stall_data_pvc);
+
 
 	xe_assert(xe, is_power_of_2(record_size));
 

-- 
2.51.0

✗ CI.checkpatch: warning for drm/xe: Add Xe3p support (rev3)

[Patchwork]

== Series Details ==

Series: drm/xe: Add Xe3p support (rev3)
URL   : https://patchwork.freedesktop.org/series/155866/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit e1a80fa10ae2bf2125632f4336b8fb939b51fb07
Author: Harish Chegondi <harish.chegondi@intel.com>
Date:   Thu Oct 16 19:26:43 2025 -0700

    drm/xe/xe3p: Add xe3p EU stall data format
    
    Starting with Xe3p, IP address in EU stall data increases to 61 bits.
    While at it, re-order the if-else ladder so the officially supported
    platforms come before PVC.
    
    Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
    Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
    Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
    Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+ /mt/dim checkpatch b4f191dddaee9ae1871344e3dabcc40f2f14d2cb drm-intel
736395592c93 drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05
-:46: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#46: FILE: drivers/gpu/drm/xe/xe_wa.c:698:
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)),

total: 0 errors, 1 warnings, 0 checks, 62 lines checked
07053f5d333d drm/xe/xe3p: Add support for media IP versions 35.00 & 35.03
-:6: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#6: 
Xe3p_LPM/Xe3p_HPM are very similar to Xe3_LPM on the kmd interface, so it can use

total: 0 errors, 1 warnings, 0 checks, 8 lines checked
b21feb2bdfcb drm/xe: Drop CTC_MODE register read
58549871124d drm/xe: Add GT_VER() to check version specific to gt type
be927915701b drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs
2e528beab1b7 drm/xe/xe3p_lpm: Handle MCR steering
c03378c50cf3 drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting
e16717c916f2 drm/xe/xe3p: Determine service copy availability from fuse
0c6c87e70b45 drm/xe: Dump CURRENT_LRCA register
2f087f3536f8 drm/xe/xe3p: Dump CSMQDEBUG register
9d2d4262261d drm/xe/nvl: Define NVL-S platform
-:63: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#63: FILE: include/drm/intel/pciids.h:891:
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+	MACRO__(0xD740, ## __VA_ARGS__), \
+	MACRO__(0xD741, ## __VA_ARGS__), \
+	MACRO__(0xD742, ## __VA_ARGS__), \
+	MACRO__(0xD743, ## __VA_ARGS__), \
+	MACRO__(0xD744, ## __VA_ARGS__), \
+	MACRO__(0xD745, ## __VA_ARGS__)

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:63: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#63: FILE: include/drm/intel/pciids.h:891:
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+	MACRO__(0xD740, ## __VA_ARGS__), \
+	MACRO__(0xD741, ## __VA_ARGS__), \
+	MACRO__(0xD742, ## __VA_ARGS__), \
+	MACRO__(0xD743, ## __VA_ARGS__), \
+	MACRO__(0xD744, ## __VA_ARGS__), \
+	MACRO__(0xD745, ## __VA_ARGS__)

total: 1 errors, 0 warnings, 1 checks, 44 lines checked
7dc3e9ccff16 drm/xe/nvls: Define GuC firmware for NVL-S
9d3ec48a50ff drm/xe/nvls: Attach MOCS table for NVL-S
7d25e77357b9 drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition
2887a725ff61 drm/xe/xe3p_xpc: Add L3 bank mask
003f6cafac76 drm/xe/xe3p_xpc: Add MCR steering
2514dfb8c450 drm/xe/irq: Rename fuse mask variables
-:59: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#59: FILE: drivers/gpu/drm/xe/xe_irq.c:179:
+		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
 		                           ^

-:62: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#62: FILE: drivers/gpu/drm/xe/xe_irq.c:181:
+		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
 		                           ^

-:65: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#65: FILE: drivers/gpu/drm/xe/xe_irq.c:183:
+		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
 		                           ^

-:68: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#68: FILE: drivers/gpu/drm/xe/xe_irq.c:185:
+		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
 		                           ^

-:71: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#71: FILE: drivers/gpu/drm/xe/xe_irq.c:187:
+		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
 		                           ^

-:74: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#74: FILE: drivers/gpu/drm/xe/xe_irq.c:189:
+		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
 		                           ^

total: 0 errors, 0 warnings, 6 checks, 68 lines checked
25ab6c9292c8 drm/xe/irq: Split irq mask per engine class
5d4ce85c32c7 drm/xe/irq: Rename bits used with all engines
36d49abe0386 drm/xe/irq: Check fuse mask for media engines
bc0099ddda99 drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx
91e540f76b8a drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs
00a3dcec2d2d drm/xe/xe3p_xpc: Setup PAT table
-:31: ERROR:SPACING: space prohibited after that open parenthesis '('
#31: FILE: drivers/gpu/drm/xe/xe_pat.c:165:
+static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );

-:31: ERROR:SPACING: space prohibited before that close parenthesis ')'
#31: FILE: drivers/gpu/drm/xe/xe_pat.c:165:
+static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );

-:32: ERROR:SPACING: space prohibited after that open parenthesis '('
#32: FILE: drivers/gpu/drm/xe/xe_pat.c:166:
+static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );

-:32: ERROR:SPACING: space prohibited before that close parenthesis ')'
#32: FILE: drivers/gpu/drm/xe/xe_pat.c:166:
+static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );

-:35: ERROR:SPACING: space prohibited after that open square bracket '['
#35: FILE: drivers/gpu/drm/xe/xe_pat.c:169:
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),

-:35: ERROR:SPACING: space prohibited after that open parenthesis '('
#35: FILE: drivers/gpu/drm/xe/xe_pat.c:169:
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),

-:35: ERROR:SPACING: space prohibited before that close parenthesis ')'
#35: FILE: drivers/gpu/drm/xe/xe_pat.c:169:
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),

-:36: ERROR:SPACING: space prohibited after that open square bracket '['
#36: FILE: drivers/gpu/drm/xe/xe_pat.c:170:
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),

-:36: ERROR:SPACING: space prohibited after that open parenthesis '('
#36: FILE: drivers/gpu/drm/xe/xe_pat.c:170:
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),

-:36: ERROR:SPACING: space prohibited before that close parenthesis ')'
#36: FILE: drivers/gpu/drm/xe/xe_pat.c:170:
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),

-:37: ERROR:SPACING: space prohibited after that open square bracket '['
#37: FILE: drivers/gpu/drm/xe/xe_pat.c:171:
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),

-:37: ERROR:SPACING: space prohibited after that open parenthesis '('
#37: FILE: drivers/gpu/drm/xe/xe_pat.c:171:
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),

-:37: ERROR:SPACING: space prohibited before that close parenthesis ')'
#37: FILE: drivers/gpu/drm/xe/xe_pat.c:171:
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),

-:38: ERROR:SPACING: space prohibited after that open square bracket '['
#38: FILE: drivers/gpu/drm/xe/xe_pat.c:172:
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),

-:38: ERROR:SPACING: space prohibited after that open parenthesis '('
#38: FILE: drivers/gpu/drm/xe/xe_pat.c:172:
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),

-:38: ERROR:SPACING: space prohibited before that close parenthesis ')'
#38: FILE: drivers/gpu/drm/xe/xe_pat.c:172:
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),

-:39: ERROR:SPACING: space prohibited after that open square bracket '['
#39: FILE: drivers/gpu/drm/xe/xe_pat.c:173:
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),

-:39: ERROR:SPACING: space prohibited after that open parenthesis '('
#39: FILE: drivers/gpu/drm/xe/xe_pat.c:173:
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),

-:39: ERROR:SPACING: space prohibited before that close parenthesis ')'
#39: FILE: drivers/gpu/drm/xe/xe_pat.c:173:
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),

-:40: ERROR:SPACING: space prohibited after that open square bracket '['
#40: FILE: drivers/gpu/drm/xe/xe_pat.c:174:
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),

-:40: ERROR:SPACING: space prohibited after that open parenthesis '('
#40: FILE: drivers/gpu/drm/xe/xe_pat.c:174:
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),

-:40: ERROR:SPACING: space prohibited before that close parenthesis ')'
#40: FILE: drivers/gpu/drm/xe/xe_pat.c:174:
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),

-:41: ERROR:SPACING: space prohibited after that open square bracket '['
#41: FILE: drivers/gpu/drm/xe/xe_pat.c:175:
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),

-:41: ERROR:SPACING: space prohibited after that open parenthesis '('
#41: FILE: drivers/gpu/drm/xe/xe_pat.c:175:
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),

-:41: ERROR:SPACING: space prohibited before that close parenthesis ')'
#41: FILE: drivers/gpu/drm/xe/xe_pat.c:175:
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),

-:42: ERROR:SPACING: space prohibited after that open square bracket '['
#42: FILE: drivers/gpu/drm/xe/xe_pat.c:176:
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),

-:42: ERROR:SPACING: space prohibited after that open parenthesis '('
#42: FILE: drivers/gpu/drm/xe/xe_pat.c:176:
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),

-:42: ERROR:SPACING: space prohibited before that close parenthesis ')'
#42: FILE: drivers/gpu/drm/xe/xe_pat.c:176:
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),

-:43: ERROR:SPACING: space prohibited after that open square bracket '['
#43: FILE: drivers/gpu/drm/xe/xe_pat.c:177:
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),

-:43: ERROR:SPACING: space prohibited after that open parenthesis '('
#43: FILE: drivers/gpu/drm/xe/xe_pat.c:177:
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),

-:43: ERROR:SPACING: space prohibited before that close parenthesis ')'
#43: FILE: drivers/gpu/drm/xe/xe_pat.c:177:
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),

-:44: ERROR:SPACING: space prohibited after that open square bracket '['
#44: FILE: drivers/gpu/drm/xe/xe_pat.c:178:
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),

-:44: ERROR:SPACING: space prohibited after that open parenthesis '('
#44: FILE: drivers/gpu/drm/xe/xe_pat.c:178:
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),

-:44: ERROR:SPACING: space prohibited before that close parenthesis ')'
#44: FILE: drivers/gpu/drm/xe/xe_pat.c:178:
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),

-:45: ERROR:SPACING: space prohibited after that open parenthesis '('
#45: FILE: drivers/gpu/drm/xe/xe_pat.c:179:
+	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),

-:45: ERROR:SPACING: space prohibited before that close parenthesis ')'
#45: FILE: drivers/gpu/drm/xe/xe_pat.c:179:
+	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),

-:47: ERROR:SPACING: space prohibited after that open parenthesis '('
#47: FILE: drivers/gpu/drm/xe/xe_pat.c:181:
+	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),

-:47: ERROR:SPACING: space prohibited before that close parenthesis ')'
#47: FILE: drivers/gpu/drm/xe/xe_pat.c:181:
+	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),

-:48: ERROR:SPACING: space prohibited after that open parenthesis '('
#48: FILE: drivers/gpu/drm/xe/xe_pat.c:182:
+	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),

-:48: ERROR:SPACING: space prohibited before that close parenthesis ')'
#48: FILE: drivers/gpu/drm/xe/xe_pat.c:182:
+	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),

-:49: ERROR:SPACING: space prohibited after that open parenthesis '('
#49: FILE: drivers/gpu/drm/xe/xe_pat.c:183:
+	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),

-:49: ERROR:SPACING: space prohibited before that close parenthesis ')'
#49: FILE: drivers/gpu/drm/xe/xe_pat.c:183:
+	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),

-:50: ERROR:SPACING: space prohibited after that open parenthesis '('
#50: FILE: drivers/gpu/drm/xe/xe_pat.c:184:
+	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),

-:50: ERROR:SPACING: space prohibited before that close parenthesis ')'
#50: FILE: drivers/gpu/drm/xe/xe_pat.c:184:
+	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),

-:51: ERROR:SPACING: space prohibited after that open parenthesis '('
#51: FILE: drivers/gpu/drm/xe/xe_pat.c:185:
+	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),

-:51: ERROR:SPACING: space prohibited before that close parenthesis ')'
#51: FILE: drivers/gpu/drm/xe/xe_pat.c:185:
+	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),

-:52: ERROR:SPACING: space prohibited after that open parenthesis '('
#52: FILE: drivers/gpu/drm/xe/xe_pat.c:186:
+	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),

-:52: ERROR:SPACING: space prohibited before that close parenthesis ')'
#52: FILE: drivers/gpu/drm/xe/xe_pat.c:186:
+	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),

-:53: ERROR:SPACING: space prohibited after that open parenthesis '('
#53: FILE: drivers/gpu/drm/xe/xe_pat.c:187:
+	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),

-:53: ERROR:SPACING: space prohibited before that close parenthesis ')'
#53: FILE: drivers/gpu/drm/xe/xe_pat.c:187:
+	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),

-:54: ERROR:SPACING: space prohibited after that open parenthesis '('
#54: FILE: drivers/gpu/drm/xe/xe_pat.c:188:
+	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),

-:54: ERROR:SPACING: space prohibited before that close parenthesis ')'
#54: FILE: drivers/gpu/drm/xe/xe_pat.c:188:
+	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),

-:55: ERROR:SPACING: space prohibited after that open parenthesis '('
#55: FILE: drivers/gpu/drm/xe/xe_pat.c:189:
+	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),

-:55: ERROR:SPACING: space prohibited before that close parenthesis ')'
#55: FILE: drivers/gpu/drm/xe/xe_pat.c:189:
+	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),

total: 54 errors, 0 warnings, 0 checks, 110 lines checked
e1a80fa10ae2 drm/xe/xe3p: Add xe3p EU stall data format

✓ CI.KUnit: success for drm/xe: Add Xe3p support (rev3)

[Patchwork]

== Series Details ==

Series: drm/xe: Add Xe3p support (rev3)
URL   : https://patchwork.freedesktop.org/series/155866/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[02:35:41] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:35:45] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:36:16] Starting KUnit Kernel (1/1)...
[02:36:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:36:16] ================== guc_buf (11 subtests) ===================
[02:36:16] [PASSED] test_smallest
[02:36:16] [PASSED] test_largest
[02:36:16] [PASSED] test_granular
[02:36:16] [PASSED] test_unique
[02:36:16] [PASSED] test_overlap
[02:36:16] [PASSED] test_reusable
[02:36:16] [PASSED] test_too_big
[02:36:16] [PASSED] test_flush
[02:36:16] [PASSED] test_lookup
[02:36:16] [PASSED] test_data
[02:36:16] [PASSED] test_class
[02:36:16] ===================== [PASSED] guc_buf =====================
[02:36:16] =================== guc_dbm (7 subtests) ===================
[02:36:16] [PASSED] test_empty
[02:36:16] [PASSED] test_default
[02:36:16] ======================== test_size  ========================
[02:36:16] [PASSED] 4
[02:36:16] [PASSED] 8
[02:36:16] [PASSED] 32
[02:36:16] [PASSED] 256
[02:36:16] ==================== [PASSED] test_size ====================
[02:36:16] ======================= test_reuse  ========================
[02:36:16] [PASSED] 4
[02:36:16] [PASSED] 8
[02:36:16] [PASSED] 32
[02:36:16] [PASSED] 256
[02:36:16] =================== [PASSED] test_reuse ====================
[02:36:16] =================== test_range_overlap  ====================
[02:36:16] [PASSED] 4
[02:36:16] [PASSED] 8
[02:36:16] [PASSED] 32
[02:36:16] [PASSED] 256
[02:36:16] =============== [PASSED] test_range_overlap ================
[02:36:16] =================== test_range_compact  ====================
[02:36:16] [PASSED] 4
[02:36:16] [PASSED] 8
[02:36:16] [PASSED] 32
[02:36:16] [PASSED] 256
[02:36:16] =============== [PASSED] test_range_compact ================
[02:36:16] ==================== test_range_spare  =====================
[02:36:16] [PASSED] 4
[02:36:16] [PASSED] 8
[02:36:16] [PASSED] 32
[02:36:16] [PASSED] 256
[02:36:16] ================ [PASSED] test_range_spare =================
[02:36:16] ===================== [PASSED] guc_dbm =====================
[02:36:16] =================== guc_idm (6 subtests) ===================
[02:36:16] [PASSED] bad_init
[02:36:16] [PASSED] no_init
[02:36:16] [PASSED] init_fini
[02:36:16] [PASSED] check_used
[02:36:16] [PASSED] check_quota
[02:36:16] [PASSED] check_all
[02:36:16] ===================== [PASSED] guc_idm =====================
[02:36:16] ================== no_relay (3 subtests) ===================
[02:36:16] [PASSED] xe_drops_guc2pf_if_not_ready
[02:36:16] [PASSED] xe_drops_guc2vf_if_not_ready
[02:36:16] [PASSED] xe_rejects_send_if_not_ready
[02:36:16] ==================== [PASSED] no_relay =====================
[02:36:16] ================== pf_relay (14 subtests) ==================
[02:36:16] [PASSED] pf_rejects_guc2pf_too_short
[02:36:16] [PASSED] pf_rejects_guc2pf_too_long
[02:36:16] [PASSED] pf_rejects_guc2pf_no_payload
[02:36:16] [PASSED] pf_fails_no_payload
[02:36:16] [PASSED] pf_fails_bad_origin
[02:36:16] [PASSED] pf_fails_bad_type
[02:36:16] [PASSED] pf_txn_reports_error
[02:36:16] [PASSED] pf_txn_sends_pf2guc
[02:36:16] [PASSED] pf_sends_pf2guc
[02:36:16] [SKIPPED] pf_loopback_nop
[02:36:16] [SKIPPED] pf_loopback_echo
[02:36:16] [SKIPPED] pf_loopback_fail
[02:36:16] [SKIPPED] pf_loopback_busy
[02:36:16] [SKIPPED] pf_loopback_retry
[02:36:16] ==================== [PASSED] pf_relay =====================
[02:36:16] ================== vf_relay (3 subtests) ===================
[02:36:16] [PASSED] vf_rejects_guc2vf_too_short
[02:36:16] [PASSED] vf_rejects_guc2vf_too_long
[02:36:16] [PASSED] vf_rejects_guc2vf_no_payload
[02:36:16] ==================== [PASSED] vf_relay =====================
[02:36:16] ===================== lmtt (1 subtest) =====================
[02:36:16] ======================== test_ops  =========================
[02:36:16] [PASSED] 2-level
[02:36:16] [PASSED] multi-level
[02:36:16] ==================== [PASSED] test_ops =====================
[02:36:16] ====================== [PASSED] lmtt =======================
[02:36:16] ================= pf_service (11 subtests) =================
[02:36:16] [PASSED] pf_negotiate_any
[02:36:16] [PASSED] pf_negotiate_base_match
[02:36:16] [PASSED] pf_negotiate_base_newer
[02:36:16] [PASSED] pf_negotiate_base_next
[02:36:16] [SKIPPED] pf_negotiate_base_older
[02:36:16] [PASSED] pf_negotiate_base_prev
[02:36:16] [PASSED] pf_negotiate_latest_match
[02:36:16] [PASSED] pf_negotiate_latest_newer
[02:36:16] [PASSED] pf_negotiate_latest_next
[02:36:16] [SKIPPED] pf_negotiate_latest_older
[02:36:16] [SKIPPED] pf_negotiate_latest_prev
[02:36:16] =================== [PASSED] pf_service ====================
[02:36:16] ================= xe_guc_g2g (2 subtests) ==================
[02:36:16] ============== xe_live_guc_g2g_kunit_default  ==============
[02:36:16] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[02:36:16] ============== xe_live_guc_g2g_kunit_allmem  ===============
[02:36:16] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[02:36:16] =================== [SKIPPED] xe_guc_g2g ===================
[02:36:16] =================== xe_mocs (2 subtests) ===================
[02:36:16] ================ xe_live_mocs_kernel_kunit  ================
[02:36:16] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[02:36:16] ================ xe_live_mocs_reset_kunit  =================
[02:36:16] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[02:36:16] ==================== [SKIPPED] xe_mocs =====================
[02:36:16] ================= xe_migrate (2 subtests) ==================
[02:36:16] ================= xe_migrate_sanity_kunit  =================
[02:36:16] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[02:36:16] ================== xe_validate_ccs_kunit  ==================
[02:36:16] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[02:36:16] =================== [SKIPPED] xe_migrate ===================
[02:36:16] ================== xe_dma_buf (1 subtest) ==================
[02:36:16] ==================== xe_dma_buf_kunit  =====================
[02:36:16] ================ [SKIPPED] xe_dma_buf_kunit ================
[02:36:16] =================== [SKIPPED] xe_dma_buf ===================
[02:36:16] ================= xe_bo_shrink (1 subtest) =================
[02:36:16] =================== xe_bo_shrink_kunit  ====================
[02:36:16] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[02:36:16] ================== [SKIPPED] xe_bo_shrink ==================
[02:36:16] ==================== xe_bo (2 subtests) ====================
[02:36:16] ================== xe_ccs_migrate_kunit  ===================
[02:36:16] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[02:36:16] ==================== xe_bo_evict_kunit  ====================
[02:36:16] =============== [SKIPPED] xe_bo_evict_kunit ================
[02:36:16] ===================== [SKIPPED] xe_bo ======================
[02:36:16] ==================== args (11 subtests) ====================
[02:36:16] [PASSED] count_args_test
[02:36:16] [PASSED] call_args_example
[02:36:16] [PASSED] call_args_test
[02:36:16] [PASSED] drop_first_arg_example
[02:36:16] [PASSED] drop_first_arg_test
[02:36:16] [PASSED] first_arg_example
[02:36:16] [PASSED] first_arg_test
[02:36:16] [PASSED] last_arg_example
[02:36:16] [PASSED] last_arg_test
[02:36:16] [PASSED] pick_arg_example
[02:36:16] [PASSED] sep_comma_example
[02:36:16] ====================== [PASSED] args =======================
[02:36:16] =================== xe_pci (3 subtests) ====================
[02:36:16] ==================== check_graphics_ip  ====================
[02:36:16] [PASSED] 12.00 Xe_LP
[02:36:16] [PASSED] 12.10 Xe_LP+
[02:36:16] [PASSED] 12.55 Xe_HPG
[02:36:16] [PASSED] 12.60 Xe_HPC
[02:36:16] [PASSED] 12.70 Xe_LPG
[02:36:16] [PASSED] 12.71 Xe_LPG
[02:36:16] [PASSED] 12.74 Xe_LPG+
[02:36:16] [PASSED] 20.01 Xe2_HPG
[02:36:16] [PASSED] 20.02 Xe2_HPG
[02:36:16] [PASSED] 20.04 Xe2_LPG
[02:36:16] [PASSED] 30.00 Xe3_LPG
[02:36:16] [PASSED] 30.01 Xe3_LPG
[02:36:16] [PASSED] 30.03 Xe3_LPG
[02:36:16] [PASSED] 30.04 Xe3_LPG
[02:36:16] [PASSED] 30.05 Xe3_LPG
[02:36:16] [PASSED] 35.11 Xe3p_XPC
[02:36:16] ================ [PASSED] check_graphics_ip ================
[02:36:16] ===================== check_media_ip  ======================
[02:36:16] [PASSED] 12.00 Xe_M
[02:36:16] [PASSED] 12.55 Xe_HPM
[02:36:16] [PASSED] 13.00 Xe_LPM+
[02:36:16] [PASSED] 13.01 Xe2_HPM
[02:36:16] [PASSED] 20.00 Xe2_LPM
[02:36:16] [PASSED] 30.00 Xe3_LPM
[02:36:16] [PASSED] 30.02 Xe3_LPM
[02:36:16] [PASSED] 35.00 Xe3p_LPM
[02:36:16] [PASSED] 35.03 Xe3p_HPM
[02:36:16] ================= [PASSED] check_media_ip ==================
[02:36:16] ================= check_platform_gt_count  =================
[02:36:16] [PASSED] 0x9A60 (TIGERLAKE)
[02:36:16] [PASSED] 0x9A68 (TIGERLAKE)
[02:36:16] [PASSED] 0x9A70 (TIGERLAKE)
[02:36:16] [PASSED] 0x9A40 (TIGERLAKE)
[02:36:16] [PASSED] 0x9A49 (TIGERLAKE)
[02:36:16] [PASSED] 0x9A59 (TIGERLAKE)
[02:36:16] [PASSED] 0x9A78 (TIGERLAKE)
[02:36:16] [PASSED] 0x9AC0 (TIGERLAKE)
[02:36:16] [PASSED] 0x9AC9 (TIGERLAKE)
[02:36:16] [PASSED] 0x9AD9 (TIGERLAKE)
[02:36:16] [PASSED] 0x9AF8 (TIGERLAKE)
[02:36:16] [PASSED] 0x4C80 (ROCKETLAKE)
[02:36:16] [PASSED] 0x4C8A (ROCKETLAKE)
[02:36:16] [PASSED] 0x4C8B (ROCKETLAKE)
[02:36:16] [PASSED] 0x4C8C (ROCKETLAKE)
[02:36:16] [PASSED] 0x4C90 (ROCKETLAKE)
[02:36:16] [PASSED] 0x4C9A (ROCKETLAKE)
[02:36:16] [PASSED] 0x4680 (ALDERLAKE_S)
[02:36:16] [PASSED] 0x4682 (ALDERLAKE_S)
[02:36:16] [PASSED] 0x4688 (ALDERLAKE_S)
[02:36:16] [PASSED] 0x468A (ALDERLAKE_S)
[02:36:16] [PASSED] 0x468B (ALDERLAKE_S)
[02:36:16] [PASSED] 0x4690 (ALDERLAKE_S)
[02:36:16] [PASSED] 0x4692 (ALDERLAKE_S)
[02:36:16] [PASSED] 0x4693 (ALDERLAKE_S)
[02:36:16] [PASSED] 0x46A0 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46A1 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46A2 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46A3 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46A6 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46A8 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46AA (ALDERLAKE_P)
[02:36:16] [PASSED] 0x462A (ALDERLAKE_P)
[02:36:16] [PASSED] 0x4626 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x4628 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46B0 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46B1 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46B2 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46B3 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46C0 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46C1 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46C2 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46C3 (ALDERLAKE_P)
[02:36:16] [PASSED] 0x46D0 (ALDERLAKE_N)
[02:36:16] [PASSED] 0x46D1 (ALDERLAKE_N)
[02:36:16] [PASSED] 0x46D2 (ALDERLAKE_N)
[02:36:16] [PASSED] 0x46D3 (ALDERLAKE_N)
[02:36:16] [PASSED] 0x46D4 (ALDERLAKE_N)
[02:36:16] [PASSED] 0xA721 (ALDERLAKE_P)
[02:36:16] [PASSED] 0xA7A1 (ALDERLAKE_P)
[02:36:16] [PASSED] 0xA7A9 (ALDERLAKE_P)
[02:36:16] [PASSED] 0xA7AC (ALDERLAKE_P)
[02:36:16] [PASSED] 0xA7AD (ALDERLAKE_P)
[02:36:16] [PASSED] 0xA720 (ALDERLAKE_P)
[02:36:16] [PASSED] 0xA7A0 (ALDERLAKE_P)
[02:36:16] [PASSED] 0xA7A8 (ALDERLAKE_P)
[02:36:16] [PASSED] 0xA7AA (ALDERLAKE_P)
[02:36:16] [PASSED] 0xA7AB (ALDERLAKE_P)
[02:36:16] [PASSED] 0xA780 (ALDERLAKE_S)
[02:36:16] [PASSED] 0xA781 (ALDERLAKE_S)
[02:36:16] [PASSED] 0xA782 (ALDERLAKE_S)
[02:36:16] [PASSED] 0xA783 (ALDERLAKE_S)
[02:36:16] [PASSED] 0xA788 (ALDERLAKE_S)
[02:36:16] [PASSED] 0xA789 (ALDERLAKE_S)
[02:36:16] [PASSED] 0xA78A (ALDERLAKE_S)
[02:36:16] [PASSED] 0xA78B (ALDERLAKE_S)
[02:36:16] [PASSED] 0x4905 (DG1)
[02:36:16] [PASSED] 0x4906 (DG1)
[02:36:16] [PASSED] 0x4907 (DG1)
[02:36:16] [PASSED] 0x4908 (DG1)
[02:36:16] [PASSED] 0x4909 (DG1)
[02:36:16] [PASSED] 0x56C0 (DG2)
[02:36:16] [PASSED] 0x56C2 (DG2)
[02:36:16] [PASSED] 0x56C1 (DG2)
[02:36:16] [PASSED] 0x7D51 (METEORLAKE)
[02:36:16] [PASSED] 0x7DD1 (METEORLAKE)
[02:36:16] [PASSED] 0x7D41 (METEORLAKE)
[02:36:16] [PASSED] 0x7D67 (METEORLAKE)
[02:36:16] [PASSED] 0xB640 (METEORLAKE)
[02:36:16] [PASSED] 0x56A0 (DG2)
[02:36:16] [PASSED] 0x56A1 (DG2)
[02:36:16] [PASSED] 0x56A2 (DG2)
[02:36:16] [PASSED] 0x56BE (DG2)
[02:36:16] [PASSED] 0x56BF (DG2)
[02:36:16] [PASSED] 0x5690 (DG2)
[02:36:16] [PASSED] 0x5691 (DG2)
[02:36:16] [PASSED] 0x5692 (DG2)
[02:36:16] [PASSED] 0x56A5 (DG2)
[02:36:16] [PASSED] 0x56A6 (DG2)
[02:36:16] [PASSED] 0x56B0 (DG2)
[02:36:16] [PASSED] 0x56B1 (DG2)
[02:36:16] [PASSED] 0x56BA (DG2)
[02:36:16] [PASSED] 0x56BB (DG2)
[02:36:16] [PASSED] 0x56BC (DG2)
[02:36:16] [PASSED] 0x56BD (DG2)
[02:36:16] [PASSED] 0x5693 (DG2)
[02:36:16] [PASSED] 0x5694 (DG2)
[02:36:16] [PASSED] 0x5695 (DG2)
[02:36:16] [PASSED] 0x56A3 (DG2)
[02:36:16] [PASSED] 0x56A4 (DG2)
[02:36:16] [PASSED] 0x56B2 (DG2)
[02:36:16] [PASSED] 0x56B3 (DG2)
[02:36:16] [PASSED] 0x5696 (DG2)
[02:36:16] [PASSED] 0x5697 (DG2)
[02:36:16] [PASSED] 0xB69 (PVC)
[02:36:16] [PASSED] 0xB6E (PVC)
[02:36:16] [PASSED] 0xBD4 (PVC)
[02:36:16] [PASSED] 0xBD5 (PVC)
[02:36:16] [PASSED] 0xBD6 (PVC)
[02:36:16] [PASSED] 0xBD7 (PVC)
[02:36:16] [PASSED] 0xBD8 (PVC)
[02:36:16] [PASSED] 0xBD9 (PVC)
[02:36:16] [PASSED] 0xBDA (PVC)
[02:36:16] [PASSED] 0xBDB (PVC)
[02:36:16] [PASSED] 0xBE0 (PVC)
[02:36:16] [PASSED] 0xBE1 (PVC)
[02:36:16] [PASSED] 0xBE5 (PVC)
[02:36:16] [PASSED] 0x7D40 (METEORLAKE)
[02:36:16] [PASSED] 0x7D45 (METEORLAKE)
[02:36:16] [PASSED] 0x7D55 (METEORLAKE)
[02:36:16] [PASSED] 0x7D60 (METEORLAKE)
[02:36:16] [PASSED] 0x7DD5 (METEORLAKE)
[02:36:16] [PASSED] 0x6420 (LUNARLAKE)
[02:36:16] [PASSED] 0x64A0 (LUNARLAKE)
[02:36:16] [PASSED] 0x64B0 (LUNARLAKE)
[02:36:16] [PASSED] 0xE202 (BATTLEMAGE)
[02:36:16] [PASSED] 0xE209 (BATTLEMAGE)
[02:36:16] [PASSED] 0xE20B (BATTLEMAGE)
[02:36:16] [PASSED] 0xE20C (BATTLEMAGE)
[02:36:16] [PASSED] 0xE20D (BATTLEMAGE)
[02:36:16] [PASSED] 0xE210 (BATTLEMAGE)
[02:36:16] [PASSED] 0xE211 (BATTLEMAGE)
[02:36:16] [PASSED] 0xE212 (BATTLEMAGE)
[02:36:16] [PASSED] 0xE216 (BATTLEMAGE)
[02:36:16] [PASSED] 0xE220 (BATTLEMAGE)
[02:36:16] [PASSED] 0xE221 (BATTLEMAGE)
[02:36:16] [PASSED] 0xE222 (BATTLEMAGE)
[02:36:16] [PASSED] 0xE223 (BATTLEMAGE)
[02:36:16] [PASSED] 0xB080 (PANTHERLAKE)
[02:36:16] [PASSED] 0xB081 (PANTHERLAKE)
[02:36:16] [PASSED] 0xB082 (PANTHERLAKE)
[02:36:16] [PASSED] 0xB083 (PANTHERLAKE)
[02:36:16] [PASSED] 0xB084 (PANTHERLAKE)
[02:36:16] [PASSED] 0xB085 (PANTHERLAKE)
[02:36:16] [PASSED] 0xB086 (PANTHERLAKE)
[02:36:16] [PASSED] 0xB087 (PANTHERLAKE)
[02:36:16] [PASSED] 0xB08F (PANTHERLAKE)
[02:36:16] [PASSED] 0xB090 (PANTHERLAKE)
[02:36:16] [PASSED] 0xB0A0 (PANTHERLAKE)
[02:36:16] [PASSED] 0xB0B0 (PANTHERLAKE)
[02:36:16] [PASSED] 0xFD80 (PANTHERLAKE)
[02:36:16] [PASSED] 0xFD81 (PANTHERLAKE)
[02:36:16] [PASSED] 0xD740 (NOVALAKE_S)
[02:36:16] [PASSED] 0xD741 (NOVALAKE_S)
[02:36:16] [PASSED] 0xD742 (NOVALAKE_S)
[02:36:16] [PASSED] 0xD743 (NOVALAKE_S)
[02:36:16] [PASSED] 0xD744 (NOVALAKE_S)
[02:36:16] [PASSED] 0xD745 (NOVALAKE_S)
[02:36:16] ============= [PASSED] check_platform_gt_count =============
[02:36:16] ===================== [PASSED] xe_pci ======================
[02:36:16] =================== xe_rtp (2 subtests) ====================
[02:36:16] =============== xe_rtp_process_to_sr_tests  ================
[02:36:16] [PASSED] coalesce-same-reg
[02:36:16] [PASSED] no-match-no-add
[02:36:16] [PASSED] match-or
[02:36:16] [PASSED] match-or-xfail
[02:36:16] [PASSED] no-match-no-add-multiple-rules
[02:36:16] [PASSED] two-regs-two-entries
[02:36:16] [PASSED] clr-one-set-other
[02:36:16] [PASSED] set-field
[02:36:16] [PASSED] conflict-duplicate
[02:36:16] [PASSED] conflict-not-disjoint
[02:36:16] [PASSED] conflict-reg-type
[02:36:16] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[02:36:16] ================== xe_rtp_process_tests  ===================
[02:36:16] [PASSED] active1
[02:36:16] [PASSED] active2
[02:36:16] [PASSED] active-inactive
[02:36:16] [PASSED] inactive-active
[02:36:16] [PASSED] inactive-1st_or_active-inactive
[02:36:16] [PASSED] inactive-2nd_or_active-inactive
[02:36:16] [PASSED] inactive-last_or_active-inactive
[02:36:16] [PASSED] inactive-no_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[02:36:16] ============== [PASSED] xe_rtp_process_tests ===============
[02:36:16] ===================== [PASSED] xe_rtp ======================
[02:36:16] ==================== xe_wa (1 subtest) =====================
[02:36:16] ======================== xe_wa_gt  =========================
[02:36:16] [PASSED] TIGERLAKE B0
[02:36:16] [PASSED] DG1 A0
[02:36:16] [PASSED] DG1 B0
[02:36:16] [PASSED] ALDERLAKE_S A0
[02:36:16] [PASSED] ALDERLAKE_S B0
[02:36:16] [PASSED] ALDERLAKE_S C0
[02:36:16] [PASSED] ALDERLAKE_S D0
[02:36:16] [PASSED] ALDERLAKE_P A0
[02:36:16] [PASSED] ALDERLAKE_P B0
[02:36:16] [PASSED] ALDERLAKE_P C0
[02:36:16] [PASSED] ALDERLAKE_S RPLS D0
[02:36:16] [PASSED] ALDERLAKE_P RPLU E0
[02:36:16] [PASSED] DG2 G10 C0
[02:36:16] [PASSED] DG2 G11 B1
[02:36:16] [PASSED] DG2 G12 A1
[02:36:16] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[02:36:16] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[02:36:16] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[02:36:16] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[02:36:16] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[02:36:16] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[02:36:16] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[02:36:16] ==================== [PASSED] xe_wa_gt =====================
[02:36:16] ====================== [PASSED] xe_wa ======================
[02:36:16] ============================================================
[02:36:16] Testing complete. Ran 317 tests: passed: 299, skipped: 18
[02:36:16] Elapsed time: 34.821s total, 4.171s configuring, 30.283s building, 0.334s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[02:36:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:36:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:36:42] Starting KUnit Kernel (1/1)...
[02:36:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:36:42] ============ drm_test_pick_cmdline (2 subtests) ============
[02:36:42] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[02:36:42] =============== drm_test_pick_cmdline_named  ===============
[02:36:42] [PASSED] NTSC
[02:36:42] [PASSED] NTSC-J
[02:36:42] [PASSED] PAL
[02:36:42] [PASSED] PAL-M
[02:36:42] =========== [PASSED] drm_test_pick_cmdline_named ===========
[02:36:42] ============== [PASSED] drm_test_pick_cmdline ==============
[02:36:42] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[02:36:42] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[02:36:42] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[02:36:42] =========== drm_validate_clone_mode (2 subtests) ===========
[02:36:42] ============== drm_test_check_in_clone_mode  ===============
[02:36:42] [PASSED] in_clone_mode
[02:36:42] [PASSED] not_in_clone_mode
[02:36:42] ========== [PASSED] drm_test_check_in_clone_mode ===========
[02:36:42] =============== drm_test_check_valid_clones  ===============
[02:36:42] [PASSED] not_in_clone_mode
[02:36:42] [PASSED] valid_clone
[02:36:42] [PASSED] invalid_clone
[02:36:42] =========== [PASSED] drm_test_check_valid_clones ===========
[02:36:42] ============= [PASSED] drm_validate_clone_mode =============
[02:36:42] ============= drm_validate_modeset (1 subtest) =============
[02:36:42] [PASSED] drm_test_check_connector_changed_modeset
[02:36:42] ============== [PASSED] drm_validate_modeset ===============
[02:36:42] ====== drm_test_bridge_get_current_state (2 subtests) ======
[02:36:42] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[02:36:42] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[02:36:42] ======== [PASSED] drm_test_bridge_get_current_state ========
[02:36:42] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[02:36:42] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[02:36:42] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[02:36:42] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[02:36:42] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[02:36:42] ============== drm_bridge_alloc (2 subtests) ===============
[02:36:42] [PASSED] drm_test_drm_bridge_alloc_basic
[02:36:42] [PASSED] drm_test_drm_bridge_alloc_get_put
[02:36:42] ================ [PASSED] drm_bridge_alloc =================
[02:36:42] ================== drm_buddy (8 subtests) ==================
[02:36:42] [PASSED] drm_test_buddy_alloc_limit
[02:36:42] [PASSED] drm_test_buddy_alloc_optimistic
[02:36:42] [PASSED] drm_test_buddy_alloc_pessimistic
[02:36:42] [PASSED] drm_test_buddy_alloc_pathological
[02:36:42] [PASSED] drm_test_buddy_alloc_contiguous
[02:36:42] [PASSED] drm_test_buddy_alloc_clear
[02:36:43] [PASSED] drm_test_buddy_alloc_range_bias
[02:36:43] [PASSED] drm_test_buddy_fragmentation_performance
[02:36:43] ==================== [PASSED] drm_buddy ====================
[02:36:43] ============= drm_cmdline_parser (40 subtests) =============
[02:36:43] [PASSED] drm_test_cmdline_force_d_only
[02:36:43] [PASSED] drm_test_cmdline_force_D_only_dvi
[02:36:43] [PASSED] drm_test_cmdline_force_D_only_hdmi
[02:36:43] [PASSED] drm_test_cmdline_force_D_only_not_digital
[02:36:43] [PASSED] drm_test_cmdline_force_e_only
[02:36:43] [PASSED] drm_test_cmdline_res
[02:36:43] [PASSED] drm_test_cmdline_res_vesa
[02:36:43] [PASSED] drm_test_cmdline_res_vesa_rblank
[02:36:43] [PASSED] drm_test_cmdline_res_rblank
[02:36:43] [PASSED] drm_test_cmdline_res_bpp
[02:36:43] [PASSED] drm_test_cmdline_res_refresh
[02:36:43] [PASSED] drm_test_cmdline_res_bpp_refresh
[02:36:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[02:36:43] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[02:36:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[02:36:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[02:36:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[02:36:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[02:36:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[02:36:43] [PASSED] drm_test_cmdline_res_margins_force_on
[02:36:43] [PASSED] drm_test_cmdline_res_vesa_margins
[02:36:43] [PASSED] drm_test_cmdline_name
[02:36:43] [PASSED] drm_test_cmdline_name_bpp
[02:36:43] [PASSED] drm_test_cmdline_name_option
[02:36:43] [PASSED] drm_test_cmdline_name_bpp_option
[02:36:43] [PASSED] drm_test_cmdline_rotate_0
[02:36:43] [PASSED] drm_test_cmdline_rotate_90
[02:36:43] [PASSED] drm_test_cmdline_rotate_180
[02:36:43] [PASSED] drm_test_cmdline_rotate_270
[02:36:43] [PASSED] drm_test_cmdline_hmirror
[02:36:43] [PASSED] drm_test_cmdline_vmirror
[02:36:43] [PASSED] drm_test_cmdline_margin_options
[02:36:43] [PASSED] drm_test_cmdline_multiple_options
[02:36:43] [PASSED] drm_test_cmdline_bpp_extra_and_option
[02:36:43] [PASSED] drm_test_cmdline_extra_and_option
[02:36:43] [PASSED] drm_test_cmdline_freestanding_options
[02:36:43] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[02:36:43] [PASSED] drm_test_cmdline_panel_orientation
[02:36:43] ================ drm_test_cmdline_invalid  =================
[02:36:43] [PASSED] margin_only
[02:36:43] [PASSED] interlace_only
[02:36:43] [PASSED] res_missing_x
[02:36:43] [PASSED] res_missing_y
[02:36:43] [PASSED] res_bad_y
[02:36:43] [PASSED] res_missing_y_bpp
[02:36:43] [PASSED] res_bad_bpp
[02:36:43] [PASSED] res_bad_refresh
[02:36:43] [PASSED] res_bpp_refresh_force_on_off
[02:36:43] [PASSED] res_invalid_mode
[02:36:43] [PASSED] res_bpp_wrong_place_mode
[02:36:43] [PASSED] name_bpp_refresh
[02:36:43] [PASSED] name_refresh
[02:36:43] [PASSED] name_refresh_wrong_mode
[02:36:43] [PASSED] name_refresh_invalid_mode
[02:36:43] [PASSED] rotate_multiple
[02:36:43] [PASSED] rotate_invalid_val
[02:36:43] [PASSED] rotate_truncated
[02:36:43] [PASSED] invalid_option
[02:36:43] [PASSED] invalid_tv_option
[02:36:43] [PASSED] truncated_tv_option
[02:36:43] ============ [PASSED] drm_test_cmdline_invalid =============
[02:36:43] =============== drm_test_cmdline_tv_options  ===============
[02:36:43] [PASSED] NTSC
[02:36:43] [PASSED] NTSC_443
[02:36:43] [PASSED] NTSC_J
[02:36:43] [PASSED] PAL
[02:36:43] [PASSED] PAL_M
[02:36:43] [PASSED] PAL_N
[02:36:43] [PASSED] SECAM
[02:36:43] [PASSED] MONO_525
[02:36:43] [PASSED] MONO_625
[02:36:43] =========== [PASSED] drm_test_cmdline_tv_options ===========
[02:36:43] =============== [PASSED] drm_cmdline_parser ================
[02:36:43] ========== drmm_connector_hdmi_init (20 subtests) ==========
[02:36:43] [PASSED] drm_test_connector_hdmi_init_valid
[02:36:43] [PASSED] drm_test_connector_hdmi_init_bpc_8
[02:36:43] [PASSED] drm_test_connector_hdmi_init_bpc_10
[02:36:43] [PASSED] drm_test_connector_hdmi_init_bpc_12
[02:36:43] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[02:36:43] [PASSED] drm_test_connector_hdmi_init_bpc_null
[02:36:43] [PASSED] drm_test_connector_hdmi_init_formats_empty
[02:36:43] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[02:36:43] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[02:36:43] [PASSED] supported_formats=0x9 yuv420_allowed=1
[02:36:43] [PASSED] supported_formats=0x9 yuv420_allowed=0
[02:36:43] [PASSED] supported_formats=0x3 yuv420_allowed=1
[02:36:43] [PASSED] supported_formats=0x3 yuv420_allowed=0
[02:36:43] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[02:36:43] [PASSED] drm_test_connector_hdmi_init_null_ddc
[02:36:43] [PASSED] drm_test_connector_hdmi_init_null_product
[02:36:43] [PASSED] drm_test_connector_hdmi_init_null_vendor
[02:36:43] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[02:36:43] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[02:36:43] [PASSED] drm_test_connector_hdmi_init_product_valid
[02:36:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[02:36:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[02:36:43] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[02:36:43] ========= drm_test_connector_hdmi_init_type_valid  =========
[02:36:43] [PASSED] HDMI-A
[02:36:43] [PASSED] HDMI-B
[02:36:43] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[02:36:43] ======== drm_test_connector_hdmi_init_type_invalid  ========
[02:36:43] [PASSED] Unknown
[02:36:43] [PASSED] VGA
[02:36:43] [PASSED] DVI-I
[02:36:43] [PASSED] DVI-D
[02:36:43] [PASSED] DVI-A
[02:36:43] [PASSED] Composite
[02:36:43] [PASSED] SVIDEO
[02:36:43] [PASSED] LVDS
[02:36:43] [PASSED] Component
[02:36:43] [PASSED] DIN
[02:36:43] [PASSED] DP
[02:36:43] [PASSED] TV
[02:36:43] [PASSED] eDP
[02:36:43] [PASSED] Virtual
[02:36:43] [PASSED] DSI
[02:36:43] [PASSED] DPI
[02:36:43] [PASSED] Writeback
[02:36:43] [PASSED] SPI
[02:36:43] [PASSED] USB
[02:36:43] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[02:36:43] ============ [PASSED] drmm_connector_hdmi_init =============
[02:36:43] ============= drmm_connector_init (3 subtests) =============
[02:36:43] [PASSED] drm_test_drmm_connector_init
[02:36:43] [PASSED] drm_test_drmm_connector_init_null_ddc
[02:36:43] ========= drm_test_drmm_connector_init_type_valid  =========
[02:36:43] [PASSED] Unknown
[02:36:43] [PASSED] VGA
[02:36:43] [PASSED] DVI-I
[02:36:43] [PASSED] DVI-D
[02:36:43] [PASSED] DVI-A
[02:36:43] [PASSED] Composite
[02:36:43] [PASSED] SVIDEO
[02:36:43] [PASSED] LVDS
[02:36:43] [PASSED] Component
[02:36:43] [PASSED] DIN
[02:36:43] [PASSED] DP
[02:36:43] [PASSED] HDMI-A
[02:36:43] [PASSED] HDMI-B
[02:36:43] [PASSED] TV
[02:36:43] [PASSED] eDP
[02:36:43] [PASSED] Virtual
[02:36:43] [PASSED] DSI
[02:36:43] [PASSED] DPI
[02:36:43] [PASSED] Writeback
[02:36:43] [PASSED] SPI
[02:36:43] [PASSED] USB
[02:36:43] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[02:36:43] =============== [PASSED] drmm_connector_init ===============
[02:36:43] ========= drm_connector_dynamic_init (6 subtests) ==========
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_init
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_init_properties
[02:36:43] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[02:36:43] [PASSED] Unknown
[02:36:43] [PASSED] VGA
[02:36:43] [PASSED] DVI-I
[02:36:43] [PASSED] DVI-D
[02:36:43] [PASSED] DVI-A
[02:36:43] [PASSED] Composite
[02:36:43] [PASSED] SVIDEO
[02:36:43] [PASSED] LVDS
[02:36:43] [PASSED] Component
[02:36:43] [PASSED] DIN
[02:36:43] [PASSED] DP
[02:36:43] [PASSED] HDMI-A
[02:36:43] [PASSED] HDMI-B
[02:36:43] [PASSED] TV
[02:36:43] [PASSED] eDP
[02:36:43] [PASSED] Virtual
[02:36:43] [PASSED] DSI
[02:36:43] [PASSED] DPI
[02:36:43] [PASSED] Writeback
[02:36:43] [PASSED] SPI
[02:36:43] [PASSED] USB
[02:36:43] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[02:36:43] ======== drm_test_drm_connector_dynamic_init_name  =========
[02:36:43] [PASSED] Unknown
[02:36:43] [PASSED] VGA
[02:36:43] [PASSED] DVI-I
[02:36:43] [PASSED] DVI-D
[02:36:43] [PASSED] DVI-A
[02:36:43] [PASSED] Composite
[02:36:43] [PASSED] SVIDEO
[02:36:43] [PASSED] LVDS
[02:36:43] [PASSED] Component
[02:36:43] [PASSED] DIN
[02:36:43] [PASSED] DP
[02:36:43] [PASSED] HDMI-A
[02:36:43] [PASSED] HDMI-B
[02:36:43] [PASSED] TV
[02:36:43] [PASSED] eDP
[02:36:43] [PASSED] Virtual
[02:36:43] [PASSED] DSI
[02:36:43] [PASSED] DPI
[02:36:43] [PASSED] Writeback
[02:36:43] [PASSED] SPI
[02:36:43] [PASSED] USB
[02:36:43] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[02:36:43] =========== [PASSED] drm_connector_dynamic_init ============
[02:36:43] ==== drm_connector_dynamic_register_early (4 subtests) =====
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[02:36:43] ====== [PASSED] drm_connector_dynamic_register_early =======
[02:36:43] ======= drm_connector_dynamic_register (7 subtests) ========
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[02:36:43] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[02:36:43] ========= [PASSED] drm_connector_dynamic_register ==========
[02:36:43] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[02:36:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[02:36:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[02:36:43] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[02:36:43] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[02:36:43] ========== drm_test_get_tv_mode_from_name_valid  ===========
[02:36:43] [PASSED] NTSC
[02:36:43] [PASSED] NTSC-443
[02:36:43] [PASSED] NTSC-J
[02:36:43] [PASSED] PAL
[02:36:43] [PASSED] PAL-M
[02:36:43] [PASSED] PAL-N
[02:36:43] [PASSED] SECAM
[02:36:43] [PASSED] Mono
[02:36:43] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[02:36:43] [PASSED] drm_test_get_tv_mode_from_name_truncated
[02:36:43] ============ [PASSED] drm_get_tv_mode_from_name ============
[02:36:43] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[02:36:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[02:36:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[02:36:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[02:36:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[02:36:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[02:36:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[02:36:43] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[02:36:43] [PASSED] VIC 96
[02:36:43] [PASSED] VIC 97
[02:36:43] [PASSED] VIC 101
[02:36:43] [PASSED] VIC 102
[02:36:43] [PASSED] VIC 106
[02:36:43] [PASSED] VIC 107
[02:36:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[02:36:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[02:36:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[02:36:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[02:36:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[02:36:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[02:36:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[02:36:43] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[02:36:43] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[02:36:43] [PASSED] Automatic
[02:36:43] [PASSED] Full
[02:36:43] [PASSED] Limited 16:235
[02:36:43] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[02:36:43] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[02:36:43] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[02:36:43] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[02:36:43] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[02:36:43] [PASSED] RGB
[02:36:43] [PASSED] YUV 4:2:0
[02:36:43] [PASSED] YUV 4:2:2
[02:36:43] [PASSED] YUV 4:4:4
[02:36:43] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[02:36:43] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[02:36:43] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[02:36:43] ============= drm_damage_helper (21 subtests) ==============
[02:36:43] [PASSED] drm_test_damage_iter_no_damage
[02:36:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[02:36:43] [PASSED] drm_test_damage_iter_no_damage_src_moved
[02:36:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[02:36:43] [PASSED] drm_test_damage_iter_no_damage_not_visible
[02:36:43] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[02:36:43] [PASSED] drm_test_damage_iter_no_damage_no_fb
[02:36:43] [PASSED] drm_test_damage_iter_simple_damage
[02:36:43] [PASSED] drm_test_damage_iter_single_damage
[02:36:43] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[02:36:43] [PASSED] drm_test_damage_iter_single_damage_outside_src
[02:36:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[02:36:43] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[02:36:43] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[02:36:43] [PASSED] drm_test_damage_iter_single_damage_src_moved
[02:36:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[02:36:43] [PASSED] drm_test_damage_iter_damage
[02:36:43] [PASSED] drm_test_damage_iter_damage_one_intersect
[02:36:43] [PASSED] drm_test_damage_iter_damage_one_outside
[02:36:43] [PASSED] drm_test_damage_iter_damage_src_moved
[02:36:43] [PASSED] drm_test_damage_iter_damage_not_visible
[02:36:43] ================ [PASSED] drm_damage_helper ================
[02:36:43] ============== drm_dp_mst_helper (3 subtests) ==============
[02:36:43] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[02:36:43] [PASSED] Clock 154000 BPP 30 DSC disabled
[02:36:43] [PASSED] Clock 234000 BPP 30 DSC disabled
[02:36:43] [PASSED] Clock 297000 BPP 24 DSC disabled
[02:36:43] [PASSED] Clock 332880 BPP 24 DSC enabled
[02:36:43] [PASSED] Clock 324540 BPP 24 DSC enabled
[02:36:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[02:36:43] ============== drm_test_dp_mst_calc_pbn_div  ===============
[02:36:43] [PASSED] Link rate 2000000 lane count 4
[02:36:43] [PASSED] Link rate 2000000 lane count 2
[02:36:43] [PASSED] Link rate 2000000 lane count 1
[02:36:43] [PASSED] Link rate 1350000 lane count 4
[02:36:43] [PASSED] Link rate 1350000 lane count 2
[02:36:43] [PASSED] Link rate 1350000 lane count 1
[02:36:43] [PASSED] Link rate 1000000 lane count 4
[02:36:43] [PASSED] Link rate 1000000 lane count 2
[02:36:43] [PASSED] Link rate 1000000 lane count 1
[02:36:43] [PASSED] Link rate 810000 lane count 4
[02:36:43] [PASSED] Link rate 810000 lane count 2
[02:36:43] [PASSED] Link rate 810000 lane count 1
[02:36:43] [PASSED] Link rate 540000 lane count 4
[02:36:43] [PASSED] Link rate 540000 lane count 2
[02:36:43] [PASSED] Link rate 540000 lane count 1
[02:36:43] [PASSED] Link rate 270000 lane count 4
[02:36:43] [PASSED] Link rate 270000 lane count 2
[02:36:43] [PASSED] Link rate 270000 lane count 1
[02:36:43] [PASSED] Link rate 162000 lane count 4
[02:36:43] [PASSED] Link rate 162000 lane count 2
[02:36:43] [PASSED] Link rate 162000 lane count 1
[02:36:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[02:36:43] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[02:36:43] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[02:36:43] [PASSED] DP_POWER_UP_PHY with port number
[02:36:43] [PASSED] DP_POWER_DOWN_PHY with port number
[02:36:43] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[02:36:43] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[02:36:43] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[02:36:43] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[02:36:43] [PASSED] DP_QUERY_PAYLOAD with port number
[02:36:43] [PASSED] DP_QUERY_PAYLOAD with VCPI
[02:36:43] [PASSED] DP_REMOTE_DPCD_READ with port number
[02:36:43] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[02:36:43] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[02:36:43] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[02:36:43] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[02:36:43] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[02:36:43] [PASSED] DP_REMOTE_I2C_READ with port number
[02:36:43] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[02:36:43] [PASSED] DP_REMOTE_I2C_READ with transactions array
[02:36:43] [PASSED] DP_REMOTE_I2C_WRITE with port number
[02:36:43] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[02:36:43] [PASSED] DP_REMOTE_I2C_WRITE with data array
[02:36:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[02:36:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[02:36:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[02:36:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[02:36:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[02:36:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[02:36:43] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[02:36:43] ================ [PASSED] drm_dp_mst_helper ================
[02:36:43] ================== drm_exec (7 subtests) ===================
[02:36:43] [PASSED] sanitycheck
[02:36:43] [PASSED] test_lock
[02:36:43] [PASSED] test_lock_unlock
[02:36:43] [PASSED] test_duplicates
[02:36:43] [PASSED] test_prepare
[02:36:43] [PASSED] test_prepare_array
[02:36:43] [PASSED] test_multiple_loops
[02:36:43] ==================== [PASSED] drm_exec =====================
[02:36:43] =========== drm_format_helper_test (17 subtests) ===========
[02:36:43] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[02:36:43] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[02:36:43] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[02:36:43] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[02:36:43] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[02:36:43] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[02:36:43] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[02:36:43] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[02:36:43] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[02:36:43] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[02:36:43] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[02:36:43] ============== drm_test_fb_xrgb8888_to_mono  ===============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[02:36:43] ==================== drm_test_fb_swab  =====================
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ================ [PASSED] drm_test_fb_swab =================
[02:36:43] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[02:36:43] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[02:36:43] [PASSED] single_pixel_source_buffer
[02:36:43] [PASSED] single_pixel_clip_rectangle
[02:36:43] [PASSED] well_known_colors
[02:36:43] [PASSED] destination_pitch
[02:36:43] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[02:36:43] ================= drm_test_fb_clip_offset  =================
[02:36:43] [PASSED] pass through
[02:36:43] [PASSED] horizontal offset
[02:36:43] [PASSED] vertical offset
[02:36:43] [PASSED] horizontal and vertical offset
[02:36:43] [PASSED] horizontal offset (custom pitch)
[02:36:43] [PASSED] vertical offset (custom pitch)
[02:36:43] [PASSED] horizontal and vertical offset (custom pitch)
[02:36:43] ============= [PASSED] drm_test_fb_clip_offset =============
[02:36:43] =================== drm_test_fb_memcpy  ====================
[02:36:43] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[02:36:43] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[02:36:43] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[02:36:43] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[02:36:43] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[02:36:43] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[02:36:43] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[02:36:43] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[02:36:43] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[02:36:43] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[02:36:43] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[02:36:43] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[02:36:43] =============== [PASSED] drm_test_fb_memcpy ================
[02:36:43] ============= [PASSED] drm_format_helper_test ==============
[02:36:43] ================= drm_format (18 subtests) =================
[02:36:43] [PASSED] drm_test_format_block_width_invalid
[02:36:43] [PASSED] drm_test_format_block_width_one_plane
[02:36:43] [PASSED] drm_test_format_block_width_two_plane
[02:36:43] [PASSED] drm_test_format_block_width_three_plane
[02:36:43] [PASSED] drm_test_format_block_width_tiled
[02:36:43] [PASSED] drm_test_format_block_height_invalid
[02:36:43] [PASSED] drm_test_format_block_height_one_plane
[02:36:43] [PASSED] drm_test_format_block_height_two_plane
[02:36:43] [PASSED] drm_test_format_block_height_three_plane
[02:36:43] [PASSED] drm_test_format_block_height_tiled
[02:36:43] [PASSED] drm_test_format_min_pitch_invalid
[02:36:43] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[02:36:43] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[02:36:43] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[02:36:43] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[02:36:43] [PASSED] drm_test_format_min_pitch_two_plane
[02:36:43] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[02:36:43] [PASSED] drm_test_format_min_pitch_tiled
[02:36:43] =================== [PASSED] drm_format ====================
[02:36:43] ============== drm_framebuffer (10 subtests) ===============
[02:36:43] ========== drm_test_framebuffer_check_src_coords  ==========
[02:36:43] [PASSED] Success: source fits into fb
[02:36:43] [PASSED] Fail: overflowing fb with x-axis coordinate
[02:36:43] [PASSED] Fail: overflowing fb with y-axis coordinate
[02:36:43] [PASSED] Fail: overflowing fb with source width
[02:36:43] [PASSED] Fail: overflowing fb with source height
[02:36:43] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[02:36:43] [PASSED] drm_test_framebuffer_cleanup
[02:36:43] =============== drm_test_framebuffer_create  ===============
[02:36:43] [PASSED] ABGR8888 normal sizes
[02:36:43] [PASSED] ABGR8888 max sizes
[02:36:43] [PASSED] ABGR8888 pitch greater than min required
[02:36:43] [PASSED] ABGR8888 pitch less than min required
[02:36:43] [PASSED] ABGR8888 Invalid width
[02:36:43] [PASSED] ABGR8888 Invalid buffer handle
[02:36:43] [PASSED] No pixel format
[02:36:43] [PASSED] ABGR8888 Width 0
[02:36:43] [PASSED] ABGR8888 Height 0
[02:36:43] [PASSED] ABGR8888 Out of bound height * pitch combination
[02:36:43] [PASSED] ABGR8888 Large buffer offset
[02:36:43] [PASSED] ABGR8888 Buffer offset for inexistent plane
[02:36:43] [PASSED] ABGR8888 Invalid flag
[02:36:43] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[02:36:43] [PASSED] ABGR8888 Valid buffer modifier
[02:36:43] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[02:36:43] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[02:36:43] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[02:36:43] [PASSED] NV12 Normal sizes
[02:36:43] [PASSED] NV12 Max sizes
[02:36:43] [PASSED] NV12 Invalid pitch
[02:36:43] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[02:36:43] [PASSED] NV12 different  modifier per-plane
[02:36:43] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[02:36:43] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[02:36:43] [PASSED] NV12 Modifier for inexistent plane
[02:36:43] [PASSED] NV12 Handle for inexistent plane
[02:36:43] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[02:36:43] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[02:36:43] [PASSED] YVU420 Normal sizes
[02:36:43] [PASSED] YVU420 Max sizes
[02:36:43] [PASSED] YVU420 Invalid pitch
[02:36:43] [PASSED] YVU420 Different pitches
[02:36:43] [PASSED] YVU420 Different buffer offsets/pitches
[02:36:43] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[02:36:43] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[02:36:43] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[02:36:43] [PASSED] YVU420 Valid modifier
[02:36:43] [PASSED] YVU420 Different modifiers per plane
[02:36:43] [PASSED] YVU420 Modifier for inexistent plane
[02:36:43] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[02:36:43] [PASSED] X0L2 Normal sizes
[02:36:43] [PASSED] X0L2 Max sizes
[02:36:43] [PASSED] X0L2 Invalid pitch
[02:36:43] [PASSED] X0L2 Pitch greater than minimum required
[02:36:43] [PASSED] X0L2 Handle for inexistent plane
[02:36:43] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[02:36:43] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[02:36:43] [PASSED] X0L2 Valid modifier
[02:36:43] [PASSED] X0L2 Modifier for inexistent plane
[02:36:43] =========== [PASSED] drm_test_framebuffer_create ===========
[02:36:43] [PASSED] drm_test_framebuffer_free
[02:36:43] [PASSED] drm_test_framebuffer_init
[02:36:43] [PASSED] drm_test_framebuffer_init_bad_format
[02:36:43] [PASSED] drm_test_framebuffer_init_dev_mismatch
[02:36:43] [PASSED] drm_test_framebuffer_lookup
[02:36:43] [PASSED] drm_test_framebuffer_lookup_inexistent
[02:36:43] [PASSED] drm_test_framebuffer_modifiers_not_supported
[02:36:43] ================= [PASSED] drm_framebuffer =================
[02:36:43] ================ drm_gem_shmem (8 subtests) ================
[02:36:43] [PASSED] drm_gem_shmem_test_obj_create
[02:36:43] [PASSED] drm_gem_shmem_test_obj_create_private
[02:36:43] [PASSED] drm_gem_shmem_test_pin_pages
[02:36:43] [PASSED] drm_gem_shmem_test_vmap
[02:36:43] [PASSED] drm_gem_shmem_test_get_pages_sgt
[02:36:43] [PASSED] drm_gem_shmem_test_get_sg_table
[02:36:43] [PASSED] drm_gem_shmem_test_madvise
[02:36:43] [PASSED] drm_gem_shmem_test_purge
[02:36:43] ================== [PASSED] drm_gem_shmem ==================
[02:36:43] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[02:36:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[02:36:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[02:36:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[02:36:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[02:36:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[02:36:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[02:36:43] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[02:36:43] [PASSED] Automatic
[02:36:43] [PASSED] Full
[02:36:43] [PASSED] Limited 16:235
[02:36:43] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[02:36:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[02:36:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[02:36:43] [PASSED] drm_test_check_disable_connector
[02:36:43] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[02:36:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[02:36:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[02:36:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[02:36:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[02:36:43] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[02:36:43] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[02:36:43] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[02:36:43] [PASSED] drm_test_check_output_bpc_dvi
[02:36:43] [PASSED] drm_test_check_output_bpc_format_vic_1
[02:36:43] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[02:36:43] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[02:36:43] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[02:36:43] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[02:36:43] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[02:36:43] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[02:36:43] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[02:36:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[02:36:43] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[02:36:43] [PASSED] drm_test_check_broadcast_rgb_value
[02:36:43] [PASSED] drm_test_check_bpc_8_value
[02:36:43] [PASSED] drm_test_check_bpc_10_value
[02:36:43] [PASSED] drm_test_check_bpc_12_value
[02:36:43] [PASSED] drm_test_check_format_value
[02:36:43] [PASSED] drm_test_check_tmds_char_value
[02:36:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[02:36:43] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[02:36:43] [PASSED] drm_test_check_mode_valid
[02:36:43] [PASSED] drm_test_check_mode_valid_reject
[02:36:43] [PASSED] drm_test_check_mode_valid_reject_rate
[02:36:43] [PASSED] drm_test_check_mode_valid_reject_max_clock
[02:36:43] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[02:36:43] ================= drm_managed (2 subtests) =================
[02:36:43] [PASSED] drm_test_managed_release_action
[02:36:43] [PASSED] drm_test_managed_run_action
[02:36:43] =================== [PASSED] drm_managed ===================
[02:36:43] =================== drm_mm (6 subtests) ====================
[02:36:43] [PASSED] drm_test_mm_init
[02:36:43] [PASSED] drm_test_mm_debug
[02:36:43] [PASSED] drm_test_mm_align32
[02:36:43] [PASSED] drm_test_mm_align64
[02:36:43] [PASSED] drm_test_mm_lowest
[02:36:43] [PASSED] drm_test_mm_highest
[02:36:43] ===================== [PASSED] drm_mm ======================
[02:36:43] ============= drm_modes_analog_tv (5 subtests) =============
[02:36:43] [PASSED] drm_test_modes_analog_tv_mono_576i
[02:36:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[02:36:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[02:36:43] [PASSED] drm_test_modes_analog_tv_pal_576i
[02:36:43] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[02:36:43] =============== [PASSED] drm_modes_analog_tv ===============
[02:36:43] ============== drm_plane_helper (2 subtests) ===============
[02:36:43] =============== drm_test_check_plane_state  ================
[02:36:43] [PASSED] clipping_simple
[02:36:43] [PASSED] clipping_rotate_reflect
[02:36:43] [PASSED] positioning_simple
[02:36:43] [PASSED] upscaling
[02:36:43] [PASSED] downscaling
[02:36:43] [PASSED] rounding1
[02:36:43] [PASSED] rounding2
[02:36:43] [PASSED] rounding3
[02:36:43] [PASSED] rounding4
[02:36:43] =========== [PASSED] drm_test_check_plane_state ============
[02:36:43] =========== drm_test_check_invalid_plane_state  ============
[02:36:43] [PASSED] positioning_invalid
[02:36:43] [PASSED] upscaling_invalid
[02:36:43] [PASSED] downscaling_invalid
[02:36:43] ======= [PASSED] drm_test_check_invalid_plane_state ========
[02:36:43] ================ [PASSED] drm_plane_helper =================
[02:36:43] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[02:36:43] ====== drm_test_connector_helper_tv_get_modes_check  =======
[02:36:43] [PASSED] None
[02:36:43] [PASSED] PAL
[02:36:43] [PASSED] NTSC
[02:36:43] [PASSED] Both, NTSC Default
[02:36:43] [PASSED] Both, PAL Default
[02:36:43] [PASSED] Both, NTSC Default, with PAL on command-line
[02:36:43] [PASSED] Both, PAL Default, with NTSC on command-line
[02:36:43] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[02:36:43] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[02:36:43] ================== drm_rect (9 subtests) ===================
[02:36:43] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[02:36:43] [PASSED] drm_test_rect_clip_scaled_not_clipped
[02:36:43] [PASSED] drm_test_rect_clip_scaled_clipped
[02:36:43] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[02:36:43] ================= drm_test_rect_intersect  =================
[02:36:43] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[02:36:43] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[02:36:43] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[02:36:43] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[02:36:43] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[02:36:43] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[02:36:43] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[02:36:43] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[02:36:43] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[02:36:43] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[02:36:43] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[02:36:43] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[02:36:43] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[02:36:43] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[02:36:43] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[02:36:43] ============= [PASSED] drm_test_rect_intersect =============
[02:36:43] ================ drm_test_rect_calc_hscale  ================
[02:36:43] [PASSED] normal use
[02:36:43] [PASSED] out of max range
[02:36:43] [PASSED] out of min range
[02:36:43] [PASSED] zero dst
[02:36:43] [PASSED] negative src
[02:36:43] [PASSED] negative dst
[02:36:43] ============ [PASSED] drm_test_rect_calc_hscale ============
[02:36:43] ================ drm_test_rect_calc_vscale  ================
[02:36:43] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[02:36:43] [PASSED] out of max range
[02:36:43] [PASSED] out of min range
[02:36:43] [PASSED] zero dst
[02:36:43] [PASSED] negative src
[02:36:43] [PASSED] negative dst
[02:36:43] ============ [PASSED] drm_test_rect_calc_vscale ============
[02:36:43] ================== drm_test_rect_rotate  ===================
[02:36:43] [PASSED] reflect-x
[02:36:43] [PASSED] reflect-y
[02:36:43] [PASSED] rotate-0
[02:36:43] [PASSED] rotate-90
[02:36:43] [PASSED] rotate-180
[02:36:43] [PASSED] rotate-270
[02:36:43] ============== [PASSED] drm_test_rect_rotate ===============
[02:36:43] ================ drm_test_rect_rotate_inv  =================
[02:36:43] [PASSED] reflect-x
[02:36:43] [PASSED] reflect-y
[02:36:43] [PASSED] rotate-0
[02:36:43] [PASSED] rotate-90
[02:36:43] [PASSED] rotate-180
[02:36:43] [PASSED] rotate-270
[02:36:43] ============ [PASSED] drm_test_rect_rotate_inv =============
[02:36:43] ==================== [PASSED] drm_rect =====================
[02:36:43] ============ drm_sysfb_modeset_test (1 subtest) ============
[02:36:43] ============ drm_test_sysfb_build_fourcc_list  =============
[02:36:43] [PASSED] no native formats
[02:36:43] [PASSED] XRGB8888 as native format
[02:36:43] [PASSED] remove duplicates
[02:36:43] [PASSED] convert alpha formats
[02:36:43] [PASSED] random formats
[02:36:43] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[02:36:43] ============= [PASSED] drm_sysfb_modeset_test ==============
[02:36:43] ============================================================
[02:36:43] Testing complete. Ran 622 tests: passed: 622
[02:36:43] Elapsed time: 26.759s total, 1.638s configuring, 24.698s building, 0.392s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[02:36:43] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:36:45] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:36:54] Starting KUnit Kernel (1/1)...
[02:36:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:36:54] ================= ttm_device (5 subtests) ==================
[02:36:54] [PASSED] ttm_device_init_basic
[02:36:54] [PASSED] ttm_device_init_multiple
[02:36:54] [PASSED] ttm_device_fini_basic
[02:36:54] [PASSED] ttm_device_init_no_vma_man
[02:36:54] ================== ttm_device_init_pools  ==================
[02:36:54] [PASSED] No DMA allocations, no DMA32 required
[02:36:54] [PASSED] DMA allocations, DMA32 required
[02:36:54] [PASSED] No DMA allocations, DMA32 required
[02:36:54] [PASSED] DMA allocations, no DMA32 required
[02:36:54] ============== [PASSED] ttm_device_init_pools ==============
[02:36:54] =================== [PASSED] ttm_device ====================
[02:36:54] ================== ttm_pool (8 subtests) ===================
[02:36:54] ================== ttm_pool_alloc_basic  ===================
[02:36:54] [PASSED] One page
[02:36:54] [PASSED] More than one page
[02:36:54] [PASSED] Above the allocation limit
[02:36:54] [PASSED] One page, with coherent DMA mappings enabled
[02:36:54] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[02:36:54] ============== [PASSED] ttm_pool_alloc_basic ===============
[02:36:54] ============== ttm_pool_alloc_basic_dma_addr  ==============
[02:36:54] [PASSED] One page
[02:36:54] [PASSED] More than one page
[02:36:54] [PASSED] Above the allocation limit
[02:36:54] [PASSED] One page, with coherent DMA mappings enabled
[02:36:54] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[02:36:54] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[02:36:54] [PASSED] ttm_pool_alloc_order_caching_match
[02:36:54] [PASSED] ttm_pool_alloc_caching_mismatch
[02:36:54] [PASSED] ttm_pool_alloc_order_mismatch
[02:36:54] [PASSED] ttm_pool_free_dma_alloc
[02:36:54] [PASSED] ttm_pool_free_no_dma_alloc
[02:36:54] [PASSED] ttm_pool_fini_basic
[02:36:54] ==================== [PASSED] ttm_pool =====================
[02:36:54] ================ ttm_resource (8 subtests) =================
[02:36:54] ================= ttm_resource_init_basic  =================
[02:36:54] [PASSED] Init resource in TTM_PL_SYSTEM
[02:36:54] [PASSED] Init resource in TTM_PL_VRAM
[02:36:54] [PASSED] Init resource in a private placement
[02:36:54] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[02:36:54] ============= [PASSED] ttm_resource_init_basic =============
[02:36:54] [PASSED] ttm_resource_init_pinned
[02:36:54] [PASSED] ttm_resource_fini_basic
[02:36:54] [PASSED] ttm_resource_manager_init_basic
[02:36:54] [PASSED] ttm_resource_manager_usage_basic
[02:36:54] [PASSED] ttm_resource_manager_set_used_basic
[02:36:54] [PASSED] ttm_sys_man_alloc_basic
[02:36:54] [PASSED] ttm_sys_man_free_basic
[02:36:54] ================== [PASSED] ttm_resource ===================
[02:36:54] =================== ttm_tt (15 subtests) ===================
[02:36:54] ==================== ttm_tt_init_basic  ====================
[02:36:54] [PASSED] Page-aligned size
[02:36:54] [PASSED] Extra pages requested
[02:36:54] ================ [PASSED] ttm_tt_init_basic ================
[02:36:54] [PASSED] ttm_tt_init_misaligned
[02:36:54] [PASSED] ttm_tt_fini_basic
[02:36:54] [PASSED] ttm_tt_fini_sg
[02:36:54] [PASSED] ttm_tt_fini_shmem
[02:36:54] [PASSED] ttm_tt_create_basic
[02:36:54] [PASSED] ttm_tt_create_invalid_bo_type
[02:36:54] [PASSED] ttm_tt_create_ttm_exists
[02:36:54] [PASSED] ttm_tt_create_failed
[02:36:54] [PASSED] ttm_tt_destroy_basic
[02:36:54] [PASSED] ttm_tt_populate_null_ttm
[02:36:54] [PASSED] ttm_tt_populate_populated_ttm
[02:36:54] [PASSED] ttm_tt_unpopulate_basic
[02:36:54] [PASSED] ttm_tt_unpopulate_empty_ttm
[02:36:54] [PASSED] ttm_tt_swapin_basic
[02:36:54] ===================== [PASSED] ttm_tt ======================
[02:36:54] =================== ttm_bo (14 subtests) ===================
[02:36:54] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[02:36:54] [PASSED] Cannot be interrupted and sleeps
[02:36:54] [PASSED] Cannot be interrupted, locks straight away
[02:36:54] [PASSED] Can be interrupted, sleeps
[02:36:54] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[02:36:54] [PASSED] ttm_bo_reserve_locked_no_sleep
[02:36:54] [PASSED] ttm_bo_reserve_no_wait_ticket
[02:36:54] [PASSED] ttm_bo_reserve_double_resv
[02:36:54] [PASSED] ttm_bo_reserve_interrupted
[02:36:54] [PASSED] ttm_bo_reserve_deadlock
[02:36:54] [PASSED] ttm_bo_unreserve_basic
[02:36:54] [PASSED] ttm_bo_unreserve_pinned
[02:36:54] [PASSED] ttm_bo_unreserve_bulk
[02:36:54] [PASSED] ttm_bo_fini_basic
[02:36:54] [PASSED] ttm_bo_fini_shared_resv
[02:36:54] [PASSED] ttm_bo_pin_basic
[02:36:54] [PASSED] ttm_bo_pin_unpin_resource
[02:36:54] [PASSED] ttm_bo_multiple_pin_one_unpin
[02:36:54] ===================== [PASSED] ttm_bo ======================
[02:36:54] ============== ttm_bo_validate (21 subtests) ===============
[02:36:54] ============== ttm_bo_init_reserved_sys_man  ===============
[02:36:54] [PASSED] Buffer object for userspace
[02:36:54] [PASSED] Kernel buffer object
[02:36:54] [PASSED] Shared buffer object
[02:36:54] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[02:36:54] ============== ttm_bo_init_reserved_mock_man  ==============
[02:36:54] [PASSED] Buffer object for userspace
[02:36:54] [PASSED] Kernel buffer object
[02:36:54] [PASSED] Shared buffer object
[02:36:54] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[02:36:54] [PASSED] ttm_bo_init_reserved_resv
[02:36:54] ================== ttm_bo_validate_basic  ==================
[02:36:54] [PASSED] Buffer object for userspace
[02:36:54] [PASSED] Kernel buffer object
[02:36:54] [PASSED] Shared buffer object
[02:36:54] ============== [PASSED] ttm_bo_validate_basic ==============
[02:36:54] [PASSED] ttm_bo_validate_invalid_placement
[02:36:54] ============= ttm_bo_validate_same_placement  ==============
[02:36:54] [PASSED] System manager
[02:36:54] [PASSED] VRAM manager
[02:36:54] ========= [PASSED] ttm_bo_validate_same_placement ==========
[02:36:54] [PASSED] ttm_bo_validate_failed_alloc
[02:36:54] [PASSED] ttm_bo_validate_pinned
[02:36:54] [PASSED] ttm_bo_validate_busy_placement
[02:36:54] ================ ttm_bo_validate_multihop  =================
[02:36:54] [PASSED] Buffer object for userspace
[02:36:54] [PASSED] Kernel buffer object
[02:36:54] [PASSED] Shared buffer object
[02:36:54] ============ [PASSED] ttm_bo_validate_multihop =============
[02:36:54] ========== ttm_bo_validate_no_placement_signaled  ==========
[02:36:54] [PASSED] Buffer object in system domain, no page vector
[02:36:54] [PASSED] Buffer object in system domain with an existing page vector
[02:36:54] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[02:36:54] ======== ttm_bo_validate_no_placement_not_signaled  ========
[02:36:54] [PASSED] Buffer object for userspace
[02:36:54] [PASSED] Kernel buffer object
[02:36:54] [PASSED] Shared buffer object
[02:36:54] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[02:36:54] [PASSED] ttm_bo_validate_move_fence_signaled
[02:36:54] ========= ttm_bo_validate_move_fence_not_signaled  =========
[02:36:54] [PASSED] Waits for GPU
[02:36:54] [PASSED] Tries to lock straight away
[02:36:54] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[02:36:54] [PASSED] ttm_bo_validate_happy_evict
[02:36:54] [PASSED] ttm_bo_validate_all_pinned_evict
[02:36:54] [PASSED] ttm_bo_validate_allowed_only_evict
[02:36:54] [PASSED] ttm_bo_validate_deleted_evict
[02:36:54] [PASSED] ttm_bo_validate_busy_domain_evict
[02:36:54] [PASSED] ttm_bo_validate_evict_gutting
[02:36:54] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[02:36:54] ================= [PASSED] ttm_bo_validate =================
[02:36:54] ============================================================
[02:36:54] Testing complete. Ran 101 tests: passed: 101
[02:36:54] Elapsed time: 11.383s total, 1.738s configuring, 9.428s building, 0.185s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: Add Xe3p support (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1456 bytes --]

== Series Details ==

Series: drm/xe: Add Xe3p support (rev3)
URL   : https://patchwork.freedesktop.org/series/155866/
State : success

== Summary ==

CI Bug Log - changes from xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb_BAT -> xe-pw-155866v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-155866v3_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_flip@basic-plain-flip@d-edp1:
    - bat-adlp-7:         [DMESG-WARN][1] ([Intel XE#4543]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/bat-adlp-7/igt@kms_flip@basic-plain-flip@d-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/bat-adlp-7/igt@kms_flip@basic-plain-flip@d-edp1.html

  
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543


Build changes
-------------

  * Linux: xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb -> xe-pw-155866v3

  IGT_8589: 8589
  xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb: b4f191dddaee9ae1871344e3dabcc40f2f14d2cb
  xe-pw-155866v3: 155866v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/index.html

[-- Attachment #2: Type: text/html, Size: 2021 bytes --]

✗ Xe.CI.Full: failure for drm/xe: Add Xe3p support (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 46846 bytes --]

== Series Details ==

Series: drm/xe: Add Xe3p support (rev3)
URL   : https://patchwork.freedesktop.org/series/155866/
State : failure

== Summary ==

CI Bug Log - changes from xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb_FULL -> xe-pw-155866v3_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-155866v3_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-155866v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-155866v3_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane_cursor@viewport:
    - shard-bmg:          [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-4/igt@kms_plane_cursor@viewport.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-2/igt@kms_plane_cursor@viewport.html

  * igt@kms_pm_rpm@drm-resources-equal:
    - shard-bmg:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-7/igt@kms_pm_rpm@drm-resources-equal.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_pm_rpm@drm-resources-equal.html

  * igt@xe_gt_freq@freq_fixed_idle:
    - shard-dg2-set2:     [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-433/igt@xe_gt_freq@freq_fixed_idle.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-433/igt@xe_gt_freq@freq_fixed_idle.html

  * igt@xe_pm@s3-mocs:
    - shard-adlp:         NOTRUN -> [INCOMPLETE][7]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@xe_pm@s3-mocs.html

  
Known issues
------------

  Here are the changes found in xe-pw-155866v3_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2327]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-adlp:         NOTRUN -> [SKIP][9] ([Intel XE#1124]) +4 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-adlp:         NOTRUN -> [SKIP][10] ([Intel XE#316]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][11] ([Intel XE#4543]) +4 other tests dmesg-fail
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#1124]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][13] ([Intel XE#607])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-adlp:         NOTRUN -> [SKIP][14] ([Intel XE#367]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][15] ([Intel XE#455] / [Intel XE#787]) +17 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-434/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][17] ([Intel XE#787]) +6 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-434/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#3432])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][19] ([Intel XE#2907]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][20] ([Intel XE#787]) +26 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][21] -> [INCOMPLETE][22] ([Intel XE#2705] / [Intel XE#4212])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [PASS][23] -> [INCOMPLETE][24] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) +1 other test incomplete
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2887]) +3 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-adlp:         NOTRUN -> [SKIP][26] ([Intel XE#373]) +4 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_color@ctm-limited-range:
    - shard-adlp:         NOTRUN -> [SKIP][27] ([Intel XE#306])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_chamelium_color@ctm-limited-range.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2252]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2390])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-adlp:         NOTRUN -> [SKIP][30] ([Intel XE#308]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2321])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][32] ([Intel XE#2953] / [Intel XE#4173]) +3 other tests dmesg-warn
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
    - shard-adlp:         NOTRUN -> [SKIP][33] ([Intel XE#309]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][34] -> [SKIP][35] ([Intel XE#2291]) +4 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-bmg:          [PASS][36] -> [SKIP][37] ([Intel XE#4294])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-7/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2244]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_feature_discovery@display-4x:
    - shard-adlp:         NOTRUN -> [SKIP][39] ([Intel XE#1138])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@psr2:
    - shard-adlp:         NOTRUN -> [SKIP][40] ([Intel XE#1135])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-bmg:          [PASS][41] -> [FAIL][42] ([Intel XE#3149] / [Intel XE#5352]) +1 other test fail
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-3/igt@kms_flip@2x-blocking-wf_vblank.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-blocking-wf_vblank@ac-dp2-hdmi-a3:
    - shard-bmg:          [PASS][43] -> [FAIL][44] ([Intel XE#5352]) +4 other tests fail
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-3/igt@kms_flip@2x-blocking-wf_vblank@ac-dp2-hdmi-a3.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_flip@2x-blocking-wf_vblank@ac-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-adlp:         NOTRUN -> [SKIP][45] ([Intel XE#310]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-bmg:          [PASS][46] -> [SKIP][47] ([Intel XE#2316]) +3 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-5/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][48] ([Intel XE#4543]) +3 other tests dmesg-warn
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-rmfb-interruptible:
    - shard-adlp:         [PASS][49] -> [DMESG-WARN][50] ([Intel XE#4543] / [Intel XE#5208])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-6/igt@kms_flip@flip-vs-rmfb-interruptible.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-2/igt@kms_flip@flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
    - shard-adlp:         [PASS][51] -> [DMESG-WARN][52] ([Intel XE#4543]) +4 other tests dmesg-warn
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-2/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-adlp:         NOTRUN -> [SKIP][53] ([Intel XE#455]) +12 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#2380]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][55] ([Intel XE#4543] / [Intel XE#4921]) +1 other test dmesg-fail
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2311]) +6 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
    - shard-adlp:         NOTRUN -> [SKIP][57] ([Intel XE#656]) +19 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#5390]) +2 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-rte:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#5427])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-rte.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen:
    - shard-adlp:         NOTRUN -> [SKIP][60] ([Intel XE#651]) +7 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][61] ([Intel XE#651])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
    - shard-adlp:         NOTRUN -> [SKIP][62] ([Intel XE#653]) +7 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][63] ([Intel XE#653])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#2313]) +6 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-adlp:         NOTRUN -> [SKIP][65] ([Intel XE#1158])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-bmg:          [PASS][66] -> [SKIP][67] ([Intel XE#1503])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-5/igt@kms_hdr@invalid-metadata-sizes.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][68] ([Intel XE#346])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][69] ([Intel XE#3012])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_lease@empty-lease:
    - shard-bmg:          [PASS][70] -> [DMESG-WARN][71] ([Intel XE#3428]) +6 other tests dmesg-warn
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-3/igt@kms_lease@empty-lease.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_lease@empty-lease.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc:
    - shard-adlp:         [PASS][72] -> [DMESG-WARN][73] ([Intel XE#2953] / [Intel XE#4173]) +12 other tests dmesg-warn
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@kms_pipe_crc_basic@disable-crc-after-crtc.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-2/igt@kms_pipe_crc_basic@disable-crc-after-crtc.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-adlp:         NOTRUN -> [SKIP][74] ([Intel XE#4596])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#5021])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-bmg:          [PASS][76] -> [SKIP][77] ([Intel XE#2571])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-3/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#2392])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_rpm@drm-resources-equal:
    - shard-adlp:         NOTRUN -> [SKIP][79] ([Intel XE#6070])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@kms_pm_rpm@drm-resources-equal.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-adlp:         NOTRUN -> [SKIP][80] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-adlp:         NOTRUN -> [SKIP][82] ([Intel XE#1122] / [Intel XE#1406] / [Intel XE#5580])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@kms_psr@fbc-psr-dpms.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-adlp:         NOTRUN -> [SKIP][84] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +6 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-adlp:         NOTRUN -> [SKIP][85] ([Intel XE#3414]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-bmg:          [PASS][86] -> [SKIP][87] ([Intel XE#1435])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-5/igt@kms_setmode@clone-exclusive-crtc.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@xe_compute_preempt@compute-preempt-many-all-ram:
    - shard-adlp:         NOTRUN -> [SKIP][88] ([Intel XE#6360])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_compute_preempt@compute-preempt-many-all-ram.html

  * igt@xe_create@create-big-vram:
    - shard-adlp:         NOTRUN -> [SKIP][89] ([Intel XE#1062])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_create@create-big-vram.html

  * igt@xe_eu_stall@blocking-read:
    - shard-adlp:         NOTRUN -> [SKIP][90] ([Intel XE#5626]) +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_eu_stall@blocking-read.html

  * igt@xe_eudebug@basic-vm-access-parameters-faultable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][91] ([Intel XE#4837])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-435/igt@xe_eudebug@basic-vm-access-parameters-faultable.html

  * igt@xe_eudebug@basic-vm-access-parameters-userptr-faultable:
    - shard-adlp:         NOTRUN -> [SKIP][92] ([Intel XE#4837] / [Intel XE#5565]) +6 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@xe_eudebug@basic-vm-access-parameters-userptr-faultable.html

  * igt@xe_eudebug_online@basic-breakpoint:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#4837]) +3 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@xe_eudebug_online@basic-breakpoint.html

  * igt@xe_evict@evict-beng-large-external-cm:
    - shard-adlp:         NOTRUN -> [SKIP][94] ([Intel XE#261] / [Intel XE#5564])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_evict@evict-beng-large-external-cm.html

  * igt@xe_evict@evict-beng-small:
    - shard-adlp:         NOTRUN -> [SKIP][95] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688]) +2 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_evict@evict-beng-small.html

  * igt@xe_evict@evict-cm-threads-small-multi-vm:
    - shard-adlp:         NOTRUN -> [SKIP][96] ([Intel XE#261])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_evict@evict-cm-threads-small-multi-vm.html

  * igt@xe_evict@evict-mixed-threads-small:
    - shard-adlp:         NOTRUN -> [SKIP][97] ([Intel XE#261] / [Intel XE#688])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_evict@evict-mixed-threads-small.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate-race:
    - shard-adlp:         NOTRUN -> [SKIP][98] ([Intel XE#1392] / [Intel XE#5575]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-null:
    - shard-bmg:          NOTRUN -> [SKIP][99] ([Intel XE#2322])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@xe_exec_basic@multigpu-no-exec-null.html

  * igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault:
    - shard-adlp:         NOTRUN -> [SKIP][100] ([Intel XE#288] / [Intel XE#5561]) +16 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence:
    - shard-adlp:         NOTRUN -> [SKIP][101] ([Intel XE#2360])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html

  * igt@xe_exec_system_allocator@once-mmap-remap-ro-dontunmap:
    - shard-adlp:         NOTRUN -> [SKIP][102] ([Intel XE#4915]) +153 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@xe_exec_system_allocator@once-mmap-remap-ro-dontunmap.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
    - shard-bmg:          NOTRUN -> [SKIP][103] ([Intel XE#4943]) +3 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-8/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-race-nomemset:
    - shard-dg2-set2:     NOTRUN -> [SKIP][104] ([Intel XE#4915]) +10 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-434/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-race-nomemset.html

  * igt@xe_oa@blocking:
    - shard-dg2-set2:     NOTRUN -> [SKIP][105] ([Intel XE#3573])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-435/igt@xe_oa@blocking.html

  * igt@xe_oa@rc6-disable:
    - shard-adlp:         NOTRUN -> [SKIP][106] ([Intel XE#3573]) +3 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_oa@rc6-disable.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-adlp:         NOTRUN -> [SKIP][107] ([Intel XE#1337] / [Intel XE#5572])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pm@s2idle-vm-bind-userptr:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][108] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_pm@s2idle-vm-bind-userptr.html

  * igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0:
    - shard-adlp:         NOTRUN -> [TIMEOUT][109] ([Intel XE#5213]) +1 other test timeout
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0.html

  * igt@xe_pxp@pxp-termination-key-update-post-termination-irq:
    - shard-adlp:         NOTRUN -> [SKIP][110] ([Intel XE#4733] / [Intel XE#5594]) +3 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_pxp@pxp-termination-key-update-post-termination-irq.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-adlp:         NOTRUN -> [SKIP][111] ([Intel XE#944])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-6/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  
#### Possible fixes ####

  * igt@kms_addfb_basic@no-handle:
    - shard-adlp:         [DMESG-WARN][112] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][113] +4 other tests pass
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-8/igt@kms_addfb_basic@no-handle.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-8/igt@kms_addfb_basic@no-handle.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-bmg:          [FAIL][114] ([Intel XE#3718] / [Intel XE#6078]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2:
    - shard-bmg:          [FAIL][116] ([Intel XE#6078]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][118] ([Intel XE#4633]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][120] ([Intel XE#301]) -> [PASS][121] +1 other test pass
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-rmfb:
    - shard-adlp:         [DMESG-WARN][122] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-2/igt@kms_flip@flip-vs-rmfb.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_flip@flip-vs-suspend@d-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][124] ([Intel XE#4543]) -> [PASS][125] +7 other tests pass
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-2/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][126] ([Intel XE#1503]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-3/igt@kms_hdr@invalid-hdr.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc:
    - shard-dg2-set2:     [INCOMPLETE][128] -> [PASS][129] +2 other tests pass
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-463/igt@kms_pipe_crc_basic@disable-crc-after-crtc.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-434/igt@kms_pipe_crc_basic@disable-crc-after-crtc.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][130] ([Intel XE#6321]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html

  * {igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma}:
    - shard-lnl:          [FAIL][132] ([Intel XE#5625]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-lnl-4/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  
#### Warnings ####

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-adlp:         [DMESG-FAIL][134] ([Intel XE#4543]) -> [DMESG-FAIL][135] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][136] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [INCOMPLETE][137] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-set2:     [INCOMPLETE][138] ([Intel XE#4907]) -> [INCOMPLETE][139] ([Intel XE#4842] / [Intel XE#4907]) +1 other test incomplete
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-dg2-466/igt@kms_content_protection@atomic-dpms.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-dg2-466/igt@kms_content_protection@atomic-dpms.html
    - shard-bmg:          [FAIL][140] ([Intel XE#1178]) -> [SKIP][141] ([Intel XE#2341])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-7/igt@kms_content_protection@atomic-dpms.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-bmg:          [SKIP][142] ([Intel XE#2321]) -> [SKIP][143] ([Intel XE#2320])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-7/igt@kms_cursor_crc@cursor-random-512x170.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_flip@flip-vs-panning-vs-hang@d-hdmi-a1:
    - shard-adlp:         [TIMEOUT][144] ([Intel XE#4543]) -> [DMESG-WARN][145] ([Intel XE#4543]) +1 other test dmesg-warn
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-2/igt@kms_flip@flip-vs-panning-vs-hang@d-hdmi-a1.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-1/igt@kms_flip@flip-vs-panning-vs-hang@d-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-adlp:         [DMESG-WARN][146] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [DMESG-WARN][147] ([Intel XE#4543])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-adlp-2/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][148] ([Intel XE#2311]) -> [SKIP][149] ([Intel XE#2312]) +8 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][150] ([Intel XE#5390]) -> [SKIP][151] ([Intel XE#2312]) +2 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-bmg:          [SKIP][152] ([Intel XE#2313]) -> [SKIP][153] ([Intel XE#2312]) +7 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1062]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1062
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4842]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4842
  [Intel XE#4907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4907
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4921]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4921
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5352
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5427
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5572]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5572
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5580]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5580
  [Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6070]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6070
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#6259]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6259
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6313
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
  [Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb -> xe-pw-155866v3

  IGT_8589: 8589
  xe-3938-b4f191dddaee9ae1871344e3dabcc40f2f14d2cb: b4f191dddaee9ae1871344e3dabcc40f2f14d2cb
  xe-pw-155866v3: 155866v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v3/index.html

[-- Attachment #2: Type: text/html, Size: 53825 bytes --]

Re: [PATCH v3 00/24] drm/xe: Add Xe3p support

[Lucas De Marchi]

On Thu, Oct 16, 2025 at 07:26:19PM -0700, Lucas De Marchi wrote:
>This begins the support for the Xe3p arch - it contains generic support
>for graphics version 35 and the Xe3p_xpc IP, the Xe3p_LPM IP for media
>and support for Nova Lake S (NVL-S), that uses a mix of IPs - the
>display side for NVL-S will be submitted separately.
>
>Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
>Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
>Changes in v3:
>- Add more patches for irq refactors as discussed in v2
>- Fix vecs irqs from v2
>- s/Xe3p_LPM/Xe3p_HPM/ where appropriate
>- Some other changes, mentioned in the individual commits


thanks you all for the reviews. I merged the GuC patch to
topic/xe-for-CI and all other patches in this version to drm-xe-next.

Lucas De Marchi