From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
Dave Jiang <dave.jiang@intel.com>,
Robert Richter <rrichter@amd.com>
Subject: [PATCH v3 1/9] cxl/acpi: Register CXL host ports by bridge device
Date: Wed, 9 Nov 2022 11:40:51 +0100 [thread overview]
Message-ID: <20221109104059.766720-2-rrichter@amd.com> (raw)
In-Reply-To: <20221109104059.766720-1-rrichter@amd.com>
A port of a CXL host bridge links to the bridge's acpi device
(&adev->dev) with its corresponding uport/dport device (uport_dev and
dport_dev respectively). The device is not a direct parent device in
the PCI topology as pdev->dev.parent points to a PCI bridge's (struct
pci_host_bridge) device. The following CXL memory device hierarchy
would be valid for an endpoint once an RCD EP would be enabled (note
this will be done in a later patch):
VH mode:
cxlmd->dev.parent->parent
^^^\^^^^^^\ ^^^^^^\
\ \ pci_dev (Type 1, Downstream Port)
\ pci_dev (Type 0, PCI Express Endpoint)
cxl mem device
RCD mode:
cxlmd->dev.parent->parent
^^^\^^^^^^\ ^^^^^^\
\ \ pci_host_bridge
\ pci_dev (Type 0, RCiEP)
cxl mem device
In VH mode a downstream port is created by port enumeration and thus
always exists.
Now, in RCD mode the host bridge also already exists but it references
to an ACPI device. A port lookup by the PCI device's parent device
will fail as a direct link to the registered port is missing. The ACPI
device of the bridge must be determined first.
To prevent this, change port registration of a CXL host to use the
bridge device instead. Do this also for the VH case as port topology
will better reflect the PCI topology then.
If a mock device is registered by a test driver, the bridge pointer
can be NULL. Keep using the matching ACPI device (&adev->dev) as a
fallback in this case.
Signed-off-by: Robert Richter <rrichter@amd.com>
---
drivers/cxl/acpi.c | 48 ++++++++++++++++++++++++++++++----------------
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index fb9f72813067..06150c953f58 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -185,6 +185,17 @@ __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
return NULL;
}
+static inline struct acpi_pci_root *to_cxl_pci_root(struct device *host,
+ struct device *match)
+{
+ struct acpi_device *adev = to_cxl_host_bridge(host, match);
+
+ if (!adev)
+ return NULL;
+
+ return acpi_pci_find_root(adev->handle);
+}
+
/*
* A host bridge is a dport to a CFMWS decode and it is a uport to the
* dport (PCIe Root Ports) in the host bridge.
@@ -193,35 +204,35 @@ static int add_host_bridge_uport(struct device *match, void *arg)
{
struct cxl_port *root_port = arg;
struct device *host = root_port->dev.parent;
- struct acpi_device *bridge = to_cxl_host_bridge(host, match);
- struct acpi_pci_root *pci_root;
+ struct acpi_pci_root *pci_root = to_cxl_pci_root(host, match);
struct cxl_dport *dport;
struct cxl_port *port;
+ struct device *bridge;
int rc;
- if (!bridge)
+ if (!pci_root)
return 0;
- dport = cxl_find_dport_by_dev(root_port, match);
+ /*
+ * If it is a mock dev, the bridge can be NULL, use matching
+ * device (&adev->dev) as a fallback then then.
+ */
+ bridge = pci_root->bus->bridge ?: match;
+ dport = cxl_find_dport_by_dev(root_port, bridge);
if (!dport) {
dev_dbg(host, "host bridge expected and not found\n");
return 0;
}
- /*
- * Note that this lookup already succeeded in
- * to_cxl_host_bridge(), so no need to check for failure here
- */
- pci_root = acpi_pci_find_root(bridge->handle);
- rc = devm_cxl_register_pci_bus(host, match, pci_root->bus);
+ rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
if (rc)
return rc;
- port = devm_cxl_add_port(host, match, dport->component_reg_phys, dport);
+ port = devm_cxl_add_port(host, bridge, dport->component_reg_phys, dport);
if (IS_ERR(port))
return PTR_ERR(port);
- dev_info(pci_root->bus->bridge, "host supports CXL\n");
+ dev_info(bridge, "host supports CXL\n");
return 0;
}
@@ -258,13 +269,16 @@ static int add_host_bridge_dport(struct device *match, void *arg)
struct cxl_chbs_context ctx;
struct cxl_port *root_port = arg;
struct device *host = root_port->dev.parent;
- struct acpi_device *bridge = to_cxl_host_bridge(host, match);
+ struct acpi_pci_root *pci_root = to_cxl_pci_root(host, match);
+ struct device *bridge;
+ acpi_handle handle;
- if (!bridge)
+ if (!pci_root)
return 0;
- status = acpi_evaluate_integer(bridge->handle, METHOD_NAME__UID, NULL,
- &uid);
+ bridge = pci_root->bus->bridge ?: match;
+ handle = pci_root->device->handle;
+ status = acpi_evaluate_integer(handle, METHOD_NAME__UID, NULL, &uid);
if (status != AE_OK) {
dev_err(match, "unable to retrieve _UID\n");
return -ENODEV;
@@ -285,7 +299,7 @@ static int add_host_bridge_dport(struct device *match, void *arg)
dev_dbg(match, "CHBCR found: 0x%08llx\n", (u64)ctx.chbcr);
- dport = devm_cxl_add_dport(root_port, match, uid, ctx.chbcr);
+ dport = devm_cxl_add_dport(root_port, bridge, uid, ctx.chbcr);
if (IS_ERR(dport))
return PTR_ERR(dport);
--
2.30.2
next prev parent reply other threads:[~2022-11-09 10:41 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-09 10:40 [PATCH v3 0/9] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-11-09 10:40 ` Robert Richter [this message]
2022-11-09 23:11 ` [PATCH v3 1/9] cxl/acpi: Register CXL host ports by bridge device Bjorn Helgaas
2022-11-14 20:22 ` Dan Williams
2022-11-15 10:37 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 2/9] cxl/acpi: Extract component registers of restricted hosts from RCRB Robert Richter
2022-11-14 21:30 ` Dan Williams
2022-11-15 12:17 ` Robert Richter
2022-11-15 17:54 ` Dan Williams
2022-11-17 12:43 ` Robert Richter
2022-11-17 17:20 ` Dan Williams
2022-11-17 18:25 ` Robert Richter
2022-11-17 19:23 ` Dan Williams
2022-11-18 8:12 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 3/9] cxl/mem: Adjust cxl_mem_find_port() to find an RCH's port Robert Richter
2022-11-14 23:45 ` Dan Williams
2022-11-15 13:12 ` Robert Richter
2022-11-15 18:06 ` Dan Williams
2022-11-17 18:13 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 4/9] cxl/mem: Skip intermediate port enumeration of restricted endpoints (RCDs) Robert Richter
2022-11-09 16:55 ` Dave Jiang
2022-11-15 0:07 ` Dan Williams
2022-11-15 13:17 ` Robert Richter
2022-11-15 18:08 ` Dan Williams
2022-11-17 18:46 ` Robert Richter
2022-11-15 0:24 ` Dan Williams
2022-11-15 13:28 ` Robert Richter
2022-11-15 18:09 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 5/9] cxl/pci: Only register RCDs with device 0, function 0 as CXL memory device Robert Richter
2022-11-16 19:24 ` Dan Williams
2022-11-17 15:56 ` Robert Richter
2022-11-17 17:27 ` Dan Williams
2022-11-18 8:27 ` Robert Richter
2022-11-18 16:55 ` Dan Williams
2022-11-18 19:53 ` Robert Richter
2022-11-18 20:30 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 6/9] cxl/pci: Do not ignore PCI config read errors in match_add_dports() Robert Richter
2022-11-09 23:09 ` Bjorn Helgaas
2022-11-11 11:56 ` Robert Richter
2022-11-11 12:07 ` Robert Richter
2022-11-16 19:36 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 7/9] cxl/pci: Factor out code in match_add_dports() to pci_dev_add_dport() Robert Richter
2022-11-16 19:37 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 8/9] cxl/pci: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Robert Richter
2022-11-11 11:59 ` Robert Richter
2022-11-16 20:55 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 9/9] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support Robert Richter
2022-11-09 12:22 ` Rafael J. Wysocki
2022-11-09 23:35 ` Bjorn Helgaas
2022-11-10 0:51 ` Verma, Vishal L
2022-11-10 17:10 ` Bjorn Helgaas
2022-11-10 19:43 ` Terry Bowman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221109104059.766720-2-rrichter@amd.com \
--to=rrichter@amd.com \
--cc=Jonathan.Cameron@huawei.com \
--cc=alison.schofield@intel.com \
--cc=bhelgaas@google.com \
--cc=bwidawsk@kernel.org \
--cc=dan.j.williams@intel.com \
--cc=dave.jiang@intel.com \
--cc=dave@stgolabs.net \
--cc=ira.weiny@intel.com \
--cc=lenb@kernel.org \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=rafael@kernel.org \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox