From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
Dave Jiang <dave.jiang@intel.com>,
Robert Richter <rrichter@amd.com>
Subject: [PATCH v3 5/9] cxl/pci: Only register RCDs with device 0, function 0 as CXL memory device
Date: Wed, 9 Nov 2022 11:40:55 +0100 [thread overview]
Message-ID: <20221109104059.766720-6-rrichter@amd.com> (raw)
In-Reply-To: <20221109104059.766720-1-rrichter@amd.com>
The Device 0, Function 0 DVSEC controls the CXL functionality of the
entire device. Add a check to prevent registration of any other PCI
device on the bus as a CXL memory device.
Signed-off-by: Robert Richter <rrichter@amd.com>
---
drivers/cxl/pci.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index faeb5d9d7a7a..cc4f206f24b3 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -428,11 +428,26 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds)
}
}
+static int check_restricted_device(struct pci_dev *pdev, u16 pcie_dvsec)
+{
+ if (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_END)
+ return 0; /* no RCD */
+
+ if (pdev->devfn == PCI_DEVFN(0, 0) && pcie_dvsec)
+ return 0; /* ok */
+
+ dev_warn(&pdev->dev, "Skipping RCD: devfn=0x%02x dvsec=%u\n",
+ pdev->devfn, pcie_dvsec);
+
+ return -ENODEV;
+}
+
static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct cxl_register_map map;
struct cxl_memdev *cxlmd;
struct cxl_dev_state *cxlds;
+ u16 pcie_dvsec;
int rc;
/*
@@ -442,6 +457,13 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) !=
offsetof(struct cxl_regs, device_regs.memdev));
+ pcie_dvsec = pci_find_dvsec_capability(
+ pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
+
+ rc = check_restricted_device(pdev, pcie_dvsec);
+ if (rc)
+ return rc;
+
rc = pcim_enable_device(pdev);
if (rc)
return rc;
@@ -451,8 +473,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
return PTR_ERR(cxlds);
cxlds->serial = pci_get_dsn(pdev);
- cxlds->cxl_dvsec = pci_find_dvsec_capability(
- pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
+ cxlds->cxl_dvsec = pcie_dvsec;
if (!cxlds->cxl_dvsec)
dev_warn(&pdev->dev,
"Device DVSEC not present, skip CXL.mem init\n");
--
2.30.2
next prev parent reply other threads:[~2022-11-09 10:41 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-09 10:40 [PATCH v3 0/9] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-11-09 10:40 ` [PATCH v3 1/9] cxl/acpi: Register CXL host ports by bridge device Robert Richter
2022-11-09 23:11 ` Bjorn Helgaas
2022-11-14 20:22 ` Dan Williams
2022-11-15 10:37 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 2/9] cxl/acpi: Extract component registers of restricted hosts from RCRB Robert Richter
2022-11-14 21:30 ` Dan Williams
2022-11-15 12:17 ` Robert Richter
2022-11-15 17:54 ` Dan Williams
2022-11-17 12:43 ` Robert Richter
2022-11-17 17:20 ` Dan Williams
2022-11-17 18:25 ` Robert Richter
2022-11-17 19:23 ` Dan Williams
2022-11-18 8:12 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 3/9] cxl/mem: Adjust cxl_mem_find_port() to find an RCH's port Robert Richter
2022-11-14 23:45 ` Dan Williams
2022-11-15 13:12 ` Robert Richter
2022-11-15 18:06 ` Dan Williams
2022-11-17 18:13 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 4/9] cxl/mem: Skip intermediate port enumeration of restricted endpoints (RCDs) Robert Richter
2022-11-09 16:55 ` Dave Jiang
2022-11-15 0:07 ` Dan Williams
2022-11-15 13:17 ` Robert Richter
2022-11-15 18:08 ` Dan Williams
2022-11-17 18:46 ` Robert Richter
2022-11-15 0:24 ` Dan Williams
2022-11-15 13:28 ` Robert Richter
2022-11-15 18:09 ` Dan Williams
2022-11-09 10:40 ` Robert Richter [this message]
2022-11-16 19:24 ` [PATCH v3 5/9] cxl/pci: Only register RCDs with device 0, function 0 as CXL memory device Dan Williams
2022-11-17 15:56 ` Robert Richter
2022-11-17 17:27 ` Dan Williams
2022-11-18 8:27 ` Robert Richter
2022-11-18 16:55 ` Dan Williams
2022-11-18 19:53 ` Robert Richter
2022-11-18 20:30 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 6/9] cxl/pci: Do not ignore PCI config read errors in match_add_dports() Robert Richter
2022-11-09 23:09 ` Bjorn Helgaas
2022-11-11 11:56 ` Robert Richter
2022-11-11 12:07 ` Robert Richter
2022-11-16 19:36 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 7/9] cxl/pci: Factor out code in match_add_dports() to pci_dev_add_dport() Robert Richter
2022-11-16 19:37 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 8/9] cxl/pci: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Robert Richter
2022-11-11 11:59 ` Robert Richter
2022-11-16 20:55 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 9/9] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support Robert Richter
2022-11-09 12:22 ` Rafael J. Wysocki
2022-11-09 23:35 ` Bjorn Helgaas
2022-11-10 0:51 ` Verma, Vishal L
2022-11-10 17:10 ` Bjorn Helgaas
2022-11-10 19:43 ` Terry Bowman
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