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From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>,
	Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	"Davidlohr Bueso" <dave@stgolabs.net>,
	Dave Jiang <dave.jiang@intel.com>,
	Robert Richter <rrichter@amd.com>
Subject: [PATCH v3 6/9] cxl/pci: Do not ignore PCI config read errors in match_add_dports()
Date: Wed, 9 Nov 2022 11:40:56 +0100	[thread overview]
Message-ID: <20221109104059.766720-7-rrichter@amd.com> (raw)
In-Reply-To: <20221109104059.766720-1-rrichter@amd.com>

The link capabilities of a PCI device are read when enumerating its
dports. This is done by reading the PCI config space. If that fails
port enumeration ignores that error. However, reading the PCI config
space should reliably work.

To reduce some complexity to the code flow when factoring out parts of
the code in match_add_dports() for later reuse, change this to throw
an error.

Signed-off-by: Robert Richter <rrichter@amd.com>
---
 drivers/cxl/core/pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 0dbbe8d39b07..8271b8abde7a 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -47,7 +47,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
 		return 0;
 	if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
 				  &lnkcap))
-		return 0;
+		return -ENXIO;
 
 	rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
 	if (rc)
-- 
2.30.2


  parent reply	other threads:[~2022-11-09 10:41 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-09 10:40 [PATCH v3 0/9] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-11-09 10:40 ` [PATCH v3 1/9] cxl/acpi: Register CXL host ports by bridge device Robert Richter
2022-11-09 23:11   ` Bjorn Helgaas
2022-11-14 20:22   ` Dan Williams
2022-11-15 10:37     ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 2/9] cxl/acpi: Extract component registers of restricted hosts from RCRB Robert Richter
2022-11-14 21:30   ` Dan Williams
2022-11-15 12:17     ` Robert Richter
2022-11-15 17:54       ` Dan Williams
2022-11-17 12:43         ` Robert Richter
2022-11-17 17:20           ` Dan Williams
2022-11-17 18:25             ` Robert Richter
2022-11-17 19:23               ` Dan Williams
2022-11-18  8:12                 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 3/9] cxl/mem: Adjust cxl_mem_find_port() to find an RCH's port Robert Richter
2022-11-14 23:45   ` Dan Williams
2022-11-15 13:12     ` Robert Richter
2022-11-15 18:06       ` Dan Williams
2022-11-17 18:13         ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 4/9] cxl/mem: Skip intermediate port enumeration of restricted endpoints (RCDs) Robert Richter
2022-11-09 16:55   ` Dave Jiang
2022-11-15  0:07   ` Dan Williams
2022-11-15 13:17     ` Robert Richter
2022-11-15 18:08       ` Dan Williams
2022-11-17 18:46         ` Robert Richter
2022-11-15  0:24   ` Dan Williams
2022-11-15 13:28     ` Robert Richter
2022-11-15 18:09       ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 5/9] cxl/pci: Only register RCDs with device 0, function 0 as CXL memory device Robert Richter
2022-11-16 19:24   ` Dan Williams
2022-11-17 15:56     ` Robert Richter
2022-11-17 17:27       ` Dan Williams
2022-11-18  8:27         ` Robert Richter
2022-11-18 16:55           ` Dan Williams
2022-11-18 19:53             ` Robert Richter
2022-11-18 20:30               ` Dan Williams
2022-11-09 10:40 ` Robert Richter [this message]
2022-11-09 23:09   ` [PATCH v3 6/9] cxl/pci: Do not ignore PCI config read errors in match_add_dports() Bjorn Helgaas
2022-11-11 11:56     ` Robert Richter
2022-11-11 12:07       ` Robert Richter
2022-11-16 19:36   ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 7/9] cxl/pci: Factor out code in match_add_dports() to pci_dev_add_dport() Robert Richter
2022-11-16 19:37   ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 8/9] cxl/pci: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Robert Richter
2022-11-11 11:59   ` Robert Richter
2022-11-16 20:55   ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 9/9] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support Robert Richter
2022-11-09 12:22   ` Rafael J. Wysocki
2022-11-09 23:35   ` Bjorn Helgaas
2022-11-10  0:51     ` Verma, Vishal L
2022-11-10 17:10       ` Bjorn Helgaas
2022-11-10 19:43     ` Terry Bowman

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