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From: Robert Richter <rrichter@amd.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>, <linux-cxl@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>,
	"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Dave Jiang <dave.jiang@intel.com>,
	Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v3 2/9] cxl/acpi: Extract component registers of restricted hosts from RCRB
Date: Thu, 17 Nov 2022 13:43:52 +0100	[thread overview]
Message-ID: <Y3YoBpIsgRRbRyLk@rric.localdomain> (raw)
In-Reply-To: <6373d24866bc9_12cdff294e3@dwillia2-xfh.jf.intel.com.notmuch>

On 15.11.22 09:54:16, Dan Williams wrote:
> Robert Richter wrote:
> > On 14.11.22 13:30:01, Dan Williams wrote:
> > > Robert Richter wrote:
> > 
> > > > diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> > > > index ec178e69b18f..7a5bde81e949 100644
> > > > --- a/drivers/cxl/core/regs.c
> > > > +++ b/drivers/cxl/core/regs.c
> > > > @@ -307,3 +307,49 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> > > >  	return -ENODEV;
> > > >  }
> > > >  EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
> > > > +
> > > > +resource_size_t cxl_rcrb_to_component(struct device *dev,
> > > > +				      resource_size_t rcrb,
> > > > +				      enum cxl_rcrb which)
> > > > +{
> > > > +	resource_size_t component_reg_phys;
> > > > +	u32 bar0, bar1;
> > > > +	void *addr;
> > > > +
> > > > +	if (which == CXL_RCRB_UPSTREAM)
> > > > +		rcrb += SZ_4K;
> > > > +
> > > > +	/*
> > > > +	 * RCRB's BAR[0..1] point to component block containing CXL
> > > > +	 * subsystem component registers. MEMBAR extraction follows
> > > > +	 * the PCI Base spec here, esp. 64 bit extraction and memory
> > > > +	 * ranges alignment (6.0, 7.5.1.2.1).
> > > > +	 */
> > > 
> > > A request_mem_region() is needed here to ensure ownership and expected
> > > sequencing of accessing the RCRB to locate the component registers, and
> > > accessing the RCRB to manipulate the component registers. It also helps
> > > to sanity check that the BIOS mapped an exclusive range for the RCRB.
> > 
> > Right, that is missing.
> > 
> > > 
> > > > +	addr = ioremap(rcrb, PCI_BASE_ADDRESS_0 + SZ_8);
> > > 
> > > That PCI_BASE_ADDRESS_0 does not belong there. It ends up being benign
> > > and forcing ioremap to map 12K instead of 8K, but it is a
> > > config-register offset, not part of the RCRB size.
> > 
> > Note this is BAR0 + 8 bytes, not 8k, and it does not map the whole
> > RCRB region but instead the first part of the config space up to
> > including the 64 bit BAR.
> 
> Oh, sorry, yes, my mistake. However, there is not much value in mapping
> less than 4K since all ioremap requests are rounded up to PAGE_SIZE.
> Since an RCRB is only 4K per port lets just map the whole thing.

I was going to keep the ranges small to avoid conflicts with other
requests for the same page (though request_mem_region() was missing
yet).

> 
> > > > +	if (!addr) {
> > > > +		dev_err(dev, "Failed to map region %pr\n", addr);
> > > > +		return CXL_RESOURCE_NONE;
> > > > +	}
> > > > +
> > > > +	bar0 = readl(addr + PCI_BASE_ADDRESS_0);
> > > > +	bar1 = readl(addr + PCI_BASE_ADDRESS_1);
> > > > +	iounmap(addr);
> > > 
> > > ...corresponding release_mem_region() would go here.
> > > 
> > > > +
> > > > +	/* sanity check */
> > > > +	if (bar0 & (PCI_BASE_ADDRESS_MEM_TYPE_1M | PCI_BASE_ADDRESS_SPACE_IO))
> > > > +		return CXL_RESOURCE_NONE;
> > > 
> > > I would have also expected:
> > > 
> > > - a sanity check for "Memory Space Enable" being set in the command
> > >   register.
> > 
> > Ok.
> > 
> > > 
> > > - an explicit check for 0xffffffff for the case when the upstream-port
> > >   implements "no RCRB" mode.
> > 
> > Yes, I left support for this to a later patch, but it's better to
> > check it here already and possibly fall back to reg loc DVSEC then.
> 
> Yeah, I think simply failing on 0xffffffff is sufficient for now.
> 
> > > 
> > > - some check that BIOS initialized the BAR values post reset given these
> > >   BARs are invisible to the PCI core resource assignment 
> > 
> > What check do you have in mind here? There is already the NULL check
> > which would be the out-of-reset value.
> 
> I was thinking more along the lines of sanity checking that the
> programmed RCRB range falls within the assigned MMIO space of the
> host-bridge, but perhaps that is overkill since it would just be
> validating self consistency between 2 BIOS provided values. Robustness
> principle would say try to continue if those disagree.

Ok, will drop a check here.

Thanks,

-Robert

  reply	other threads:[~2022-11-17 12:47 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-09 10:40 [PATCH v3 0/9] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-11-09 10:40 ` [PATCH v3 1/9] cxl/acpi: Register CXL host ports by bridge device Robert Richter
2022-11-09 23:11   ` Bjorn Helgaas
2022-11-14 20:22   ` Dan Williams
2022-11-15 10:37     ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 2/9] cxl/acpi: Extract component registers of restricted hosts from RCRB Robert Richter
2022-11-14 21:30   ` Dan Williams
2022-11-15 12:17     ` Robert Richter
2022-11-15 17:54       ` Dan Williams
2022-11-17 12:43         ` Robert Richter [this message]
2022-11-17 17:20           ` Dan Williams
2022-11-17 18:25             ` Robert Richter
2022-11-17 19:23               ` Dan Williams
2022-11-18  8:12                 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 3/9] cxl/mem: Adjust cxl_mem_find_port() to find an RCH's port Robert Richter
2022-11-14 23:45   ` Dan Williams
2022-11-15 13:12     ` Robert Richter
2022-11-15 18:06       ` Dan Williams
2022-11-17 18:13         ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 4/9] cxl/mem: Skip intermediate port enumeration of restricted endpoints (RCDs) Robert Richter
2022-11-09 16:55   ` Dave Jiang
2022-11-15  0:07   ` Dan Williams
2022-11-15 13:17     ` Robert Richter
2022-11-15 18:08       ` Dan Williams
2022-11-17 18:46         ` Robert Richter
2022-11-15  0:24   ` Dan Williams
2022-11-15 13:28     ` Robert Richter
2022-11-15 18:09       ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 5/9] cxl/pci: Only register RCDs with device 0, function 0 as CXL memory device Robert Richter
2022-11-16 19:24   ` Dan Williams
2022-11-17 15:56     ` Robert Richter
2022-11-17 17:27       ` Dan Williams
2022-11-18  8:27         ` Robert Richter
2022-11-18 16:55           ` Dan Williams
2022-11-18 19:53             ` Robert Richter
2022-11-18 20:30               ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 6/9] cxl/pci: Do not ignore PCI config read errors in match_add_dports() Robert Richter
2022-11-09 23:09   ` Bjorn Helgaas
2022-11-11 11:56     ` Robert Richter
2022-11-11 12:07       ` Robert Richter
2022-11-16 19:36   ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 7/9] cxl/pci: Factor out code in match_add_dports() to pci_dev_add_dport() Robert Richter
2022-11-16 19:37   ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 8/9] cxl/pci: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Robert Richter
2022-11-11 11:59   ` Robert Richter
2022-11-16 20:55   ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 9/9] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support Robert Richter
2022-11-09 12:22   ` Rafael J. Wysocki
2022-11-09 23:35   ` Bjorn Helgaas
2022-11-10  0:51     ` Verma, Vishal L
2022-11-10 17:10       ` Bjorn Helgaas
2022-11-10 19:43     ` Terry Bowman

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