Linux CXL
 help / color / mirror / Atom feed
From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>,
	Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	"Davidlohr Bueso" <dave@stgolabs.net>,
	Dave Jiang <dave.jiang@intel.com>,
	Robert Richter <rrichter@amd.com>
Subject: [PATCH v3 7/9] cxl/pci: Factor out code in match_add_dports() to pci_dev_add_dport()
Date: Wed, 9 Nov 2022 11:40:57 +0100	[thread overview]
Message-ID: <20221109104059.766720-8-rrichter@amd.com> (raw)
In-Reply-To: <20221109104059.766720-1-rrichter@amd.com>

Factor out the code to register a PCI device's dport to a port. It
will be reused to implement RCD mode.

Signed-off-by: Robert Richter <rrichter@amd.com>
---
 drivers/cxl/core/pci.c | 37 ++++++++++++++++++++++++++-----------
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 8271b8abde7a..667de4f125f6 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -29,14 +29,32 @@ struct cxl_walk_context {
 	int count;
 };
 
+static int pci_dev_add_dport(struct pci_dev *pdev, struct cxl_port *port,
+			      resource_size_t component_reg_phys)
+{
+	struct cxl_dport *dport;
+	u32 lnkcap, port_num;
+
+	if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
+				  &lnkcap))
+		return -ENXIO;
+
+	port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
+	dport = devm_cxl_add_dport(port, &pdev->dev, port_num,
+				   component_reg_phys);
+	if (IS_ERR(dport))
+		return PTR_ERR(dport);
+
+	return 0;
+}
+
 static int match_add_dports(struct pci_dev *pdev, void *data)
 {
 	struct cxl_walk_context *ctx = data;
 	struct cxl_port *port = ctx->port;
 	int type = pci_pcie_type(pdev);
 	struct cxl_register_map map;
-	struct cxl_dport *dport;
-	u32 lnkcap, port_num;
+	resource_size_t component_reg_phys;
 	int rc;
 
 	if (pdev->bus != ctx->bus)
@@ -45,21 +63,18 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
 		return 0;
 	if (type != ctx->type)
 		return 0;
-	if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
-				  &lnkcap))
-		return -ENXIO;
 
 	rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
 	if (rc)
 		dev_dbg(&port->dev, "failed to find component registers\n");
 
-	port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
-	dport = devm_cxl_add_dport(port, &pdev->dev, port_num,
-				   cxl_regmap_to_base(pdev, &map));
-	if (IS_ERR(dport)) {
-		ctx->error = PTR_ERR(dport);
-		return PTR_ERR(dport);
+	component_reg_phys = cxl_regmap_to_base(pdev, &map);
+	rc = pci_dev_add_dport(pdev, port, component_reg_phys);
+	if (rc) {
+		ctx->error = rc;
+		return rc;
 	}
+
 	ctx->count++;
 
 	return 0;
-- 
2.30.2


  parent reply	other threads:[~2022-11-09 10:42 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-09 10:40 [PATCH v3 0/9] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-11-09 10:40 ` [PATCH v3 1/9] cxl/acpi: Register CXL host ports by bridge device Robert Richter
2022-11-09 23:11   ` Bjorn Helgaas
2022-11-14 20:22   ` Dan Williams
2022-11-15 10:37     ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 2/9] cxl/acpi: Extract component registers of restricted hosts from RCRB Robert Richter
2022-11-14 21:30   ` Dan Williams
2022-11-15 12:17     ` Robert Richter
2022-11-15 17:54       ` Dan Williams
2022-11-17 12:43         ` Robert Richter
2022-11-17 17:20           ` Dan Williams
2022-11-17 18:25             ` Robert Richter
2022-11-17 19:23               ` Dan Williams
2022-11-18  8:12                 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 3/9] cxl/mem: Adjust cxl_mem_find_port() to find an RCH's port Robert Richter
2022-11-14 23:45   ` Dan Williams
2022-11-15 13:12     ` Robert Richter
2022-11-15 18:06       ` Dan Williams
2022-11-17 18:13         ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 4/9] cxl/mem: Skip intermediate port enumeration of restricted endpoints (RCDs) Robert Richter
2022-11-09 16:55   ` Dave Jiang
2022-11-15  0:07   ` Dan Williams
2022-11-15 13:17     ` Robert Richter
2022-11-15 18:08       ` Dan Williams
2022-11-17 18:46         ` Robert Richter
2022-11-15  0:24   ` Dan Williams
2022-11-15 13:28     ` Robert Richter
2022-11-15 18:09       ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 5/9] cxl/pci: Only register RCDs with device 0, function 0 as CXL memory device Robert Richter
2022-11-16 19:24   ` Dan Williams
2022-11-17 15:56     ` Robert Richter
2022-11-17 17:27       ` Dan Williams
2022-11-18  8:27         ` Robert Richter
2022-11-18 16:55           ` Dan Williams
2022-11-18 19:53             ` Robert Richter
2022-11-18 20:30               ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 6/9] cxl/pci: Do not ignore PCI config read errors in match_add_dports() Robert Richter
2022-11-09 23:09   ` Bjorn Helgaas
2022-11-11 11:56     ` Robert Richter
2022-11-11 12:07       ` Robert Richter
2022-11-16 19:36   ` Dan Williams
2022-11-09 10:40 ` Robert Richter [this message]
2022-11-16 19:37   ` [PATCH v3 7/9] cxl/pci: Factor out code in match_add_dports() to pci_dev_add_dport() Dan Williams
2022-11-09 10:40 ` [PATCH v3 8/9] cxl/pci: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Robert Richter
2022-11-11 11:59   ` Robert Richter
2022-11-16 20:55   ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 9/9] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support Robert Richter
2022-11-09 12:22   ` Rafael J. Wysocki
2022-11-09 23:35   ` Bjorn Helgaas
2022-11-10  0:51     ` Verma, Vishal L
2022-11-10 17:10       ` Bjorn Helgaas
2022-11-10 19:43     ` Terry Bowman

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221109104059.766720-8-rrichter@amd.com \
    --to=rrichter@amd.com \
    --cc=Jonathan.Cameron@huawei.com \
    --cc=alison.schofield@intel.com \
    --cc=bhelgaas@google.com \
    --cc=bwidawsk@kernel.org \
    --cc=dan.j.williams@intel.com \
    --cc=dave.jiang@intel.com \
    --cc=dave@stgolabs.net \
    --cc=ira.weiny@intel.com \
    --cc=lenb@kernel.org \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=rafael@kernel.org \
    --cc=vishal.l.verma@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox