From: Dave Jiang <dave.jiang@intel.com>
To: Robert Richter <rrichter@amd.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Davidlohr Bueso <dave@stgolabs.net>
Subject: Re: [PATCH v3 4/9] cxl/mem: Skip intermediate port enumeration of restricted endpoints (RCDs)
Date: Wed, 9 Nov 2022 09:55:20 -0700 [thread overview]
Message-ID: <edb40147-5455-525d-1758-990c3aac3859@intel.com> (raw)
In-Reply-To: <20221109104059.766720-5-rrichter@amd.com>
On 11/9/2022 2:40 AM, Robert Richter wrote:
> When an endpoint is found, all ports in beetween the endpoint and the
s/beetween/between/
DJ
> CXL host bridge need to be created. In the RCH case there are no ports
> in between a host bridge and the endpoint. Skip the enumeration of
> intermediate ports.
>
> The port enumeration does not only create all ports, it also
> initializes the endpoint chain by adding the endpoint to every
> downstream port up to the root bridge. This must be done also in RCD
> mode, but is much more simple as the endpoint only needs to be added
> to the host bridge's dport.
>
> Note: For endpoint removal the cxl_detach_ep() is not needed as it is
> released in cxl_port_release().
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> ---
> drivers/cxl/core/port.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index d10c3580719b..e21a9c3fe4da 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1366,8 +1366,24 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
> {
> struct device *dev = &cxlmd->dev;
> struct device *iter;
> + struct cxl_dport *dport;
> + struct cxl_port *port;
> int rc;
>
> + /*
> + * Skip intermediate port enumeration in the RCH case, there
> + * are no ports in between a host bridge and an endpoint. Only
> + * initialize the EP chain.
> + */
> + if (is_cxl_restricted(cxlmd)) {
> + port = cxl_mem_find_port(cxlmd, &dport);
> + if (!port)
> + return -ENXIO;
> + rc = cxl_add_ep(dport, &cxlmd->dev);
> + put_device(&port->dev);
> + return rc;
> + }
> +
> rc = devm_add_action_or_reset(&cxlmd->dev, cxl_detach_ep, cxlmd);
> if (rc)
> return rc;
> @@ -1381,8 +1397,6 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
> for (iter = dev; iter; iter = grandparent(iter)) {
> struct device *dport_dev = grandparent(iter);
> struct device *uport_dev;
> - struct cxl_dport *dport;
> - struct cxl_port *port;
>
> if (!dport_dev)
> return 0;
next prev parent reply other threads:[~2022-11-09 16:58 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-09 10:40 [PATCH v3 0/9] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-11-09 10:40 ` [PATCH v3 1/9] cxl/acpi: Register CXL host ports by bridge device Robert Richter
2022-11-09 23:11 ` Bjorn Helgaas
2022-11-14 20:22 ` Dan Williams
2022-11-15 10:37 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 2/9] cxl/acpi: Extract component registers of restricted hosts from RCRB Robert Richter
2022-11-14 21:30 ` Dan Williams
2022-11-15 12:17 ` Robert Richter
2022-11-15 17:54 ` Dan Williams
2022-11-17 12:43 ` Robert Richter
2022-11-17 17:20 ` Dan Williams
2022-11-17 18:25 ` Robert Richter
2022-11-17 19:23 ` Dan Williams
2022-11-18 8:12 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 3/9] cxl/mem: Adjust cxl_mem_find_port() to find an RCH's port Robert Richter
2022-11-14 23:45 ` Dan Williams
2022-11-15 13:12 ` Robert Richter
2022-11-15 18:06 ` Dan Williams
2022-11-17 18:13 ` Robert Richter
2022-11-09 10:40 ` [PATCH v3 4/9] cxl/mem: Skip intermediate port enumeration of restricted endpoints (RCDs) Robert Richter
2022-11-09 16:55 ` Dave Jiang [this message]
2022-11-15 0:07 ` Dan Williams
2022-11-15 13:17 ` Robert Richter
2022-11-15 18:08 ` Dan Williams
2022-11-17 18:46 ` Robert Richter
2022-11-15 0:24 ` Dan Williams
2022-11-15 13:28 ` Robert Richter
2022-11-15 18:09 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 5/9] cxl/pci: Only register RCDs with device 0, function 0 as CXL memory device Robert Richter
2022-11-16 19:24 ` Dan Williams
2022-11-17 15:56 ` Robert Richter
2022-11-17 17:27 ` Dan Williams
2022-11-18 8:27 ` Robert Richter
2022-11-18 16:55 ` Dan Williams
2022-11-18 19:53 ` Robert Richter
2022-11-18 20:30 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 6/9] cxl/pci: Do not ignore PCI config read errors in match_add_dports() Robert Richter
2022-11-09 23:09 ` Bjorn Helgaas
2022-11-11 11:56 ` Robert Richter
2022-11-11 12:07 ` Robert Richter
2022-11-16 19:36 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 7/9] cxl/pci: Factor out code in match_add_dports() to pci_dev_add_dport() Robert Richter
2022-11-16 19:37 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 8/9] cxl/pci: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Robert Richter
2022-11-11 11:59 ` Robert Richter
2022-11-16 20:55 ` Dan Williams
2022-11-09 10:40 ` [PATCH v3 9/9] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support Robert Richter
2022-11-09 12:22 ` Rafael J. Wysocki
2022-11-09 23:35 ` Bjorn Helgaas
2022-11-10 0:51 ` Verma, Vishal L
2022-11-10 17:10 ` Bjorn Helgaas
2022-11-10 19:43 ` Terry Bowman
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