[PATCH v3 00/47] clk: qcom: Tie CX power domains to GCCs

[PATCH v3 00/47] clk: qcom: Tie CX power domains to GCCs

[Abel Vesa]

Tie the CX power domain to GCC clock controllers for SDM670, SDM845,
SM8150, SM8250, SM8350, SM8450, SM8550, SM8650, SM8750, SM6350,
SM4450, QDU1000, QCS8300, SDX75, SAR2130P, SC7180, SC7280, SA8775P,
X1E80100, Eliza, Kaanapali, and QCS615.

Also enable the runtime PM in each of the GCC provider drivers.

Update the GCC bindings to document and require the CX power-domain
dependency for the affected compatibles.

Only Kaanapali and Eliza require Fixes tags, as runtime PM support was not
available when the other platforms were upstreamed.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
- Rebased on next-20260821.
- Pick up Dmitry's and Konrad's R-b tags.
- Add binding updates that document and require the CX power domain.
- Add SDM670, SDM845, SM8150, SM6350, SM4450, QDU1000, QCS8300,
  SDX75, SAR2130P, SC7180, SC7280, SA8775P, X1E80100, and Eliza to the
  list.
- Link to v2: https://patch.msgid.link/20260820-qcom-tie-cx-to-gcc-v2-0-e67ea30d8b7b@oss.qualcomm.com

Changes in v2:
- Clarify the runtime PM rationale in the GCC driver commit messages.
- Picked up Konrad's R-b tag for the dts patches.
- Link to v1: https://patch.msgid.link/20260819-qcom-tie-cx-to-gcc-v1-0-840034124e73@oss.qualcomm.com

To: Bjorn Andersson <andersson@kernel.org>
To: Stephen Boyd <sboyd@kernel.org>
To: Brian Masney <bmasney+clk@redhat.com>
To: Jerome Brunet <jbrunet+clk@baylibre.com>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Taniya Das <taniya.das@oss.qualcomm.com>
To: Vinod Koul <vkoul@kernel.org>
To: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
To: Abel Vesa <abel.vesa@oss.qualcomm.com>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Krzysztof Kozlowski <krzk@kernel.org>

---
Abel Vesa (47):
      dt-bindings: clock: qcom: gcc-sdm845: Add CX power domain
      dt-bindings: clock: qcom: gcc-sm8150: Add CX power domain
      dt-bindings: clock: qcom: gcc-sm8250: Add CX power domain
      dt-bindings: clock: qcom: gcc-sm8350: Add CX power domain
      dt-bindings: clock: qcom: gcc-sm8450: Add CX power domain
      dt-bindings: clock: qcom: qcs615-gcc: Add CX power domain
      dt-bindings: clock: qcom: sm8550-gcc: Add CX power domain
      dt-bindings: clock: qcom: sm8650-gcc: Add CX power domain
      dt-bindings: clock: qcom: sm8750-gcc: Add CX power domain
      clk: qcom: gcc-eliza: Tie the CX power domain to controller
      clk: qcom: gcc-kaanapali: Tie the CX power domain to controller
      clk: qcom: gcc-qcs615: Tie the CX power domain to controller
      clk: qcom: gcc-qcs8300: Tie the CX power domain to controller
      clk: qcom: gcc-qdu1000: Tie the CX power domain to controller
      clk: qcom: gcc-sa8775p: Tie the CX power domain to controller
      clk: qcom: gcc-sar2130p: Tie the CX power domain to controller
      clk: qcom: gcc-sc7180: Tie the CX power domain to controller
      clk: qcom: gcc-sc7280: Tie the CX power domain to controller
      clk: qcom: gcc-sdm670: Tie the CX power domain to controller
      clk: qcom: gcc-sdm845: Tie the CX power domain to controller
      clk: qcom: gcc-sdx75: Tie the CX power domain to controller
      clk: qcom: gcc-sm4450: Tie the CX power domain to controller
      clk: qcom: gcc-sm6350: Tie the CX power domain to controller
      clk: qcom: gcc-sm8150: Tie the CX power domain to controller
      clk: qcom: gcc-sm8250: Tie the CX power domain to controller
      clk: qcom: gcc-sm8350: Tie the CX power domain to controller
      clk: qcom: gcc-sm8450: Tie the CX power domain to controller
      clk: qcom: gcc-sm8550: Tie the CX power domain to controller
      clk: qcom: gcc-sm8650: Tie the CX power domain to controller
      clk: qcom: gcc-sm8750: Tie the CX power domain to controller
      clk: qcom: gcc-x1e80100: Tie the CX power domain to controller
      arm64: dts: qcom: kaanapali: Add GCC CX power domain
      arm64: dts: qcom: monaco: Add GCC CX power domain
      arm64: dts: qcom: qdu1000: Add GCC CX power domain
      arm64: dts: qcom: sar2130p: Add GCC CX power domain
      arm64: dts: qcom: sdm670: Add GCC CX power domain
      arm64: dts: qcom: sdx75: Add GCC CX power domain
      arm64: dts: qcom: sm4450: Add GCC CX power domain
      arm64: dts: qcom: sm6350: Add GCC CX power domain
      arm64: dts: qcom: sm8150: Add GCC CX power domain
      arm64: dts: qcom: sm8250: Add GCC CX power domain
      arm64: dts: qcom: sm8350: Add GCC CX power domain
      arm64: dts: qcom: sm8450: Add GCC CX power domain
      arm64: dts: qcom: sm8550: Add GCC CX power domain
      arm64: dts: qcom: sm8650: Add GCC CX power domain
      arm64: dts: qcom: sm8750: Add GCC CX power domain
      arm64: dts: qcom: talos: Add GCC CX power domain

 Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml | 8 ++++++++
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml | 8 ++++++++
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml | 8 ++++++++
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml | 8 ++++++++
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml | 8 ++++++++
 Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml | 8 ++++++++
 Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml | 8 ++++++++
 Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml | 8 ++++++++
 Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml | 8 ++++++++
 arch/arm64/boot/dts/qcom/kaanapali.dtsi                      | 2 ++
 arch/arm64/boot/dts/qcom/monaco.dtsi                         | 1 +
 arch/arm64/boot/dts/qcom/qdu1000.dtsi                        | 1 +
 arch/arm64/boot/dts/qcom/sar2130p.dtsi                       | 1 +
 arch/arm64/boot/dts/qcom/sdm670.dtsi                         | 1 +
 arch/arm64/boot/dts/qcom/sdx75.dtsi                          | 1 +
 arch/arm64/boot/dts/qcom/sm4450.dtsi                         | 1 +
 arch/arm64/boot/dts/qcom/sm6350.dtsi                         | 1 +
 arch/arm64/boot/dts/qcom/sm8150.dtsi                         | 1 +
 arch/arm64/boot/dts/qcom/sm8250.dtsi                         | 1 +
 arch/arm64/boot/dts/qcom/sm8350.dtsi                         | 1 +
 arch/arm64/boot/dts/qcom/sm8450.dtsi                         | 1 +
 arch/arm64/boot/dts/qcom/sm8550.dtsi                         | 1 +
 arch/arm64/boot/dts/qcom/sm8650.dtsi                         | 2 ++
 arch/arm64/boot/dts/qcom/sm8750.dtsi                         | 2 ++
 arch/arm64/boot/dts/qcom/talos.dtsi                          | 2 ++
 drivers/clk/qcom/gcc-eliza.c                                 | 1 +
 drivers/clk/qcom/gcc-kaanapali.c                             | 1 +
 drivers/clk/qcom/gcc-qcs615.c                                | 1 +
 drivers/clk/qcom/gcc-qcs8300.c                               | 1 +
 drivers/clk/qcom/gcc-qdu1000.c                               | 1 +
 drivers/clk/qcom/gcc-sa8775p.c                               | 1 +
 drivers/clk/qcom/gcc-sar2130p.c                              | 1 +
 drivers/clk/qcom/gcc-sc7180.c                                | 1 +
 drivers/clk/qcom/gcc-sc7280.c                                | 1 +
 drivers/clk/qcom/gcc-sdm845.c                                | 2 ++
 drivers/clk/qcom/gcc-sdx75.c                                 | 1 +
 drivers/clk/qcom/gcc-sm4450.c                                | 1 +
 drivers/clk/qcom/gcc-sm6350.c                                | 1 +
 drivers/clk/qcom/gcc-sm8150.c                                | 1 +
 drivers/clk/qcom/gcc-sm8250.c                                | 1 +
 drivers/clk/qcom/gcc-sm8350.c                                | 1 +
 drivers/clk/qcom/gcc-sm8450.c                                | 1 +
 drivers/clk/qcom/gcc-sm8550.c                                | 1 +
 drivers/clk/qcom/gcc-sm8650.c                                | 1 +
 drivers/clk/qcom/gcc-sm8750.c                                | 1 +
 drivers/clk/qcom/gcc-x1e80100.c                              | 1 +
 46 files changed, 114 insertions(+)
---
base-commit: 903c1cf6dff9964e71eda98a39e2e5d442050472
change-id: 20260819-qcom-tie-cx-to-gcc-67e6697639b5

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

[PATCH v3 01/47] dt-bindings: clock: qcom: gcc-sdm845: Add CX power domain

[Abel Vesa]

Describe the CX power-domain dependency for SDM845 and SDM670 GCCs, and
require it for both compatibles.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
index a7523a414341..980edcd244a2 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
@@ -31,6 +31,8 @@ properties:
     maxItems: 5
 
   power-domains:
+    description:
+      A phandle and PM domain specifier for the CX power domain.
     maxItems: 1
 
 required:
@@ -56,6 +58,8 @@ allOf:
             - const: bi_tcxo
             - const: bi_tcxo_ao
             - const: sleep_clk
+      required:
+        - power-domains
 
   - if:
       properties:
@@ -78,6 +82,8 @@ allOf:
             - const: sleep_clk
             - const: pcie_0_pipe_clk
             - const: pcie_1_pipe_clk
+      required:
+        - power-domains
 
 unevaluatedProperties: false
 
@@ -85,6 +91,7 @@ examples:
   # Example for GCC for SDM845:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sdm845";
       reg = <0x100000 0x1f0000>;
@@ -94,6 +101,7 @@ examples:
                <&pcie0_lane>,
                <&pcie1_lane>;
       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
+      power-domains = <&rpmhpd SDM845_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

Re: [PATCH v3 01/47] dt-bindings: clock: qcom: gcc-sdm845: Add CX power domain

[Krzysztof Kozlowski]

On 24/08/2026 13:53, Abel Vesa wrote:
> Describe the CX power-domain dependency for SDM845 and SDM670 GCCs, and
> require it for both compatibles.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> index a7523a414341..980edcd244a2 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> @@ -31,6 +31,8 @@ properties:
>      maxItems: 5
>  
>    power-domains:
> +    description:
> +      A phandle and PM domain specifier for the CX power domain.

Describe items instead:
items:
  - description:

Also, "A phandle and PM domain specifier for the" is redundant part of
sentence. This cannot be anything else than phandle and PM domain, thus
just say "CX power domain".

>      maxItems: 1
>  
>  required:
> @@ -56,6 +58,8 @@ allOf:
>              - const: bi_tcxo
>              - const: bi_tcxo_ao
>              - const: sleep_clk
> +      required:
> +        - power-domains

Why? Commit msg should tell me why you are changing ABI. It is actual
ABI break without an explanation...

Best regards,
Krzysztof

Re: [PATCH v3 01/47] dt-bindings: clock: qcom: gcc-sdm845: Add CX power domain

[Abel Vesa]

On 26-08-24 22:39:28, Krzysztof Kozlowski wrote:
> On 24/08/2026 13:53, Abel Vesa wrote:
> > Describe the CX power-domain dependency for SDM845 and SDM670 GCCs, and
> > require it for both compatibles.
> > 
> > Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > ---
> >  Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> > index a7523a414341..980edcd244a2 100644
> > --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> > @@ -31,6 +31,8 @@ properties:
> >      maxItems: 5
> >  
> >    power-domains:
> > +    description:
> > +      A phandle and PM domain specifier for the CX power domain.
> 
> Describe items instead:
> items:
>   - description:
> 
> Also, "A phandle and PM domain specifier for the" is redundant part of
> sentence. This cannot be anything else than phandle and PM domain, thus
> just say "CX power domain".

Will fix.

> 
> >      maxItems: 1
> >  
> >  required:
> > @@ -56,6 +58,8 @@ allOf:
> >              - const: bi_tcxo
> >              - const: bi_tcxo_ao
> >              - const: sleep_clk
> > +      required:
> > +        - power-domains
> 
> Why? Commit msg should tell me why you are changing ABI. It is actual
> ABI break without an explanation...

Actually, I should've kept the same commit message as for the other
bindings.

Thanks for reviewing.

Abel

Re: [PATCH v3 01/47] dt-bindings: clock: qcom: gcc-sdm845: Add CX power domain

[Krzysztof Kozlowski]

On 25/08/2026 09:30, Abel Vesa wrote:
>>>  
>>>  required:
>>> @@ -56,6 +58,8 @@ allOf:
>>>              - const: bi_tcxo
>>>              - const: bi_tcxo_ao
>>>              - const: sleep_clk
>>> +      required:
>>> +        - power-domains
>>
>> Why? Commit msg should tell me why you are changing ABI. It is actual
>> ABI break without an explanation...
> 
> Actually, I should've kept the same commit message as for the other
> bindings.
> 
> Thanks for reviewing.

The others only mention "to match hardware description" but that is poor
reason for ABI break. If everything was working fine, thus domain is not
really required, why would "matching the hardware description" matter?

Best regards,
Krzysztof

Re: [PATCH v3 01/47] dt-bindings: clock: qcom: gcc-sdm845: Add CX power domain

[Abel Vesa]

On 26-08-25 09:34:47, Krzysztof Kozlowski wrote:
> On 25/08/2026 09:30, Abel Vesa wrote:
> >>>  
> >>>  required:
> >>> @@ -56,6 +58,8 @@ allOf:
> >>>              - const: bi_tcxo
> >>>              - const: bi_tcxo_ao
> >>>              - const: sleep_clk
> >>> +      required:
> >>> +        - power-domains
> >>
> >> Why? Commit msg should tell me why you are changing ABI. It is actual
> >> ABI break without an explanation...
> > 
> > Actually, I should've kept the same commit message as for the other
> > bindings.
> > 
> > Thanks for reviewing.
> 
> The others only mention "to match hardware description" but that is poor
> reason for ABI break. If everything was working fine, thus domain is not
> really required, why would "matching the hardware description" matter?

An off-list discussion a while ago has concluded that GCC without CX as
PD could undervolt in some scenarios, as RPMh not adjusting
properly, due to consumers not voting on CX as they should.

Will add an explanation along those lines.

Thanks.

[PATCH v3 02/47] dt-bindings: clock: qcom: gcc-sm8150: Add CX power domain

[Abel Vesa]

Describe the CX power-domain dependency for SM8150 GCC and require it in
the binding.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
index 5f3f69fe9ddb..dcdbcda2c212 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
@@ -30,10 +30,16 @@ properties:
       - const: bi_tcxo
       - const: sleep_clk
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier for the CX power domain.
+    maxItems: 1
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -44,12 +50,14 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sm8150";
       reg = <0x00100000 0x1f0000>;
       clocks = <&rpmhcc RPMH_CXO_CLK>,
                <&sleep_clk>;
       clock-names = "bi_tcxo", "sleep_clk";
+      power-domains = <&rpmhpd SM8150_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v3 03/47] dt-bindings: clock: qcom: gcc-sm8250: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8250 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required,
matching the hardware description needed by the GCC node.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
index f4cd5a509c60..7c0c3cc63281 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
@@ -32,10 +32,16 @@ properties:
       - const: bi_tcxo_ao
       - const: sleep_clk
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier for the CX power domain.
+    maxItems: 1
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -46,6 +52,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sm8250";
       reg = <0x00100000 0x1f0000>;
@@ -53,6 +60,7 @@ examples:
                <&rpmhcc RPMH_CXO_CLK_A>,
                <&sleep_clk>;
       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v3 04/47] dt-bindings: clock: qcom: gcc-sm8350: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8350 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required,
matching the hardware description needed by the GCC node.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
index 97ffae3b5522..d249b1574e0f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
@@ -51,10 +51,16 @@ properties:
       - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
     minItems: 2
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier for the CX power domain.
+    maxItems: 1
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -65,12 +71,14 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sm8350";
       reg = <0x00100000 0x1f0000>;
       clocks = <&rpmhcc RPMH_CXO_CLK>,
                <&sleep_clk>;
       clock-names = "bi_tcxo", "sleep_clk";
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

Re: [PATCH v3 04/47] dt-bindings: clock: qcom: gcc-sm8350: Add CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The DT binding example includes the legacy `qcom-rpmpd.h` header instead of the correct `qcom,rpmhpd.h` for resolving RPMh power domain macros.
--

--- Patch [4]: [PATCH v3 04/47] dt-bindings: clock: qcom: gcc-sm8350: Add CX power domain ---
commit da9ae2ea7784410b1afc05b6fc669ae089286661
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

dt-bindings: clock: qcom: gcc-sm8350: Add CX power domain

The GDSCs provided by the SM8350 GCC are supplied by the RPMh CX power
domain. This commit models that parent domain in the GCC binding and
makes the CX power-domain entry required.

> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
> index 97ffae3b55227..d249b1574e0f6 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml

[ ... ]

> @@ -65,12 +71,14 @@ unevaluatedProperties: false
>  examples:
>    - |
>      #include <dt-bindings/clock/qcom,rpmh.h>
> +    #include <dt-bindings/power/qcom-rpmpd.h>

[Severity: Low]
This isn't a bug, but should this example include the RPMh specific header
dt-bindings/power/qcom,rpmhpd.h instead of the legacy
dt-bindings/power/qcom-rpmpd.h to resolve the RPMHPD_CX macro?

While dt-bindings/power/qcom-rpmpd.h transitively includes the correct
header, relying on the legacy RPM power domain header for an RPMh SoC might
provide misleading documentation for developers referencing the example.

>      clock-controller@100000 {
>        compatible = "qcom,gcc-sm8350";
>        reg = <0x00100000 0x1f0000>;
>        clocks = <&rpmhcc RPMH_CXO_CLK>,
>                 <&sleep_clk>;
>        clock-names = "bi_tcxo", "sleep_clk";
> +      power-domains = <&rpmhpd RPMHPD_CX>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=4

[PATCH v3 05/47] dt-bindings: clock: qcom: gcc-sm8450: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8450 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required,
matching the hardware description needed by the GCC node.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
index 3169ac05e1d8..f6f73db26896 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
@@ -47,10 +47,16 @@ properties:
       - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
     minItems: 2
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier for the CX power domain.
+    maxItems: 1
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -61,11 +67,13 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sm8450";
       reg = <0x00100000 0x001f4200>;
       clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
       clock-names = "bi_tcxo", "sleep_clk";
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

Re: [PATCH v3 05/47] dt-bindings: clock: qcom: gcc-sm8450: Add CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incorrect header inclusion in the device tree binding example.
--

--- Patch [5]: [PATCH v3 05/47] dt-bindings: clock: qcom: gcc-sm8450: Add CX power domain ---
commit c1e862ec1e73b4d84d9b6b88d3c32be76ca192d0
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

dt-bindings: clock: qcom: gcc-sm8450: Add CX power domain

This patch updates the SM8450 GCC device tree binding to model the 
dependency on the RPMh CX power domain. It adds the required power-domain
property and updates the example to demonstrate its use.

> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> index 3169ac05e1d8a..f6f73db268965 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
[ ... ]
> @@ -61,11 +67,13 @@ unevaluatedProperties: false
>  examples:
>    - |
>      #include <dt-bindings/clock/qcom,rpmh.h>
> +    #include <dt-bindings/power/qcom-rpmpd.h>

[Severity: Low]
Should this example include <dt-bindings/power/qcom,rpmhpd.h> instead?

Since SM8450 is a modern SoC using RPMh, it might be more appropriate to
directly include the correct RPMh power domain header rather than relying on
the legacy qcom-rpmpd.h header to transitively resolve the RPMHPD_CX macro.

>      clock-controller@100000 {
>        compatible = "qcom,gcc-sm8450";
>        reg = <0x00100000 0x001f4200>;
>        clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>        clock-names = "bi_tcxo", "sleep_clk";
> +      power-domains = <&rpmhpd RPMHPD_CX>;
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=5

[PATCH v3 06/47] dt-bindings: clock: qcom: qcs615-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the QCS615 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required,
matching the hardware description needed by the GCC node.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
index 4a828e102d25..5fa73104df0d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
@@ -31,10 +31,16 @@ properties:
       - const: bi_tcxo_ao
       - const: sleep_clk
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier for the CX power domain.
+    maxItems: 1
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -45,6 +51,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
     clock-controller@100000 {
       compatible = "qcom,qcs615-gcc";
       reg = <0x00100000 0x1f0000>;
@@ -52,6 +59,7 @@ examples:
                <&rpmhcc RPMH_CXO_CLK_A>,
                <&sleep_clk>;
       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v3 07/47] dt-bindings: clock: qcom: sm8550-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8550 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required,
matching the hardware description needed by the GCC node.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
index c4e9b9bb63f5..26b78bd0afe6 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
@@ -31,9 +31,15 @@ properties:
       - description: UFS Phy Tx symbol 0 clock source
       - description: USB3 Phy wrapper pipe clock source
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier for the CX power domain.
+    maxItems: 1
+
 required:
   - compatible
   - clocks
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -44,6 +50,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
     clock-controller@100000 {
       compatible = "qcom,sm8550-gcc";
       reg = <0x00100000 0x001f4200>;
@@ -55,6 +62,7 @@ examples:
                <&ufs_mem_phy 1>,
                <&ufs_mem_phy 2>,
                <&usb_1_qmpphy>;
+       power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

Re: [PATCH v3 07/47] dt-bindings: clock: qcom: sm8550-gcc: Add CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] Making `power-domains` unconditionally `required` breaks schema backwards compatibility for existing Device Trees.
- [Low] Inconsistent indentation in the YAML example node.
--

--- Patch [7]: [PATCH v3 07/47] dt-bindings: clock: qcom: sm8550-gcc: Add CX power domain ---
commit 6ec2187de5227c13379772ac36b81930a158c612
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

dt-bindings: clock: qcom: sm8550-gcc: Add CX power domain

This commit adds the CX power domain to the SM8550 GCC binding so the provider
can describe the dependency in devicetree. It also updates the required
properties list and adds the property to the example.

> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
> index c4e9b9bb63f51..26b78bd0afe6b 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
[ ... ]
> @@ -31,9 +31,15 @@ properties:
[ ... ]
>  required:
>    - compatible
>    - clocks
> +  - power-domains

[Severity: Low]
Does making power-domains unconditionally required here break schema validation
for older devicetrees that were created before this property was introduced?

>    - '#power-domain-cells'
>  
>  allOf:
[ ... ]
> @@ -55,6 +62,7 @@ examples:
>                 <&ufs_mem_phy 1>,
>                 <&ufs_mem_phy 2>,
>                 <&usb_1_qmpphy>;
> +       power-domains = <&rpmhpd RPMHPD_CX>;

[Severity: Low]
This isn't a bug, but the indentation here uses 7 spaces whereas the surrounding
properties use 6. Should this be aligned to match the rest of the example node?

>        #clock-cells = <1>;
>        #reset-cells = <1>;
>        #power-domain-cells = <1>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=7

[PATCH v3 08/47] dt-bindings: clock: qcom: sm8650-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8650 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required,
matching the hardware description needed by the GCC node.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
index c7143e2abc80..f77b184e0b1e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
@@ -32,9 +32,15 @@ properties:
       - description: UFS Phy Tx symbol 0 clock source
       - description: USB3 Phy wrapper pipe clock source
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier for the CX power domain.
+    maxItems: 1
+
 required:
   - compatible
   - clocks
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -45,6 +51,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
     clock-controller@100000 {
       compatible = "qcom,sm8650-gcc";
       reg = <0x00100000 0x001f4200>;
@@ -58,6 +65,7 @@ examples:
                <&ufs_mem_phy 1>,
                <&ufs_mem_phy 2>,
                <&usb_1_qmpphy>;
+       power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

Re: [PATCH v3 08/47] dt-bindings: clock: qcom: sm8650-gcc: Add CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The YAML example includes the legacy RPM power domain header instead of the correct RPMh header.
- [Low] Incorrect indentation for the added `power-domains` property in the YAML example.
--

--- Patch [8]: [PATCH v3 08/47] dt-bindings: clock: qcom: sm8650-gcc: Add CX power domain ---
commit 1e67472888818783bc114028708b08007c44b70d
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

dt-bindings: clock: qcom: sm8650-gcc: Add CX power domain

This commit adds a required CX power domain to the SM8650 GCC clock
binding. It updates the schema to reflect this requirement and adds
the power domain to the example.

> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml

[ ... ]

> @@ -45,6 +51,7 @@ unevaluatedProperties: false
>  examples:
>    - |
>      #include <dt-bindings/clock/qcom,rpmh.h>
> +    #include <dt-bindings/power/qcom-rpmpd.h>

[Severity: Low]
Does this example include the correct header? This includes the legacy RPM 
power domain header (qcom-rpmpd.h) rather than the RPMh header appropriate 
for the SM8650 SoC.

>      clock-controller@100000 {
>        compatible = "qcom,sm8650-gcc";
>        reg = <0x00100000 0x001f4200>;
> @@ -58,6 +65,7 @@ examples:
>                 <&ufs_mem_phy 1>,
>                 <&ufs_mem_phy 2>,
>                 <&usb_1_qmpphy>;
> +       power-domains = <&rpmhpd RPMHPD_CX>;

[Severity: Low]
This is just a stylistic formatting issue, but is the indentation here
aligned correctly? The power-domains property appears to be indented with
7 spaces, whereas the sibling properties below it use 6 spaces.

>        #clock-cells = <1>;
>        #reset-cells = <1>;
>        #power-domain-cells = <1>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=8

[PATCH v3 09/47] dt-bindings: clock: qcom: sm8750-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8750 and Kaanapali GCCs are supplied by the
RPMh CX power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required,
matching the hardware description needed by the GCC node.

Fixes: 342d2a607450 ("dt-bindings: clock: qcom: Add Kaanapali Global clock controller")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
index 0114d347b26f..f54e836f3135 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
@@ -34,9 +34,15 @@ properties:
       - description: UFS Phy Tx symbol 0 clock source
       - description: USB3 Phy wrapper pipe clock source
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier for the CX power domain.
+    maxItems: 1
+
 required:
   - compatible
   - clocks
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -47,6 +53,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
     clock-controller@100000 {
       compatible = "qcom,sm8750-gcc";
       reg = <0x00100000 0x001f4200>;
@@ -58,6 +65,7 @@ examples:
                <&ufs_mem_phy 1>,
                <&ufs_mem_phy 2>,
                <&usb_1_qmpphy>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v3 10/47] clk: qcom: gcc-eliza: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Fixes: 6393a36fe184 ("clk: qcom: Add support for Global clock controller on Eliza")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-eliza.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c
index fe18942a59ac..e26e6e6e52f1 100644
--- a/drivers/clk/qcom/gcc-eliza.c
+++ b/drivers/clk/qcom/gcc-eliza.c
@@ -3068,6 +3068,7 @@ static const struct qcom_cc_desc gcc_eliza_desc = {
 	.num_resets = ARRAY_SIZE(gcc_eliza_resets),
 	.gdscs = gcc_eliza_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_eliza_gdscs),
+	.use_rpm = true,
 	.driver_data = &gcc_eliza_driver_data,
 };
 

-- 
2.54.0

[PATCH v3 11/47] clk: qcom: gcc-kaanapali: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Fixes: d1919c375f21 ("clk: qcom: Add support for Global clock controller on Kaanapali")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-kaanapali.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-kaanapali.c b/drivers/clk/qcom/gcc-kaanapali.c
index 5bcbcd178657..c40d2da1086a 100644
--- a/drivers/clk/qcom/gcc-kaanapali.c
+++ b/drivers/clk/qcom/gcc-kaanapali.c
@@ -3502,6 +3502,7 @@ static const struct qcom_cc_desc gcc_kaanapali_desc = {
 	.num_resets = ARRAY_SIZE(gcc_kaanapali_resets),
 	.gdscs = gcc_kaanapali_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_kaanapali_gdscs),
+	.use_rpm = true,
 	.driver_data = &gcc_kaanapali_driver_data,
 };
 

-- 
2.54.0

[PATCH v3 12/47] clk: qcom: gcc-qcs615: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-qcs615.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-qcs615.c b/drivers/clk/qcom/gcc-qcs615.c
index 57f8c80c6f32..601c81c84450 100644
--- a/drivers/clk/qcom/gcc-qcs615.c
+++ b/drivers/clk/qcom/gcc-qcs615.c
@@ -2967,6 +2967,7 @@ static const struct qcom_cc_desc gcc_qcs615_desc = {
 	.resets = gcc_qcs615_resets,
 	.num_resets = ARRAY_SIZE(gcc_qcs615_resets),
 	.gdscs = gcc_qcs615_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_qcs615_gdscs),
 };
 

-- 
2.54.0

Re: [PATCH v3 12/47] clk: qcom: gcc-qcs615: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The CLK_IS_CRITICAL flags on gcc_cpuss_ahb_clk and gcc_sys_noc_cpuss_ahb_clk permanently hold a runtime PM reference on the GCC controller, preventing the CX domain from ever powering down.
--

--- Patch [12]: [PATCH v3 12/47] clk: qcom: gcc-qcs615: Tie the CX power domain to controller ---
commit 4f409a8e397d7df1fcb5c05bdd3d11eaa2987e04
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-qcs615: Tie the CX power domain to controller
    
Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-qcs615.c b/drivers/clk/qcom/gcc-qcs615.c
> index 57f8c80c6f324..601c81c844505 100644
> --- a/drivers/clk/qcom/gcc-qcs615.c
> +++ b/drivers/clk/qcom/gcc-qcs615.c
> @@ -2967,6 +2967,7 @@ static const struct qcom_cc_desc gcc_qcs615_desc = {
>  	.resets = gcc_qcs615_resets,
>  	.num_resets = ARRAY_SIZE(gcc_qcs615_resets),
>  	.gdscs = gcc_qcs615_gdscs,
> +	.use_rpm = true,

[Severity: High]
The commit message states this allows CX to be powered down once all
consumers have released their clocks. Will the CX domain actually be able to
power down?

Looking at gcc_cpuss_ahb_clk and gcc_sys_noc_cpuss_ahb_clk in this driver,
they are both marked with CLK_IS_CRITICAL.

When the clock framework prepares critical clocks during initialization,
clk_core_prepare() calls clk_pm_runtime_get(), which increments the runtime PM
usage count for the GCC controller. Since critical clocks are never unprepared,
this reference is never dropped.

Will these critical clocks permanently hold the runtime PM usage count above
zero, preventing the GCC controller from ever entering runtime suspend and
keeping the CX domain powered on indefinitely?

>  	.num_gdscs = ARRAY_SIZE(gcc_qcs615_gdscs),
>  };
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=12

[PATCH v3 13/47] clk: qcom: gcc-qcs8300: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-qcs8300.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-qcs8300.c b/drivers/clk/qcom/gcc-qcs8300.c
index 146b3b5dfead..d04980e4a0bb 100644
--- a/drivers/clk/qcom/gcc-qcs8300.c
+++ b/drivers/clk/qcom/gcc-qcs8300.c
@@ -3681,6 +3681,7 @@ static const struct qcom_cc_desc gcc_qcs8300_desc = {
 	.num_resets = ARRAY_SIZE(gcc_qcs8300_resets),
 	.gdscs = gcc_qcs8300_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_qcs8300_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_qcs8300_match_table[] = {

-- 
2.54.0

Re: [PATCH v3 13/47] clk: qcom: gcc-qcs8300: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The GCC reset implementation does not take a pm_runtime reference before accessing reset registers, risking bus errors when consumers assert/deassert resets while the GCC controller is suspended.
--

--- Patch [13]: [PATCH v3 13/47] clk: qcom: gcc-qcs8300: Tie the CX power domain to controller ---
commit cad1ca2d5bc9c295249e6fa075b1dac72fab663e
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-qcs8300: Tie the CX power domain to controller
    
Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-qcs8300.c b/drivers/clk/qcom/gcc-qcs8300.c
> index 146b3b5dfead3..d04980e4a0bba 100644
> --- a/drivers/clk/qcom/gcc-qcs8300.c
> +++ b/drivers/clk/qcom/gcc-qcs8300.c
> @@ -3681,6 +3681,7 @@ static const struct qcom_cc_desc gcc_qcs8300_desc = {
>  	.num_resets = ARRAY_SIZE(gcc_qcs8300_resets),
>  	.gdscs = gcc_qcs8300_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gcc_qcs8300_gdscs),
> +	.use_rpm = true,

[Severity: High]
This is a pre-existing issue, but does enabling use_rpm expose a risk of bus
errors during reset assertions?

By setting use_rpm to true, the GCC controller and its CX power domain are
allowed to runtime suspend when all clocks and GDSCs are released. However,
the generic QCOM reset operations do not ensure the device is runtime-active
before performing register writes.

For example, when qcom_reset_set_assert() in drivers/clk/qcom/reset.c is
called, it performs:

    regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);

If a consumer asserts or deasserts a reset while the GCC controller is
suspended (such as from an error recovery interrupt, a teardown path, or by
a driver not utilizing PM runtime), could this register write fault and crash
the system?

Furthermore, because the reset operations use a fast_io regmap, they can be
invoked in an atomic context. If a consumer asserts a reset from an interrupt
handler while the GCC is suspended, it seems structurally impossible for the
consumer to wake the GCC controller first since doing so would sleep.

Is there a mechanism to prevent suspended register access during resets when
use_rpm is enabled?

>  };
>  
>  static const struct of_device_id gcc_qcs8300_match_table[] = {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=13

[PATCH v3 14/47] clk: qcom: gcc-qdu1000: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-qdu1000.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 915bb9b4ff81..172303ac4c9b 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -2649,6 +2649,7 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = {
 	.num_resets = ARRAY_SIZE(gcc_qdu1000_resets),
 	.gdscs = gcc_qdu1000_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_qdu1000_match_table[] = {

-- 
2.54.0

Re: [PATCH v3 14/47] clk: qcom: gcc-qdu1000: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [Low] Missing DT Binding Update for `power-domains` property.

Pre-existing issues:
- [High] System crash (synchronous external abort) due to unclocked register access during `clk_round_rate()` on DFS clocks.
- [High] System crash due to missing PM Runtime protection in reset operations.
--

--- Patch [14]: [PATCH v3 14/47] clk: qcom: gcc-qdu1000: Tie the CX power domain to controller ---
commit 51623b28802cf5aef15aece18cd9939c8e2691bb
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-qdu1000: Tie the CX power domain to controller
    
Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
> index 915bb9b4ff813..172303ac4c9bb 100644
> --- a/drivers/clk/qcom/gcc-qdu1000.c
> +++ b/drivers/clk/qcom/gcc-qdu1000.c
> @@ -2649,6 +2649,7 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = {
>  	.num_resets = ARRAY_SIZE(gcc_qdu1000_resets),
>  	.gdscs = gcc_qdu1000_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs),
> +	.use_rpm = true,

[Severity: Low]
Does enabling runtime PM here introduce a dependency on a power-domains
property that needs to be documented in the controller's specific binding?
Without updating qcom,qdu1000-gcc.yaml, might this lead to missing DT
constraints or dtbs_check warnings?

[Severity: High]
This isn't a bug introduced by this patch, but enabling runtime PM for this
controller exposes a pre-existing issue in the DFS clocks implementation.

When a consumer driver calls clk_round_rate() on an unprepared DFS clock,
the CCF clk_round_rate() API calls determine_rate() without holding a PM
runtime reference.

If the GCC device is suspended (CX domain off), can this sequence cause a
synchronous external abort due to unclocked register access?

drivers/clk/qcom/clk-rcg2.c:clk_rcg2_dfs_determine_rate() {
    ...
    ret = clk_rcg2_dfs_populate_freq_table(rcg);
    ...
}

drivers/clk/qcom/clk-rcg2.c:clk_rcg2_dfs_populate_freq_table() {
    ...
    regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
    ...
}

[Severity: High]
This is a pre-existing issue, but enabling runtime PM on the QDU1000
controller also exposes a vulnerability in the reset operations.

The reset functions appear to access hardware registers directly without
using pm_runtime_resume_and_get() on the GCC device.

If a consumer asserts or deasserts a reset while the GCC provider is
runtime suspended, will this unclocked register access crash the system?

drivers/clk/qcom/reset.c:qcom_reset_set_assert() {
    ...
    regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);
    ...
}

>  };
>  
>  static const struct of_device_id gcc_qdu1000_match_table[] = {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=14

[PATCH v3 15/47] clk: qcom: gcc-sa8775p: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sa8775p.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
index dca316decd0e..2f867596bbc5 100644
--- a/drivers/clk/qcom/gcc-sa8775p.c
+++ b/drivers/clk/qcom/gcc-sa8775p.c
@@ -4652,6 +4652,7 @@ static const struct qcom_cc_desc gcc_sa8775p_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sa8775p_resets),
 	.gdscs = gcc_sa8775p_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sa8775p_match_table[] = {

-- 
2.54.0

[PATCH v3 16/47] clk: qcom: gcc-sar2130p: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sar2130p.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sar2130p.c b/drivers/clk/qcom/gcc-sar2130p.c
index 475e2cda3618..1a16f9d68bab 100644
--- a/drivers/clk/qcom/gcc-sar2130p.c
+++ b/drivers/clk/qcom/gcc-sar2130p.c
@@ -2308,6 +2308,7 @@ static const struct qcom_cc_desc gcc_sar2130p_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sar2130p_resets),
 	.gdscs = gcc_sar2130p_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sar2130p_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sar2130p_match_table[] = {

-- 
2.54.0

Re: [PATCH v3 16/47] clk: qcom: gcc-sar2130p: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] In gdsc_register(), when an error occurs during gdsc_init() or subsequent subdomain attachment, the function fails to unregister the previously initialized pm_genpd domains, leading to a permanent leak and linked-list corruption upon driver reprobe.
--

--- Patch [16]: [PATCH v3 16/47] clk: qcom: gcc-sar2130p: Tie the CX power domain to controller ---
commit a5913ce7b2e1ade74a139dc203b812733f756b77
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-sar2130p: Tie the CX power domain to controller

This commit enables runtime PM for the controller by setting use_rpm to true
in the gcc_sar2130p_desc structure. This allows the CX power domain to be
powered down once all GCC consumers release their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-sar2130p.c b/drivers/clk/qcom/gcc-sar2130p.c
> index 475e2cda3618b..1a16f9d68babb 100644
> --- a/drivers/clk/qcom/gcc-sar2130p.c
> +++ b/drivers/clk/qcom/gcc-sar2130p.c
> @@ -2308,6 +2308,7 @@ static const struct qcom_cc_desc gcc_sar2130p_desc = {
>  	.num_resets = ARRAY_SIZE(gcc_sar2130p_resets),
>  	.gdscs = gcc_sar2130p_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gcc_sar2130p_gdscs),

[Severity: High]
This is a pre-existing issue, but I noticed something when looking at how
GDSCs are registered for this controller.

If gdsc_register() in drivers/clk/qcom/gdsc.c fails, could this lead to a
memory leak and linked-list corruption on a subsequent driver reprobe?

drivers/clk/qcom/gdsc.c:gdsc_register() {
    ...
		ret = gdsc_init(scs[i]);
		if (ret)
			return ret;
    ...
err_pm_subdomain_remove:
	gdsc_pm_subdomain_remove(desc, i);

	return ret;
}

When an error occurs during gdsc_init() or subsequent subdomain attachment,
the function returns without unregistering the previously initialized pm_genpd
domains.

Since the gdsc structs and their embedded generic_pm_domain structs are
typically statically allocated by clock drivers, a subsequent driver reprobe
(such as from deferred probe) will call pm_genpd_init() again on the same
structs.

Will this attempt to list_add() the node into gpd_list when it is already
linked, corrupting the list?

> +	.use_rpm = true,
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=16

[PATCH v3 17/47] clk: qcom: gcc-sc7180: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sc7180.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index 4a49ad7a9e5b..f3a245470a4d 100644
--- a/drivers/clk/qcom/gcc-sc7180.c
+++ b/drivers/clk/qcom/gcc-sc7180.c
@@ -2418,6 +2418,7 @@ static const struct qcom_cc_desc gcc_sc7180_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sc7180_resets),
 	.gdscs = gcc_sc7180_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sc7180_match_table[] = {

-- 
2.54.0

Re: [PATCH v3 17/47] clk: qcom: gcc-sc7180: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Enabling runtime PM on the gcc-sc7180 controller fails to allow the CX power domain to power down because CLK_IS_CRITICAL clocks hold permanent PM runtime references.
- [Medium] Manual register configurations performed in probe() will be permanently lost if the CX power domain successfully powers down.
--

--- Patch [17]: [PATCH v3 17/47] clk: qcom: gcc-sc7180: Tie the CX power domain to controller ---
commit bda4bbdc6882e3eeb0fc4bbaf2482c52d18aab7d
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-sc7180: Tie the CX power domain to controller
    
Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
> index 4a49ad7a9e5be..f3a245470a4de 100644
> --- a/drivers/clk/qcom/gcc-sc7180.c
> +++ b/drivers/clk/qcom/gcc-sc7180.c
> @@ -2418,6 +2418,7 @@ static const struct qcom_cc_desc gcc_sc7180_desc = {
>  	.num_resets = ARRAY_SIZE(gcc_sc7180_resets),
>  	.gdscs = gcc_sc7180_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
> +	.use_rpm = true,

[Severity: Medium]
Will the CX power domain actually be able to power down?

The Common Clock Framework automatically prepares clocks marked with
CLK_IS_CRITICAL during initialization, such as gcc_cpuss_ahb_clk:

drivers/clk/qcom/gcc-sc7180.c:gcc_cpuss_ahb_clk {
    ...
			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
    ...
}

Preparing these clocks calls clk_pm_runtime_get(), which increments the
runtime PM usage counter of the GCC provider device. Since critical clocks
are never unprepared, this reference is never dropped.

Does this prevent the controller's usage count from ever reaching zero?

[Severity: Medium]
If the controller does manage to runtime suspend and the CX power domain
powers off, will the manual register configurations performed in
gcc_sc7180_probe() be lost?

For example:

drivers/clk/qcom/gcc-sc7180.c:gcc_sc7180_probe() {
    ...
	regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
	regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
	regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
    ...
}

Because gcc_sc7180_driver lacks dev_pm_ops with a runtime_resume callback
to restore these settings, and does not use a regcache, will the controller
resume in an uninitialized default state?

>  };
>  
>  static const struct of_device_id gcc_sc7180_match_table[] = {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=17

[PATCH v3 18/47] clk: qcom: gcc-sc7280: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sc7280.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
index 4502926a2691..bb8f6efb88b1 100644
--- a/drivers/clk/qcom/gcc-sc7280.c
+++ b/drivers/clk/qcom/gcc-sc7280.c
@@ -3446,6 +3446,7 @@ static const struct qcom_cc_desc gcc_sc7280_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sc7280_resets),
 	.gdscs = gcc_sc7280_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sc7280_match_table[] = {

-- 
2.54.0

Re: [PATCH v3 18/47] clk: qcom: gcc-sc7280: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Enabling runtime PM on the GCC controller (`use_rpm = true`) introduces a crash during reset operations because `qcom_reset_ops` perform raw regmap accesses without taking a runtime PM reference. Asserting a reset when the GCC device is suspended will access unpowered registers.
--

--- Patch [18]: [PATCH v3 18/47] clk: qcom: gcc-sc7280: Tie the CX power domain to controller ---
commit 759cca681f45c71a5a8669a98523e27fad8124b8
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-sc7280: Tie the CX power domain to controller

Enable runtime PM for the controller, allowing CX to be powered down once all
GCC consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
> index 4502926a2691a..bb8f6efb88b1c 100644
> --- a/drivers/clk/qcom/gcc-sc7280.c
> +++ b/drivers/clk/qcom/gcc-sc7280.c
> @@ -3446,6 +3446,7 @@ static const struct qcom_cc_desc gcc_sc7280_desc = {
>  	.num_resets = ARRAY_SIZE(gcc_sc7280_resets),
>  	.gdscs = gcc_sc7280_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs),
> +	.use_rpm = true,

[Severity: High]
Does enabling runtime PM here introduce a potential crash during reset
operations?

Looking at drivers/clk/qcom/reset.c, the reset operations perform raw regmap
accesses without taking a runtime PM reference:

drivers/clk/qcom/reset.c:qcom_reset_set_assert() {
	...
	regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);
	...
}

If a consumer asserts a reset while the GCC controller is suspended, could
this access unpowered registers and cause a synchronous external abort?

Since the regmap configuration lacks .pm_runtime = true and the reset code
does not wrap the regmap accesses with pm_runtime_resume_and_get(), this
might allow accessing the hardware while the CX domain is powered off.

>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=18

[PATCH v3 19/47] clk: qcom: gcc-sdm670: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sdm845.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 6d0f9cede5cf..57d54b45fa52 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3948,6 +3948,7 @@ static const struct qcom_cc_desc gcc_sdm670_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sdm845_resets),
 	.gdscs = gcc_sdm670_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sdm670_gdscs),
+	.use_rpm = true,
 };
 
 static const struct qcom_cc_desc gcc_sdm845_desc = {

-- 
2.54.0

Re: [PATCH v3 19/47] clk: qcom: gcc-sdm670: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:

New issues:
- [High] The patch adds `.use_rpm = true` to allow the CX power domain to power down when idle, but `CLK_IS_CRITICAL` clocks permanently prevent the device from suspending, entirely defeating the patch's goal.
- [High] Enabling runtime PM introduces a permanent PM runtime usage count leak on probe deferral.

Pre-existing issues:
- [High] Missing `sync_state` callback causes GDSCs initialized as active by the bootloader to stay powered on indefinitely, defeating the patch's purpose of powering down CX.
- [High] If `gdsc_init()` or `pm_genpd_add_subdomain()` fails in `gdsc_register()`, previously initialized generic PM domains are not removed, leading to a Use-After-Free.
--

--- Patch [19]: [PATCH v3 19/47] clk: qcom: gcc-sdm670: Tie the CX power domain to controller ---
commit b55a4bcc407393a5d2f7c186b77a4841507253c0
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-sdm670: Tie the CX power domain to controller

This commit sets use_rpm to true in the gcc_sdm670_desc configuration to
enable runtime PM for the controller. The goal is to allow the CX power
domain to be powered down when all consumers have released their clocks and
GDSCs.

> diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
> index 6d0f9cede5cfe..57d54b45fa527 100644
> --- a/drivers/clk/qcom/gcc-sdm845.c
> +++ b/drivers/clk/qcom/gcc-sdm845.c
> @@ -3948,6 +3948,7 @@ static const struct qcom_cc_desc gcc_sdm670_desc = {
>  	.num_resets = ARRAY_SIZE(gcc_sdm845_resets),
>  	.gdscs = gcc_sdm670_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gcc_sdm670_gdscs),
> +	.use_rpm = true,

[Severity: High]
Does setting use_rpm to true actually allow the device to suspend?

When use_rpm is true, clk_core_prepare() takes a PM runtime vote on the GCC
device. However, critical clocks are permanently prepared at registration:

drivers/clk/qcom/gcc-sdm845.c:gcc_camera_ahb_clk {
	...
	.flags = CLK_IS_CRITICAL,
}

Since critical clocks are never unprepared, the runtime PM vote is never
dropped, which appears to keep the CX power domain permanently active. Does
this prevent the patch from achieving its power-savings objective?


[Severity: High]
Will enabling runtime PM here introduce a usage count leak on probe deferral?

Critical clocks take a PM runtime reference during registration. If probe
defers later (for example in qcom_cc_icc_register()), the clocks are
unregistered via clk_unregister().

However, clk_unregister() doesn't unprepare critical clocks or drop the PM
runtime reference:

drivers/clk/clk.c:clk_unregister() {
	if (clk->core->prepare_count)
		pr_warn("%s: unregistering prepared clock: %s\n",
				__func__, clk->core->name);
	...
}

Does this lead to permanently unbalanced usage counts every time probe defers?

>  };
>  
>  static const struct qcom_cc_desc gcc_sdm845_desc = {

[Severity: High]
This isn't a bug introduced by this patch, but does the lack of a sync_state
callback in gcc_sdm845_driver prevent the CX power domain from powering down?

When GDSCs are initialized as active by the bootloader, pm_genpd_init() is
called with is_off=false, and the genpd framework sets stay_on=true. This
flag is only cleared when the device driver's sync_state callback fires.

Since gcc_sdm845_driver lacks a sync_state callback (like
of_genpd_sync_state), the stay_on flag is never cleared:

drivers/clk/qcom/gcc-sdm845.c:gcc_sdm845_driver {
	.probe		= gcc_sdm845_probe,
	.driver		= {
		.name	= "gcc-sdm845",
		.of_match_table = gcc_sdm845_match_table,
	},
}

Could this cause active GDSCs to stay powered on indefinitely?


[Severity: High]
This is a pre-existing issue, but can the error path in gdsc_register() lead
to a use-after-free?

If gdsc_init() or pm_genpd_add_subdomain() fails during the loop in
gdsc_register(), it exits immediately and only cleans up subdomains:

drivers/clk/qcom/gdsc.c:gdsc_register() {
	...
		ret = gdsc_init(scs[i]);
		if (ret)
			return ret;
	...
err_pm_subdomain_remove:
	gdsc_pm_subdomain_remove(desc, i);

	return ret;
}

The error path fails to call pm_genpd_remove() for the previously
initialized generic PM domains, leaving them in the global gpd_list. If the
module is later unloaded, the statically allocated GDSC structures are
freed, which might cause a kernel panic on the next gpd_list traversal.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=19

[PATCH v3 20/47] clk: qcom: gcc-sdm845: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sdm845.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 57d54b45fa52..cde863dcf185 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3959,6 +3959,7 @@ static const struct qcom_cc_desc gcc_sdm845_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sdm845_resets),
 	.gdscs = gcc_sdm845_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sdm845_match_table[] = {

-- 
2.54.0

Re: [PATCH v3 20/47] clk: qcom: gcc-sdm845: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [Medium] The patch attempts to allow the CX power domain to power down when idle by enabling runtime PM for the GCC controller, but critical clocks defined in the driver will keep the controller permanently active.
- [Medium] Enabling runtime PM on a clock controller with `CLK_IS_CRITICAL` clocks causes a permanent runtime PM reference leak on probe failure or driver unbind.

Pre-existing issues:
- [High] Reset operations lack runtime PM protection, leading to unpowered register accesses if the controller suspends.
--

--- Patch [20]: [PATCH v3 20/47] clk: qcom: gcc-sdm845: Tie the CX power domain to controller ---
commit c6cece4b4445a4812f7e7d75a76e3be120d33d8f
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-sdm845: Tie the CX power domain to controller

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
> index 57d54b45fa527..cde863dcf1851 100644
> --- a/drivers/clk/qcom/gcc-sdm845.c
> +++ b/drivers/clk/qcom/gcc-sdm845.c
> @@ -3959,6 +3959,7 @@ static const struct qcom_cc_desc gcc_sdm845_desc = {
>  	.num_resets = ARRAY_SIZE(gcc_sdm845_resets),
>  	.gdscs = gcc_sdm845_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
> +	.use_rpm = true,

[Severity: Medium]
Does enabling runtime PM actually allow the controller to suspend given
the CLK_IS_CRITICAL clocks defined in this driver?

For example, gcc_camera_ahb_clk is defined with the CLK_IS_CRITICAL flag.
During clock registration, the clock framework prepares these always-on
clocks and calls pm_runtime_resume_and_get() on the provider. Since these
clocks are never unprepared, the usage count will never drop to zero,
which seems to prevent the CX power domain from ever powering down.

[Severity: Medium]
Additionally, if qcom_cc_really_probe() fails later (for instance, during
qcom_cc_icc_register), devres will clean up by calling clk_unregister().

Since clk_unregister() intentionally does not unprepare clocks, does this
leave a permanent runtime PM reference leak for any clocks marked with 
CLK_IS_CRITICAL that were registered before the failure?

[Severity: High]
This isn't a bug introduced by this patch, but enabling runtime PM
exposes a potential crash during reset operations.

In drivers/clk/qcom/reset.c, qcom_reset_set_assert() accesses hardware
registers without taking a runtime PM reference:

qcom_reset_set_assert() {
    ...
    regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);
    ...
}

If the controller successfully suspends, and a consumer driver asserts a 
reset before explicitly preparing its clocks, will this access unpowered 
hardware and cause a synchronous external abort?

>  };
>  
>  static const struct of_device_id gcc_sdm845_match_table[] = {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=20

[PATCH v3 21/47] clk: qcom: gcc-sdx75: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sdx75.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c
index 6712e76f875c..7a17e300abce 100644
--- a/drivers/clk/qcom/gcc-sdx75.c
+++ b/drivers/clk/qcom/gcc-sdx75.c
@@ -2913,6 +2913,7 @@ static const struct qcom_cc_desc gcc_sdx75_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sdx75_resets),
 	.gdscs = gcc_sdx75_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sdx75_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sdx75_match_table[] = {

-- 
2.54.0

[PATCH v3 22/47] clk: qcom: gcc-sm4450: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm4450.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm4450.c b/drivers/clk/qcom/gcc-sm4450.c
index 30fc7af09930..41d5f35c8f5e 100644
--- a/drivers/clk/qcom/gcc-sm4450.c
+++ b/drivers/clk/qcom/gcc-sm4450.c
@@ -2823,6 +2823,7 @@ static const struct qcom_cc_desc gcc_sm4450_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sm4450_resets),
 	.gdscs = gcc_sm4450_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sm4450_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sm4450_match_table[] = {

-- 
2.54.0

[PATCH v3 23/47] clk: qcom: gcc-sm6350: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm6350.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm6350.c b/drivers/clk/qcom/gcc-sm6350.c
index a4d6dff9d0f7..b99a5bc53048 100644
--- a/drivers/clk/qcom/gcc-sm6350.c
+++ b/drivers/clk/qcom/gcc-sm6350.c
@@ -2545,6 +2545,7 @@ static const struct qcom_cc_desc gcc_sm6350_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sm6350_resets),
 	.gdscs = gcc_sm6350_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sm6350_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sm6350_match_table[] = {

-- 
2.54.0

Re: [PATCH v3 23/47] clk: qcom: gcc-sm6350: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The GCC controller will never enter runtime suspend, preventing the CX power domain from powering down at runtime as intended due to critical clocks.
--

--- Patch [23]: [PATCH v3 23/47] clk: qcom: gcc-sm6350: Tie the CX power domain to controller ---
commit 5be3761ba3c42a260ccac2e7a6451b101d998dad
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-sm6350: Tie the CX power domain to controller

This commit sets use_rpm = true in the gcc_sm6350_desc struct to enable
runtime PM for the GCC controller. The stated intent is to allow the CX
power domain to be powered down once all consumers have released their
clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-sm6350.c b/drivers/clk/qcom/gcc-sm6350.c
> index a4d6dff9d0f7f..b99a5bc530483 100644
> --- a/drivers/clk/qcom/gcc-sm6350.c
> +++ b/drivers/clk/qcom/gcc-sm6350.c
> @@ -2545,6 +2545,7 @@ static const struct qcom_cc_desc gcc_sm6350_desc = {
>  	.num_resets = ARRAY_SIZE(gcc_sm6350_resets),
>  	.gdscs = gcc_sm6350_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gcc_sm6350_gdscs),
> +	.use_rpm = true,

[Severity: Medium]
Will this actually allow the GCC controller to enter runtime suspend?

Looking at drivers/clk/qcom/gcc-sm6350.c, there are multiple clocks
registered with the CLK_IS_CRITICAL flag, such as gcc_camera_ahb_clk.

When use_rpm is set to true, the clock core takes a runtime PM reference on
the GCC device during clock preparation. Since critical clocks are prepared
during initialization and never unprepared, their runtime PM references are
never dropped.

Won't the usage counter permanently stay above zero, preventing the CX power
domain from ever powering down?

>  };
>  
>  static const struct of_device_id gcc_sm6350_match_table[] = {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=23

[PATCH v3 24/47] clk: qcom: gcc-sm8150: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8150.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index a93d1f412a7b..1404996d33c3 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -3771,6 +3771,7 @@ static const struct qcom_cc_desc gcc_sm8150_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sm8150_resets),
 	.gdscs = gcc_sm8150_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sm8150_match_table[] = {

-- 
2.54.0

Re: [PATCH v3 24/47] clk: qcom: gcc-sm8150: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Medium] Enabling runtime PM is ineffective because existing critical clocks permanently hold the runtime PM usage counter.

Pre-existing issues:
- [High] Memory leak and Use-After-Free if `gdsc_register()` fails during probe.
--

--- Patch [24]: [PATCH v3 24/47] clk: qcom: gcc-sm8150: Tie the CX power domain to controller ---
commit ff2aa55fcb39d64d3dce326e500a4af7e5279711
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-sm8150: Tie the CX power domain to controller

This commit enables runtime PM for the controller, allowing CX to be powered
down once all GCC consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index a93d1f412a7b6..1404996d33c31 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -3771,6 +3771,7 @@ static const struct qcom_cc_desc gcc_sm8150_desc = {
>  	.num_resets = ARRAY_SIZE(gcc_sm8150_resets),
>  	.gdscs = gcc_sm8150_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
> +	.use_rpm = true,

[Severity: Medium]
Does this actually allow the device to suspend?

The GCC driver registers multiple clocks with the CLK_IS_CRITICAL flag,
such as gcc_disp_ahb_clk. During registration, the clock core automatically
calls clk_core_prepare() on these clocks, which in turn calls
clk_pm_runtime_get() and increments the provider device's runtime PM usage
counter. 

Since these clocks are never unprepared, won't the usage counter never
drop to zero, preventing the device from entering RPM_SUSPENDED and keeping
the CX power domain permanently active?

[Severity: High]
This isn't a bug introduced by this patch, but is there a memory leak and
use-after-free risk if driver probe fails in gdsc_register()?

In drivers/clk/qcom/gdsc.c:gdsc_register(), gdsc_init() links the domain
into the global gpd_list via pm_genpd_init().

If a subsequent iteration fails:

drivers/clk/qcom/gdsc.c:gdsc_register() {
    ...
		ret = gdsc_init(scs[i]);
		if (ret)
			return ret;
    ...
}

Or if subdomain addition or provider registration fails:

drivers/clk/qcom/gdsc.c:gdsc_register() {
    ...
err_pm_subdomain_remove:
	gdsc_pm_subdomain_remove(desc, i);

	return ret;
}

The function returns without unregistering the GDSCs initialized in previous
iterations (pm_genpd_remove() is not called). Because the cleanup action is
only added on success via devm_add_action_or_reset(), do the successfully
initialized GDSCs remain in the global gpd_list?

If the module is later unloaded, could this leave dangling pointers in the
global list and cause a kernel panic upon the next traversal?

>  };
>  
>  static const struct of_device_id gcc_sm8150_match_table[] = {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=24

[PATCH v3 25/47] clk: qcom: gcc-sm8250: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8250.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c
index 1c59d70e0f96..86c2be3804c1 100644
--- a/drivers/clk/qcom/gcc-sm8250.c
+++ b/drivers/clk/qcom/gcc-sm8250.c
@@ -3618,6 +3618,7 @@ static const struct qcom_cc_desc gcc_sm8250_desc = {
 	.resets = gcc_sm8250_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8250_resets),
 	.gdscs = gcc_sm8250_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs),
 };
 

-- 
2.54.0

[PATCH v3 26/47] clk: qcom: gcc-sm8350: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8350.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
index 2d94f3046b71..996ee8592fab 100644
--- a/drivers/clk/qcom/gcc-sm8350.c
+++ b/drivers/clk/qcom/gcc-sm8350.c
@@ -3786,6 +3786,7 @@ static const struct qcom_cc_desc gcc_sm8350_desc = {
 	.resets = gcc_sm8350_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8350_resets),
 	.gdscs = gcc_sm8350_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
 };
 

-- 
2.54.0

Re: [PATCH v3 26/47] clk: qcom: gcc-sm8350: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] This problem wasn't introduced by this patch, but missing pm_genpd_remove cleanup on error paths in gdsc_register leads to leaked PM domains and global list corruption upon reprobe.
--

--- Patch [26]: [PATCH v3 26/47] clk: qcom: gcc-sm8350: Tie the CX power domain to controller ---
commit 463c8123d4d3a81e488b69352069b211c58bd412
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-sm8350: Tie the CX power domain to controller

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
> index 2d94f3046b711..996ee8592fabe 100644
> --- a/drivers/clk/qcom/gcc-sm8350.c
> +++ b/drivers/clk/qcom/gcc-sm8350.c
> @@ -3786,6 +3786,7 @@ static const struct qcom_cc_desc gcc_sm8350_desc = {
>  	.resets = gcc_sm8350_resets,
>  	.num_resets = ARRAY_SIZE(gcc_sm8350_resets),
>  	.gdscs = gcc_sm8350_gdscs,
> +	.use_rpm = true,

[Severity: High]
This is a pre-existing issue, but missing pm_genpd_remove cleanup on error
paths in gdsc_register() leads to leaked PM domains and global list corruption
upon reprobe.

If gdsc_init() or subsequent subdomain additions fail in gdsc_register(),
the function returns without calling pm_genpd_remove() for the successfully
initialized domains:

drivers/clk/qcom/gdsc.c:gdsc_register() {
    ...
		ret = gdsc_init(scs[i]);
		if (ret)
			return ret;
    ...
	err_pm_subdomain_remove:
	gdsc_pm_subdomain_remove(desc, i);

	return ret;
}

Because the gdsc structures are statically allocated (like gcc_sm8350_gdscs),
the leaked PM domains remain permanently linked in the kernel's global
gpd_list.

If the driver is reprobed (e.g., via sysfs bind/unbind or late probe
deferral), pm_genpd_init() is called again on the same static objects,
triggering a list_add() on nodes already present in the list.

Does this break the list pointers and cause a kernel panic due to list
corruption?

>  	.num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=26

[PATCH v3 27/47] clk: qcom: gcc-sm8450: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8450.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index b18bb34889ab..b3ab458048dc 100644
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -3399,6 +3399,7 @@ static const struct qcom_cc_desc gcc_sm8450_desc = {
 	.resets = gcc_sm8450_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8450_resets),
 	.gdscs = gcc_sm8450_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs),
 };
 

-- 
2.54.0

[PATCH v3 28/47] clk: qcom: gcc-sm8550: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8550.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index 36a5b7de5b55..427ae9cf28c1 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -3326,6 +3326,7 @@ static const struct qcom_cc_desc gcc_sm8550_desc = {
 	.resets = gcc_sm8550_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8550_resets),
 	.gdscs = gcc_sm8550_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8550_gdscs),
 };
 

-- 
2.54.0

[PATCH v3 29/47] clk: qcom: gcc-sm8650: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8650.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c
index f7e2d7ec60c9..b5cd4e3917b7 100644
--- a/drivers/clk/qcom/gcc-sm8650.c
+++ b/drivers/clk/qcom/gcc-sm8650.c
@@ -3784,6 +3784,7 @@ static const struct qcom_cc_desc gcc_sm8650_desc = {
 	.resets = gcc_sm8650_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8650_resets),
 	.gdscs = gcc_sm8650_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8650_gdscs),
 };
 

-- 
2.54.0

[PATCH v3 30/47] clk: qcom: gcc-sm8750: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8750.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c
index 6cfe90122268..a4a3ece74f40 100644
--- a/drivers/clk/qcom/gcc-sm8750.c
+++ b/drivers/clk/qcom/gcc-sm8750.c
@@ -3195,6 +3195,7 @@ static const struct qcom_cc_desc gcc_sm8750_desc = {
 	.resets = gcc_sm8750_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8750_resets),
 	.gdscs = gcc_sm8750_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8750_gdscs),
 };
 

-- 
2.54.0

[PATCH v3 31/47] clk: qcom: gcc-x1e80100: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-x1e80100.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index 8c146d62c077..832633a85f1a 100644
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -7449,6 +7449,7 @@ static const struct qcom_cc_desc gcc_x1e80100_desc = {
 	.num_resets = ARRAY_SIZE(gcc_x1e80100_resets),
 	.gdscs = gcc_x1e80100_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_x1e80100_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_x1e80100_match_table[] = {

-- 
2.54.0

[PATCH v3 32/47] arm64: dts: qcom: kaanapali: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on Kaanapali are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Fixes: 2eeb5767d53f ("arm64: dts: qcom: Introduce Kaanapali SoC")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 131fd2a16c54..c1528cc8b7b3 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -552,6 +552,8 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 2>,
 				 <0>;
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

[PATCH v3 33/47] arm64: dts: qcom: monaco: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on QCS8300 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index cfe39f923224..0786ab4c5f0d 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -898,6 +898,7 @@ gcc: clock-controller@100000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&sleep_clk>,
 				 <&pcie0_phy>,

-- 
2.54.0

Re: [PATCH v3 33/47] arm64: dts: qcom: monaco: Add GCC CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `power-domains` property is added to the `gcc` node in `monaco.dtsi`, but the corresponding Device Tree binding schema (`Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml`) was not updated to permit this property.
--

--- Patch [33]: [PATCH v3 33/47] arm64: dts: qcom: monaco: Add GCC CX power domain ---
commit c01d37fc2cc8cfc1732e168d2e3f85648e0aed4c
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>
Subject: arm64: dts: qcom: monaco: Add GCC CX power domain

This commit adds the CX power-domain reference to the GCC node in
qcom/monaco.dtsi. This ensures that votes from GCC GDSC consumers can
propagate to RPMh CX.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index cfe39f923224f..0786ab4c5f0dc 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -898,6 +898,7 @@ gcc: clock-controller@100000 {
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;
> +			power-domains = <&rpmhpd RPMHPD_CX>;

[Severity: Low]
Is the power-domains property allowed by the Device Tree binding schema
for this node?

It appears Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml
was not updated to permit this property, which could cause validation errors
during make dtbs_check.

Follow-up patches in this series updated bindings for other SoCs (like SM8550
and QCS615) to explicitly include power-domains, but it looks like QCS8300
was omitted.

>  			clocks = <&rpmhcc RPMH_CXO_CLK>,
>  				 <&sleep_clk>,
>  				 <&pcie0_phy>,

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=33

[PATCH v3 34/47] arm64: dts: qcom: qdu1000: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on QDU1000 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index af106aebd30d..accb4b989655 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -396,6 +396,7 @@ gcc: clock-controller@80000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd QDU1000_CX>;
 		};
 
 		ecpricc: clock-controller@280000 {

-- 
2.54.0

Re: [PATCH v3 34/47] arm64: dts: qcom: qdu1000: Add GCC CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `power-domains` property is added to the `gcc` node in `qdu1000.dtsi`, but the corresponding dt-binding `qcom,qdu1000-gcc.yaml` is not updated to allow it.
--

--- Patch [34]: [PATCH v3 34/47] arm64: dts: qcom: qdu1000: Add GCC CX power domain ---
commit a47858da198026a42957240d575a834059b75374
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: qdu1000: Add GCC CX power domain

This commit adds the CX power-domain reference to the GCC node in the
QDU1000 device tree. This allows votes from GCC GDSC consumers to propagate
to the RPMh CX domain.

> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> index af106aebd30dc..accb4b989655d 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -396,6 +396,7 @@ gcc: clock-controller@80000 {
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;
> +			power-domains = <&rpmhpd QDU1000_CX>;

[Severity: Low]
Does this new property require a corresponding update to the dt-binding
schema?

Because Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml sets
unevaluatedProperties: false and does not currently define power-domains,
will this addition cause make dtbs_check to fail during validation?

>  		};
>  
>  		ecpricc: clock-controller@280000 {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=34

[PATCH v3 35/47] arm64: dts: qcom: sar2130p: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SAR2130P are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sar2130p.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
index a2d93fd68299..b6ca31b87d1f 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
@@ -475,6 +475,7 @@ gcc: clock-controller@100000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&sleep_clk>,
 				 <&pcie0_phy>,

-- 
2.54.0

[PATCH v3 36/47] arm64: dts: qcom: sdm670: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SDM670 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 5c60ea36f04a..1978a54db23b 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -626,6 +626,7 @@ gcc: clock-controller@100000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd SDM670_CX>;
 		};
 
 		qfprom: qfprom@784000 {

-- 
2.54.0

[PATCH v3 37/47] arm64: dts: qcom: sdx75: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SDX75 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sdx75.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index 85cc9c6e6f83..d4ef90c4a8db 100644
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -487,6 +487,7 @@ gcc: clock-controller@80000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

Re: [PATCH v3 37/47] arm64: dts: qcom: sdx75: Add GCC CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `power-domains` property is added to the GCC device tree node, but it is not documented in the corresponding `qcom,sdx75-gcc.yaml` device tree binding schema.
--

--- Patch [37]: [PATCH v3 37/47] arm64: dts: qcom: sdx75: Add GCC CX power domain ---
commit 31a230bc14fd1ed4b8fc915db1a0015701f6c99b
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: sdx75: Add GCC CX power domain

This commit adds a reference to the RPMh CX power domain in the SDX75 GCC
node. This allows consumers of GCC-provided GDSCs to propagate their local
domain votes to the required CX state.

> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> index 85cc9c6e6f83f..d4ef90c4a8db2 100644
> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> @@ -487,6 +487,7 @@ gcc: clock-controller@80000 {
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;
> +			power-domains = <&rpmhpd RPMHPD_CX>;

[Severity: Low]
Will adding this property cause a dtbs_check validation regression?

The Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml schema
does not appear to document the power-domains property, and it enforces
unevaluatedProperties: false.

Does the schema need to be updated alongside this change to prevent
validation errors?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=37

[PATCH v3 38/47] arm64: dts: qcom: sm4450: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM4450 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm4450.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index b7dc40f3778c..0057f68732b1 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -390,6 +390,7 @@ gcc: clock-controller@100000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&sleep_clk>,
 				 <0>,

-- 
2.54.0

[PATCH v3 39/47] arm64: dts: qcom: sm6350: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM6350 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 15d38b7e803c..ded5c3a45891 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -794,6 +794,7 @@ gcc: clock-controller@100000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd SM6350_CX>;
 			clock-names = "bi_tcxo",
 				      "bi_tcxo_ao",
 				      "sleep_clk";

-- 
2.54.0

Re: [PATCH v3 39/47] arm64: dts: qcom: sm6350: Add GCC CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Adding the `power-domains` property to the `gcc` node without updating its DT binding schema will trigger a dtbs_check warning.
--

--- Patch [39]: [PATCH v3 39/47] arm64: dts: qcom: sm6350: Add GCC CX power domain ---
commit e7cbb98ab7c0a2a7495045fc51188886857246b1
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: sm6350: Add GCC CX power domain

The GCC GDSCs on SM6350 are backed by the RPMh CX power domain. This commit
adds the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 15d38b7e803c5..ded5c3a45891b 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -794,6 +794,7 @@ gcc: clock-controller@100000 {
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;
> +			power-domains = <&rpmhpd SM6350_CX>;

[Severity: Low]
Will adding this property without updating the device tree binding schema
trigger a dtbs_check warning?

The schema in Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
uses unevaluatedProperties: false but lacks the definition for power-domains,
which typically causes dtbs_check to flag newly added properties as an error.

>  			clock-names = "bi_tcxo",
>  				      "bi_tcxo_ao",
>  				      "sleep_clk";

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com?part=39

[PATCH v3 40/47] arm64: dts: qcom: sm8150: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8150 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 94a3b02cb289..397c0142ea57 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -913,6 +913,7 @@ gcc: clock-controller@100000 {
 				      "sleep_clk";
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&sleep_clk>;
+			power-domains = <&rpmhpd SM8150_CX>;
 		};
 
 		gpi_dma0: dma-controller@800000 {

-- 
2.54.0

[PATCH v3 41/47] arm64: dts: qcom: sm8250: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8250 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 90f8b091634e..50790cf1c3ca 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -971,6 +971,7 @@ gcc: clock-controller@100000 {
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK_A>,
 				 <&sleep_clk>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

[PATCH v3 42/47] arm64: dts: qcom: sm8350: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8350 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 32b47f5ec1f6..84012a407c4b 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -699,6 +699,7 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 2>,
 				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 				 <0>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

[PATCH v3 43/47] arm64: dts: qcom: sm8450: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8450 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index b8793482b181..176cced72245 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -942,6 +942,7 @@ gcc: clock-controller@100000 {
 				      "ufs_phy_rx_symbol_1_clk",
 				      "ufs_phy_tx_symbol_0_clk",
 				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		gpi_dma2: dma-controller@800000 {

-- 
2.54.0

[PATCH v3 44/47] arm64: dts: qcom: sm8550: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8550 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 0e701e709235..7137efb45346 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1195,6 +1195,7 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 1>,
 				 <&ufs_mem_phy 2>,
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

[PATCH v3 45/47] arm64: dts: qcom: sm8650: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8650 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index b679fd8afb7d..962797c15abf 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2019,6 +2019,8 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 2>,
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

[PATCH v3 46/47] arm64: dts: qcom: sm8750: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8750 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index dd738d13df8e..cda18d4dc6a1 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -676,6 +676,8 @@ gcc: clock-controller@100000 {
 				 <0>,
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

[PATCH v3 47/47] arm64: dts: qcom: talos: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on QCS615 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/talos.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index eedfdce3c479..06ca54acf565 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -706,6 +706,8 @@ gcc: clock-controller@100000 {
 				      "bi_tcxo_ao",
 				      "sleep_clk";
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

Re: [PATCH v3 00/47] clk: qcom: Tie CX power domains to GCCs

[Vinod Koul]

On 24-08-26, 14:53, Abel Vesa wrote:
> Tie the CX power domain to GCC clock controllers for SDM670, SDM845,
> SM8150, SM8250, SM8350, SM8450, SM8550, SM8650, SM8750, SM6350,
> SM4450, QDU1000, QCS8300, SDX75, SAR2130P, SC7180, SC7280, SA8775P,
> X1E80100, Eliza, Kaanapali, and QCS615.

> 
> ---
> Abel Vesa (47):
>       dt-bindings: clock: qcom: gcc-sdm845: Add CX power domain
...
>       arm64: dts: qcom: kaanapali: Add GCC CX power domain
>       arm64: dts: qcom: monaco: Add GCC CX power domain
>       arm64: dts: qcom: qdu1000: Add GCC CX power domain
>       arm64: dts: qcom: sar2130p: Add GCC CX power domain
>       arm64: dts: qcom: sdm670: Add GCC CX power domain
>       arm64: dts: qcom: sdx75: Add GCC CX power domain
>       arm64: dts: qcom: sm4450: Add GCC CX power domain
>       arm64: dts: qcom: sm6350: Add GCC CX power domain
>       arm64: dts: qcom: sm8150: Add GCC CX power domain
>       arm64: dts: qcom: sm8250: Add GCC CX power domain
>       arm64: dts: qcom: sm8350: Add GCC CX power domain
>       arm64: dts: qcom: sm8450: Add GCC CX power domain
>       arm64: dts: qcom: sm8550: Add GCC CX power domain
>       arm64: dts: qcom: sm8650: Add GCC CX power domain
>       arm64: dts: qcom: sm8750: Add GCC CX power domain
>       arm64: dts: qcom: talos: Add GCC CX power domain

Don't see 845 dts updated?

-- 
~Vinod

Re: [PATCH v3 00/47] clk: qcom: Tie CX power domains to GCCs

[Abel Vesa]

On 26-08-24 21:58:55, Vinod Koul wrote:
> On 24-08-26, 14:53, Abel Vesa wrote:
> > Tie the CX power domain to GCC clock controllers for SDM670, SDM845,
> > SM8150, SM8250, SM8350, SM8450, SM8550, SM8650, SM8750, SM6350,
> > SM4450, QDU1000, QCS8300, SDX75, SAR2130P, SC7180, SC7280, SA8775P,
> > X1E80100, Eliza, Kaanapali, and QCS615.
> 
> > 
> > ---
> > Abel Vesa (47):
> >       dt-bindings: clock: qcom: gcc-sdm845: Add CX power domain
> ...
> >       arm64: dts: qcom: kaanapali: Add GCC CX power domain
> >       arm64: dts: qcom: monaco: Add GCC CX power domain
> >       arm64: dts: qcom: qdu1000: Add GCC CX power domain
> >       arm64: dts: qcom: sar2130p: Add GCC CX power domain
> >       arm64: dts: qcom: sdm670: Add GCC CX power domain
> >       arm64: dts: qcom: sdx75: Add GCC CX power domain
> >       arm64: dts: qcom: sm4450: Add GCC CX power domain
> >       arm64: dts: qcom: sm6350: Add GCC CX power domain
> >       arm64: dts: qcom: sm8150: Add GCC CX power domain
> >       arm64: dts: qcom: sm8250: Add GCC CX power domain
> >       arm64: dts: qcom: sm8350: Add GCC CX power domain
> >       arm64: dts: qcom: sm8450: Add GCC CX power domain
> >       arm64: dts: qcom: sm8550: Add GCC CX power domain
> >       arm64: dts: qcom: sm8650: Add GCC CX power domain
> >       arm64: dts: qcom: sm8750: Add GCC CX power domain
> >       arm64: dts: qcom: talos: Add GCC CX power domain
> 
> Don't see 845 dts updated?

The sdm845 already has the CX attached to GCC, it's just the driver
that needs to change, to enable the runtime PM.

I'll fix the cover letter as well to be consistent.

Thanks for reviewing.

Abel