[PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot

[PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch set introduces boot support for the Altera SoCFPGA Agilex 5
platform in U-Boot. The changes include:
	1. Board-specific configurations and setup required to enable Agilex 5
	   operation in U-Boot.
	2. Integration of cache coherency unit (CCU) initialization routine,
	   including CCU conguration in DT.
	3. Clock, firewall (configured in DT), SMMU, low level initialization
	   specific to Agilex 5.
	4. Integration of memory initialization routine, including DDR setup.

This patch set has been tested on Agilex 5 devkit with QSPI boot (UBI/UBIFS)
and RAM boot (TFTP & ARM DS debugger).

Alif Zakuan Yuslaimi (1):
  configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS

Tien Fong Chee (18):
  arm: socfpga: agilex5: Add new system manager base addresses
  arm: socfpga: Add support for agilex5 clock manager
  linker: Add SPL linker script for SoC64 devices
  arm: socfpga: agilex5: Add low level initialization
  arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device
  arm: dts: agilex5: Add HPS cache coherency unit configuration settings
  arm: dts: agilex5: Add firewall configure settings
  arm: dts: agilex5: Enable XGMAC
  sysreset:  Add reset support to SoCFPGA Agilex5 device
  arm: socfpga: agilex5: Enable cache flush for system memory cache in
    CCU
  arm: socfpga: agilex5: Add SMMU initialization
  arm: socfpga: agilex5: Update CPU info
  arm: socfpga: Export board ID as U-Boot environment variable
  configs: agilex5: Add configuration for malloc pool
  arm: socfpga: smc: Add memory coherency support to mailbox command
  arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA
  configs: socfpga: soc64: agilex5: Enable XGMAC
  arm: socfpga: soc64: Add support for board_boot_order()

Tingting Meng (1):
  ddr: altera: Add DDR driver for Agilex5 series

 MAINTAINERS                                   |   2 +
 arch/arm/Kconfig                              |   1 +
 arch/arm/dts/socfpga_agilex5-u-boot.dtsi      | 660 ++++++++++++++++++
 arch/arm/dts/socfpga_agilex5.dtsi             |   7 +
 .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi |  33 +
 arch/arm/mach-socfpga/Makefile                |   6 +
 arch/arm/mach-socfpga/ccu_ncore3.c            |  64 ++
 arch/arm/mach-socfpga/include/mach/firewall.h |  23 +-
 .../mach-socfpga/include/mach/handoff_soc64.h |   4 +-
 arch/arm/mach-socfpga/include/mach/misc.h     |   1 +
 .../include/mach/reset_manager_soc64.h        |  12 +-
 .../include/mach/system_manager_soc64.h       | 129 ++--
 arch/arm/mach-socfpga/lowlevel_init_agilex5.S |  57 ++
 arch/arm/mach-socfpga/misc.c                  |  24 +-
 arch/arm/mach-socfpga/misc_soc64.c            |  12 +-
 arch/arm/mach-socfpga/smc_api.c               |  13 +-
 arch/arm/mach-socfpga/spl_agilex5.c           |  84 +++
 arch/arm/mach-socfpga/spl_soc64.c             | 120 +++-
 arch/arm/mach-socfpga/u-boot-spl-soc64.lds    |  80 +++
 arch/arm/mach-socfpga/wrap_handoff_soc64.c    |  10 +-
 configs/socfpga_agilex5_defconfig             |   6 +
 drivers/ddr/altera/Makefile                   |   1 +
 drivers/ddr/altera/iossm_mailbox.c            | 613 ++++++++++++++++
 drivers/ddr/altera/iossm_mailbox.h            | 186 +++++
 drivers/ddr/altera/sdram_agilex5.c            | 377 ++++++++++
 drivers/ddr/altera/sdram_soc64.c              |  78 ++-
 drivers/ddr/altera/sdram_soc64.h              |  32 +-
 drivers/sysreset/Kconfig                      |   7 +
 drivers/sysreset/Makefile                     |   1 +
 drivers/sysreset/sysreset_socfpga_agilex5.c   |  47 ++
 include/configs/socfpga_soc64_common.h        |   5 +
 31 files changed, 2605 insertions(+), 90 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/ccu_ncore3.c
 create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S
 create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c
 create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds
 create mode 100644 drivers/ddr/altera/iossm_mailbox.c
 create mode 100644 drivers/ddr/altera/iossm_mailbox.h
 create mode 100644 drivers/ddr/altera/sdram_agilex5.c
 create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c

-- 
2.25.1

[PATCH v1 01/20] arm: socfpga: agilex5: Add new system manager base addresses

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Initial creation of new system manager base addresses for Agilex5.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 .../include/mach/system_manager_soc64.h       | 129 +++++++++++-------
 1 file changed, 83 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index a8009664fee..b1ef4a70641 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2019-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2024 Intel Corporation <www.intel.com>
  */
 
 #ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -11,22 +11,43 @@ void sysmgr_pinmux_init(void);
 void populate_sysmgr_fpgaintf_module(void);
 void populate_sysmgr_pinmux(void);
 
-#define SYSMGR_SOC64_WDDBG			0x08
-#define SYSMGR_SOC64_DMA			0x20
-#define SYSMGR_SOC64_DMA_PERIPH			0x24
-#define SYSMGR_SOC64_SDMMC			0x28
-#define SYSMGR_SOC64_SDMMC_L3MASTER		0x2c
-#define SYSMGR_SOC64_EMAC_GLOBAL		0x40
-#define SYSMGR_SOC64_EMAC0			0x44
-#define SYSMGR_SOC64_EMAC1			0x48
-#define SYSMGR_SOC64_EMAC2			0x4c
-#define SYSMGR_SOC64_EMAC0_ACE			0x50
-#define SYSMGR_SOC64_EMAC1_ACE			0x54
-#define SYSMGR_SOC64_EMAC2_ACE			0x58
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SYSMGR_SOC64_SILICONID_1		0x00
+#define SYSMGR_SOC64_SILICONID_2		0x04
+#define SYSMGR_SOC64_MPU_STATUS			0x10
+#define SYSMGR_SOC64_COMBOPHY_DFISEL		0xfc
+#define SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC	0x1
+#define SYSMGR_SOC64_NANDGRP_L3MASTER		0x34
+#define SYSMGR_SOC64_USB0_L3MASTER		0x38
+#define SYSMGR_SOC64_USB1_L3MASTER		0x3c
+#define SYSMGR_SOC64_DMAC0_L3_MASTER		0x74
+#define SYSMGR_SOC64_ETR_L3_MASTER		0x78
+#define SYSMGR_SOC64_DMAC1_L3_MASTER		0x7C
+#define SYSMGR_SOC64_SEC_CTRL_SLT		0x80
+#define SYSMGR_SOC64_OSC_TRIM			0x84
+#define SYSMGR_SOC64_DMAC0_CTRL_STATUS_REG	0x88
+#define SYSMGR_SOC64_DMAC1_CTRL_STATUS_REG	0x8C
+#define SYSMGR_SOC64_ECC_INTMASK_VALUE		0x90
+#define SYSMGR_SOC64_ECC_INTMASK_SET		0x94
+#define SYSMGR_SOC64_ECC_INTMASK_CLR		0x98
+#define SYSMGR_SOC64_ECC_INTMASK_SERR		0x9C
+#define SYSMGR_SOC64_ECC_INTMASK_DERR		0xA0
+#define SYSMGR_SOC64_MPFE_CONFIG		0x228
+#define SYSMGR_SOC64_BOOT_SCRATCH_POR0		0x258
+#define SYSMGR_SOC64_BOOT_SCRATCH_POR1		0x25C
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK		GENMASK(31, 0)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK	GENMASK(31, 29)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_SHIFT	29
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK	BIT(27)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK	BIT(28)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK	GENMASK(28, 27)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_DBE_MASK	BIT(1)
+#define ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK	BIT(0)
+#define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK	BIT(0)
+#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK	BIT(0)
+#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK	BIT(1)
+#else
 #define SYSMGR_SOC64_NAND_AXUSER		0x5c
-#define SYSMGR_SOC64_FPGAINTF_EN1		0x68
-#define SYSMGR_SOC64_FPGAINTF_EN2		0x6c
-#define SYSMGR_SOC64_FPGAINTF_EN3		0x70
 #define SYSMGR_SOC64_DMA_L3MASTER		0x74
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 #define SYSMGR_SOC64_DDR_MODE			0xb8
@@ -34,39 +55,56 @@ void populate_sysmgr_pinmux(void);
 #define SYSMGR_SOC64_HMC_CLK			0xb4
 #define SYSMGR_SOC64_IO_PA_CTRL			0xb8
 #endif
-#define SYSMGR_SOC64_NOC_TIMEOUT		0xc0
-#define SYSMGR_SOC64_NOC_IDLEREQ_SET		0xc4
-#define SYSMGR_SOC64_NOC_IDLEREQ_CLR		0xc8
-#define SYSMGR_SOC64_NOC_IDLEREQ_VAL		0xcc
-#define SYSMGR_SOC64_NOC_IDLEACK		0xd0
-#define SYSMGR_SOC64_NOC_IDLESTATUS		0xd4
-#define SYSMGR_SOC64_FPGA2SOC_CTRL		0xd8
-#define SYSMGR_SOC64_FPGA_CONFIG		0xdc
 #define SYSMGR_SOC64_IOCSRCLK_GATE		0xe0
 #define SYSMGR_SOC64_GPO			0xe4
 #define SYSMGR_SOC64_GPI			0xe8
 #define SYSMGR_SOC64_MPU			0xf0
-/*
- * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit
- * storing qspi ref clock (kHz)
- */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0		0x200
-/* store osc1 clock freq */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1		0x204
-/* store fpga clock freq */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2		0x208
-/* reserved for customer use */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3		0x20c
-/* store PSCI_CPU_ON value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4		0x210
-/* store PSCI_CPU_ON value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5		0x214
-/* store VBAR_EL3 value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6		0x218
-/* store VBAR_EL3 value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7		0x21c
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8		0x220
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9		0x224
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK	GENMASK(27, 0)
+#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/
+
+#define SYSMGR_SOC64_DMA			0x20
+#define SYSMGR_SOC64_DMA_PERIPH			0x24
+#define SYSMGR_SOC64_WDDBG			0x08
+#define SYSMGR_SOC64_SDMMC			0x28
+#define SYSMGR_SOC64_SDMMC_L3MASTER		0x2C
+#define SYSMGR_SOC64_FPGAINTF_EN1		0x68
+#define SYSMGR_SOC64_FPGAINTF_EN2		0x6C
+#define SYSMGR_SOC64_FPGAINTF_EN3		0x70
+#define SYSMGR_SOC64_NOC_TIMEOUT		0xC0
+#define SYSMGR_SOC64_NOC_IDLEREQ_SET		0xC4
+#define SYSMGR_SOC64_NOC_IDLEREQ_CLR		0xC8
+#define SYSMGR_SOC64_NOC_IDLEREQ_VAL		0xCC
+#define SYSMGR_SOC64_NOC_IDLEACK		0xd0
+#define SYSMGR_SOC64_NOC_IDLESTATUS		0xD4
+#define SYSMGR_SOC64_FPGA2SOC_CTRL		0xD8
+#define SYSMGR_SOC64_FPGA_CONFIG		0xDC
+
+#define SYSMGR_SOC64_TSN_GLOBAL			0x40
+#define SYSMGR_SOC64_TSN_0			0x44
+#define SYSMGR_SOC64_TSN_1			0x48
+#define SYSMGR_SOC64_TSN_2			0x4C
+#define SYSMGR_SOC64_TSN_0_ACE			0x50
+#define SYSMGR_SOC64_TSN_1_ACE			0x54
+#define SYSMGR_SOC64_TSN_2_ACE			0x58
+#define SYSMGR_SOC64_EMAC_GLOBAL	SYSMGR_SOC64_TSN_GLOBAL
+#define SYSMGR_SOC64_EMAC0		SYSMGR_SOC64_TSN_0
+#define SYSMGR_SOC64_EMAC1		SYSMGR_SOC64_TSN_1
+#define SYSMGR_SOC64_EMAC2		SYSMGR_SOC64_TSN_2
+#define SYSMGR_SOC64_EMAC0_ACE		SYSMGR_SOC64_TSN_0_ACE
+#define SYSMGR_SOC64_EMAC1_ACE		SYSMGR_SOC64_TSN_1_ACE
+#define SYSMGR_SOC64_EMAC2_ACE		SYSMGR_SOC64_TSN_2_ACE
+
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0	0x200
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1	0x204
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2	0x208
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3	0x20C
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4	0x210
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5	0x214
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6	0x218
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7	0x21C
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8	0x220
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9	0x224
+
 #define SYSMGR_SOC64_PINSEL0			0x1000
 #define SYSMGR_SOC64_IOCTRL0			0x1130
 #define SYSMGR_SOC64_EMAC0_USEFPGA		0x1300
@@ -97,7 +135,6 @@ void populate_sysmgr_pinmux(void);
  * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit
  * storing qspi ref clock (kHz)
  */
-#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK		GENMASK(27, 0)
 #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK	BIT(31)
 #define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK		BIT(30)
 #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK	(BIT(29) | BIT(28))
-- 
2.25.1

Re: [PATCH v1 01/20] arm: socfpga: agilex5: Add new system manager base addresses

[Marek Vasut]

On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Initial creation of new system manager base addresses for Agilex5.
How much of this can be converted to DT probing ?

RE: [PATCH v1 01/20] arm: socfpga: agilex5: Add new system manager base addresses

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, September 21, 2024 9:47 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 01/20] arm: socfpga: agilex5: Add new system
> manager base addresses
> 
> On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Initial creation of new system manager base addresses for Agilex5.
> How much of this can be converted to DT probing ?

Yes, we have dedicated resource is working to convert this to DT in conjunction with syscon support to provide
System-wide configuration.

I can pull in this for Agilex5 first if you want to see it here or separate submission on the changes since it impacts all devices, more tests
are needed to cover all devices.

Let me know your preference.

Thanks.

Regards,
Tien Fong.

Re: [PATCH v1 01/20] arm: socfpga: agilex5: Add new system manager base addresses

[Marek Vasut]

On 9/24/24 6:45 AM, Chee, Tien Fong wrote:

Hi,

>>> Initial creation of new system manager base addresses for Agilex5.
>> How much of this can be converted to DT probing ?
> 
> Yes, we have dedicated resource is working to convert this to DT in conjunction with syscon support to provide
> System-wide configuration.
> 
> I can pull in this for Agilex5 first if you want to see it here or separate submission on the changes since it impacts all devices, more tests
> are needed to cover all devices.
> 
> Let me know your preference.
Either option is fine as long as this is moving toward DT probing, thanks .

[PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock manager

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Adding mechanism to retrieve base address for Agilex5 Clock Mananger.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/misc.c | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 495ba2a0d41..6cf2ee60038 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2024 Altera Corporation <www.altera.com>
  */
 
 #include <config.h>
@@ -252,15 +252,19 @@ void socfpga_get_managers_addr(void)
 	if (ret)
 		hang();
 
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
-	ret = socfpga_get_base_addr("intel,agilex-clkmgr",
-				    &socfpga_clkmgr_base);
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
-	ret = socfpga_get_base_addr("intel,n5x-clkmgr",
-				    &socfpga_clkmgr_base);
-#else
-	ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
-#endif
+	if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX))
+		ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+					    &socfpga_clkmgr_base);
+	else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
+		ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+					    &socfpga_clkmgr_base);
+	else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
+		ret = socfpga_get_base_addr("intel,agilex5-clkmgr",
+					    &socfpga_clkmgr_base);
+	else
+		ret = socfpga_get_base_addr("altr,clk-mgr",
+					    &socfpga_clkmgr_base);
+
 	if (ret)
 		hang();
 }
-- 
2.25.1

Re: [PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock manager

[Marek Vasut]

On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Adding mechanism to retrieve base address for Agilex5 Clock Mananger.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Can this be turned into clock driver and probe from DT ?

RE: [PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock manager

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, September 21, 2024 9:48 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock
> manager
> 
> On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Adding mechanism to retrieve base address for Agilex5 Clock Mananger.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Can this be turned into clock driver and probe from DT ?

I will remove this patch, because I just noticed the clk driver for Agilex 5 is already in driver model (DT).

Regards,
Tien Fong.

[PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add a new .data section for preserving the original state of the
.data section of SoC64 SPL. This new .data section is required to
make SPL reentrant after warm reset.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 80 ++++++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds

diff --git a/arch/arm/mach-socfpga/u-boot-spl-soc64.lds b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds
new file mode 100644
index 00000000000..91cf8dd3139
--- /dev/null
+++ b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+	__image_copy_start = ADDR(.text);
+	.text : {
+		. = ALIGN(8);
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	} >.sram
+
+	.rodata : {
+		. = ALIGN(8);
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} >.sram
+
+	.data : {
+		. = ALIGN(8);
+		/* Run time .data section starting at this location */
+		__data_start = .;
+		*(.data*)
+		/* Run time .data section ending at this location */
+		__data_end = .;
+	} >.sram
+
+	. = ALIGN(8);
+	/* Preserve original .data section starting at this location */
+	__preserve_data_start = .;
+	. = __preserve_data_start + (__data_end - __data_start);
+	/* Preserve original .data section ending at this location */
+	__preserve_data_end = .;
+
+	. = ALIGN(8);
+	__u_boot_list . : {
+		KEEP(*(SORT(__u_boot_list*)));
+	} >.sram
+
+	. = ALIGN(8);
+	__image_copy_end = .;
+
+	_end = .;
+
+	_image_binary_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(8);
+		__bss_end = .;
+	} >.sdram
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
-- 
2.25.1

Re: [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices

[Marek Vasut]

On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Add a new .data section for preserving the original state of the
> .data section of SoC64 SPL. This new .data section is required to
> make SPL reentrant after warm reset.
Where is the linker script copied from ? What is the original file name 
and path ?

RE: [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, September 21, 2024 9:49 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices
> 
> On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Add a new .data section for preserving the original state of the .data
> > section of SoC64 SPL. This new .data section is required to make SPL
> > reentrant after warm reset.
> Where is the linker script copied from ? What is the original file name and
> path ?

I think the script is copied from arch/arm/cpu/armv8/u-boot-spl.lds .

Regards,
Tien Fong.

Re: [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices

[Marek Vasut]

On 9/24/24 7:48 AM, Chee, Tien Fong wrote:

Hi,

>>> Add a new .data section for preserving the original state of the .data
>>> section of SoC64 SPL. This new .data section is required to make SPL
>>> reentrant after warm reset.
>> Where is the linker script copied from ? What is the original file name and
>> path ?
> 
> I think the script is copied from arch/arm/cpu/armv8/u-boot-spl.lds .
Can arch/arm/cpu/armv8/u-boot-spl.lds be extended somehow instead , or 
are there too many differences ?

RE: [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Wednesday, September 25, 2024 2:36 AM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices
> 
> On 9/24/24 7:48 AM, Chee, Tien Fong wrote:
> 
> Hi,
> 
> >>> Add a new .data section for preserving the original state of the
> >>> .data section of SoC64 SPL. This new .data section is required to
> >>> make SPL reentrant after warm reset.
> >> Where is the linker script copied from ? What is the original file
> >> name and path ?
> >
> > I think the script is copied from arch/arm/cpu/armv8/u-boot-spl.lds .
> Can arch/arm/cpu/armv8/u-boot-spl.lds be extended somehow instead , or
> are there too many differences ?

We think can use arch/arm/cpu/armv8/u-boot-spl.lds, because we just noticed the CONFIG_SPL_RECOVER_DATA_SECTION was added into lds and this should be the same design with current patch.

Thanks.

Best regards,
Tien Fong

Re: [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices

[Marek Vasut]

On 9/25/24 8:06 AM, Chee, Tien Fong wrote:

Hi,

>>>>> Add a new .data section for preserving the original state of the
>>>>> .data section of SoC64 SPL. This new .data section is required to
>>>>> make SPL reentrant after warm reset.
>>>> Where is the linker script copied from ? What is the original file
>>>> name and path ?
>>>
>>> I think the script is copied from arch/arm/cpu/armv8/u-boot-spl.lds .
>> Can arch/arm/cpu/armv8/u-boot-spl.lds be extended somehow instead , or
>> are there too many differences ?
> 
> We think can use arch/arm/cpu/armv8/u-boot-spl.lds, because we just noticed the CONFIG_SPL_RECOVER_DATA_SECTION was added into lds and this should be the same design with current patch.
Excellent !

[PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Create new low level initialization for Agile5 due to the new ARM core
composition and warm reset behavior.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/Makefile                |  1 +
 .../include/mach/reset_manager_soc64.h        | 12 +++-
 arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 57 +++++++++++++++++++
 3 files changed, 68 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 67c6a8dfec5..53c91d1d2a5 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -58,6 +58,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
 obj-y	+= clock_manager_agilex5.o
+obj-y	+= lowlevel_init_agilex5.o
 obj-y	+= mailbox_s10.o
 obj-y	+= misc_soc64.o
 obj-y	+= mmu-arm64_s10.o
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index c8bb727aa2b..d373ec0dc70 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -1,15 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- *  Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *  Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
  */
 
 #ifndef _RESET_MANAGER_SOC64_H_
 #define _RESET_MANAGER_SOC64_H_
 
+#ifndef __ASSEMBLY__
 void reset_deassert_peripherals_handoff(void);
 int cpu_has_been_warmreset(void);
 void print_reset_info(void);
 void socfpga_bridges_reset(int enable);
+#endif
 
 #define RSTMGR_SOC64_STATUS	0x00
 #define RSTMGR_SOC64_MPUMODRST	0x20
@@ -23,14 +25,20 @@ void socfpga_bridges_reset(int enable);
 #define RSTMGR_BRGMODRST_FPGA2SOC_MASK	0x00000004
 
 /* SDM, Watchdogs and MPU warm reset mask */
-#define RSTMGR_STAT_SDMWARMRST		BIT(1)
+#define RSTMGR_STAT_SDMWARMRST		0x2
 #define RSTMGR_STAT_MPU0RST_BITPOS	8
 #define RSTMGR_STAT_L4WD0RST_BITPOS	16
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define RSTMGR_STAT_L4WD0RST_BIT	0x1F0000
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK	(RSTMGR_STAT_SDMWARMRST | \
+		RSTMGR_STAT_L4WD0RST_BIT)
+#else
 #define RSTMGR_L4WD_MPU_WARMRESET_MASK	(RSTMGR_STAT_SDMWARMRST | \
 		GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \
 			RSTMGR_STAT_MPU0RST_BITPOS) | \
 		GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \
 			RSTMGR_STAT_L4WD0RST_BITPOS))
+#endif
 
 /*
  * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/lowlevel_init_agilex5.S b/arch/arm/mach-socfpga/lowlevel_init_agilex5.S
new file mode 100644
index 00000000000..27430577719
--- /dev/null
+++ b/arch/arm/mach-socfpga/lowlevel_init_agilex5.S
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Intel Corporation. All rights reserved
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arch/reset_manager_soc64.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	mov	x29, lr			/* Save LR */
+
+	/* Enable Async */
+	msr daifclr, #4
+
+#ifdef CONFIG_SPL_BUILD
+	branch_if_slave x0, 3f
+
+	/* Check rstmgr.stat for warm reset status */
+	ldr	w1, =SOCFPGA_RSTMGR_ADDRESS
+	ldr	w0, [x1]
+	/* Check whether any L4 watchdogs or SDM had triggered warm reset */
+	ldr	x2, =RSTMGR_L4WD_MPU_WARMRESET_MASK
+	ands	x0, x0, x2
+	/*
+	 * If current Reset Manager's status is warm reset just reload the
+	 * .data section by copying the data from data preserve section.
+	 * Otherwise, copy the .data section to the data preserve section to
+	 * keep an original copy of .data section. This ensure SPL is
+	 * reentrant after warm reset.
+	 */
+	b.ne	reload_data_section
+	/* Copy from .data to preserved .data to backup the SPL state */
+	ldr	x0, =__data_start
+	ldr	x1, =__preserve_data_start
+	ldr	x2, =__preserve_data_end
+	b	copy_loop
+reload_data_section:
+	/* Copy from preserved .data to .data to restore the SPL state */
+	ldr	x0, =__preserve_data_start
+	ldr	x1, =__data_start
+	ldr	x2, =__data_end
+copy_loop:
+	ldr	w3, [x0]
+	add	x0, x0, #4
+	str	w3, [x1]
+	add	x1, x1, #4
+	cmp	x1, x2
+	b.ne	copy_loop
+3:
+#endif
+
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(lowlevel_init)
-- 
2.25.1

Re: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization

[Marek Vasut]

On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Create new low level initialization for Agile5 due to the new ARM core
> composition and warm reset behavior.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>   arch/arm/mach-socfpga/Makefile                |  1 +
>   .../include/mach/reset_manager_soc64.h        | 12 +++-
>   arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 57 +++++++++++++++++++
>   3 files changed, 68 insertions(+), 2 deletions(-)
>   create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 67c6a8dfec5..53c91d1d2a5 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -58,6 +58,7 @@ endif
>   
>   ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
>   obj-y	+= clock_manager_agilex5.o
> +obj-y	+= lowlevel_init_agilex5.o
>   obj-y	+= mailbox_s10.o
>   obj-y	+= misc_soc64.o
>   obj-y	+= mmu-arm64_s10.o
Can this be wired into existing early hook function, like s_init or so ?

RE: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, September 21, 2024 9:49 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level
> initialization
> 
> On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Create new low level initialization for Agile5 due to the new ARM core
> > composition and warm reset behavior.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >   arch/arm/mach-socfpga/Makefile                |  1 +
> >   .../include/mach/reset_manager_soc64.h        | 12 +++-
> >   arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 57
> +++++++++++++++++++
> >   3 files changed, 68 insertions(+), 2 deletions(-)
> >   create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S
> >
> > diff --git a/arch/arm/mach-socfpga/Makefile
> > b/arch/arm/mach-socfpga/Makefile index 67c6a8dfec5..53c91d1d2a5
> 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -58,6 +58,7 @@ endif
> >
> >   ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
> >   obj-y	+= clock_manager_agilex5.o
> > +obj-y	+= lowlevel_init_agilex5.o
> >   obj-y	+= mailbox_s10.o
> >   obj-y	+= misc_soc64.o
> >   obj-y	+= mmu-arm64_s10.o
> Can this be wired into existing early hook function, like s_init or so ?

I cannot find the caller for s_init, wonder where is the s_init is called?
What's concern with lowlevel_init()? It's also wired into existing early hook function which's located inside start.S

Regards,
Tien Fong.

Re: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization

[Marek Vasut]

On 9/24/24 5:14 AM, Chee, Tien Fong wrote:

Hi,

>>> diff --git a/arch/arm/mach-socfpga/Makefile
>>> b/arch/arm/mach-socfpga/Makefile index 67c6a8dfec5..53c91d1d2a5
>> 100644
>>> --- a/arch/arm/mach-socfpga/Makefile
>>> +++ b/arch/arm/mach-socfpga/Makefile
>>> @@ -58,6 +58,7 @@ endif
>>>
>>>    ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
>>>    obj-y	+= clock_manager_agilex5.o
>>> +obj-y	+= lowlevel_init_agilex5.o
>>>    obj-y	+= mailbox_s10.o
>>>    obj-y	+= misc_soc64.o
>>>    obj-y	+= mmu-arm64_s10.o
>> Can this be wired into existing early hook function, like s_init or so ?
> 
> I cannot find the caller for s_init, wonder where is the s_init is called?

arch/arm/cpu/armv7/lowlevel_init.S:.pushsection .text.s_init, "ax"
arch/arm/cpu/armv7/lowlevel_init.S:WEAK(s_init)
arch/arm/cpu/armv7/lowlevel_init.S:ENDPROC(s_init)
arch/arm/cpu/armv7/lowlevel_init.S:     bl      s_init

Maybe such a default lowlevel_init for armv8 could also have an s_init ?

> What's concern with lowlevel_init()? It's also wired into existing early hook function which's located inside start.S
I would like to avoid duplicating lowlevel_init functionality as much as 
possible , common lowlevel_init would be very welcome .

RE: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Wednesday, September 25, 2024 2:32 AM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level
> initialization
> 
> On 9/24/24 5:14 AM, Chee, Tien Fong wrote:
> 
> Hi,
> 
> >>> diff --git a/arch/arm/mach-socfpga/Makefile
> >>> b/arch/arm/mach-socfpga/Makefile index 67c6a8dfec5..53c91d1d2a5
> >> 100644
> >>> --- a/arch/arm/mach-socfpga/Makefile
> >>> +++ b/arch/arm/mach-socfpga/Makefile
> >>> @@ -58,6 +58,7 @@ endif
> >>>
> >>>    ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
> >>>    obj-y	+= clock_manager_agilex5.o
> >>> +obj-y	+= lowlevel_init_agilex5.o
> >>>    obj-y	+= mailbox_s10.o
> >>>    obj-y	+= misc_soc64.o
> >>>    obj-y	+= mmu-arm64_s10.o
> >> Can this be wired into existing early hook function, like s_init or so ?
> >
> > I cannot find the caller for s_init, wonder where is the s_init is called?
> 
> arch/arm/cpu/armv7/lowlevel_init.S:.pushsection .text.s_init, "ax"
> arch/arm/cpu/armv7/lowlevel_init.S:WEAK(s_init)
> arch/arm/cpu/armv7/lowlevel_init.S:ENDPROC(s_init)
> arch/arm/cpu/armv7/lowlevel_init.S:     bl      s_init
> 
> Maybe such a default lowlevel_init for armv8 could also have an s_init ?
> 
> > What's concern with lowlevel_init()? It's also wired into existing
> > early hook function which's located inside start.S
> I would like to avoid duplicating lowlevel_init functionality as much as
> possible , common lowlevel_init would be very welcome .

Sure, I can add the s_init to common lowlevel_init and moving the codes to s_init.

Thanks.

Regards,
Tien Fong

Re: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization

[Marek Vasut]

On 9/25/24 7:40 AM, Chee, Tien Fong wrote:

Hi,

>> arch/arm/cpu/armv7/lowlevel_init.S:.pushsection .text.s_init, "ax"
>> arch/arm/cpu/armv7/lowlevel_init.S:WEAK(s_init)
>> arch/arm/cpu/armv7/lowlevel_init.S:ENDPROC(s_init)
>> arch/arm/cpu/armv7/lowlevel_init.S:     bl      s_init
>>
>> Maybe such a default lowlevel_init for armv8 could also have an s_init ?
>>
>>> What's concern with lowlevel_init()? It's also wired into existing
>>> early hook function which's located inside start.S
>> I would like to avoid duplicating lowlevel_init functionality as much as
>> possible , common lowlevel_init would be very welcome .
> 
> Sure, I can add the s_init to common lowlevel_init and moving the codes to s_init.
Thanks. Then the question is, how much of this stuff can be removed 
because it is part of generic lowlevel_init, I hope a lot.

RE: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization

[Chee, Tien Fong]

Hi,

> >> arch/arm/cpu/armv7/lowlevel_init.S:.pushsection .text.s_init, "ax"
> >> arch/arm/cpu/armv7/lowlevel_init.S:WEAK(s_init)
> >> arch/arm/cpu/armv7/lowlevel_init.S:ENDPROC(s_init)
> >> arch/arm/cpu/armv7/lowlevel_init.S:     bl      s_init
> >>
> >> Maybe such a default lowlevel_init for armv8 could also have an s_init ?
> >>
> >>> What's concern with lowlevel_init()? It's also wired into existing
> >>> early hook function which's located inside start.S
> >> I would like to avoid duplicating lowlevel_init functionality as much
> >> as possible , common lowlevel_init would be very welcome .
> >
> > Sure, I can add the s_init to common lowlevel_init and moving the codes to
> s_init.
> Thanks. Then the question is, how much of this stuff can be removed
> because it is part of generic lowlevel_init, I hope a lot.

I'm not sure I completely understand your question, but I can share what we're going to do.
Declaring a weak s_init function at lowlevel_init.S

.pushsection .text.s_init, "ax"
WEAK(s_init)
	bx	lr
ENDPROC(s_init)
.popsection

Calling s_init before lowlevel_init returned to parent call
              [...]
	bl s_init
	move lr, x29
              ret

We will move the codes to s_init which is declared in our platform driver, arch/arm/mach-socfpga .

The codes is needed to backup the data section as earlier as possible to support
warm reset / watchdog due to warm reset use case, where reloading SPL would be skipped after reset.

Thanks.

Regards,
Tien Fong

Re: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization

[Marek Vasut]

On 9/26/24 8:02 AM, Chee, Tien Fong wrote:
> Hi,

Hi,

>>>> arch/arm/cpu/armv7/lowlevel_init.S:.pushsection .text.s_init, "ax"
>>>> arch/arm/cpu/armv7/lowlevel_init.S:WEAK(s_init)
>>>> arch/arm/cpu/armv7/lowlevel_init.S:ENDPROC(s_init)
>>>> arch/arm/cpu/armv7/lowlevel_init.S:     bl      s_init
>>>>
>>>> Maybe such a default lowlevel_init for armv8 could also have an s_init ?
>>>>
>>>>> What's concern with lowlevel_init()? It's also wired into existing
>>>>> early hook function which's located inside start.S
>>>> I would like to avoid duplicating lowlevel_init functionality as much
>>>> as possible , common lowlevel_init would be very welcome .
>>>
>>> Sure, I can add the s_init to common lowlevel_init and moving the codes to
>> s_init.
>> Thanks. Then the question is, how much of this stuff can be removed
>> because it is part of generic lowlevel_init, I hope a lot.
> 
> I'm not sure I completely understand your question, but I can share what we're going to do.

I am wondering if some of the code here can be deduplicated by using the 
generic lowlevel_init.S , i.e. if some of the code in lowlevel_init.S is 
duplicate of the code in this custom lowlevel_init.S implementation.

> Declaring a weak s_init function at lowlevel_init.S
> 
> .pushsection .text.s_init, "ax"
> WEAK(s_init)
> 	bx	lr
> ENDPROC(s_init)
> .popsection
> 
> Calling s_init before lowlevel_init returned to parent call
>                [...]
> 	bl s_init
> 	move lr, x29
>                ret
> 
> We will move the codes to s_init which is declared in our platform driver, arch/arm/mach-socfpga .
> 
> The codes is needed to backup the data section as earlier as possible to support
> warm reset / watchdog due to warm reset use case, where reloading SPL would be skipped after reset.
If you need to run code very early and back up critical data, look at 
save_boot_params .

RE: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization

[Chee, Tien Fong]

Hi,
 
> >>>> arch/arm/cpu/armv7/lowlevel_init.S:.pushsection .text.s_init, "ax"
> >>>> arch/arm/cpu/armv7/lowlevel_init.S:WEAK(s_init)
> >>>> arch/arm/cpu/armv7/lowlevel_init.S:ENDPROC(s_init)
> >>>> arch/arm/cpu/armv7/lowlevel_init.S:     bl      s_init
> >>>>
> >>>> Maybe such a default lowlevel_init for armv8 could also have an s_init ?
> >>>>
> >>>>> What's concern with lowlevel_init()? It's also wired into existing
> >>>>> early hook function which's located inside start.S
> >>>> I would like to avoid duplicating lowlevel_init functionality as
> >>>> much as possible , common lowlevel_init would be very welcome .
> >>>
> >>> Sure, I can add the s_init to common lowlevel_init and moving the
> >>> codes to
> >> s_init.
> >> Thanks. Then the question is, how much of this stuff can be removed
> >> because it is part of generic lowlevel_init, I hope a lot.
> >
> > I'm not sure I completely understand your question, but I can share what
> we're going to do.
> 
> I am wondering if some of the code here can be deduplicated by using the
> generic lowlevel_init.S , i.e. if some of the code in lowlevel_init.S is duplicate
> of the code in this custom lowlevel_init.S implementation.

No duplicate codes in both common lowlevel_init.S and custom lowlevel_init.S.

> 
> > Declaring a weak s_init function at lowlevel_init.S
> >
> > .pushsection .text.s_init, "ax"
> > WEAK(s_init)
> > 	bx	lr
> > ENDPROC(s_init)
> > .popsection
> >
> > Calling s_init before lowlevel_init returned to parent call
> >                [...]
> > 	bl s_init
> > 	move lr, x29
> >                ret
> >
> > We will move the codes to s_init which is declared in our platform driver,
> arch/arm/mach-socfpga .
> >
> > The codes is needed to backup the data section as earlier as possible
> > to support warm reset / watchdog due to warm reset use case, where
> reloading SPL would be skipped after reset.
> If you need to run code very early and back up critical data, look at
> save_boot_params .

Thanks for suggesting this, we will try this out.

Regards,
Tien Fong

[PATCH v1 05/20] arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Agilex5 supports both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and Agilex5 device.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/Makefile                     |  1 +
 arch/arm/mach-socfpga/include/mach/handoff_soc64.h |  4 ++--
 arch/arm/mach-socfpga/wrap_handoff_soc64.c         | 10 ++++++++--
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 53c91d1d2a5..e0ada69dd5a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -63,6 +63,7 @@ obj-y	+= mailbox_s10.o
 obj-y	+= misc_soc64.o
 obj-y	+= mmu-arm64_s10.o
 obj-y	+= reset_manager_s10.o
+obj-y	+= wrap_handoff_soc64.o
 obj-y	+= wrap_pll_config_soc64.o
 endif
 
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index d839f288411..918d25a1b61 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -17,9 +17,9 @@
 #define SOC64_HANDOFF_MAGIC_FPGA	0x46504741
 #define SOC64_HANDOFF_MAGIC_DELAY	0x444C4159
 #define SOC64_HANDOFF_MAGIC_CLOCK	0x434C4B53
+#define SOC64_HANDOFF_MAGIC_SDRAM	0x5344524d
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_MAGIC_PERI	0x50455249
-#define SOC64_HANDOFF_MAGIC_SDRAM	0x5344524d
 #else
 #define SOC64_HANDOFF_MAGIC_MISC	0x4D495343
 #endif
@@ -68,7 +68,7 @@
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_PERI		(SOC64_HANDOFF_BASE + 0x620)
 #define SOC64_HANDOFF_SDRAM		(SOC64_HANDOFF_BASE + 0x634)
-#define SOC64_HANDOFF_SDRAM_LEN		1
+#define SOC64_HANDOFF_SDRAM_LEN		5
 #endif
 
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index 92051d19b73..c8456c8dd6a 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -1,15 +1,16 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2024 Intel Corporation <www.intel.com>
  *
  */
 
+#include <errno.h>
 #include <asm/arch/handoff_soc64.h>
 #include <asm/io.h>
-#include <errno.h>
 #include "log.h"
 
 #ifndef __ASSEMBLY__
+#include <asm/types.h>
 enum endianness {
 	LITTLE_ENDIAN = 0,
 	BIG_ENDIAN,
@@ -26,7 +27,12 @@ static enum endianness check_endianness(u32 handoff)
 	case SOC64_HANDOFF_MAGIC_FPGA:
 	case SOC64_HANDOFF_MAGIC_DELAY:
 	case SOC64_HANDOFF_MAGIC_CLOCK:
+	case SOC64_HANDOFF_MAGIC_SDRAM:
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+	case SOC64_HANDOFF_MAGIC_PERI:
+#else
 	case SOC64_HANDOFF_MAGIC_MISC:
+#endif
 		return BIG_ENDIAN;
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 	case SOC64_HANDOFF_DDR_UMCTL2_MAGIC:
-- 
2.25.1

[PATCH v1 06/20] arm: dts: agilex5: Add HPS cache coherency unit configuration settings

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

These configuration settings are required to enable cache maintenance and
access between initiators and targets.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 209 +++++++++++++++++++++++
 1 file changed, 209 insertions(+)

diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index a8167e5c14a..ec42fd01a9c 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -13,6 +13,215 @@
 		#size-cells = <2>;
 		bootph-all;
 	};
+
+	soc {
+		bootph-all;
+
+		socfpga_ccu_config: socfpga-ccu-config {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* DSU */
+			i_ccu_caiu0@1c000000 {
+				reg = <0x1c000000 0x00001000>;
+				intel,offset-settings =
+					/* CAIUMIFSR */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DII1_MPFEREGS */
+					<0x00000414 0x00018000 0xffffffff>,
+					<0x00000418 0x00000000 0x000000ff>,
+					<0x00000410 0xc0e00200 0xc1f03e1f>,
+					/* DII2_GICREGS */
+					<0x00000424 0x0001d000 0xffffffff>,
+					<0x00000428 0x00000000 0x000000ff>,
+					<0x00000420 0xc0800400 0xc1f03e1f>,
+					/* NCAIU0_LWSOC2FPGA */
+					<0x00000444 0x00020000 0xffffffff>,
+					<0x00000448 0x00000000 0x000000ff>,
+					<0x00000440 0xc1100006 0xc1f03e1f>,
+					/* NCAIU0_SOC2FPGA_1G */
+					<0x00000454 0x00040000 0xffffffff>,
+					<0x00000458 0x00000000 0x000000ff>,
+					<0x00000450 0xc1200006 0xc1f03e1f>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* NCAIU0_SOC2FPGA_16G */
+					<0x00000474 0x00400000 0xffffffff>,
+					<0x00000478 0x00000000 0x000000ff>,
+					<0x00000470 0xc1600006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* NCAIU0_SOC2FPGA_256G */
+					<0x00000494 0x04000000 0xffffffff>,
+					<0x00000498 0x00000000 0x000000ff>,
+					<0x00000490 0xc1a00006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* FPGA2SOC */
+			i_ccu_ncaiu0@1c001000 {
+				reg = <0x1c001000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU0MIFSR */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* PSS */
+					<0x00000404 0x00010000 0xffffffff>,
+					<0x00000408 0x00000000 0x000000ff>,
+					<0x00000400 0xC0F00000 0xc1f03e1f>,
+					/* DII1_MPFEREGS */
+					<0x00000414 0x00018000 0xffffffff>,
+					<0x00000418 0x00000000 0x000000ff>,
+					<0x00000410 0xc0e00200 0xc1f03e1f>,
+					/* NCAIU0_LWSOC2FPGA */
+					<0x00000444 0x00020000 0xffffffff>,
+					<0x00000448 0x00000000 0x000000ff>,
+					<0x00000440 0xc1100006 0xc1f03e1f>,
+					/* NCAIU0_SOC2FPGA_1G */
+					<0x00000454 0x00040000 0xffffffff>,
+					<0x00000458 0x00000000 0x000000ff>,
+					<0x00000450 0xc1200006 0xc1f03e1f>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* NCAIU0_SOC2FPGA_16G */
+					<0x00000474 0x00400000 0xffffffff>,
+					<0x00000478 0x00000000 0x000000ff>,
+					<0x00000470 0xc1600006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* NCAIU0_SOC2FPGA_256G */
+					<0x00000494 0x04000000 0xffffffff>,
+					<0x00000498 0x00000000 0x000000ff>,
+					<0x00000490 0xc1a00006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* GIC_M */
+			i_ccu_ncaiu1@1c002000 {
+				reg = <0x1c002000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU1MIFSR */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* SMMU */
+			i_ccu_ncaiu2@1c003000 {
+				reg = <0x1c003000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU2MIFSR */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* PSS NOC */
+			i_ccu_ncaiu3@1c004000 {
+				reg = <0x1c004000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU3MIFSR */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DII1_MPFEREGS */
+					<0x00000414 0x00018000 0xffffffff>,
+					<0x00000418 0x00000000 0x000000ff>,
+					<0x00000410 0xc0e00200 0xc1f03e1f>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* DCE0 */
+			i_ccu_dce0@1c005000 {
+				reg = <0x1c005000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUMIFSR0 */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* DCE1 */
+			i_ccu_dce1@1c006000 {
+				reg = <0x1c006000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUMIFSR1 */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* DMI0 */
+			i_ccu_dmi0@1c007000 {
+				reg = <0x1c007000 0x00001000>;
+				intel,offset-settings =
+					/* DMIUSMCTCR */
+					<0x00000300 0x00000001 0x00000003>,
+					<0x00000300 0x00000003 0x00000003>;
+				bootph-all;
+			};
+
+			/* DMI1 */
+			i_ccu_dmi0@1c008000 {
+				reg = <0x1c008000 0x00001000>;
+				intel,offset-settings =
+					/* DMIUSMCTCR */
+					<0x00000300 0x00000001 0x00000003>,
+					<0x00000300 0x00000003 0x00000003>;
+				bootph-all;
+			};
+		};
+	};
 };
 
 &clkmgr {
-- 
2.25.1

[PATCH v1 07/20] arm: dts: agilex5: Add firewall configure settings

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

These firewall configure settings are needed to disable firewall on
respective hardware component so both secure and non-secure transactions
are allowed.


Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 166 +++++++++++++++++++++++
 1 file changed, 166 insertions(+)

diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index ec42fd01a9c..bf30b3b8858 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -221,6 +221,172 @@
 				bootph-all;
 			};
 		};
+
+		socfpga_firewall_config: socfpga-firewall-config {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* L4 peripherals firewall */
+			noc_fw_l4_per@10d21000 {
+				reg = <0x10d21000 0x0000008c>;
+				intel,offset-settings =
+					/* NAND */
+					<0x00000000 0x01010001 0x01010001>,
+					/* USB0 */
+					<0x0000000c 0x01010001 0x01010001>,
+					/* USB1 */
+					<0x00000010 0x01010001 0x01010001>,
+					/* SPI_MAIN0 */
+					<0x0000001c 0x01010301 0x01010301>,
+					/* SPI_MAIN1 */
+					<0x00000020 0x01010301 0x01010301>,
+					/* SPI_SECONDARY0 */
+					<0x00000024 0x01010301 0x01010301>,
+					/* SPI_SECONDARY1 */
+					<0x00000028 0x01010301 0x01010301>,
+					/* EMAC0 */
+					<0x0000002c 0x01010001 0x01010001>,
+					/* EMAC1 */
+					<0x00000030 0x01010001 0x01010001>,
+					/* EMAC2 */
+					<0x00000034 0x01010001 0x01010001>,
+					/* SDMMC */
+					<0x00000040 0x01010001 0x01010001>,
+					/* GPIO0 */
+					<0x00000044 0x01010301 0x01010301>,
+					/* GPIO1 */
+					<0x00000048 0x01010301 0x01010301>,
+					/* I2C0 */
+					<0x00000050 0x01010301 0x01010301>,
+					/* I2C1 */
+					<0x00000054 0x01010301 0x01010301>,
+					/* I2C2 */
+					<0x00000058 0x01010301 0x01010301>,
+					/* I2C3 */
+					<0x0000005c 0x01010301 0x01010301>,
+					/* I2C4 */
+					<0x00000060 0x01010301 0x01010301>,
+					/* SP_TIMER0 */
+					<0x00000064 0x01010301 0x01010301>,
+					/* SP_TIMER1 */
+					<0x00000068 0x01010301 0x01010301>,
+					/* UART0 */
+					<0x0000006c 0x01010301 0x01010301>,
+					/* UART1 */
+					<0x00000070 0x01010301 0x01010301>,
+					/* I3C0 */
+					<0x00000074 0x01010301 0x01010301>,
+					/* I3C1 */
+					<0x00000078 0x01010301 0x01010301>,
+					/* DMA0 */
+					<0x0000007c 0x01010001 0x01010001>,
+					/* DMA1 */
+					<0x00000080 0x01010001 0x01010001>,
+					/* COMBO_PHY */
+					<0x00000084 0x01010001 0x01010001>,
+					/* NAND_SDMA */
+					<0x00000088 0x01010301 0x01010301>;
+				bootph-all;
+			};
+
+			/* L4 system firewall */
+			noc_fw_l4_sys@10d21100 {
+				reg = <0x10d21100 0x00000098>;
+				intel,offset-settings =
+					/* DMA_ECC */
+					<0x00000008 0x01010001 0x01010001>,
+					/* EMAC0RX_ECC */
+					<0x0000000c 0x01010001 0x01010001>,
+					/* EMAC0TX_ECC */
+					<0x00000010 0x01010001 0x01010001>,
+					/* EMAC1RX_ECC */
+					<0x00000014 0x01010001 0x01010001>,
+					/* EMAC1TX_ECC */
+					<0x00000018 0x01010001 0x01010001>,
+					/* EMAC2RX_ECC */
+					<0x0000001c 0x01010001 0x01010001>,
+					/* EMAC2TX_ECC */
+					<0x00000020 0x01010001 0x01010001>,
+					/* NAND_ECC */
+					<0x0000002c 0x01010001 0x01010001>,
+					/* NAND_READ_ECC */
+					<0x00000030 0x01010001 0x01010001>,
+					/* NAND_WRITE_ECC */
+					<0x00000034 0x01010001 0x01010001>,
+					/* OCRAM_ECC */
+					<0x00000038 0x01010001 0x01010001>,
+					/* SDMMC_ECC */
+					<0x00000040 0x01010001 0x01010001>,
+					/* USB0_ECC */
+					<0x00000044 0x01010001 0x01010001>,
+					/* USB1_CACHEECC */
+					<0x00000048 0x01010001 0x01010001>,
+					/* CLOCK_MANAGER */
+					<0x0000004c 0x01010001 0x01010001>,
+					/* IO_MANAGER */
+					<0x00000054 0x01010001 0x01010001>,
+					/* RESET_MANAGER */
+					<0x00000058 0x01010001 0x01010001>,
+					/* SYSTEM_MANAGER */
+					<0x0000005c 0x01010001 0x01010001>,
+					/* OSC0_TIMER */
+					<0x00000060 0x01010301 0x01010301>,
+					/* OSC1_TIMER0*/
+					<0x00000064 0x01010301 0x01010301>,
+					/* WATCHDOG0 */
+					<0x00000068 0x01010301 0x01010301>,
+					/* WATCHDOG1 */
+					<0x0000006c 0x01010301 0x01010301>,
+					/* WATCHDOG2 */
+					<0x00000070 0x01010301 0x01010301>,
+					/* WATCHDOG3 */
+					<0x00000074 0x01010301 0x01010301>,
+					/* DAP */
+					<0x00000078 0x03010001 0x03010001>,
+					/* WATCHDOG4 */
+					<0x0000007c 0x01010301 0x01010301>,
+					/* POWER_MANAGER */
+					<0x00000080 0x01010001 0x01010001>,
+					/* USB1_RXECC */
+					<0x00000084 0x01010001 0x01010001>,
+					/* USB1_TXECC */
+					<0x00000088 0x01010001 0x01010001>,
+					/* L4_NOC_PROBES */
+					<0x00000090 0x01010001 0x01010001>,
+					/* L4_NOC_QOS */
+					<0x00000094 0x01010001 0x01010001>;
+				bootph-all;
+			};
+
+			/* Light weight SoC2FPGA */
+			noc_fw_lwsoc2fpga@10d21300 {
+				reg = <0x10d21300 0x0000004>;
+				intel,offset-settings =
+					/* LWSOC2FPGA_CSR */
+					<0x00000000 0x0ffe0301 0x0ffe0301>;
+				bootph-all;
+			};
+
+			/* SoC2FPGA */
+			noc_fw_soc2fpga@10d21200 {
+				reg = <0x10d21200 0x0000004>;
+				intel,offset-settings =
+					/* SOC2FPGA_CSR */
+					<0x00000000 0x0ffe0301 0x0ffe0301>;
+				bootph-all;
+			};
+
+			/* TCU */
+			noc_fw_tcu@10d21400 {
+				reg = <0x10d21400 0x0000004>;
+				intel,offset-settings =
+					/* TCU_CSR */
+					<0x00000000 0x01010001 0x01010001>;
+				bootph-all;
+			};
+		};
 	};
 };
 
-- 
2.25.1

[PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enable XGMAC for SoCFPGA Agilex5 devkit.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index 9eb21d65428..75ab05031bc 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -122,3 +122,36 @@
 	bootph-all;
 };
 
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&emac0_phy0>;
+
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwxgmac-mdio";
+		emac0_phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
+&gmac2 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&emac2_phy0>;
+
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwxgmac-mdio";
+		emac2_phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
-- 
2.25.1

Re: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC

[Marek Vasut]

On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Enable XGMAC for SoCFPGA Agilex5 devkit.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>   .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 33 +++++++++++++++++++
>   1 file changed, 33 insertions(+)
> 
> diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> index 9eb21d65428..75ab05031bc 100644
> --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> @@ -122,3 +122,36 @@
>   	bootph-all;
>   };
>   
> +&gmac0 {
> +	status = "okay";
> +	phy-mode = "rgmii";
> +	phy-handle = <&emac0_phy0>;
Shouldn't this be part of Linux DT already ?

RE: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, September 21, 2024 9:51 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC
> 
> On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Enable XGMAC for SoCFPGA Agilex5 devkit.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >   .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 33
> +++++++++++++++++++
> >   1 file changed, 33 insertions(+)
> >
> > diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> > index 9eb21d65428..75ab05031bc 100644
> > --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> > +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> > @@ -122,3 +122,36 @@
> >   	bootph-all;
> >   };
> >
> > +&gmac0 {
> > +	status = "okay";
> > +	phy-mode = "rgmii";
> > +	phy-handle = <&emac0_phy0>;
> Shouldn't this be part of Linux DT already ?

This enablement not yet in Linux DT, I believe our Linux team is still working on it.

Regards,
Tien Fong

Re: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC

[Marek Vasut]

On 9/24/24 8:02 AM, Chee, Tien Fong wrote:
> Hi,

Hi,

>>> diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
>> b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
>>> index 9eb21d65428..75ab05031bc 100644
>>> --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
>>> +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
>>> @@ -122,3 +122,36 @@
>>>    	bootph-all;
>>>    };
>>>
>>> +&gmac0 {
>>> +	status = "okay";
>>> +	phy-mode = "rgmii";
>>> +	phy-handle = <&emac0_phy0>;
>> Shouldn't this be part of Linux DT already ?
> 
> This enablement not yet in Linux DT, I believe our Linux team is still working on it.
Is there at least a patch posted upstream ?

RE: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Wednesday, September 25, 2024 2:36 AM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC
> 
> On 9/24/24 8:02 AM, Chee, Tien Fong wrote:
> > Hi,
> 
> Hi,
> 
> >>> diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> >> b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> >>> index 9eb21d65428..75ab05031bc 100644
> >>> --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> >>> +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> >>> @@ -122,3 +122,36 @@
> >>>    	bootph-all;
> >>>    };
> >>>
> >>> +&gmac0 {
> >>> +	status = "okay";
> >>> +	phy-mode = "rgmii";
> >>> +	phy-handle = <&emac0_phy0>;
> >> Shouldn't this be part of Linux DT already ?
> >
> > This enablement not yet in Linux DT, I believe our Linux team is still working
> on it.
> Is there at least a patch posted upstream ?

Having two patches posted now in Linux mainline, but gmac device is still not yet added into these dt.
https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts

I think we can do a cleanup if the duplicated found in U-Boot later.

Thanks.

Regards,
Tien Fong

Re: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC

[Marek Vasut]

On 9/25/24 8:13 AM, Chee, Tien Fong wrote:
> Hi,
> 
>> -----Original Message-----
>> From: Marek Vasut <marex@denx.de>
>> Sent: Wednesday, September 25, 2024 2:36 AM
>> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
>> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
>> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
>> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
>> <kok.kiang.hea@intel.com>
>> Subject: Re: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC
>>
>> On 9/24/24 8:02 AM, Chee, Tien Fong wrote:
>>> Hi,
>>
>> Hi,
>>
>>>>> diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
>>>> b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
>>>>> index 9eb21d65428..75ab05031bc 100644
>>>>> --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
>>>>> +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
>>>>> @@ -122,3 +122,36 @@
>>>>>     	bootph-all;
>>>>>     };
>>>>>
>>>>> +&gmac0 {
>>>>> +	status = "okay";
>>>>> +	phy-mode = "rgmii";
>>>>> +	phy-handle = <&emac0_phy0>;
>>>> Shouldn't this be part of Linux DT already ?
>>>
>>> This enablement not yet in Linux DT, I believe our Linux team is still working
>> on it.
>> Is there at least a patch posted upstream ?
> 
> Having two patches posted now in Linux mainline, but gmac device is still not yet added into these dt.
> https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> 
> I think we can do a cleanup if the duplicated found in U-Boot later.
At least reference the two patches (lore links) in the V2 of this patch.

RE: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Wednesday, September 25, 2024 8:51 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC
> 
> On 9/25/24 8:13 AM, Chee, Tien Fong wrote:
> > Hi,
> >
> >> -----Original Message-----
> >> From: Marek Vasut <marex@denx.de>
> >> Sent: Wednesday, September 25, 2024 2:36 AM
> >> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> >> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng,
> >> Tingting <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> >> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> >> <kok.kiang.hea@intel.com>
> >> Subject: Re: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC
> >>
> >> On 9/24/24 8:02 AM, Chee, Tien Fong wrote:
> >>> Hi,
> >>
> >> Hi,
> >>
> >>>>> diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> >>>> b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> >>>>> index 9eb21d65428..75ab05031bc 100644
> >>>>> --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> >>>>> +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> >>>>> @@ -122,3 +122,36 @@
> >>>>>     	bootph-all;
> >>>>>     };
> >>>>>
> >>>>> +&gmac0 {
> >>>>> +	status = "okay";
> >>>>> +	phy-mode = "rgmii";
> >>>>> +	phy-handle = <&emac0_phy0>;
> >>>> Shouldn't this be part of Linux DT already ?
> >>>
> >>> This enablement not yet in Linux DT, I believe our Linux team is
> >>> still working
> >> on it.
> >> Is there at least a patch posted upstream ?
> >
> > Having two patches posted now in Linux mainline, but gmac device is still
> not yet added into these dt.
> > https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/inte
> > l/socfpga_agilex5.dtsi
> > https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/inte
> > l/socfpga_agilex5_socdk.dts
> >
> > I think we can do a cleanup if the duplicated found in U-Boot later.
> At least reference the two patches (lore links) in the V2 of this patch.

Noted. Will do.

Thanks.

Regards,
Tien Fong

[PATCH v1 09/20] sysreset: Add reset support to SoCFPGA Agilex5 device

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

The reset driver can support both cold reset and warm reset with SMCC
to ATF.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/Kconfig                            |  1 +
 drivers/sysreset/Kconfig                    |  7 +++
 drivers/sysreset/Makefile                   |  1 +
 drivers/sysreset/sysreset_socfpga_agilex5.c | 47 +++++++++++++++++++++
 4 files changed, 56 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ba0359fed5a..8e9a39e7d23 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1123,6 +1123,7 @@ config ARCH_SOCFPGA
 	select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
 	  TARGET_SOCFPGA_SOC64
+	select SYSRESET_SOCFPGA_AGILEX5 if TARGET_SOCFPGA_AGILEX5
 	imply CMD_DM
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 121194e4418..8dc1e7fec58 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -156,6 +156,13 @@ config SYSRESET_SOCFPGA_SOC64
 	  This enables the system reset driver support for Intel SOCFPGA
 	  SoC64 SoCs.
 
+config SYSRESET_SOCFPGA_AGILEX5
+	bool "Enable support for Intel SOCFPGA AGILEX5 device"
+	depends on ARCH_SOCFPGA && TARGET_SOCFPGA_AGILEX5
+	help
+	  This enables the system reset driver support for Intel SOCFPGA
+	  AGILEX5 device.
+
 config SYSRESET_TEGRA
 	bool "Tegra PMC system reset driver"
 	depends on ARCH_TEGRA
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index a6a0584585c..c090db48af4 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
 obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o
 obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
 obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
+obj-$(CONFIG_SYSRESET_SOCFPGA_AGILEX5) += sysreset_socfpga_agilex5.o
 obj-$(CONFIG_SYSRESET_TEGRA) += sysreset_tegra.o
 obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_TPS65910) += sysreset_tps65910.o
diff --git a/drivers/sysreset/sysreset_socfpga_agilex5.c b/drivers/sysreset/sysreset_socfpga_agilex5.c
new file mode 100644
index 00000000000..3cb7849ec88
--- /dev/null
+++ b/drivers/sysreset/sysreset_socfpga_agilex5.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/system.h>
+
+static int socfpga_sysreset_request(struct udevice *dev,
+				    enum sysreset_t type)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	const char *reset = env_get("reset");
+
+	if (reset && !strcmp(reset, "warm")) {
+		/* Ensure content in dcache is flushed to system memory */
+		flush_dcache_all();
+
+		/* request a warm reset */
+		puts("Do warm reset now...\n");
+
+		/* doing architecture system reset */
+		psci_system_reset2(0, 0);
+	} else {
+		puts("Issuing cold reset REBOOT_HPS\n");
+		psci_system_reset();
+	}
+#endif
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops socfpga_sysreset = {
+	.request = socfpga_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_socfpga) = {
+	.id	= UCLASS_SYSRESET,
+	.name	= "socfpga_sysreset",
+	.ops	= &socfpga_sysreset,
+};
-- 
2.25.1

Re: [PATCH v1 09/20] sysreset: Add reset support to SoCFPGA Agilex5 device

[Marek Vasut]

On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:

[...]

> +	if (reset && !strcmp(reset, "warm")) {
> +		/* Ensure content in dcache is flushed to system memory */
> +		flush_dcache_all();
> +
> +		/* request a warm reset */
> +		puts("Do warm reset now...\n");
> +
> +		/* doing architecture system reset */
> +		psci_system_reset2(0, 0);
Can this use SYSRESET_PSCI driver instead ?

RE: [PATCH v1 09/20] sysreset: Add reset support to SoCFPGA Agilex5 device

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, September 21, 2024 9:52 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 09/20] sysreset: Add reset support to SoCFPGA
> Agilex5 device
> 
> On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> 
> [...]
> 
> > +	if (reset && !strcmp(reset, "warm")) {
> > +		/* Ensure content in dcache is flushed to system memory */
> > +		flush_dcache_all();
> > +
> > +		/* request a warm reset */
> > +		puts("Do warm reset now...\n");
> > +
> > +		/* doing architecture system reset */
> > +		psci_system_reset2(0, 0);
> Can this use SYSRESET_PSCI driver instead ?

This driver seems can be used after quick check, we will try out this.

Thanks.

Regards,
Tien Fong

[PATCH v1 10/20] arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

set/way instructions "dc cisw" ehich is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/Makefile     |  1 +
 arch/arm/mach-socfpga/ccu_ncore3.c | 64 ++++++++++++++++++++++++++++++
 2 files changed, 65 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/ccu_ncore3.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e0ada69dd5a..32b3e7a57e2 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -65,6 +65,7 @@ obj-y	+= mmu-arm64_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= wrap_handoff_soc64.o
 obj-y	+= wrap_pll_config_soc64.o
+obj-y	+= ccu_ncore3.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_N5X
diff --git a/arch/arm/mach-socfpga/ccu_ncore3.c b/arch/arm/mach-socfpga/ccu_ncore3.c
new file mode 100644
index 00000000000..18667131eb9
--- /dev/null
+++ b/arch/arm/mach-socfpga/ccu_ncore3.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
+ */
+#include <wait_bit.h>
+#include <asm/arch/base_addr_soc64.h>
+#include <linux/bitfield.h>
+
+#define CCU_DMI0_DMIUSMCTCR				SOCFPGA_CCU_ADDRESS + 0x7300
+#define CCU_DMI0_DMIUSMCMCR				SOCFPGA_CCU_ADDRESS + 0x7340
+#define CCU_DMI0_DMIUSMCMAR				SOCFPGA_CCU_ADDRESS + 0x7344
+#define CCU_DMI0_DMIUSMCMCR_MNTOP		GENMASK(3, 0)
+#define MAX_DISTRIBUTED_MEM_INTERFACE	2
+#define FLUSH_ALL_ENTRIES				0x4
+#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID	GENMASK(21, 16)
+#define ARRAY_ID_TAG					0x0
+#define ARRAY_ID_DATA					0x1
+#define CACHE_OPERATION_DONE			BIT(0)
+#define TIMEOUT_200MS					200
+
+int __asm_flush_l3_dcache(void)
+{
+	int i;
+	int ret = 0;
+
+	/* Flushing all entries in CCU system memory cache */
+	for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) {
+		/*
+		 * Skipping if the system memory cache is not enabled for
+		 * particular DMI
+		 */
+		if (!readl((uintptr_t)(CCU_DMI0_DMIUSMCTCR + (i * 0x1000))))
+			continue;
+
+		writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
+			   FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG),
+			   (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
+
+		/* Wait for cache maintenance operation done */
+		ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR +
+				(i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS,
+				false);
+		if (ret) {
+			debug("%s: Timeout while waiting for flushing tag in DMI%d done\n",
+			      __func__, i);
+			return ret;
+		}
+
+		writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
+			   FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA),
+			   (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
+
+		/* Wait for cache maintenance operation done */
+		ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR +
+				(i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS,
+				false);
+		if (ret)
+			debug("%s: Timeout waiting for flushing data in DMI%d done\n",
+			      __func__, i);
+	}
+
+	return ret;
+}
-- 
2.25.1

[PATCH v1 11/20] arm: socfpga: agilex5: Add SMMU initialization

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Allow non-secure accesses only with SMMU peripherals. This would protect
the content in DDR secure region from accidentally modified by SMMU
peripherals.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 34 ++++++++++++++++++++++++
 arch/arm/mach-socfpga/spl_soc64.c        | 17 +++++++++++-
 2 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index bf30b3b8858..9baf2cbc525 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -387,6 +387,40 @@
 				bootph-all;
 			};
 		};
+
+		socfpga_smmu_secure_config: socfpga-smmu-secure-config {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* System manager */
+			i_sys_mgt_sysmgr_csr@10d12000 {
+				reg = <0x10d12000 0x00000500>;
+				intel,offset-settings =
+					/* dma_tbu_stream_ctrl_reg_0_dma0 */
+					<0x0000017c 0x00000000 0x0000003f>,
+					/* dma_tbu_stream_ctrl_reg_0_dma1 */
+					<0x00000180 0x00000000 0x0000003f>,
+					/* sdm_tbu_stream_ctrl_reg_1_sdm */
+					<0x00000184 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_usb2 */
+					<0x00000188 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_sdmmc */
+					<0x00000190 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_nand */
+					<0x00000194 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_etr */
+					<0x00000198 0x00000000 0x0000003f>,
+					/* tsn_tbu_stream_ctrl_reg_3_tsn0 */
+					<0x0000019c 0x00000000 0x0000003f>,
+					/* tsn_tbu_stream_ctrl_reg_3_tsn1 */
+					<0x000001a0 0x00000000 0x0000003f>,
+					/* tsn_tbu_stream_ctrl_reg_3_tsn2 */
+					<0x000001a4 0x00000000 0x0000003f>;
+				bootph-all;
+			};
+		};
 	};
 };
 
diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c
index 4fe67ea0811..3bfe4bb9dd3 100644
--- a/arch/arm/mach-socfpga/spl_soc64.c
+++ b/arch/arm/mach-socfpga/spl_soc64.c
@@ -1,10 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- *  Copyright (C) 2020 Intel Corporation. All rights reserved
+ *  Copyright (C) 2020-2024 Intel Corporation. All rights reserved
  *
  */
 
+#include <hang.h>
 #include <spl.h>
+#include <dm/uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -22,3 +24,16 @@ u32 spl_boot_mode(const u32 boot_device)
 		return MMCSD_MODE_RAW;
 }
 #endif
+
+/* board specific function prior loading SSBL / U-Boot */
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-smmu-secure-config", &dev);
+	if (ret) {
+		printf("HPS SMMU secure settings init failed: %d\n", ret);
+		hang();
+	}
+}
-- 
2.25.1

[PATCH v1 12/20] arm: socfpga: agilex5: Update CPU info

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Update the print info per Agilex 5.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/misc_soc64.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index a6cc78454da..95e1c07e39f 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -45,7 +45,12 @@ static Altera_desc altera_fpga[] = {
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-	puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
+	if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) {
+		puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A55/A76)");
+		puts("\n");
+	} else {
+		puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
+	}
 
 	return 0;
 }
-- 
2.25.1

Re: [PATCH v1 12/20] arm: socfpga: agilex5: Update CPU info

[Marek Vasut]

On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Update the print info per Agilex 5.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>   arch/arm/mach-socfpga/misc_soc64.c | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
> index a6cc78454da..95e1c07e39f 100644
> --- a/arch/arm/mach-socfpga/misc_soc64.c
> +++ b/arch/arm/mach-socfpga/misc_soc64.c
> @@ -45,7 +45,12 @@ static Altera_desc altera_fpga[] = {
>   #if defined(CONFIG_DISPLAY_CPUINFO)
>   int print_cpuinfo(void)
>   {
> -	puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
> +	if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) {
> +		puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A55/A76)");
> +		puts("\n");
> +	} else {
> +		

printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n",
        IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53");

RE: [PATCH v1 12/20] arm: socfpga: agilex5: Update CPU info

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, September 21, 2024 9:53 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 12/20] arm: socfpga: agilex5: Update CPU info
> 
> On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Update the print info per Agilex 5.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >   arch/arm/mach-socfpga/misc_soc64.c | 7 ++++++-
> >   1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-
> socfpga/misc_soc64.c
> > index a6cc78454da..95e1c07e39f 100644
> > --- a/arch/arm/mach-socfpga/misc_soc64.c
> > +++ b/arch/arm/mach-socfpga/misc_soc64.c
> > @@ -45,7 +45,12 @@ static Altera_desc altera_fpga[] = {
> >   #if defined(CONFIG_DISPLAY_CPUINFO)
> >   int print_cpuinfo(void)
> >   {
> > -	puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-
> A53)\n");
> > +	if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) {
> > +		puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit
> Cortex-A55/A76)");
> > +		puts("\n");
> > +	} else {
> > +
> 
> printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n",
>         IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53");

We will fix it.

Thanks for the good comment.

Regards,
Tien Fong

[PATCH v1 13/20] arm: socfpga: Export board ID as U-Boot environment variable

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Board ID is exported as environment variable for use to boot Linux with FIT
configuration.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/include/mach/misc.h | 1 +
 arch/arm/mach-socfpga/misc_soc64.c        | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 8460acb00d9..e62bea017b0 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -52,5 +52,6 @@ void set_regular_boot(unsigned int status);
 void socfpga_pl310_clear(void);
 void socfpga_get_managers_addr(void);
 int qspi_flash_software_reset(void);
+u8 socfpga_get_board_id(void);
 
 #endif /* _SOCFPGA_MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index 95e1c07e39f..e34c54518a3 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -60,10 +60,15 @@ int print_cpuinfo(void)
 int arch_misc_init(void)
 {
 	char qspi_string[13];
+	char id[3];
 
 	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
 	env_set("qspi_clock", qspi_string);
 
+	/* Export board_id as environment variable */
+	sprintf(id, "%u", socfpga_get_board_id());
+	env_set("board_id", id);
+
 	return 0;
 }
 #endif
-- 
2.25.1

Re: [PATCH v1 13/20] arm: socfpga: Export board ID as U-Boot environment variable

[Marek Vasut]

On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Board ID is exported as environment variable for use to boot Linux with FIT
> configuration.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>   arch/arm/mach-socfpga/include/mach/misc.h | 1 +
>   arch/arm/mach-socfpga/misc_soc64.c        | 5 +++++
>   2 files changed, 6 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
> index 8460acb00d9..e62bea017b0 100644
> --- a/arch/arm/mach-socfpga/include/mach/misc.h
> +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> @@ -52,5 +52,6 @@ void set_regular_boot(unsigned int status);
>   void socfpga_pl310_clear(void);
>   void socfpga_get_managers_addr(void);
>   int qspi_flash_software_reset(void);
> +u8 socfpga_get_board_id(void);
>   
>   #endif /* _SOCFPGA_MISC_H_ */
> diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
> index 95e1c07e39f..e34c54518a3 100644
> --- a/arch/arm/mach-socfpga/misc_soc64.c
> +++ b/arch/arm/mach-socfpga/misc_soc64.c
> @@ -60,10 +60,15 @@ int print_cpuinfo(void)
>   int arch_misc_init(void)
>   {
>   	char qspi_string[13];
> +	char id[3];
>   
>   	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
>   	env_set("qspi_clock", qspi_string);
>   
> +	/* Export board_id as environment variable */
> +	sprintf(id, "%u", socfpga_get_board_id());
> +	env_set("board_id", id);
env_set_ulong()

RE: [PATCH v1 13/20] arm: socfpga: Export board ID as U-Boot environment variable

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, September 21, 2024 9:54 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 13/20] arm: socfpga: Export board ID as U-Boot
> environment variable
> 
> On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Board ID is exported as environment variable for use to boot Linux
> > with FIT configuration.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >   arch/arm/mach-socfpga/include/mach/misc.h | 1 +
> >   arch/arm/mach-socfpga/misc_soc64.c        | 5 +++++
> >   2 files changed, 6 insertions(+)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
> > b/arch/arm/mach-socfpga/include/mach/misc.h
> > index 8460acb00d9..e62bea017b0 100644
> > --- a/arch/arm/mach-socfpga/include/mach/misc.h
> > +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> > @@ -52,5 +52,6 @@ void set_regular_boot(unsigned int status);
> >   void socfpga_pl310_clear(void);
> >   void socfpga_get_managers_addr(void);
> >   int qspi_flash_software_reset(void);
> > +u8 socfpga_get_board_id(void);
> >
> >   #endif /* _SOCFPGA_MISC_H_ */
> > diff --git a/arch/arm/mach-socfpga/misc_soc64.c
> > b/arch/arm/mach-socfpga/misc_soc64.c
> > index 95e1c07e39f..e34c54518a3 100644
> > --- a/arch/arm/mach-socfpga/misc_soc64.c
> > +++ b/arch/arm/mach-socfpga/misc_soc64.c
> > @@ -60,10 +60,15 @@ int print_cpuinfo(void)
> >   int arch_misc_init(void)
> >   {
> >   	char qspi_string[13];
> > +	char id[3];
> >
> >   	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
> >   	env_set("qspi_clock", qspi_string);
> >
> > +	/* Export board_id as environment variable */
> > +	sprintf(id, "%u", socfpga_get_board_id());
> > +	env_set("board_id", id);
> env_set_ulong()

OK, we will change it.

Regards,
Tien Fong

[PATCH v1 14/20] configs: agilex5: Add configuration for malloc pool

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Adding configuration for SPL malloc pool.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 configs/socfpga_agilex5_defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index dc1cef3754e..81bbe967dcf 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -29,6 +29,10 @@ CONFIG_BOOTDELAY=5
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe"
 CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_CACHE=y
-- 
2.25.1

[PATCH v1 15/20] arm: socfpga: smc: Add memory coherency support to mailbox command

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/smc_api.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
index ebaa0b8fa17..dac888c399f 100644
--- a/arch/arm/mach-socfpga/smc_api.c
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -1,9 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2024 Intel Corporation <www.intel.com>
  *
  */
 
+#include <cpu_func.h>
 #include <asm/ptrace.h>
 #include <asm/system.h>
 #include <linux/errno.h>
@@ -40,10 +41,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
 	args[2] = len;
 	args[3] = urgent;
 	args[4] = (u64)resp_buf;
-	if (resp_buf_len)
+
+	if (arg && len > 0)
+		flush_dcache_range((u64)arg, (u64)arg + len);
+
+	if (resp_buf && resp_buf_len && *resp_buf_len > 0) {
 		args[5] = *resp_buf_len;
-	else
+		flush_dcache_range((u64)resp_buf, (u64)resp_buf + *resp_buf_len);
+	} else {
 		args[5] = 0;
+	}
 
 	ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
 			 resp, ARRAY_SIZE(resp));
-- 
2.25.1

Re: [PATCH v1 15/20] arm: socfpga: smc: Add memory coherency support to mailbox command

[Marek Vasut]

On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
> perform cache flush of buffers that are shared between U-Boot and
> ATF using secure monitor calls.
> 
> Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>   arch/arm/mach-socfpga/smc_api.c | 13 ++++++++++---
>   1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
> index ebaa0b8fa17..dac888c399f 100644
> --- a/arch/arm/mach-socfpga/smc_api.c
> +++ b/arch/arm/mach-socfpga/smc_api.c
> @@ -1,9 +1,10 @@
>   // SPDX-License-Identifier: GPL-2.0+
>   /*
> - * Copyright (C) 2020 Intel Corporation <www.intel.com>
> + * Copyright (C) 2020-2024 Intel Corporation <www.intel.com>
>    *
>    */
>   
> +#include <cpu_func.h>
>   #include <asm/ptrace.h>
>   #include <asm/system.h>
>   #include <linux/errno.h>
> @@ -40,10 +41,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
>   	args[2] = len;
>   	args[3] = urgent;
>   	args[4] = (u64)resp_buf;
> -	if (resp_buf_len)
> +
> +	if (arg && len > 0)
> +		flush_dcache_range((u64)arg, (u64)arg + len);
If really needed, the cast should be some uintptr_t

RE: [PATCH v1 15/20] arm: socfpga: smc: Add memory coherency support to mailbox command

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, September 21, 2024 9:59 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>; Rao, Mahesh <mahesh.rao@intel.com>
> Subject: Re: [PATCH v1 15/20] arm: socfpga: smc: Add memory coherency
> support to mailbox command
> 
> On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
> > perform cache flush of buffers that are shared between U-Boot and ATF
> > using secure monitor calls.
> >
> > Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >   arch/arm/mach-socfpga/smc_api.c | 13 ++++++++++---
> >   1 file changed, 10 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/smc_api.c
> > b/arch/arm/mach-socfpga/smc_api.c index ebaa0b8fa17..dac888c399f
> > 100644
> > --- a/arch/arm/mach-socfpga/smc_api.c
> > +++ b/arch/arm/mach-socfpga/smc_api.c
> > @@ -1,9 +1,10 @@
> >   // SPDX-License-Identifier: GPL-2.0+
> >   /*
> > - * Copyright (C) 2020 Intel Corporation <www.intel.com>
> > + * Copyright (C) 2020-2024 Intel Corporation <www.intel.com>
> >    *
> >    */
> >
> > +#include <cpu_func.h>
> >   #include <asm/ptrace.h>
> >   #include <asm/system.h>
> >   #include <linux/errno.h>
> > @@ -40,10 +41,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg,
> u8 urgent, u32 *resp_buf_len,
> >   	args[2] = len;
> >   	args[3] = urgent;
> >   	args[4] = (u64)resp_buf;
> > -	if (resp_buf_len)
> > +
> > +	if (arg && len > 0)
> > +		flush_dcache_range((u64)arg, (u64)arg + len);
> If really needed, the cast should be some uintptr_t

Sure,  we will fix it.

Regards,
Tien Fong

[PATCH v1 16/20] ddr: altera: Add DDR driver for Agilex5 series

[tien.fong.chee]

From: Tingting Meng <tingting.meng@intel.com>

Adding DDR driver support for Agilex5 series.

Signed-off-by: Tingting Meng <tingting.meng@intel.com>
---
 MAINTAINERS                                   |   2 +
 arch/arm/dts/socfpga_agilex5-u-boot.dtsi      | 251 +++++++
 arch/arm/dts/socfpga_agilex5.dtsi             |   7 +
 arch/arm/mach-socfpga/include/mach/firewall.h |  23 +-
 drivers/ddr/altera/Makefile                   |   1 +
 drivers/ddr/altera/iossm_mailbox.c            | 613 ++++++++++++++++++
 drivers/ddr/altera/iossm_mailbox.h            | 186 ++++++
 drivers/ddr/altera/sdram_agilex5.c            | 377 +++++++++++
 drivers/ddr/altera/sdram_soc64.c              |  78 ++-
 drivers/ddr/altera/sdram_soc64.h              |  32 +-
 10 files changed, 1547 insertions(+), 23 deletions(-)
 create mode 100644 drivers/ddr/altera/iossm_mailbox.c
 create mode 100644 drivers/ddr/altera/iossm_mailbox.h
 create mode 100644 drivers/ddr/altera/sdram_agilex5.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 2050ae24df8..1837d283b2f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -146,8 +146,10 @@ ARM ALTERA SOCFPGA
 M:	Marek Vasut <marex@denx.de>
 M:	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
 M:	Tien Fong Chee <tien.fong.chee@intel.com>
+M:	Tingting Meng <tingting.meng@intel.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
+F:	drivers/ddr/altera/
 F:	arch/arm/mach-socfpga/
 F:	drivers/sysreset/sysreset_socfpga*
 
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index 9baf2cbc525..1209a8da4b9 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -388,6 +388,230 @@
 			};
 		};
 
+		socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* DSU */
+			i_ccu_caiu0@1c000000 {
+				reg = <0x1c000000 0x00001000>;
+				intel,offset-settings =
+					/* CAIUAMIGR */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* FPGA2SOC */
+			i_ccu_ncaiu0@1c001000 {
+				reg = <0x1c001000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU0AMIGR */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* GIC_M */
+			i_ccu_ncaiu1@1c002000 {
+				reg = <0x1c002000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU1AMIGR */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* SMMU */
+			i_ccu_ncaiu2@1c003000 {
+				reg = <0x1c003000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU2AMIGR */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* PSS NOC */
+			i_ccu_ncaiu3@1c004000 {
+				reg = <0x1c004000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU3AMIGR */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* DCE0 */
+			i_ccu_dce0@1c005000 {
+				reg = <0x1c005000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUAMIGR0 */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* DCE1 */
+			i_ccu_dce1@1c006000 {
+				reg = <0x1c006000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUAMIGR1 */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+		};
+
+		socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* DSU */
+			i_ccu_caiu0@1c000000 {
+				reg = <0x1c000000 0x00001000>;
+				intel,offset-settings =
+					/* CAIUAMIGR */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* FPGA2SOC */
+			i_ccu_ncaiu0@1c001000 {
+				reg = <0x1c001000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU0AMIGR */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* GIC_M */
+			i_ccu_ncaiu1@1c002000 {
+				reg = <0x1c002000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU1AMIGR */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* SMMU */
+			i_ccu_ncaiu2@1c003000 {
+				reg = <0x1c003000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU2AMIGR */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* PSS NOC */
+			i_ccu_ncaiu3@1c004000 {
+				reg = <0x1c004000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU3AMIGR */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* DCE0 */
+			i_ccu_dce0@1c005000 {
+				reg = <0x1c005000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUAMIGR0 */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* DCE1 */
+			i_ccu_dce1@1c006000 {
+				reg = <0x1c006000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUAMIGR1 */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+		};
+
 		socfpga_smmu_secure_config: socfpga-smmu-secure-config {
 			compatible = "intel,socfpga-dtreg";
 			#address-cells = <1>;
@@ -421,6 +645,26 @@
 				bootph-all;
 			};
 		};
+
+		socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* noc fw mpfe csr */
+			i_noc_fw_mpfe_csr@18000d00 {
+				reg = <0x18000d00 0x00000100>;
+				intel,offset-settings =
+					/* mpfe scr io96b0 reg*/
+					<0x00000000 0x00000001 0x00010101>,
+					/* mpfe scr io96b1 reg*/
+					<0x00000004 0x00000001 0x00010101>,
+					/* mpfe scr noc csr*/
+					<0x00000008 0x00000001 0x00010101>;
+				bootph-all;
+			};
+		};
 	};
 };
 
@@ -466,6 +710,13 @@
 	bootph-all;
 };
 
+&sdr {
+	compatible = "intel,sdr-ctl-agilex5";
+	reg = <0x18000000 0x400000>;
+	resets = <&rst DDRSCH_RESET>;
+	bootph-all;
+};
+
 &sysmgr {
 	compatible = "altr,sys-mgr", "syscon";
 	bootph-all;
diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi
index 03b55040497..4f17d8fc21e 100644
--- a/arch/arm/dts/socfpga_agilex5.dtsi
+++ b/arch/arm/dts/socfpga_agilex5.dtsi
@@ -544,6 +544,13 @@
 			status = "disabled";
 		};
 
+		sdr: sdr@18000000 {
+			compatible = "intel,sdr-ctl-agilex5";
+			reg = <0x18000000 0x400000>;
+			resets = <&rst DDRSCH_RESET>;
+			bootph-all;
+		};
+
 		/* QSPI address not available yet */
 		qspi: spi@108d2000 {
 			compatible = "cdns,qspi-nor";
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index 5cb7f23f8f0..9c3f3313af6 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -1,7 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
- *
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2024 Intel Corporation <www.intel.com>
  */
 
 #ifndef	_FIREWALL_H_
@@ -126,11 +125,27 @@ struct socfpga_firwall_l4_sys {
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT	0x9c
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD	0xff
 
+/* Firewall F2SDRAM DDR SCR registers */
+#define FW_F2SDRAM_DDR_SCR_EN				0x00
+#define FW_F2SDRAM_DDR_SCR_EN_SET			0x04
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE		0x10
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT		0x14
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT		0x18
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT		0x1c
+
 #define MPUREGION0_ENABLE				BIT(0)
 #define NONMPUREGION0_ENABLE				BIT(8)
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define FW_MPU_DDR_SCR_WRITEL(data, reg)		\
+	writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \
+	writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg))
+#define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg)		\
+	writel(data, SOCFPGA_FW_TBU2NOC_ADDRESS + (reg))
+#else
 #define FW_MPU_DDR_SCR_WRITEL(data, reg)		\
 	writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
+#endif
 
 void firewall_setup(void);
 
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 9fa5d85a27e..117868b6d01 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
 obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
 obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
 obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o
 endif
diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c
new file mode 100644
index 00000000000..5e76246dcca
--- /dev/null
+++ b/drivers/ddr/altera/iossm_mailbox.c
@@ -0,0 +1,613 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include <hang.h>
+#include <string.h>
+#include <wait_bit.h>
+#include <asm/arch/base_addr_soc64.h>
+#include <asm/io.h>
+#include <linux/bitfield.h>
+#include "iossm_mailbox.h"
+
+#define ECC_INTSTATUS_SERR SOCFPGA_SYSMGR_ADDRESS + 0x9C
+#define ECC_INISTATUS_DERR SOCFPGA_SYSMGR_ADDRESS + 0xA0
+#define ECC_UNCONRRECTABLE_ERROR_MASK \
+	BIT(2) + BIT(3) + BIT(6) + BIT(10) + BIT(12) + BIT(13)
+#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16)
+#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17)
+
+#define IO96B_MB_REQ_SETUP(v, w, x, y, z) \
+	usr_req.ip_type = v; \
+	usr_req.ip_id = w; \
+	usr_req.usr_cmd_type = x; \
+	usr_req.usr_cmd_opcode = y; \
+	usr_req.cmd_param[0] = z; \
+	for (n = 1; n < NUM_CMD_PARAM; n++) \
+		usr_req.cmd_param[n] = 0
+#define MAX_RETRY_COUNT 3
+#define NUM_CMD_RESPONSE_DATA 3
+
+#define IO96B0_PLL_A_MASK	BIT(0)
+#define IO96B0_PLL_B_MASK	BIT(1)
+#define IO96B1_PLL_A_MASK	BIT(2)
+#define IO96B1_PLL_B_MASK	BIT(3)
+
+/* supported DDR type list */
+static const char *ddr_type_list[7] = {
+		"DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN"
+};
+
+static int is_ddr_csr_clkgen_locked(u8 io96b_pll)
+{
+	int ret = 0;
+	const char *pll_names[MAX_IO96B_SUPPORTED][2] = {
+		{"io96b_0 clkgenA", "io96b_0 clkgenB"},
+		{"io96b_1 clkgenA", "io96b_1 clkgenB"}
+	};
+	u32 masks[MAX_IO96B_SUPPORTED][2] = {
+		{IO96B0_PLL_A_MASK, IO96B0_PLL_B_MASK},
+		{IO96B1_PLL_A_MASK, IO96B1_PLL_B_MASK}
+	};
+	u32 lock_masks[MAX_IO96B_SUPPORTED] = {
+		DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK,
+		DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK
+	};
+
+	for (int i = 0; i < MAX_IO96B_SUPPORTED ; i++) {
+		/* Check for PLL_A */
+		if (io96b_pll & masks[i][0]) {
+			ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR), lock_masks[i],
+						true, TIMEOUT, false);
+
+			if (ret) {
+				debug("%s: ddr csr %s locked is timeout\n",
+				      __func__, pll_names[i][0]);
+				goto err;
+			} else {
+				debug("%s: ddr csr %s is successfully locked\n",
+				      __func__, pll_names[i][0]);
+			}
+		}
+
+		/* Check for PLL_B */
+		if (io96b_pll & masks[i][1]) {
+			ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR), lock_masks[i],
+						true, TIMEOUT, false);
+
+			if (ret) {
+				debug("%s: ddr csr %s locked is timeout\n",
+				      __func__, pll_names[i][1]);
+				goto err;
+			} else {
+				debug("%s: ddr csr %s is successfully locked\n",
+				      __func__, pll_names[i][1]);
+			}
+		}
+	}
+
+err:
+	return ret;
+}
+
+/*
+ * Mailbox request function
+ * This function will send the request to IOSSM mailbox and wait for response return
+ *
+ * @io96b_csr_addr: CSR address for the target IO96B
+ * @req:            Structure contain command request for IOSSM mailbox command
+ * @resp_data_len:  User desire extra response data fields other than
+ *		    CMD_RESPONSE_DATA_SHORT field on CMD_RESPONSE_STATUS
+ * @resp:           Structure contain responses returned from the requested IOSSM
+ *		    mailbox command
+ */
+int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req,
+		 u32 resp_data_len, struct io96b_mb_resp *resp)
+{
+	int i, ret;
+	u32 cmd_req;
+
+	if (!resp) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	/* Zero initialization for responses */
+	resp->cmd_resp_status = 0;
+
+	/* Ensure CMD_REQ is cleared before write any command request */
+	ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_REQ_OFFSET),
+				GENMASK(31, 0), false, TIMEOUT, false);
+	if (ret) {
+		printf("%s: Timeout of waiting DDR mailbox ready to be functioned!\n",
+		       __func__);
+		goto err;
+	}
+
+	/* Write CMD_PARAM_* */
+	for (i = 0; i < NUM_CMD_PARAM ; i++) {
+		switch (i) {
+		case 0:
+			if (req.cmd_param[0])
+				writel(req.cmd_param[0], io96b_csr_addr + IOSSM_CMD_PARAM_0_OFFSET);
+			break;
+		case 1:
+			if (req.cmd_param[1])
+				writel(req.cmd_param[1], io96b_csr_addr + IOSSM_CMD_PARAM_1_OFFSET);
+			break;
+		case 2:
+			if (req.cmd_param[2])
+				writel(req.cmd_param[2], io96b_csr_addr + IOSSM_CMD_PARAM_2_OFFSET);
+			break;
+		case 3:
+			if (req.cmd_param[3])
+				writel(req.cmd_param[3], io96b_csr_addr + IOSSM_CMD_PARAM_3_OFFSET);
+			break;
+		case 4:
+			if (req.cmd_param[4])
+				writel(req.cmd_param[4], io96b_csr_addr + IOSSM_CMD_PARAM_4_OFFSET);
+			break;
+		case 5:
+			if (req.cmd_param[5])
+				writel(req.cmd_param[5], io96b_csr_addr + IOSSM_CMD_PARAM_5_OFFSET);
+			break;
+		case 6:
+			if (req.cmd_param[6])
+				writel(req.cmd_param[6], io96b_csr_addr + IOSSM_CMD_PARAM_6_OFFSET);
+			break;
+		default:
+			printf("%s: Invalid command parameter\n", __func__);
+		}
+	}
+
+	/* Write CMD_REQ (IP_TYPE, IP_INSTANCE_ID, CMD_TYPE and CMD_OPCODE) */
+	cmd_req = FIELD_PREP(CMD_TARGET_IP_TYPE_MASK, req.ip_type) |
+		FIELD_PREP(CMD_TARGET_IP_INSTANCE_ID_MASK, req.ip_id) |
+		FIELD_PREP(CMD_TYPE_MASK, req.usr_cmd_type) |
+		FIELD_PREP(CMD_OPCODE_MASK, req.usr_cmd_opcode);
+	writel(cmd_req, io96b_csr_addr + IOSSM_CMD_REQ_OFFSET);
+
+	debug("%s: Write 0x%x to IOSSM_CMD_REQ_OFFSET 0x%llx\n", __func__, cmd_req,
+	      io96b_csr_addr + IOSSM_CMD_REQ_OFFSET);
+
+	/* Read CMD_RESPONSE_READY in CMD_RESPONSE_STATUS */
+	ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET),
+				IOSSM_STATUS_COMMAND_RESPONSE_READY, true, TIMEOUT, false);
+
+	/* read CMD_RESPONSE_STATUS */
+	resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET);
+
+	debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr +
+	      IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status);
+
+	if (ret) {
+		printf("%s: CMD_RESPONSE ERROR:\n", __func__);
+
+		printf("%s: STATUS_GENERAL_ERROR: 0x%lx\n", __func__,
+		       IOSSM_STATUS_GENERAL_ERROR(resp->cmd_resp_status));
+		printf("%s: STATUS_CMD_RESPONSE_ERROR: 0x%lx\n", __func__,
+		       IOSSM_STATUS_CMD_RESPONSE_ERROR(resp->cmd_resp_status));
+		goto err;
+	}
+
+	/* read CMD_RESPONSE_DATA_* */
+	for (i = 0; i < resp_data_len; i++) {
+		switch (i) {
+		case 0:
+			resp->cmd_resp_data[i] =
+					readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET);
+
+			debug("%s: IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x%llx: 0x%x\n", __func__,
+			      io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET,
+			      resp->cmd_resp_data[i]);
+			break;
+		case 1:
+			resp->cmd_resp_data[i] =
+					readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET);
+
+			debug("%s: IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x%llx: 0x%x\n", __func__,
+			      io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET,
+			      resp->cmd_resp_data[i]);
+			break;
+		case 2:
+			resp->cmd_resp_data[i] =
+					readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET);
+
+			debug("%s: IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x%llx: 0x%x\n", __func__,
+			      io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET,
+			      resp->cmd_resp_data[i]);
+			break;
+		default:
+			resp->cmd_resp_data[i] = 0;
+			printf("%s: Invalid response data\n", __func__);
+		}
+	}
+
+	/* write CMD_RESPONSE_READY = 0 */
+	clrbits_le32((u32 *)(uintptr_t)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET),
+		     IOSSM_STATUS_COMMAND_RESPONSE_READY);
+
+	debug("%s: After clear CMD_RESPONSE_READY bit: 0x%llx: 0x%x\n", __func__,
+	      io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET,
+	      readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET));
+
+err:
+	return ret;
+}
+
+/*
+ * Initial function to be called to set memory interface IP type and instance ID
+ * IP type and instance ID need to be determined before sending mailbox command
+ */
+void io96b_mb_init(struct io96b_info *io96b_ctrl)
+{
+	struct io96b_mb_req usr_req;
+	struct io96b_mb_resp usr_resp;
+	u8 ip_type_ret, instance_id_ret;
+	int i, j, k, n, ret;
+
+	debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance);
+
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		debug("%s: get memory interface IO96B %d\n", __func__, i);
+
+		IO96B_MB_REQ_SETUP(0, 0, CMD_GET_SYS_INFO, GET_MEM_INTF_INFO, 0);
+
+		/* Get memory interface IP type and instance ID (IP identifier) */
+		ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 2, &usr_resp);
+		if (ret) {
+			printf("%s: get memory interface IO96B %d failed\n", __func__, i);
+			hang();
+		}
+
+		debug("%s: get response from memory interface IO96B %d\n", __func__, i);
+
+		/* Retrieve number of memory interface(s) */
+		io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface =
+			IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & 0x3;
+
+		debug("%s: IO96B %d: num_mem_interface: 0x%x\n", __func__, i,
+		      io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface);
+
+		/* Retrieve memory interface IP type and instance ID (IP identifier) */
+		j = 0;
+		for (k = 0; k < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; k++) {
+			ip_type_ret = FIELD_GET(INTF_IP_TYPE_MASK, usr_resp.cmd_resp_data[k]);
+			instance_id_ret = FIELD_GET(INTF_INSTANCE_ID_MASK,
+						    usr_resp.cmd_resp_data[k]);
+
+			if (ip_type_ret) {
+				io96b_ctrl->io96b[i].mb_ctrl.ip_type[j] = ip_type_ret;
+				io96b_ctrl->io96b[i].mb_ctrl.ip_id[j] = instance_id_ret;
+
+				debug("%s: IO96B %d mem_interface %d: ip_type_ret: 0x%x\n",
+				      __func__, i, j, ip_type_ret);
+				debug("%s: IO96B %d mem_interface %d: instance_id_ret: 0x%x\n",
+				      __func__, i, j, instance_id_ret);
+
+				j++;
+			}
+		}
+	}
+}
+
+int io96b_cal_status(phys_addr_t addr)
+{
+	u32 cal_success, cal_fail;
+	phys_addr_t status_addr = addr + IOSSM_STATUS_OFFSET;
+	u32 start = get_timer(0);
+
+	do {
+		if (get_timer(start) > TIMEOUT_60000MS) {
+			printf("%s: SDRAM calibration for IO96B instance 0x%llx timeout!\n",
+			       __func__, status_addr);
+			hang();
+		}
+
+		udelay(1);
+		schedule();
+
+		/* Polling until getting any calibration result */
+		cal_success = readl(status_addr) & IOSSM_STATUS_CAL_SUCCESS;
+		cal_fail = readl(status_addr) & IOSSM_STATUS_CAL_FAIL;
+	} while (!cal_success && !cal_fail);
+
+	debug("%s: Calibration for IO96B instance 0x%llx done at %ld msec!\n",
+	      __func__,  status_addr, get_timer(start));
+
+	if (cal_success && !cal_fail)
+		return 0;
+	else
+		return -EPERM;
+}
+
+void init_mem_cal(struct io96b_info *io96b_ctrl)
+{
+	int count, i, ret;
+
+	/* Initialize overall calibration status */
+	io96b_ctrl->overall_cal_status = false;
+
+	if (io96b_ctrl->ckgen_lock) {
+		ret = is_ddr_csr_clkgen_locked(io96b_ctrl->io96b_pll);
+		if (ret) {
+			printf("%s: iossm IO96B ckgena_lock is not locked\n", __func__);
+			hang();
+		}
+	}
+
+	/* Check initial calibration status for the assigned IO96B */
+	count = 0;
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		ret = io96b_cal_status(io96b_ctrl->io96b[i].io96b_csr_addr);
+		if (ret) {
+			io96b_ctrl->io96b[i].cal_status = false;
+
+			printf("%s: Initial DDR calibration IO96B_%d failed %d\n", __func__,
+			       i, ret);
+
+			hang();
+		}
+
+		io96b_ctrl->io96b[i].cal_status = true;
+
+		printf("%s: Initial DDR calibration IO96B_%d succeed\n", __func__, i);
+
+		count++;
+	}
+
+	if (count == io96b_ctrl->num_instance)
+		io96b_ctrl->overall_cal_status = true;
+}
+
+int get_mem_technology(struct io96b_info *io96b_ctrl)
+{
+	struct io96b_mb_req usr_req;
+	struct io96b_mb_resp usr_resp;
+	int i, j, n, ret = 0;
+	u8 ddr_type_ret;
+
+	/* Initialize ddr type */
+	io96b_ctrl->ddr_type = ddr_type_list[6];
+
+	/* Get and ensure all memory interface(s) same DDR type */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+			IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j],
+					   io96b_ctrl->io96b[i].mb_ctrl.ip_id[j],
+					   CMD_GET_MEM_INFO, GET_MEM_TECHNOLOGY, 0);
+
+			ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req,
+					   0, &usr_resp);
+
+			if (ret)
+				goto err;
+
+			ddr_type_ret =
+				IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+				& GENMASK(2, 0);
+
+			if (!strcmp(io96b_ctrl->ddr_type, "UNKNOWN"))
+				io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret];
+
+			if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) {
+				printf("%s: Mismatch DDR type on IO96B_%d\n", __func__, i);
+
+				ret = -EINVAL;
+				goto err;
+			}
+		}
+	}
+
+err:
+	return ret;
+}
+
+int get_mem_width_info(struct io96b_info *io96b_ctrl)
+{
+	struct io96b_mb_req usr_req;
+	struct io96b_mb_resp usr_resp;
+	int i, j, n, ret = 0;
+	u16 memory_size;
+	u16 total_memory_size = 0;
+
+	/* Get all memory interface(s) total memory size on all instance(s) */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		memory_size = 0;
+		for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+			IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j],
+					   io96b_ctrl->io96b[i].mb_ctrl.ip_id[j],
+					   CMD_GET_MEM_INFO, GET_MEM_WIDTH_INFO, 0);
+
+			ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req,
+					   2, &usr_resp);
+
+			if (ret)
+				goto err;
+
+			memory_size = memory_size +
+					(usr_resp.cmd_resp_data[1] & GENMASK(7, 0));
+		}
+
+		if (!memory_size) {
+			printf("%s: Failed to get valid memory size\n", __func__);
+			ret = -EINVAL;
+			goto err;
+		}
+
+		io96b_ctrl->io96b[i].size = memory_size;
+
+		total_memory_size = total_memory_size + memory_size;
+	}
+
+	if (!total_memory_size) {
+		printf("%s: Failed to get valid memory size\n", __func__);
+		ret = -EINVAL;
+	}
+
+	io96b_ctrl->overall_size = total_memory_size;
+
+err:
+	return ret;
+}
+
+int ecc_enable_status(struct io96b_info *io96b_ctrl)
+{
+	struct io96b_mb_req usr_req;
+	struct io96b_mb_resp usr_resp;
+	int i, j, n, ret = 0;
+	bool ecc_stat_set = false;
+	bool ecc_stat;
+
+	/* Initialize ECC status */
+	io96b_ctrl->ecc_status = false;
+
+	/* Get and ensure all memory interface(s) same ECC status */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+			IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j],
+					   io96b_ctrl->io96b[i].mb_ctrl.ip_id[j],
+					   CMD_TRIG_CONTROLLER_OP, ECC_ENABLE_STATUS, 0);
+
+			ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr,
+					   usr_req, 0, &usr_resp);
+
+			if (ret)
+				goto err;
+
+			ecc_stat = (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+					& GENMASK(1, 0)) == 0 ? false : true;
+
+			if (!ecc_stat_set) {
+				io96b_ctrl->ecc_status = ecc_stat;
+				ecc_stat_set = true;
+			}
+
+			if (ecc_stat != io96b_ctrl->ecc_status) {
+				printf("%s: Mismatch DDR ECC status on IO96B_%d\n", __func__, i);
+
+				ret = -EINVAL;
+				goto err;
+			}
+		}
+	}
+
+	debug("%s: ECC enable status: %d\n", __func__, io96b_ctrl->ecc_status);
+
+err:
+	return ret;
+}
+
+int ecc_interrupt_status(struct io96b_info *io96b_ctrl, bool *ecc_error_flag)
+{
+	struct io96b_mb_req usr_req;
+	struct io96b_mb_resp usr_resp;
+	int i, j, n, ret = 0;
+	u32 uncorrectable_error;
+
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+			IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j],
+					   io96b_ctrl->io96b[i].mb_ctrl.ip_id[j],
+					   CMD_TRIG_CONTROLLER_OP, ECC_INTERRUPT_STATUS, 0);
+
+			ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr,
+					   usr_req, 1, &usr_resp);
+
+			if (ret)
+				goto err;
+
+			uncorrectable_error = (usr_resp.cmd_resp_data[0]) &
+				(ECC_UNCONRRECTABLE_ERROR_MASK);
+			debug("%s: IO96B %d mem_interface %d: ECC error status:0x%08x\n",
+			      __func__, i, j, uncorrectable_error);
+
+			if (uncorrectable_error) {
+				*ecc_error_flag = true;
+				printf("DDR: ECC un-correctable error detected on IO96B_%d\n",
+				       i);
+				goto err;
+			}
+		}
+	}
+
+	*ecc_error_flag = false;
+
+err:
+	return ret;
+}
+
+int bist_mem_init_start(struct io96b_info *io96b_ctrl)
+{
+	struct io96b_mb_req usr_req;
+	struct io96b_mb_resp usr_resp;
+	int i, j, n, ret = 0;
+	bool bist_start, bist_success;
+	u32 start;
+
+	/* Full memory initialization BIST performed on all memory interface(s) */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+			bist_start = false;
+			bist_success = false;
+
+			/* Start memory initialization BIST on full memory address */
+			IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j],
+					   io96b_ctrl->io96b[i].mb_ctrl.ip_id[j],
+					   CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START,
+					   BIST_FULL_MEM);
+
+			ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr,
+					   usr_req, 0, &usr_resp);
+			if (ret)
+				goto err;
+
+			bist_start = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+				& BIT(0);
+
+			if (!bist_start) {
+				printf("%s: Failed to initialize memory on IO96B_%d\n", __func__,
+				       i);
+				printf("%s: BIST_MEM_INIT_START Error code 0x%lx\n", __func__,
+				       IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status));
+
+				ret = -EINVAL;
+				goto err;
+			}
+
+			/* Polling for the initiated memory initialization BIST status */
+			start = get_timer(0);
+			while (!bist_success) {
+				IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j],
+						   io96b_ctrl->io96b[i].mb_ctrl.ip_id[j],
+						   CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_STATUS, 0);
+
+				io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 0,
+					     &usr_resp);
+
+				bist_success =
+					IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+					& BIT(0);
+
+				if (!bist_success && (get_timer(start) > TIMEOUT)) {
+					printf("%s: Timeout initialize memory on IO96B_%d\n",
+					       __func__, i);
+					printf("%s: BIST_MEM_INIT_STATUS Error code 0x%lx\n",
+					       __func__,
+					IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status));
+
+					ret = -ETIMEDOUT;
+					goto err;
+				}
+
+				udelay(1);
+			}
+		}
+
+		debug("%s: Memory initialized successfully on IO96B_%d\n", __func__, i);
+	}
+
+err:
+	return ret;
+}
diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h
new file mode 100644
index 00000000000..49320f8211b
--- /dev/null
+++ b/drivers/ddr/altera/iossm_mailbox.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#define TIMEOUT_120000MS			120000
+#define TIMEOUT_60000MS				60000
+#define TIMEOUT					TIMEOUT_120000MS
+#define IOSSM_STATUS_CAL_SUCCESS		BIT(0)
+#define IOSSM_STATUS_CAL_FAIL			BIT(1)
+#define IOSSM_STATUS_CAL_BUSY			BIT(2)
+#define IOSSM_STATUS_COMMAND_RESPONSE_READY	BIT(0)
+#define IOSSM_CMD_RESPONSE_STATUS_OFFSET	0x45C
+#define IOSSM_CMD_RESPONSE_DATA_0_OFFSET	0x458
+#define IOSSM_CMD_RESPONSE_DATA_1_OFFSET	0x454
+#define IOSSM_CMD_RESPONSE_DATA_2_OFFSET	0x450
+#define IOSSM_CMD_REQ_OFFSET			0x43C
+#define IOSSM_CMD_PARAM_0_OFFSET		0x438
+#define IOSSM_CMD_PARAM_1_OFFSET		0x434
+#define IOSSM_CMD_PARAM_2_OFFSET		0x430
+#define IOSSM_CMD_PARAM_3_OFFSET		0x42C
+#define IOSSM_CMD_PARAM_4_OFFSET		0x428
+#define IOSSM_CMD_PARAM_5_OFFSET		0x424
+#define IOSSM_CMD_PARAM_6_OFFSET		0x420
+#define IOSSM_STATUS_OFFSET			0x400
+#define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK	GENMASK(31, 16)
+#define IOSSM_CMD_RESPONSE_DATA_SHORT(n)	FIELD_GET(IOSSM_CMD_RESPONSE_DATA_SHORT_MASK, n)
+#define IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK	GENMASK(7, 5)
+#define IOSSM_STATUS_CMD_RESPONSE_ERROR(n)	FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n)
+#define IOSSM_STATUS_GENERAL_ERROR_MASK		GENMASK(4, 1)
+#define IOSSM_STATUS_GENERAL_ERROR(n)		FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n)
+#define MAX_IO96B_SUPPORTED			2
+#define NUM_CMD_RESPONSE_DATA			3
+#define NUM_CMD_PARAM				6
+
+/* supported mailbox command type */
+enum iossm_mailbox_cmd_type  {
+	CMD_NOP,
+	CMD_GET_SYS_INFO,
+	CMD_GET_MEM_INFO,
+	CMD_GET_MEM_CAL_INFO,
+	CMD_TRIG_CONTROLLER_OP,
+	CMD_TRIG_MEM_CAL_OP
+};
+
+/* supported mailbox command opcode */
+enum iossm_mailbox_cmd_opcode  {
+	GET_MEM_INTF_INFO = 0x0001,
+	GET_MEM_TECHNOLOGY,
+	GET_MEMCLK_FREQ_KHZ,
+	GET_MEM_WIDTH_INFO,
+	ECC_ENABLE_SET = 0x0101,
+	ECC_ENABLE_STATUS,
+	ECC_INTERRUPT_STATUS,
+	ECC_INTERRUPT_ACK,
+	ECC_INTERRUPT_MASK,
+	ECC_WRITEBACK_ENABLE,
+	ECC_GET_SBE_INFO,
+	ECC_GET_DBE_INFO,
+	ECC_INJECT_ERROR,
+	ECC_SCRUB_IN_PROGRESS_STATUS = 0x0201,
+	ECC_SCRUB_MODE_0_START,
+	ECC_SCRUB_MODE_1_START,
+	BIST_STANDARD_MODE_START = 0x0301,
+	BIST_RESULTS_STATUS,
+	BIST_MEM_INIT_START,
+	BIST_MEM_INIT_STATUS,
+	BIST_SET_DATA_PATTERN_UPPER,
+	BIST_SET_DATA_PATTERN_LOWER,
+	TRIG_MEM_CAL = 0x000a,
+	GET_MEM_CAL_STATUS
+};
+
+/* response data of cmd opcode GET_MEM_INTF_INFO */
+#define INTF_IP_TYPE_MASK		GENMASK(31, 29)
+#define INTF_INSTANCE_ID_MASK		GENMASK(28, 24)
+
+/* response data of cmd opcode GET_MEM_CAL_STATUS */
+#define INTF_UNUSED			0x0
+#define INTF_MEM_CAL_STATUS_SUCCESS	0x1
+#define INTF_MEM_CAL_STATUS_FAIL	0x2
+#define INTF_MEM_CAL_STATUS_ONGOING	0x4
+
+/* cmd opcode BIST_MEM_INIT_START, BIST performed on full memory address range */
+#define BIST_FULL_MEM			BIT(6)
+
+/*
+ * IOSSM mailbox required information
+ *
+ * @num_mem_interface:	Number of memory interfaces instantiated
+ * @ip_type:		IP type implemented on the IO96B
+ * @ip_instance_id:	IP identifier for every IP instance implemented on the IO96B
+ */
+struct io96b_mb_ctrl {
+	u32 num_mem_interface;
+	u32 ip_type[2];
+	u32 ip_id[2];
+};
+
+/* CMD_REQ Register Definition */
+#define CMD_TARGET_IP_TYPE_MASK		GENMASK(31, 29)
+#define CMD_TARGET_IP_INSTANCE_ID_MASK	GENMASK(28, 24)
+#define CMD_TYPE_MASK			GENMASK(23, 16)
+#define CMD_OPCODE_MASK			GENMASK(15, 0)
+
+/*
+ * IOSSM mailbox request
+ * @ip_type:	    IP type for the specified memory interface
+ * @ip_id:	    IP instance ID for the specified memory interface
+ * @usr_cmd_type:   User desire IOSSM mailbox command type
+ * @usr_cmd_opcode: User desire IOSSM mailbox command opcode
+ * @cmd_param_*:    Parameters (if applicable) for the requested IOSSM mailbox command
+ */
+struct io96b_mb_req {
+	u32 ip_type;
+	u32 ip_id;
+	u32 usr_cmd_type;
+	u32 usr_cmd_opcode;
+	u32 cmd_param[NUM_CMD_PARAM];
+};
+
+/*
+ * IOSSM mailbox response outputs
+ *
+ * @cmd_resp_status: Command Interface status
+ * @cmd_resp_data_*: More spaces for command response
+ */
+struct io96b_mb_resp {
+	u32 cmd_resp_status;
+	u32 cmd_resp_data[NUM_CMD_RESPONSE_DATA];
+};
+
+/*
+ * IO96B instance specific information
+ *
+ * @size:		Memory size
+ * @io96b_csr_addr:	IO96B instance CSR address
+ * @cal_status:		IO96B instance calibration status
+ * @mb_ctrl:		IOSSM mailbox required information
+ */
+struct io96b_instance {
+	u16 size;
+	phys_addr_t io96b_csr_addr;
+	bool cal_status;
+	struct io96b_mb_ctrl mb_ctrl;
+};
+
+/*
+ * Overall IO96B instance(s) information
+ *
+ * @num_instance:	Number of instance(s) assigned to HPS
+ * @overall_cal_status: Overall calibration status for all IO96B instance(s)
+ * @ddr_type:		DDR memory type
+ * @ecc_status:		ECC enable status (false = disabled, true = enabled)
+ * @overall_size:	Total DDR memory size
+ * @io96b[]:		IO96B instance specific information
+ * @ckgen_lock:		IO96B GEN PLL lock (false = not locked, true = locked)
+ * @num_port:		Number of IO96B port.
+ * @io96b_pll:		Selected IO96B PLL. Example bit 0: EMIF0 PLL A selected,
+ *			bit 1: EMIF0 PLL B selected, bit 2 - EMIF1 PLL A selected,
+ *			bit 3: EMIF1 PLL B selected
+ */
+struct io96b_info {
+	u8 num_instance;
+	bool overall_cal_status;
+	const char *ddr_type;
+	bool ecc_status;
+	u16 overall_size;
+	struct io96b_instance io96b[MAX_IO96B_SUPPORTED];
+	bool ckgen_lock;
+	u8 num_port;
+	u8 io96b_pll;
+};
+
+int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req,
+		 u32 resp_data_len, struct io96b_mb_resp *resp);
+
+/* Supported IOSSM mailbox function */
+void io96b_mb_init(struct io96b_info *io96b_ctrl);
+int io96b_cal_status(phys_addr_t addr);
+void init_mem_cal(struct io96b_info *io96b_ctrl);
+int get_mem_technology(struct io96b_info *io96b_ctrl);
+int get_mem_width_info(struct io96b_info *io96b_ctrl);
+int ecc_enable_status(struct io96b_info *io96b_ctrl);
+int bist_mem_init_start(struct io96b_info *io96b_ctrl);
+int ecc_interrupt_status(struct io96b_info *io96b_ctrl, bool *ecc_error_flag);
diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c
new file mode 100644
index 00000000000..160b945b55f
--- /dev/null
+++ b/drivers/ddr/altera/sdram_agilex5.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include <div64.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <hang.h>
+#include <log.h>
+#include <ram.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <wdt.h>
+#include <linux/bitfield.h>
+#include <linux/sizes.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include "iossm_mailbox.h"
+#include "sdram_soc64.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* MPFE NOC registers */
+#define F2SDRAM_SIDEBAND_FLAGOUTSET0	0x50
+#define F2SDRAM_SIDEBAND_FLAGOUTSTATUS0	0x58
+#define SIDEBANDMGR_FLAGOUTSET0_REG	SOCFPGA_F2SDRAM_MGR_ADDRESS +\
+					F2SDRAM_SIDEBAND_FLAGOUTSET0
+#define SIDEBANDMGR_FLAGOUTSTATUS0_REG	SOCFPGA_F2SDRAM_MGR_ADDRESS +\
+					F2SDRAM_SIDEBAND_FLAGOUTSTATUS0
+
+#define BOOT_SCRATCH_COLD3_REG	(socfpga_get_sysmgr_addr() +\
+				 SYSMGR_SOC64_BOOT_SCRATCH_COLD3)
+
+#define PORT_EMIF_CONFIG_OFFSET 4
+#define EMIF_PLL_MASK	GENMASK(19, 16)
+
+#define IO96B0_DUAL_PORT_MASK		BIT(0)
+#define IO96B0_DUAL_EMIF_MASK		BIT(1)
+
+#define FIREWALL_MPFE_SCR_IO96B0_REG		0x18000d00
+#define FIREWALL_MPFE_SCR_IO96B1_REG		0x18000d04
+#define FIREWALL_MPFE_NOC_CSR_REG		0x18000d08
+
+/* Reset type */
+enum reset_type {
+	POR_RESET,
+	WARM_RESET,
+	COLD_RESET,
+	NCONFIG,
+	JTAG_CONFIG,
+	RSU_RECONFIG
+};
+
+phys_addr_t io96b_csr_reg_addr[] = {
+	0x18400000, /* IO96B_0 CSR registers address */
+	0x18800000  /* IO96B_1 CSR registers address */
+};
+
+static enum reset_type get_reset_type(u32 reg)
+{
+	return FIELD_GET(ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK, reg);
+}
+
+static void update_io96b_assigned_to_hps(bool dual_port_flag, bool dual_emif_flag)
+{
+	clrsetbits_le32(BOOT_SCRATCH_COLD3_REG,
+			ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK,
+			FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK, dual_port_flag) |
+			FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK, dual_emif_flag));
+
+	debug("%s: update dual port dual emif info: 0x%x\n", __func__,
+	      readl(BOOT_SCRATCH_COLD3_REG));
+}
+
+static void set_mpfe_config(void)
+{
+	/* Set mpfe_lite_intfcsel */
+	setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(2));
+
+	/* Set mpfe_lite_active */
+	setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(8));
+
+	debug("%s: mpfe_config: 0x%x\n", __func__,
+	      readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG));
+}
+
+static bool is_ddr_init_hang(void)
+{
+	u32 reg = readl(socfpga_get_sysmgr_addr() +
+			SYSMGR_SOC64_BOOT_SCRATCH_POR0);
+
+	debug("%s: 0x%x\n", __func__, reg);
+
+	if (reg & ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK)
+		return true;
+
+	return false;
+}
+
+static void ddr_init_inprogress(bool start)
+{
+	if (start)
+		setbits_le32(socfpga_get_sysmgr_addr() +
+				SYSMGR_SOC64_BOOT_SCRATCH_POR0,
+				ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK);
+	else
+		clrbits_le32(socfpga_get_sysmgr_addr() +
+				SYSMGR_SOC64_BOOT_SCRATCH_POR0,
+				ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK);
+}
+
+static void populate_ddr_handoff(struct udevice *dev, struct io96b_info *io96b_ctrl)
+{
+	struct altera_sdram_plat *plat = dev_get_plat(dev);
+	int i;
+	u32 len = SOC64_HANDOFF_SDRAM_LEN;
+	u32 handoff_table[len];
+
+	/* Read handoff for DDR configuration */
+	socfpga_handoff_read((void *)SOC64_HANDOFF_SDRAM, handoff_table, len);
+
+	/* Read handoff - dual port */
+	plat->dualport = FIELD_GET(IO96B0_DUAL_PORT_MASK, handoff_table[PORT_EMIF_CONFIG_OFFSET]);
+	debug("%s: dualport from handoff: 0x%x\n", __func__, plat->dualport);
+
+	if (plat->dualport)
+		io96b_ctrl->num_port = 2;
+	else
+		io96b_ctrl->num_port = 1;
+
+	/* Read handoff - dual EMIF */
+	plat->dualemif = FIELD_GET(IO96B0_DUAL_EMIF_MASK, handoff_table[PORT_EMIF_CONFIG_OFFSET]);
+	debug("%s: dualemif from handoff: 0x%x\n", __func__, plat->dualemif);
+
+	if (plat->dualemif)
+		io96b_ctrl->num_instance = 2;
+	else
+		io96b_ctrl->num_instance = 1;
+
+	io96b_ctrl->io96b_pll = FIELD_GET(EMIF_PLL_MASK,
+					  handoff_table[PORT_EMIF_CONFIG_OFFSET]);
+	debug("%s: io96b enabled pll from handoff: 0x%x\n", __func__, io96b_ctrl->io96b_pll);
+
+	update_io96b_assigned_to_hps(plat->dualport, plat->dualemif);
+
+	/* Assign IO96B CSR base address if it is valid */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		io96b_ctrl->io96b[i].io96b_csr_addr = io96b_csr_reg_addr[i];
+		debug("%s: IO96B 0x%llx CSR enabled\n", __func__,
+		      io96b_ctrl->io96b[i].io96b_csr_addr);
+	}
+}
+
+static void config_mpfe_sideband_mgr(struct udevice *dev)
+{
+	struct altera_sdram_plat *plat = dev_get_plat(dev);
+
+	/* Dual port setting */
+	if (plat->dualport)
+		setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(4));
+
+	/* Dual EMIF setting */
+	if (plat->dualemif) {
+		set_mpfe_config();
+		setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(5));
+	}
+
+	debug("%s: SIDEBANDMGR_FLAGOUTSTATUS0: 0x%x\n", __func__,
+	      readl(SIDEBANDMGR_FLAGOUTSTATUS0_REG));
+}
+
+static void config_ccu_mgr(struct udevice *dev)
+{
+	int ret = 0;
+	struct altera_sdram_plat *plat = dev_get_plat(dev);
+
+	if (plat->dualport || plat->dualemif) {
+		debug("%s: config interleaving on ccu reg\n", __func__);
+		ret = uclass_get_device_by_name(UCLASS_NOP,
+						"socfpga-ccu-ddr-interleaving-on", &dev);
+	} else {
+		debug("%s: config interleaving off ccu reg\n", __func__);
+		ret = uclass_get_device_by_name(UCLASS_NOP,
+						"socfpga-ccu-ddr-interleaving-off", &dev);
+	}
+
+	if (ret) {
+		printf("interleaving on/off ccu settings init failed: %d\n", ret);
+		hang();
+	}
+}
+
+static void config_firewall_mpfe_csr(struct udevice *dev)
+{
+	int ret = 0;
+
+	debug("%s: config Firewall setting for MPFE CSR\n", __func__);
+	ret = uclass_get_device_by_name(UCLASS_NOP,
+					"socfpga-noc-fw-mpfe-csr", &dev);
+
+	if (ret) {
+		printf("Firewall setting for MPFE CSR init failed: %d\n", ret);
+		hang();
+	}
+}
+
+static bool hps_ocram_dbe_status(void)
+{
+	u32 reg = readl(BOOT_SCRATCH_COLD3_REG);
+
+	if (reg & ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK)
+		return true;
+
+	return false;
+}
+
+int sdram_mmr_init_full(struct udevice *dev)
+{
+	int ret = 0;
+	phys_size_t hw_size;
+	struct bd_info bd = {0};
+	struct altera_sdram_plat *plat = dev_get_plat(dev);
+	struct altera_sdram_priv *priv = dev_get_priv(dev);
+	struct io96b_info *io96b_ctrl = malloc(sizeof(*io96b_ctrl));
+
+	u32 reg = readl(BOOT_SCRATCH_COLD3_REG);
+	enum reset_type reset_t = get_reset_type(reg);
+	bool full_mem_init = false;
+
+	/* DDR initialization progress status tracking */
+	bool is_ddr_hang_be4_rst = is_ddr_init_hang();
+
+	debug("DDR: SDRAM init in progress ...\n");
+	ddr_init_inprogress(true);
+
+	debug("DDR: Address MPFE 0x%llx\n", plat->mpfe_base_addr);
+
+	/* Populating DDR handoff data */
+	debug("DDR: Checking SDRAM configuration in progress ...\n");
+	populate_ddr_handoff(dev, io96b_ctrl);
+
+	/* Configuring MPFE sideband manager registers - dual port & dual emif*/
+	config_mpfe_sideband_mgr(dev);
+
+	/* Configuring Interleave/Non-interleave ccu registers */
+	config_ccu_mgr(dev);
+
+	/* Configure if polling is needed for IO96B GEN PLL locked */
+	io96b_ctrl->ckgen_lock = true;
+
+	/* Ensure calibration status passing */
+	init_mem_cal(io96b_ctrl);
+
+	printf("DDR: Calibration success\n");
+
+	/* Initiate IOSSM mailbox */
+	io96b_mb_init(io96b_ctrl);
+
+	/* DDR type, DDR size and ECC status) */
+	ret = get_mem_technology(io96b_ctrl);
+	if (ret) {
+		printf("DDR: Failed to get DDR type\n");
+
+		goto err;
+	}
+
+	ret = get_mem_width_info(io96b_ctrl);
+	if (ret) {
+		printf("DDR: Failed to get DDR size\n");
+
+		goto err;
+	}
+
+	hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8;
+
+	/* Get bank configuration from devicetree */
+	ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
+				     (phys_size_t *)&gd->ram_size, &bd);
+	if (ret) {
+		puts("DDR: Failed to decode memory node\n");
+		ret = -ENXIO;
+
+		goto err;
+	}
+
+	if (gd->ram_size != hw_size) {
+		printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",
+		       gd->ram_size >> 20);
+		printf(" mismatch with hardware (%lld MiB).\n",
+		       hw_size >> 20);
+	}
+
+	if (gd->ram_size > hw_size) {
+		printf("DDR: Error: DRAM size from device tree is greater\n");
+		printf(" than hardware size.\n");
+		hang();
+	}
+
+	printf("%s: %lld MiB\n", io96b_ctrl->ddr_type, gd->ram_size >> 20);
+
+	ret = ecc_enable_status(io96b_ctrl);
+	if (ret) {
+		printf("DDR: Failed to get ECC enabled status\n");
+
+		goto err;
+	}
+
+	/* Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC
+	 *  enabled to preserve memory content
+	 */
+	if (io96b_ctrl->ecc_status) {
+		bool ecc_error_flag;
+
+		ret = ecc_interrupt_status(io96b_ctrl, &ecc_error_flag);
+		if (ret) {
+			printf("DDR: Failed to get ECC interrupt status\n");
+
+			goto err;
+		}
+
+		if (ecc_error_flag) {
+			if (CONFIG_IS_ENABLED(WDT)) {
+				struct udevice *wdt;
+
+				printf("DDR: ECC error recover start now\n");
+				ret = uclass_first_device_err(UCLASS_WDT, &wdt);
+				if (ret) {
+					printf("DDR: Failed to trigger watchdog reset\n");
+					hang();
+				}
+
+				wdt_expire_now(wdt, 0);
+			}
+			hang();
+		}
+
+		full_mem_init = hps_ocram_dbe_status() | is_ddr_hang_be4_rst;
+		if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) {
+			ret = bist_mem_init_start(io96b_ctrl);
+			if (ret) {
+				printf("DDR: Failed to fully initialize DDR memory\n");
+
+				goto err;
+			}
+		}
+
+		printf("SDRAM-ECC: Initialized success\n");
+	}
+
+	sdram_size_check(&bd);
+	printf("DDR: size check success\n");
+
+	sdram_set_firewall(&bd);
+
+	/* Firewall setting for MPFE CSR */
+	config_firewall_mpfe_csr(dev);
+
+	printf("DDR: firewall init success\n");
+
+	priv->info.base = bd.bi_dram[0].start;
+	priv->info.size = gd->ram_size;
+
+	/* Ending DDR driver initialization success tracking */
+	ddr_init_inprogress(false);
+
+	printf("DDR: init success\n");
+
+err:
+	free(io96b_ctrl);
+
+	return ret;
+}
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index 9e57c2ecfa4..ce286cc2e76 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
- *
+ * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
  */
 
 #include <cpu_func.h>
@@ -27,6 +26,7 @@
 
 #define PGTABLE_OFF	0x4000
 
+#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
 u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
 {
 	return readl(plat->iomhc + reg);
@@ -98,8 +98,9 @@ int emif_reset(struct altera_sdram_plat *plat)
 	debug("DDR: %s triggered successly\n", __func__);
 	return 0;
 }
+#endif
 
-#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
 int poll_hmc_clock_status(void)
 {
 	return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
@@ -251,7 +252,7 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
 	return size;
 }
 
-void sdram_set_firewall(struct bd_info *bd)
+static void sdram_set_firewall_non_f2sdram(struct bd_info *bd)
 {
 	u32 i;
 	phys_size_t value;
@@ -287,7 +288,7 @@ void sdram_set_firewall(struct bd_info *bd)
 				      FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT +
 				      (i * 4 * sizeof(u32)));
 
-		/* Setting non-secure MPU limit and limit extexded */
+		/* Setting non-secure MPU limit and limit extended */
 		value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
 
 		lower = lower_32_bits(value);
@@ -300,7 +301,7 @@ void sdram_set_firewall(struct bd_info *bd)
 				      FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT +
 				      (i * 4 * sizeof(u32)));
 
-		/* Setting non-secure Non-MPU limit and limit extexded */
+		/* Setting non-secure Non-MPU limit and limit extended */
 		FW_MPU_DDR_SCR_WRITEL(lower,
 				      FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT +
 				      (i * 4 * sizeof(u32)));
@@ -313,6 +314,61 @@ void sdram_set_firewall(struct bd_info *bd)
 	}
 }
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+static void sdram_set_firewall_f2sdram(struct bd_info *bd)
+{
+	u32 i, lower, upper;
+	phys_size_t value;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		if (!bd->bi_dram[i].size)
+			continue;
+
+		value = bd->bi_dram[i].start;
+
+		/* Keep first 1MB of SDRAM memory region as secure region when
+		 * using ATF flow, where the ATF code is located.
+		 */
+		if (IS_ENABLED(CONFIG_SPL_ATF) && i == 0)
+			value += SZ_1M;
+
+		/* Setting base and base extended */
+		lower = lower_32_bits(value);
+		upper = upper_32_bits(value);
+		FW_F2SDRAM_DDR_SCR_WRITEL(lower,
+					  FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE +
+					  (i * 4 * sizeof(u32)));
+		FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff,
+					  FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT +
+					  (i * 4 * sizeof(u32)));
+
+		/* Setting limit and limit extended */
+		value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
+
+		lower = lower_32_bits(value);
+		upper = upper_32_bits(value);
+
+		FW_F2SDRAM_DDR_SCR_WRITEL(lower,
+					  FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT +
+					  (i * 4 * sizeof(u32)));
+		FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff,
+					  FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT +
+					  (i * 4 * sizeof(u32)));
+
+		FW_F2SDRAM_DDR_SCR_WRITEL(BIT(i), FW_F2SDRAM_DDR_SCR_EN_SET);
+	}
+}
+#endif
+
+void sdram_set_firewall(struct bd_info *bd)
+{
+	sdram_set_firewall_non_f2sdram(bd);
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+	sdram_set_firewall_f2sdram(bd);
+#endif
+}
+
 static int altera_sdram_of_to_plat(struct udevice *dev)
 {
 	struct altera_sdram_plat *plat = dev_get_plat(dev);
@@ -321,7 +377,12 @@ static int altera_sdram_of_to_plat(struct udevice *dev)
 	/* These regs info are part of DDR handoff in bitstream */
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 	return 0;
-#endif
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+	addr = dev_read_addr_index(dev, 0);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	plat->mpfe_base_addr = addr;
+#else
 
 	addr = dev_read_addr_index(dev, 0);
 	if (addr == FDT_ADDR_T_NONE)
@@ -337,7 +398,7 @@ static int altera_sdram_of_to_plat(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 	plat->hmc = (void __iomem *)addr;
-
+#endif
 	return 0;
 }
 
@@ -384,6 +445,7 @@ static const struct udevice_id altera_sdram_ids[] = {
 	{ .compatible = "altr,sdr-ctl-s10" },
 	{ .compatible = "intel,sdr-ctl-agilex" },
 	{ .compatible = "intel,sdr-ctl-n5x" },
+	{ .compatible = "intel,sdr-ctl-agilex5" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 87a70a861ba..f75a1e47cc3 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2024 Intel Corporation <www.intel.com>
  */
 
 #ifndef	_SDRAM_SOC64_H_
@@ -13,11 +13,19 @@ struct altera_sdram_priv {
 	struct reset_ctl_bulk resets;
 };
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+struct altera_sdram_plat {
+	fdt_addr_t mpfe_base_addr;
+	bool dualport;
+	bool dualemif;
+};
+#else
 struct altera_sdram_plat {
 	void __iomem *hmc;
 	void __iomem *ddr_sch;
 	void __iomem *iomhc;
 };
+#endif
 
 /* ECC HMC registers */
 #define DDRIOCTRL			0x8
@@ -65,6 +73,8 @@ struct altera_sdram_plat {
 #define CTRLCFG0			0x28
 #define CTRLCFG1			0x2c
 #define CTRLCFG3                        0x34
+#define CTRLCFG5                        0x3c
+#define CTRLCFG6                        0x40
 #define DRAMTIMING0			0x50
 #define CALTIMING0			0x7c
 #define CALTIMING1			0x80
@@ -79,7 +89,7 @@ struct altera_sdram_plat {
 #define NIOSRESERVED2			0x118
 
 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x)			\
-	(((x) >> 0) & 0x1F)
+	((x) & 0x1F)
 #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x)			\
 	(((x) >> 5) & 0x1F)
 #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x)		\
@@ -90,7 +100,7 @@ struct altera_sdram_plat {
 	(((x) >> 16) & 0x7)
 
 #define CTRLCFG0_CFG_MEMTYPE(x)				\
-	(((x) >> 0) & 0xF)
+	((x) & 0xF)
 #define CTRLCFG0_CFG_DIMM_TYPE(x)			\
 	(((x) >> 4) & 0x7)
 #define CTRLCFG0_CFG_AC_POS(x)				\
@@ -99,17 +109,17 @@ struct altera_sdram_plat {
 	(((x) >> 9) & 0x1F)
 
 #define CTRLCFG1_CFG_DBC3_BURST_LEN(x)			\
-	(((x) >> 0) & 0x1F)
+	((x) & 0x1F)
 #define CTRLCFG1_CFG_ADDR_ORDER(x)			\
 	(((x) >> 5) & 0x3)
 #define CTRLCFG1_CFG_CTRL_EN_ECC(x)			\
 	(((x) >> 7) & 0x1)
 
 #define DRAMTIMING0_CFG_TCL(x)				\
-	(((x) >> 0) & 0x7F)
+	((x) & 0x7F)
 
 #define CALTIMING0_CFG_ACT_TO_RDWR(x)			\
-	(((x) >> 0) & 0x3F)
+	((x) & 0x3F)
 #define CALTIMING0_CFG_ACT_TO_PCH(x)			\
 	(((x) >> 6) & 0x3F)
 #define CALTIMING0_CFG_ACT_TO_ACT(x)			\
@@ -118,7 +128,7 @@ struct altera_sdram_plat {
 	(((x) >> 18) & 0x3F)
 
 #define CALTIMING1_CFG_RD_TO_RD(x)			\
-	(((x) >> 0) & 0x3F)
+	((x) & 0x3F)
 #define CALTIMING1_CFG_RD_TO_RD_DC(x)			\
 	(((x) >> 6) & 0x3F)
 #define CALTIMING1_CFG_RD_TO_RD_DB(x)			\
@@ -129,7 +139,7 @@ struct altera_sdram_plat {
 	(((x) >> 24) & 0x3F)
 
 #define CALTIMING2_CFG_RD_TO_WR_DB(x)			\
-	(((x) >> 0) & 0x3F)
+	((x) & 0x3F)
 #define CALTIMING2_CFG_RD_TO_WR_PCH(x)			\
 	(((x) >> 6) & 0x3F)
 #define CALTIMING2_CFG_RD_AP_TO_VALID(x)		\
@@ -140,7 +150,7 @@ struct altera_sdram_plat {
 	(((x) >> 24) & 0x3F)
 
 #define CALTIMING3_CFG_WR_TO_WR_DB(x)			\
-	(((x) >> 0) & 0x3F)
+	((x) & 0x3F)
 #define CALTIMING3_CFG_WR_TO_RD(x)			\
 	(((x) >> 6) & 0x3F)
 #define CALTIMING3_CFG_WR_TO_RD_DC(x)			\
@@ -151,7 +161,7 @@ struct altera_sdram_plat {
 	(((x) >> 24) & 0x3F)
 
 #define CALTIMING4_CFG_WR_AP_TO_VALID(x)		\
-	(((x) >> 0) & 0x3F)
+	((x) & 0x3F)
 #define CALTIMING4_CFG_PCH_TO_VALID(x)			\
 	(((x) >> 6) & 0x3F)
 #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x)		\
@@ -162,7 +172,7 @@ struct altera_sdram_plat {
 	(((x) >> 26) & 0x3F)
 
 #define CALTIMING9_CFG_4_ACT_TO_ACT(x)			\
-	(((x) >> 0) & 0xFF)
+	((x) & 0xFF)
 
 /* Firewall DDR scheduler MPFE */
 #define FW_HMC_ADAPTOR_REG_ADDR			0xf8020004
-- 
2.25.1

[PATCH v1 17/20] arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add SPL support for Agilex5 SoCFPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/Makefile      |  3 ++
 arch/arm/mach-socfpga/spl_agilex5.c | 84 +++++++++++++++++++++++++++++
 2 files changed, 87 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 32b3e7a57e2..3fbe3d4fa63 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -66,6 +66,8 @@ obj-y	+= reset_manager_s10.o
 obj-y	+= wrap_handoff_soc64.o
 obj-y	+= wrap_pll_config_soc64.o
 obj-y	+= ccu_ncore3.o
+obj-y	+= system_manager_soc64.o
+obj-y	+= timer_s10.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_N5X
@@ -109,6 +111,7 @@ obj-y	+= spl_n5x.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
 obj-y	+= spl_soc64.o
+obj-y	+= spl_agilex5.o
 endif
 else
 obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c
new file mode 100644
index 00000000000..2852112f788
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_agilex5.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <hang.h>
+#include <spl.h>
+#include <asm/arch/base_addr_soc64.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <wdt.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_managers_addr();
+
+	sysmgr_pinmux_init();
+
+	/* Ensure watchdog is paused when debugging is happening */
+	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+	timer_init();
+
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	if (ret) {
+		debug("Clock init failed: %d\n", ret);
+		hang();
+	}
+
+	/*
+	 * Enable watchdog as early as possible before initializing other
+	 * component. Watchdog need to be enabled after clock driver because
+	 * it will retrieve the clock frequency from clock driver.
+	 */
+	if (CONFIG_IS_ENABLED(WDT))
+		initr_watchdog();
+
+	preloader_console_init();
+	print_reset_info();
+	cm_print_clock_quick_summary();
+
+	ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-ccu-config", &dev);
+	if (ret) {
+		printf("HPS CCU settings init failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-firewall-config", &dev);
+	if (ret) {
+		printf("HPS firewall settings init failed: %d\n", ret);
+		hang();
+	}
+
+	if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) {
+		ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+		if (ret) {
+			debug("DRAM init failed: %d\n", ret);
+			hang();
+		}
+	}
+
+	mbox_init();
+
+	if (IS_ENABLED(CONFIG_CADENCE_QSPI))
+		mbox_qspi_open();
+}
-- 
2.25.1

[PATCH v1 18/20] configs: socfpga: soc64: agilex5: Enable XGMAC

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enable XGMAC for SoCFPGA Agilex5 devkit.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 configs/socfpga_agilex5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index 81bbe967dcf..a4a5064d9c2 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -92,3 +92,4 @@ CONFIG_WDT=y
 CONFIG_PANIC_HANG=y
 CONFIG_SPL_CRC32=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_DWC_ETH_XGMAC=y
-- 
2.25.1

[PATCH v1 19/20] arm: socfpga: soc64: Add support for board_boot_order()

[tien.fong.chee]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add board_boot_order() to retrieve the list of boot devices from
spl-boot-order property in device tree. This board_boot_order()
would be used for all Intel SOC64 devices.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/spl_soc64.c | 103 ++++++++++++++++++++++++++++++
 1 file changed, 103 insertions(+)

diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c
index 3bfe4bb9dd3..9bfa15e9ded 100644
--- a/arch/arm/mach-socfpga/spl_soc64.c
+++ b/arch/arm/mach-socfpga/spl_soc64.c
@@ -15,6 +15,109 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_MMC1;
 }
 
+/* This function is to map specified node onto SPL boot devices */
+static int spl_node_to_boot_device(int node)
+{
+	const void *blob = gd->fdt_blob;
+	struct udevice *parent;
+	const char *prop;
+
+	if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent))
+		return BOOT_DEVICE_MMC1;
+	else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
+		return BOOT_DEVICE_SPI;
+	else if (!uclass_get_device_by_of_offset(UCLASS_MTD, node, &parent))
+		return BOOT_DEVICE_NAND;
+
+	prop = fdt_getprop(blob, node, "device_type", NULL);
+	if (prop) {
+		if (!strcmp(prop, "memory"))
+			return BOOT_DEVICE_RAM;
+
+		printf("%s: unknown device_type %s\n", __func__, prop);
+	}
+
+	return -ENODEV;
+}
+
+static void default_spl_boot_list(u32 *spl_boot_list, int length)
+{
+	spl_boot_list[0] = spl_boot_device();
+
+	if (length > 1)
+		spl_boot_list[1] = BOOT_DEVICE_SPI;
+
+	if (length > 2)
+		spl_boot_list[2] = BOOT_DEVICE_NAND;
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	int idx = 0;
+	const void *blob = gd->fdt_blob;
+	int chosen_node = fdt_path_offset(blob, "/chosen");
+	const char *conf;
+	int elem;
+	int boot_device;
+	int node;
+	int length;
+
+	/* expect valid initialized spl_boot_list */
+	if (!spl_boot_list)
+		return;
+
+	length = 1;
+	while (spl_boot_list[length] == spl_boot_list[length - 1])
+		length++;
+
+	debug("%s: chosen_node is %d\n", __func__, chosen_node);
+	if (chosen_node < 0) {
+		printf("%s: /chosen not found, using default\n", __func__);
+		default_spl_boot_list(spl_boot_list, length);
+		return;
+	}
+
+	for (elem = 0;
+	    (conf = fdt_stringlist_get(blob, chosen_node,
+			"u-boot,spl-boot-order", elem, NULL));
+	    elem++) {
+		if (idx >= length) {
+			printf("%s: limit %d to spl_boot_list exceeded\n", __func__,
+			       length);
+			break;
+		}
+
+		/* Resolve conf item as a path in device tree */
+		node = fdt_path_offset(blob, conf);
+		if (node < 0) {
+			debug("%s: could not find %s in FDT\n", __func__, conf);
+			continue;
+		}
+
+		/* Try to map spl node back onto SPL boot devices */
+		boot_device = spl_node_to_boot_device(node);
+		if (boot_device < 0) {
+			debug("%s: could not map node @%x to a boot-device\n",
+			      __func__, node);
+			continue;
+		}
+
+		spl_boot_list[idx] = boot_device;
+		debug("%s: spl_boot_list[%d] = %u\n", __func__, idx,
+		      spl_boot_list[idx]);
+		idx++;
+	}
+
+	if (idx == 0) {
+		if (!conf && !elem) {
+			printf("%s: spl-boot-order invalid, using default\n", __func__);
+			default_spl_boot_list(spl_boot_list, length);
+		} else {
+			printf("%s: no valid element spl-boot-order list\n", __func__);
+		}
+	}
+}
+
 #if IS_ENABLED(CONFIG_SPL_MMC)
 u32 spl_boot_mode(const u32 boot_device)
 {
-- 
2.25.1

[PATCH v1 20/20] configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS

[tien.fong.chee]

From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com>

Add the required configuration in the U-Boot env to enable Linux QSPI
boot with UBI / UBIFS.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 configs/socfpga_agilex5_defconfig      | 1 +
 include/configs/socfpga_soc64_common.h | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index a4a5064d9c2..4ac118f1fec 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -37,6 +37,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_CACHE=y
 CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_SPL_MTD=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000
 CONFIG_SPL_ATF=y
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index b7ee1dbf201..7a44f042165 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -56,6 +56,11 @@
 
 #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
 	"bootcmd_qspi=ubi detach; sf probe && " \
+	"setenv mtdids 'nor0=nor0,nand0=nand.0' && " \
+	"setenv mtdparts 'mtdparts=nor0:66m(u-boot),190m(root); " \
+	"nand.0:2m(nand_uboot),500m(nand_root)' && " \
+	"env select UBI; saveenv && " \
+	"ubi part root && " \
 	"if ubi part root && ubi readvol ${scriptaddr} script; " \
 	"then echo QSPI: Running script from UBIFS; " \
 	"elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \
-- 
2.25.1

Re: [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot

[Simon Glass]

Hi,

On Fri, 20 Sept 2024 at 09:03, <tien.fong.chee@intel.com> wrote:
>
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> This patch set introduces boot support for the Altera SoCFPGA Agilex 5
> platform in U-Boot. The changes include:
>         1. Board-specific configurations and setup required to enable Agilex 5
>            operation in U-Boot.
>         2. Integration of cache coherency unit (CCU) initialization routine,
>            including CCU conguration in DT.
>         3. Clock, firewall (configured in DT), SMMU, low level initialization
>            specific to Agilex 5.
>         4. Integration of memory initialization routine, including DDR setup.
>
> This patch set has been tested on Agilex 5 devkit with QSPI boot (UBI/UBIFS)
> and RAM boot (TFTP & ARM DS debugger).
>
> Alif Zakuan Yuslaimi (1):
>   configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS
>
> Tien Fong Chee (18):
>   arm: socfpga: agilex5: Add new system manager base addresses
>   arm: socfpga: Add support for agilex5 clock manager
>   linker: Add SPL linker script for SoC64 devices
>   arm: socfpga: agilex5: Add low level initialization
>   arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device
>   arm: dts: agilex5: Add HPS cache coherency unit configuration settings
>   arm: dts: agilex5: Add firewall configure settings
>   arm: dts: agilex5: Enable XGMAC
>   sysreset:  Add reset support to SoCFPGA Agilex5 device
>   arm: socfpga: agilex5: Enable cache flush for system memory cache in
>     CCU
>   arm: socfpga: agilex5: Add SMMU initialization
>   arm: socfpga: agilex5: Update CPU info
>   arm: socfpga: Export board ID as U-Boot environment variable
>   configs: agilex5: Add configuration for malloc pool
>   arm: socfpga: smc: Add memory coherency support to mailbox command
>   arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA
>   configs: socfpga: soc64: agilex5: Enable XGMAC
>   arm: socfpga: soc64: Add support for board_boot_order()
>
> Tingting Meng (1):
>   ddr: altera: Add DDR driver for Agilex5 series
>
>  MAINTAINERS                                   |   2 +
>  arch/arm/Kconfig                              |   1 +
>  arch/arm/dts/socfpga_agilex5-u-boot.dtsi      | 660 ++++++++++++++++++
>  arch/arm/dts/socfpga_agilex5.dtsi             |   7 +
>  .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi |  33 +
>  arch/arm/mach-socfpga/Makefile                |   6 +
>  arch/arm/mach-socfpga/ccu_ncore3.c            |  64 ++
>  arch/arm/mach-socfpga/include/mach/firewall.h |  23 +-
>  .../mach-socfpga/include/mach/handoff_soc64.h |   4 +-
>  arch/arm/mach-socfpga/include/mach/misc.h     |   1 +
>  .../include/mach/reset_manager_soc64.h        |  12 +-
>  .../include/mach/system_manager_soc64.h       | 129 ++--
>  arch/arm/mach-socfpga/lowlevel_init_agilex5.S |  57 ++
>  arch/arm/mach-socfpga/misc.c                  |  24 +-
>  arch/arm/mach-socfpga/misc_soc64.c            |  12 +-
>  arch/arm/mach-socfpga/smc_api.c               |  13 +-
>  arch/arm/mach-socfpga/spl_agilex5.c           |  84 +++
>  arch/arm/mach-socfpga/spl_soc64.c             | 120 +++-
>  arch/arm/mach-socfpga/u-boot-spl-soc64.lds    |  80 +++
>  arch/arm/mach-socfpga/wrap_handoff_soc64.c    |  10 +-
>  configs/socfpga_agilex5_defconfig             |   6 +
>  drivers/ddr/altera/Makefile                   |   1 +
>  drivers/ddr/altera/iossm_mailbox.c            | 613 ++++++++++++++++
>  drivers/ddr/altera/iossm_mailbox.h            | 186 +++++
>  drivers/ddr/altera/sdram_agilex5.c            | 377 ++++++++++
>  drivers/ddr/altera/sdram_soc64.c              |  78 ++-
>  drivers/ddr/altera/sdram_soc64.h              |  32 +-

Can we please put RAM drivers in drivers/ram ? Also, do make sure they
actually use UCLASS_RAM

>  drivers/sysreset/Kconfig                      |   7 +
>  drivers/sysreset/Makefile                     |   1 +
>  drivers/sysreset/sysreset_socfpga_agilex5.c   |  47 ++
>  include/configs/socfpga_soc64_common.h        |   5 +
>  31 files changed, 2605 insertions(+), 90 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/ccu_ncore3.c
>  create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S
>  create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c
>  create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds
>  create mode 100644 drivers/ddr/altera/iossm_mailbox.c
>  create mode 100644 drivers/ddr/altera/iossm_mailbox.h
>  create mode 100644 drivers/ddr/altera/sdram_agilex5.c
>  create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c
>
> --
> 2.25.1
>

Regards,
Simon

RE: [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Simon Glass <sjg@chromium.org>
> Sent: Friday, September 20, 2024 3:26 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>
> Cc: u-boot@lists.denx.de; Marek Vasut <marex@denx.de>; Simon
> Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-
> Boot
> 
> Hi,
> 
> On Fri, 20 Sept 2024 at 09:03, <tien.fong.chee@intel.com> wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > This patch set introduces boot support for the Altera SoCFPGA Agilex 5
> > platform in U-Boot. The changes include:
> >         1. Board-specific configurations and setup required to enable Agilex 5
> >            operation in U-Boot.
> >         2. Integration of cache coherency unit (CCU) initialization routine,
> >            including CCU conguration in DT.
> >         3. Clock, firewall (configured in DT), SMMU, low level initialization
> >            specific to Agilex 5.
> >         4. Integration of memory initialization routine, including DDR setup.
> >
> > This patch set has been tested on Agilex 5 devkit with QSPI boot
> > (UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
> >
> > Alif Zakuan Yuslaimi (1):
> >   configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS
> >
> > Tien Fong Chee (18):
> >   arm: socfpga: agilex5: Add new system manager base addresses
> >   arm: socfpga: Add support for agilex5 clock manager
> >   linker: Add SPL linker script for SoC64 devices
> >   arm: socfpga: agilex5: Add low level initialization
> >   arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device
> >   arm: dts: agilex5: Add HPS cache coherency unit configuration settings
> >   arm: dts: agilex5: Add firewall configure settings
> >   arm: dts: agilex5: Enable XGMAC
> >   sysreset:  Add reset support to SoCFPGA Agilex5 device
> >   arm: socfpga: agilex5: Enable cache flush for system memory cache in
> >     CCU
> >   arm: socfpga: agilex5: Add SMMU initialization
> >   arm: socfpga: agilex5: Update CPU info
> >   arm: socfpga: Export board ID as U-Boot environment variable
> >   configs: agilex5: Add configuration for malloc pool
> >   arm: socfpga: smc: Add memory coherency support to mailbox command
> >   arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA
> >   configs: socfpga: soc64: agilex5: Enable XGMAC
> >   arm: socfpga: soc64: Add support for board_boot_order()
> >
> > Tingting Meng (1):
> >   ddr: altera: Add DDR driver for Agilex5 series
> >
> >  MAINTAINERS                                   |   2 +
> >  arch/arm/Kconfig                              |   1 +
> >  arch/arm/dts/socfpga_agilex5-u-boot.dtsi      | 660 ++++++++++++++++++
> >  arch/arm/dts/socfpga_agilex5.dtsi             |   7 +
> >  .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi |  33 +
> >  arch/arm/mach-socfpga/Makefile                |   6 +
> >  arch/arm/mach-socfpga/ccu_ncore3.c            |  64 ++
> >  arch/arm/mach-socfpga/include/mach/firewall.h |  23 +-
> >  .../mach-socfpga/include/mach/handoff_soc64.h |   4 +-
> >  arch/arm/mach-socfpga/include/mach/misc.h     |   1 +
> >  .../include/mach/reset_manager_soc64.h        |  12 +-
> >  .../include/mach/system_manager_soc64.h       | 129 ++--
> >  arch/arm/mach-socfpga/lowlevel_init_agilex5.S |  57 ++
> >  arch/arm/mach-socfpga/misc.c                  |  24 +-
> >  arch/arm/mach-socfpga/misc_soc64.c            |  12 +-
> >  arch/arm/mach-socfpga/smc_api.c               |  13 +-
> >  arch/arm/mach-socfpga/spl_agilex5.c           |  84 +++
> >  arch/arm/mach-socfpga/spl_soc64.c             | 120 +++-
> >  arch/arm/mach-socfpga/u-boot-spl-soc64.lds    |  80 +++
> >  arch/arm/mach-socfpga/wrap_handoff_soc64.c    |  10 +-
> >  configs/socfpga_agilex5_defconfig             |   6 +
> >  drivers/ddr/altera/Makefile                   |   1 +
> >  drivers/ddr/altera/iossm_mailbox.c            | 613 ++++++++++++++++
> >  drivers/ddr/altera/iossm_mailbox.h            | 186 +++++
> >  drivers/ddr/altera/sdram_agilex5.c            | 377 ++++++++++
> >  drivers/ddr/altera/sdram_soc64.c              |  78 ++-
> >  drivers/ddr/altera/sdram_soc64.h              |  32 +-
> 
> Can we please put RAM drivers in drivers/ram ? Also, do make sure they
> actually use UCLASS_RAM

The RAM here means for DDR, and UCLASS_RAM is used in DDR driver.

[...]

Regards,
Tien Fong