[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32

[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32

[Macpaul Lin]

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
   - Code cleanup and style formatting.

Changes for v5-v6:
   - This patch also updated the following changes against the
     change after master tree (v2010.12-rc1).
   - fix upper case definitions in cache.h
   - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
   - Add readsb, writesb functions into io.h.

Changes for v7:
   - clean up
   - volatile:
    - types.h
     - remove typedef volatile unsigned char  vuchar;
     - remove typedef volatile unsigned long  vulong;
     - remove typedef volatile unsigned short vushort;
    - u-boot.h: remove bd_info_ext bi_ext
    - bitops.h: add accessor function to bit operation with volatile var.
    - system.h: add system.h for local_irq operation with flag.

 arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
 arch/nds32/include/asm/byteorder.h    |   36 +++
 arch/nds32/include/asm/cache.h        |   54 +++++
 arch/nds32/include/asm/config.h       |   26 ++
 arch/nds32/include/asm/global_data.h  |   82 +++++++
 arch/nds32/include/asm/io.h           |  410 +++++++++++++++++++++++++++++++++
 arch/nds32/include/asm/mach-types.h   |   29 +++
 arch/nds32/include/asm/memory.h       |   19 ++
 arch/nds32/include/asm/posix_types.h  |   84 +++++++
 arch/nds32/include/asm/processor.h    |   25 ++
 arch/nds32/include/asm/ptrace.h       |   22 ++
 arch/nds32/include/asm/ptregs.h       |   81 +++++++
 arch/nds32/include/asm/string.h       |   57 +++++
 arch/nds32/include/asm/system.h       |   88 +++++++
 arch/nds32/include/asm/types.h        |   63 +++++
 arch/nds32/include/asm/u-boot-nds32.h |   50 ++++
 arch/nds32/include/asm/u-boot.h       |   63 +++++
 arch/nds32/include/asm/unaligned.h    |   31 +++
 18 files changed, 1406 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/bitops.h
 create mode 100644 arch/nds32/include/asm/byteorder.h
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/config.h
 create mode 100644 arch/nds32/include/asm/global_data.h
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/include/asm/mach-types.h
 create mode 100644 arch/nds32/include/asm/memory.h
 create mode 100644 arch/nds32/include/asm/posix_types.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/include/asm/ptregs.h
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/system.h
 create mode 100644 arch/nds32/include/asm/types.h
 create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
 create mode 100644 arch/nds32/include/asm/u-boot.h
 create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..c56f04b
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void *addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+extern void clear_bit(int nr, volatile void *addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, volatile void *addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, volatile void *addr);
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ	6	/* I-cache line size */
+#define ICM_CFG_MSK_ISZ	(0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
+#define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..23421b7
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..a3e5b4c
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+#ifdef CONFIG_VFD
+	unsigned char	vfd_type;	/* display type */
+#endif
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT		0x00004	/* Silent mode			*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	*/
+#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG8
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r8")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..be097ec
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,410 @@
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <asm/memory.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+#define writeb(v, a)			__arch_putb(v, a)
+#define writew(v, a)			__arch_putw(v, a)
+#define writel(v, a)			__arch_putl(v, a)
+
+#define readb(a)			__arch_getb(a)
+#define readw(a)			__arch_getw(a)
+#define readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache)				\
+({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
+	_ret;								\
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"), 0)
+#define readw(addr)			(__readwrite_bug("readw"), 0)
+#define readl(addr)			(__readwrite_bug("readl"), 0)
+#define writeb(v, addr)			__readwrite_bug("writeb")
+#define writew(v, addr)			__readwrite_bug("writew")
+#define writel(v, addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101             0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101()	(machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101()	(0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index 0000000..5bcc4e1
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/memory.h
+ *
+ * Copyright (C) 2000-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Note: this file should not be included by non-asm/.h files
+ */
+#ifndef __ASM_NDS_MEMORY_H
+#define __ASM_NDS_MEMORY_H
+
+#endif	/* __ASM_NDS_MEMORY_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..83e8b81
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - included in common.h
+ */
+
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#include <asm/ptregs.h>
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/ptregs.h b/arch/nds32/include/asm/ptregs.h
new file mode 100644
index 0000000..f78448c
--- /dev/null
+++ b/arch/nds32/include/asm/ptregs.h
@@ -0,0 +1,81 @@
+/*
+ * linux/include/asm-arm/proc-armv/ptrace.h
+ *
+ * Copyright (C) 1996-1999 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PTREGS_H
+#define __PTREGS_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+struct pt_regs {
+	long uregs[39];
+};
+
+#define PTREGS(reg)	[reg]
+#define R0		uregs[1]	/* R0 */
+#define R1		uregs[2]
+#define R2		uregs[3]
+#define R3		uregs[4]
+#define R4		uregs[5]
+#define R5		uregs[6]
+#define R6		uregs[7]
+#define R7		uregs[8]
+#define R8		uregs[9]
+#define R9		uregs[10]
+#define R10		uregs[11]
+#define R11		uregs[12]
+#define R12		uregs[13]
+#define R13		uregs[14]
+#define R14		uregs[15]
+#define R15		uregs[16]
+#define R16		uregs[17]
+#define R17		uregs[18]
+#define R18		uregs[19]
+#define R19		uregs[20]
+#define R20		uregs[21]
+#define R21		uregs[22]
+#define R22		uregs[23]
+#define R23		uregs[24]
+#define R24		uregs[25]
+#define R25		uregs[26]
+#define R26		uregs[27]
+#define R27		uregs[28]
+#define FP		uregs[29]	/* R28 */
+#define GP		uregs[30]	/* R29 */
+#define RA		uregs[31]	/* R30 */
+#define SP		uregs[32]	/* R31 */
+#define D0HI		uregs[33]
+#define D0LO		uregs[34]
+#define D1HI		uregs[35]
+#define D1LO		uregs[36]
+#define PSW		uregs[37]	/* IR0 */
+#define PC		uregs[38]	/* PC */
+
+#define processor_mode(regs) \
+	(((regs)->PSW & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->PSW & GIE_BIT)
+
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..2383e08
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong _andesboot_start;		/* code start */
+extern ulong _andesboot_end;		/* code end */
+extern ulong _andesboot_real_end;	/* first usable RAM address */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+/* cpu/.../timer.c */
+int	timer_init(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..fafe4e4
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <environment.h>
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+
+	env_t		*bi_env;
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..ffa7e30
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Andes Technology Corporation
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _ASM_NDS_UNALIGNED_H
+#define _ASM_NDS_UNALIGNED_H
+
+#include <compiler.h>
+/*
+ * Select endianness
+ */
+#ifndef __NDSEB__
+#define get_unaligned	__get_unaligned_le
+#define put_unaligned	__put_unaligned_le
+#else
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+#endif /* __NDSEB__ */
+
+#include <asm/byteorder.h>
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+#endif /* _ASM_NDS_UNALIGNED_H */
-- 
1.7.3.5

[U-Boot] [PATCH v7 02/10] nds32: add NDS32 support into common header file

[Macpaul Lin]

Add NDS32 support into common header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
 include/common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index 54503ed..423bbd8 100644
--- a/include/common.h
+++ b/include/common.h
@@ -273,6 +273,10 @@ int	setenv	     (char *, char *);
 #ifdef CONFIG_I386		/* x86 version to be fixed! */
 # include <asm/u-boot-i386.h>
 #endif /* CONFIG_I386 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h>	/* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
-- 
1.7.3.5

[U-Boot] [PATCH v7 03/10] nds32/core N1213: NDS32 N12 core family N1213

[Macpaul Lin]

Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

NDS32 Core N1213 has the following hardware features.

 Core:
  - 16-/32-bit mixable instruction format
  - 32 general-purpose 32-bit registers
  - 8-stage pipeline
  - Dynamic branch prediction
  - 32/64/128/256 BTB
  - Return address stack (RAS)
  - Vector interrupts for internal/external
  - 3 HW-level nested interruptions
  - User and super-user mode support
  - Memory-mapped I/O
  - Address space up to 4GB

 Memory Management Unit:
  - TLB
  - Optional hardware page table walker
  - Two groups of page size support

 Memory Subsystem:
  - I & D cache
  - I & D local memory (LM)

 Bus Interface:
  - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
 arch/nds32/cpu/n1213/Makefile   |   50 +++++
 arch/nds32/cpu/n1213/start.S    |  447 +++++++++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/u-boot.lds |   68 ++++++
 3 files changed, 565 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/Makefile
 create mode 100644 arch/nds32/cpu/n1213/start.S
 create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..111d14f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..b04f3a5
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,447 @@
+/*
+ *	Andesboot - Startup Code for Whitiger core
+ *
+ *	Copyright (C) 2006	Andes Technology Corporation
+ *	Copyright (C) 2006	Shawn Lin <nobuhiro@andestech.com>
+ *	Copyright (C) 2011	Macpaul <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC		2UL
+#define DIS_DCAC		~ENA_DCAC
+#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
+#define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
+#define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY	(0x07<<3)	! D cache ways
+#define DCAC_MEM_KBF_DSZ	(0x07<<6)	! D cache line size
+
+#define PSW			$ir0
+#define EIT_INTR_PSW		$ir1		! interruption $PSW
+#define EIT_PREV_IPSW		$ir2		! previous $IPSW
+#define EIT_IVB			$ir3		! intr vector base address
+#define EIT_EVA			$ir4		! MMU related Exception Virtual Address register */
+#define EIT_PREV_EVA		$ir5		! previous $eva
+#define EIT_ITYPE		$ir6		! interruption type
+#define EIT_PREV_ITYPE		$ir7		! prev intr type
+#define EIT_MACH_ERR		$ir8		! machine error log
+#define EIT_INTR_PC		$ir9		! Interruption PC
+#define EIT_PREV_IPC		$ir10		! previous $IPC
+#define EIT_OVL_INTR_PC		$ir11		! overflow interruption PC
+#define EIT_PREV_P0		$ir12		! prev $P0
+#define EIT_PREV_P1		$ir13		! prev $p1
+#define CR_ICAC_MEM		$cr1		! I-cache/memory config reg
+#define CR_DCAC_MEM		$cr2		! D-cache/memory config reg
+#define MR_CAC_CTL		$mr8
+
+.globl _start
+
+_start:	b	reset
+	b	tlb_fill
+	b	tlb_not_present
+	b	tlb_misc
+	b	tlb_vlpt_miss
+	b	cache_parity_error
+	b	debug
+	b	general_exception
+	b	internal_interrupt		! H0I
+	b	internal_interrupt		! H1I
+	b	internal_interrupt		! H2I
+	b	internal_interrupt		! H3I
+	b	internal_interrupt		! H4I
+	b	internal_interrupt		! H5I
+
+	.balign 16
+
+!========================================================================
+! Andesboot Startup Code (reset vector)
+!
+!	1.	bootstrap
+!		1.1 reset - start of Andesboot
+!		1.2 to superuser mode - as is when reset
+!		1.4 Do lowlevel_init
+!			- (this will jump out to lowlevel_init.S in SoC)
+!			- (lowlevel_init)
+!		1.3 Turn off watchdog timer
+!			- (this will jump out to watchdog.S in SoC)
+!			- (turnoff_watchdog)
+!	2.	Do critical init when reboot (not from mem)
+!	3.	Relocate andesboot to ram
+!	4.	Setup stack
+!	5.	Jump to second stage (start_andesboot)
+!========================================================================
+
+! Note: TEXT_BASE is defined by the (board-dependent) linker script
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+.globl _andesboot_start
+_andesboot_start:
+	.word _start
+
+! Note: andesboot_end is defined by the (board-dependent) linker script
+.globl _andesboot_end
+_andesboot_end:
+	.word andesboot_end
+
+! _andesboot_real_end is the first usable RAM address behind Andesboot
+! and the various stacks
+.globl _andesboot_real_end
+_andesboot_real_end:
+	.word 0x0badc0de
+
+!=============================================
+! The bootstrap code of Andesboot
+!=============================================
+
+reset:
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	jal	load_lowlevel_init
+	jral	$p0
+#endif
+
+! Set the Whitiger core to superuser mode
+! According to spec, it is already when reset
+
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+	jal	load_turnoff_watchdog
+	jral	$p0
+#endif
+
+! Do CPU critical regs init only at reboot, not when booting from ram
+#ifdef CONFIG_INIT_CRITICAL
+	bal	cpu_init_crit			! Do CPU critical regs init
+#endif
+
+	.align 2
+relocate:
+	! relocate andesboot to RAM
+	jal	2f
+	!la	$r0, _start			! $r0 = source start addr
+	!l.w	$r2, _andesboot_start		! Andesboot start address
+	!l.w	$r3, _andesboot_end		! Andesboot end address
+	!sub	$r2, $r3, $r2			! $r2 = size of Andesboot
+	!l.w	$r1, _TEXT_BASE			! $r1 = destination start addr
+	move	$r0, $lp
+	la	$p0, _start
+	la	$p1, relocate+4
+	sub	$p0, $p1, $p0
+	sub	$r0, $r0, $p0
+
+	la	$p0, _andesboot_end
+	sub	$p0, $p0, $p1
+	move	$r3, $lp
+	lw	$r3, [$r3+$p0]			! _andesboot_end
+	addi	$p0, $p0, -4
+	move	$r2, $lp
+	lw	$r2, [$r2+$p0]			! _andesboot_start
+	sub	$r2, $r3, $r2
+	addi	$p0, $p0, -4
+	move	$r1, $lp
+	lw	$r1, [$r1+$p0]			! _TEXT_BASE
+
+	! $r0 = source address
+	! $r1 = destination address
+	! $r2 = size to copy
+copy_loop:
+	lmw.bim $r3, [$r0], $r10
+	smw.bim $r3, [$r1], $r10
+	addi	$r2, $r2, -32
+	bgez	$r2, copy_loop
+
+	! Set up the stack
+	l.w	$p0, _andesboot_end		! Defined by board linker script
+	li	$p1, CONFIG_STACKSIZE		! (128*1024) defined in config.h
+	add	$sp, $p0, $p1
+
+	bal	flib_init_bss_memory
+
+	! Jump to start_andesboot (2nd phase)
+	l.w	$p0, __start_andesboot
+	br	$p0
+
+__start_andesboot:	.word start_andesboot
+
+!=========================================================================
+! Initialize CPU critical registers
+!
+!	1.	Setup control registers
+!		1.1 Mask all IRQs
+!		1.2 Flush cache and TLB
+!		1.3 Disable MMU and cache
+!	2.	Setup memory timing
+!=========================================================================
+
+cpu_init_crit:
+	!push	ra
+	move	$r0, $lp
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	! Flush caches and TLB
+
+	! Invalidate caches
+	bal	invalidate_icac
+	bal	invalidate_dcac
+
+	! Flush TLB
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	FlushAll			! Flush TLB
+
+1:
+	! Disable MMU, Dcache
+	! Whitiger is MMU disabled when reset
+	! Disable the D$
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Set DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! write back the $CACHE_CTL reg
+	isb
+
+	! RAM is initialized in the dram_init()(board/nds32/cpe.c)
+	! Remove the memsetup.S in the board directory.
+	!pop	ra
+
+	move	$lp, $r0
+2:
+	ret
+
+flib_init_bss_memory:
+	smw.adm $r4, [$sp], $r6, #0x1
+
+	la	$r4, __bss_start
+	la	$r5, __bss_end
+	move	$r6, #0
+1:
+	swi.p	 $r6, [$r4], #4
+	blt	 $r4, $r5, 1b			! Check if done..
+
+	lmw.bim $r4, [$sp], $r6, #0x1
+	ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+	la  $r6, lowlevel_init
+	la  $r7, load_lli + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+	la  $r6, turnoff_watchdog
+	la  $r7, turnoff_wtdog + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+
+!=======================================================
+! Invalidate I$
+!=======================================================
+invalidate_icac:
+	mfsr	$t0, CR_ICAC_MEM		! read $cr1(I CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, ICAC_MEM_KBF_ISZ 	! Get the ISZ field
+	beqz	$p0, end_flush_icache		! if $p0=0, then no I CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of I$ block
+	addi	$t1, $p0, 2			! $t1= bit width of I cache line size(ISZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, ICAC_MEM_KBF_ISET	! get the ISET field
+	addi	$t2, $p1, 6			! $t2= bit width of ISET
+	andi	$p1, $t0, ICAC_MEM_KBF_IWAY	! get bitfield of Iway
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is I way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+ICAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1I_IX_INVAL
+	bnez	$p1, ICAC_LOOP
+end_flush_icache:
+	ret
+
+!=======================================================
+! Invalidate D$
+!=======================================================
+invalidate_dcac:
+	mfsr	$t0, CR_DCAC_MEM		! read $cr2(D CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, DCAC_MEM_KBF_DSZ	! Get the DSZ field
+	beqz	$p0, end_flush_dcache		! if $p0=0, then no D CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of D$ block
+	addi	$t1, $p0, 2			! $t1= bit width of D cache line size(DSZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, DCAC_MEM_KBF_DSET	! get the DSET field
+	addi	$t2, $p1, 6			! $t2= bit width of DSET
+	andi	$p1, $t0, DCAC_MEM_KBF_DWAY	! get bitfield of D way
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is D way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+DCAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1D_IX_INVAL
+	bnez	$p1, DCAC_LOOP
+end_flush_dcache:
+	ret
+
+!========================================================================
+! Interrupt handling
+!========================================================================
+
+/*
+ * exception handlers
+ */
+	.align	5
+
+		.macro	SAVE_ALL
+	! FIXME: Other way to get PC?
+	! FIXME: Update according to the newest spec!!
+1:	la	 $r28, 1
+	push $r28
+		mfsr $r28, PSW			! $PSW
+		push $r28
+		mfsr $r28, EIT_EVA		! $ir1 $EVA
+		push $r28
+		mfsr $r28, EIT_ITYPE		! $ir2 $ITYPE
+		push $r28
+		mfsr $r28, EIT_MACH_ERR		! $ir3 Mach Error
+		push $r28
+		mfsr $r28, EIT_INTR_PSW		! $ir5 $IPSW
+		push $r28
+		mfsr $r28, EIT_PREV_IPSW	! $ir6 prev $IPSW
+		push $r28
+		mfsr $r28, EIT_PREV_EVA		! $ir7 prev $EVA
+		push $r28
+		mfsr $r28, EIT_PREV_ITYPE	! $ir8 prev $ITYPE
+		push $r28
+		mfsr $r28, EIT_INTR_PC		! $ir9 Interruption PC
+		push $r28
+		mfsr $r28, EIT_PREV_IPC		! $ir10 prev INTR_PC
+		push $r28
+		mfsr $r28, EIT_OVL_INTR_PC	! $ir11 Overflowed INTR_PC
+		push $r28
+		mfusr $r28, $d1.lo
+		push $r28
+		mfusr $r28, $d1.hi
+		push $r28
+		mfusr $r28, $d0.lo
+		push $r28
+		mfusr $r28, $d0.hi
+		push $r28
+		pushm $r0,$r30			/* we will also store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp */
+		addi	$sp, $sp, -4		! make room for implicit pt_regs parameters
+		.endm
+
+	.align	5
+tlb_fill:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 1				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_not_present:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 2				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_misc:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 3				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_vlpt_miss:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 4				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+cache_parity_error:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 5				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+debug:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 6				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+general_exception:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 7				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+internal_interrupt:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 8				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+
+!===========================================
+!void reset_cpu(ulong addr);
+!	$r0: input address to jump to
+!===========================================
+.globl reset_cpu
+reset_cpu:
+! No need to disable MMU because we never enable it!
+
+	bal	invalidate_icac
+	bal	invalidate_dcac
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	FlushAll			! Flush TLB
+1:
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Clear the DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! Write back the $CACHE_CTL reg
+	br	$r0				! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..824d05d
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		arch/nds32/cpu/n1213/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	andesboot_end = .;
+
+	. = 0x02000000;
+	.u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
-- 
1.7.3.5

[U-Boot] [PATCH v7 04/10] nds32/ag101: dev offset header of SoC ag101

[Macpaul Lin]

Add header file of device offset support for SoC ag101.

SoC ag101 is the first chip using NDS32 N1213 cpu core.

Note:
   Ag101 is actually use ftsdmc021 instead of ftsdmc020
   as dram controller, which is probably wrong in the datasheet.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
 arch/nds32/include/asm/arch-ag101/ag101.h |   68 +++++++++++++++++++++++++++++
 1 files changed, 68 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE		0x90100000	/* AHB Controller */
+#define CONFIG_FTSMC020_BASE		0x90200000	/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE		0x90300000	/* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000	/* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000	/* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE		0x90600000	/* LCD Controller */
+#define CONFIG_RESERVED_01_BASE		0x90700000	/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000	/* Reserved */
+#define CONFIG_FTMAC100_BASE		0x90900000	/* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000	/* External USB host */
+#define CONFIG_USB_DEV_BASE		0x90B00000	/* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000	/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE		0x90D00000	/* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000	/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000	/* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000	/* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC	/* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE		0x98100000	/* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE	0x98300000	/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE		0x98400000	/* Counter/Timers */
+#define CONFIG_FTWDT010_BASE		0x98500000	/* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE		0x98600000	/* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE		0x98700000	/* GPIO */
+#define CONFIG_FTINTC010_BASE		0x98800000	/* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE		0x98A00000	/* I2C */
+#define CONFIG_RESERVED_04_BASE		0x98C00000	/* Reserved */
+#define CONFIG_FTCFC010_BASE		0x98D00000	/* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000	/* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE		0x99400000	/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE	0x99600000	/* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE	0x98200000	/* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000	/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE		0x98900000	/* IrDA */
+#define CONFIG_PMW_BASE			0x99100000	/* PWM - Pulse Width Modulator Controller */
+
+#endif	/* __AG101_H */
-- 
1.7.3.5

[U-Boot] [PATCH v7 05/10] nds32/ag101: lowlevel_init.S of ag101

[Macpaul Lin]

lowlevel_init.S is a peripheral initial procedure of ag101.
It configures onboard dram, clock, and power settings.
It also prepars the dram environment before moving u-boot
from rom and flash into dram.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
ChangeLog from v1-v4:
   - Code clean up and formatting style.

ChangeLog from v5-v6
   - Change hard code value into MARCO definitions.
   - ftsmc010
     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
   - ftsdmc021
     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
     - Fix the default configuration value of FTSDMC and FTSMC controller.
   - Remove some ftpmu010 and flash probe code to C functions.

 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  160 ++++++++++++++++++++++++++++
 1 files changed, 160 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S

diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..96969ba
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+	jal	mem_init
+	jal	remap
+
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	li	$r0, (CONFIG_FTSMC020_BASE+FTSMC020_BANK0_CR)
+	li	$r1, (FTSMC020_BANK1_CONFIG)			! 0x10000052
+	swi	$r1, [$r0]
+	li	$r1, (FTSMC020_BANK1_TIMING)			! 0x00151151
+	swi	$r1, [$r0+FTSMC020_BANK0_TPR]
+
+	/*
+	 * config AHB Controller
+	 */
+	li	$r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+	li	$r1, (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6)
+	swi	$r1, [$r0]
+
+	/*
+	 * config PMU
+	 */
+	li	$r0, (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+	lwi	$r1, [$r0]
+	! ftpmu010_dlldis_disable, must do it in lowleve_init
+	li	$r2, FTPMU010_PDLLCR0_DLLDIS			! 0x00010000
+	or	$r1, $r1, $r2
+	swi	$r1, [$r0]
+
+	/*
+	 * config SDRAM controller
+	 */
+	li	$r0, (CONFIG_FTSDMC021_BASE)
+	li	$r1, (CONFIG_SYS_FTSDMC021_TP1) ! 0x00011312
+	swi	$r1, [$r0]
+	li	$r1, (CONFIG_SYS_FTSDMC021_TP2) ! 0x00480180
+	swi	$r1, [$r0+FTSDMC021_OFFSET_TP2]
+	li	$r1, (CONFIG_SYS_FTSDMC021_CR1)	! 0x00002326
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR1]
+	li	$r1, (FTSDMC021_CR2_IPREC)	! 0x00000010
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+1:
+	lwi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+	andi	$r1, $r1, (CONFIG_SYS_FTSDMC021_CR2)	! 0x1C
+	bnez	$r1, 1b
+
+	li	$r1, (FTSDMC021_CR2_ISMR)	! 0x00000004
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+2:
+	lwi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+	bnez	$r1, 2b
+
+	li	$r1, (FTSDMC021_CR2_IREF)	! 0x00000008
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+3:
+	lwi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+	bnez	$r1, 3b
+
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* AG101 */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif
+
+	/*
+	 * relocation, copy ROM code to SDRAM (current at 0x10000000)
+	 */
+	li	$r4, CONFIG_SYS_RELO_ADDR		! 0x10000000
+	li	$r5, 0x0
+	la	$r1, relo_base
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(andesboot_end)
+	ori	$r6, $r6, lo12(andesboot_end)
+	add	$r6, $r6, $r2
+1:
+	lwi	$r7, [$r5]
+	swi	$r7, [$r4]
+	addi	$r5, $r5, #4
+	addi	$r4, $r4, #4
+	blt	$r5, $r6, 1b
+
+	/*
+	 * Remapping
+	 */
+	li	$r0, (CONFIG_FTSDMC021_BASE + FTSDMC021_OFFSET_TP1)
+	li	$r1, (CONFIG_SYS_FTSDMC021_BANK0_BSR)	! 0x00001100
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK0_BSR]
+	li	$r1, 0x0
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK1_BSR]
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK2_BSR]
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK3_BSR]
+	li	$r1, (FTSDMC021_BANK_ENABLE)		! 0x00001000
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK0_BSR]
+
+	li	$r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+	lwi	$r1, [$r0]
+	ori	$r1, $r1, FTAHBC020S_CR_REMAP		! 0x1
+	swi	$r1, [$r0]
+
+	li	$r0, (CONFIG_FTSMC020_BASE)
+
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif
-- 
1.7.3.5

[U-Boot] [PATCH v7 05/10] nds32/ag101: lowlevel_init.S of ag101

[Macpaul Lin]

HI Wolfgang and all,

2011/4/7 Macpaul Lin <macpaul@andestech.com>:
> lowlevel_init.S is a peripheral initial procedure of ag101.
> It configures onboard dram, clock, and power settings.
> It also prepars the dram environment before moving u-boot
> from rom and flash into dram.
>

I'm so sorry there is really a need to setup the timing related parameters
in assembly because the poor of hardware design.
Without the correct timing parameters, we cannot read/write dram.
Even we couldn't use it  to store the initial stack,

I have posted the spec of related timing parameter of memory
controller as following
(which is connected to the first bank of DRAM).
Hope you can understand the problem from the hardware (register) spec.

example:
FTSMC020_BANK0_TPR (control the dram)
value: 0x00151151

20   , RBE, set to (b'1), R/W Read byte-enable.
       If this bit is set to '1?, byte-enable will be pulled LOW when read.
       Otherwise, byte-enable will be pulled LOW only for write operation.
19-18, AST, R/W, set to (b'01),
       Address setup time.
       This register specifies the latency needed to assert
chip-enable after address assertion.
17-16, CTW, R/W, set to (b'01),
       Chip-select to write-enable delay.
       This register specifies the latency needed to assert
write-enable after chip-enable assertion.
15-12, AT1, R/W, set to (b'0001),
       Access time 1.
       This register specifies the latency to latch (read) or change
data (write)
       after write-enable assertion when general asynchronous device
is specified.
       The value must be larger than zero. Setting this register to zero is
       acceptable but the behavior will be un-predictable.
       If device is specified as burst ROM, this register indicates
the read/write latency of first data.
       If BNK_TYPE1 is set as ?1? (synchronous devices),
       this register indicates the depth of late-write and the maximum
value of this value is 2 (value exceeding 2 will be reset to zero).
11-10, Reserved, set to (b'00)
       Writing data to this register takes no effect and zero will be
returned when read.
9-8, AT2, R/W, set to (b'01)
       Access time 2.
       This register specifies the latency needed to latch the burst read data.
       This register is only used when device type is specified as burst ROM.
7-6, WTC, R/W, set to (b'01)
       Write-enable to chip-select delay.
       This register specifies the latency needed to de-assert
chip-enable after write-enable de-assertion.
5-4, AHT, R/W, set to (b'01)
       Address hold time.
       This register specifies the latency needed to de-assert address
after chip-select de-assertion.
3-0, TRNA, R/W, set to (b'0001)
       Turn-around time. This register specifies the latency needed to
re-drive data bus.

[U-Boot] [PATCH v7 06/10] nds32/ag101: cpu and init funcs of SoC ag101

[Macpaul Lin]

Add main function of SoC ag101 based on NDS32 n1213 core.

cpu.c
 According to the bootstrap procedure in n1213 Core,
 to turn off watchdog timer is suggested after the
 cpu is in superuser mdoe.

 1. bootstrap
 1.1 reset - start of Andesboot
 1.2 to superuser mode - as is when reset
 1.3 Turn off watchdog timer

 If you take look into the start.S in n1213, you will find that
 system will turn off watchdog after start.S has been retunred
 from lowlevel_init.

 Since the watchdog device is depends on the SoC is choosed.
 It should be belonged to the SoC (ag101) folder.

watchdog.S:
 If you've ran another bootloader before u-boot was started
 the watchdog might have been enabled already.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v5-v6:
  - Split watchdog.S from lowlevel_init.S.
  - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
   - reset_cpu was remove inside do_reset().

Changes for v7:
  - clean up.

 arch/nds32/cpu/n1213/ag101/Makefile   |   58 +++++++++
 arch/nds32/cpu/n1213/ag101/cpu.c      |  207 +++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/timer.c    |  204 ++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/watchdog.S |   48 ++++++++
 4 files changed, 517 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
 create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S

diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..e96b1e4
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..8e7eb0a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/* setup up stack if necessary */
+/* it makes no sense to use the caches if the MMU also isn't used */
+void cpu_init(void)
+{
+	_andesboot_real_end = _andesboot_end + CONFIG_STACKSIZE;
+}
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+	unsigned long i;
+#endif
+
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+	while (1)
+		;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr , addr + size);
+	icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..87275eb
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (APB_CLK);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / (APB_CLK);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * (APB_CLK / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl	turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+#endif
-- 
1.7.3.5

[U-Boot] [PATCH v7 07/10] nds32/lib: add generic funcs in NDS32 lib

[Macpaul Lin]

Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up and formatting style.

Changes for v5-v6:
  - board.c
   - Do some clean up and add code
   - Remove display banner which hasn't support.
   - Add ftpmu010 related power management unit code.
   - Remove useless LED related code.
   - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
   - Remove CONFIG_SOFT_I2C which hasn't been support.
   - Remove CONFIG_FSL_ESDHC which hasn't been support.
   - clean up.

Changes for v7:
  - clean up.
  - move single file patch arch/nds32/config.mk to this commit.
  - interrupts.c refine origin interrupt enable and disable.

 arch/nds32/config.mk        |   35 +++++
 arch/nds32/lib/Makefile     |   52 +++++++
 arch/nds32/lib/board.c      |  346 +++++++++++++++++++++++++++++++++++++++++++
 arch/nds32/lib/bootm.c      |  241 ++++++++++++++++++++++++++++++
 arch/nds32/lib/interrupts.c |  131 ++++++++++++++++
 5 files changed, 805 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/config.mk
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/board.c
 create mode 100644 arch/nds32/lib/bootm.c
 create mode 100644 arch/nds32/lib/interrupts.c

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..ac5d0cf
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common
+PLATFORM_RELFLAGS	+= -gdwarf-2
+PLATFORM_CPPFLAGS	+= -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-8
+
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..eca4324
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+OBJS	:= board.o bootm.o interrupts.o
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..6ed4194
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,346 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern ulong __bss_end;
+ulong monitor_flash_len;
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+const char version_string[] =
+	U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	char tmp[64];	/* long enough for environment variables */
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+			? (int) simple_strtoul(tmp, NULL, 10)
+			: CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+	pmu_init,
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init,
+#endif
+	display_dram_config,
+	NULL,
+};
+
+void start_andesboot(void)
+{
+	init_fnc_t **init_fnc_ptr;
+	char *s;
+#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
+	unsigned long addr;
+#endif
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)(_andesboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t));
+	/* compiler optimization barrier needed for GCC >= 3.4 */
+	__asm__ __volatile__("" : : : "memory");
+
+	memset((void *)gd, 0, sizeof(gd_t));
+	gd->bd = (bd_t *)((char *)gd - sizeof(bd_t));
+	memset(gd->bd, 0, sizeof(bd_t));
+
+	gd->flags |= GD_FLG_RELOC;
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	/* andesboot_start is defined in the board-specific linker script */
+	mem_malloc_init(_andesboot_start - CONFIG_SYS_MALLOC_LEN,
+			CONFIG_SYS_MALLOC_LEN);
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#ifdef CONFIG_VFD
+#	ifndef PAGE_SIZE
+#	  define PAGE_SIZE 4096
+#	endif
+	/*
+	 * reserve memory for VFD display (always full pages)
+	 */
+	/* bss_end is defined in the board-specific linker script */
+	addr = (__bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+	vfd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_VFD */
+
+#ifdef CONFIG_LCD
+	/* board init may have inited fb_base */
+	if (!gd->fb_base) {
+#		ifndef PAGE_SIZE
+#		  define PAGE_SIZE 4096
+#		endif
+		/*
+		 * reserve memory for LCD display (always full pages)
+		 */
+		/* bss_end is defined in the board-specific linker script */
+		addr = (__bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+		lcd_setmem(addr);
+		gd->fb_base = addr;
+	}
+#endif /* CONFIG_LCD */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+	onenand_init();
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#ifdef CONFIG_VFD
+	/* must do this after the framebuffer is allocated */
+	drv_vfd_init();
+#endif /* CONFIG_VFD */
+
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
+	/* IP Address */
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+	/* enable exceptions */
+	enable_interrupts();
+
+	/* Perform network card initialisation if necessary */
+
+	/* Initialize from environment */
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+	puts("Net:   ");
+#endif
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	show_boot_progress(15);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..6c3b0f0
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptregs.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+extern void reset_cpu(ulong addr);
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"ra : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->PC, regs->SP, regs->RA, regs->GP, regs->FP);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->D1HI, regs->D1LO, regs->D0HI, regs->D0LO);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->R27, regs->R26, regs->R25, regs->R24);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->R23, regs->R22, regs->R21, regs->R20);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->R19, regs->R18, regs->R17, regs->R16);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->R15, regs->R14, regs->R13, regs->R12);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->R11, regs->R10, regs->R9, regs->R8);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->R7, regs->R6, regs->R5, regs->R4);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->R3, regs->R2, regs->R1, regs->R0);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}
-- 
1.7.3.5

[U-Boot] [PATCH v7 08/10] nds32: standalone support

[Macpaul Lin]

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
 examples/standalone/nds32.lds     |   64 +++++++++++++++++++++++++++++++++++++
 examples/standalone/stubs.c       |   17 +++++++++-
 examples/standalone/x86-testapp.c |   12 +++++++
 3 files changed, 92 insertions(+), 1 deletions(-)
 create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..c2ac107
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	_end = .;
+
+	. = 0x02000000;
+	.u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 2d2e709..b711926 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
 "	jmp %%g1\n"					\
 "	nop\n"						\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	lwi	$r16, [$gp + (%0)]\n"	\
+"	lwi	$r16, [$r16 + (%1)]\n"	\
+"	jr	$r16\n"			\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
 #else
+/*"	addi	$sp, $sp, -24\n"	\
+"	br	$r16\n"			\*/
+
 #error stubs definition missing for this architecture
 #endif
 
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile (						\
 "	lw	$25, %1($25)\n"				\
 "	jr	$25\n"					\
 	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x)					\
+asm volatile (						\
+"	.globl mon_" #x "\n"				\
+"mon_" #x ":\n"						\
+"	lwi	$r16, [$gp + (%0)]\n"			\
+"	lwi	$r16, [$r16 + (%1)]\n"			\
+"	jr	$r16\n"					\
+	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
+
 #else
 #error [No stub code for this arch]
 #endif
@@ -72,6 +82,8 @@ int main(void)
 	register volatile xxx_t *pq asm("r8");
 #elif defined(__mips__)
 	register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+	register volatile xxx_t *pq asm("$r16");
 #endif
 	char buf[32];
 
-- 
1.7.3.5

[U-Boot] [PATCH v7 09/10] nds32: common bdinfo, bootm, image support

[Macpaul Lin]

Add support of NDS32 to common commands bdinfo, bootm, and image format.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
 common/cmd_bdinfo.c |   28 +++++++++++++++++++++++++++-
 common/cmd_bootm.c  |    2 ++
 common/image.c      |    1 +
 include/image.h     |    5 +++++
 4 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index bba7374..908091d 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -411,13 +411,39 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num("arch_number",	bd->bi_arch_number);
+	print_num("env_t",		(ulong)bd->bi_env);
+	print_num("boot_params",	(ulong)bd->bi_boot_params);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
 
 static void print_num(const char *name, ulong value)
 {
-	printf ("%-12s= 0x%08lX\n", name, value);
+	printf("%-12s= 0x%08lX\n", name, value);
 }
 
 #if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 18019d6..59fbc45 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -187,6 +187,8 @@ void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
   #define IH_INITRD_ARCH IH_ARCH_SH
 #elif defined(__sparc__)
   #define IH_INITRD_ARCH IH_ARCH_SPARC
+#elif defined(__nds32__)
+  #define IH_INITRD_ARCH IH_ARCH_NDS32
 #else
 # error Unknown CPU type
 #endif
diff --git a/common/image.c b/common/image.c
index f63a2ff..afe5957 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	-1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index 005e0d2..1a2be5e 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_NDS32	        19	/* ANDES Technology - NDS32  */
 
 /*
  * Image Types
@@ -504,6 +505,8 @@ static inline int image_check_target_arch (const image_header_t *hdr)
 	if (!image_check_arch (hdr, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!image_check_arch (hdr, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!image_check_arch(hdr, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
@@ -656,6 +659,8 @@ static inline int fit_image_check_target_arch (const void *fdt, int node)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!fit_image_check_arch(fdt, node, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
-- 
1.7.3.5

[U-Boot] [PATCH v7 10/10] adp-ag101: add board adp-ag101 support

[Macpaul Lin]

Add adp-ag101.c board config and related settings.
Add evaluation board "adp-ag101" configuration file adp-ag101.h.
Add board adp-ag101 into boards.cfg

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up
Changes for v5-v6:
  - adp-ag101.h
    - Refine the definitions and parameters about CLK,
      AHB controller, SDRAM controller, Static memory controllers.
    - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
    - ftahbc010:
      - Update include path of ftahbc010.
    - ftsdmc021:
      - Update include path of ftsdmc021.
    - ftsmc020:
      - Update include path of ftsmc020.
    - ftwdt010:
      - Fix WDT define and update include path.
      - Fix ftwdt010 for hardware reset.
    - ftpmu010:
      - Remove duplicate PMU definitions.
      - Add related configurations.
    - Fix MAX malloc len and fix saveenv.
    - clean up.
Changes for v7:
  - adp-ag101.c
    - Fix Makefile and remove config.mk
  - adp-ag101.h:
    - clean up.
    - Move CONFIG_SYS_TEXT_BASE from board/config.mk.

 MAINTAINERS                           |   11 +
 MAKEALL                               |    6 +
 board/AndesTech/adp-ag101/Makefile    |   57 +++++
 board/AndesTech/adp-ag101/adp-ag101.c |   81 +++++++
 boards.cfg                            |    1 +
 include/configs/adp-ag101.h           |  378 +++++++++++++++++++++++++++++++++
 6 files changed, 534 insertions(+), 0 deletions(-)
 create mode 100644 board/AndesTech/adp-ag101/Makefile
 create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
 create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 1d7e1f4..29f3b4d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1113,5 +1113,16 @@ Anton Shurpin <shurpin.aa@niistt.ru>
 	BF561-ACVILON	BF561
 
 #########################################################################
+# NDS32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+	ADP-AG101	N1213 (AG101 SoC)
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index e1b928f..286d158 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -610,6 +610,12 @@ LIST_sh="$(boards_by_arch sh)"
 
 LIST_sparc="$(boards_by_arch sparc)"
 
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
 #-----------------------------------------------------------------------
 
 build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..5a403b1
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,57 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= adp-ag101.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+ifdef CONFIG_SYS_LDSCRIPT
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else
+LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..b31b785
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->bd->bi_dram[0].start = sdram_base;
+	gd->bd->bi_dram[0].size  = actual_size;
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else
+		return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index d25f3f2..80a5863 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -242,6 +242,7 @@ vct_platinumavc              mips        mips32      vct                 microna
 vct_platinumavc_small        mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
+adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..9e1d50e
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,378 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Timer
+ */
+
+/*
+ * ag101:	CONFIG_SYS_HZ:	APB_CLK (ag101 original timer clock frequency)
+ *
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+
+/*
+ * APB_CLK, AHB_CLK, SYS_CLK are from an old configuration
+ * in the earlist nds32 bootloader.
+ *
+ * CONFIG_SYS_HZ = APB_CLK = SYS_CLK = CONFIG_SYS_CLK_FREQ /2
+ *
+ * Since the power management (PWM) Timer 4 uses a counter of
+ * 15625 for 10 ms, so we need it to wrap 100 times
+ * (total 1562500) to get 1 sec.
+ *
+ * #define CONFIG_HZ		1562500
+ * 1562500*25=3906250
+ */
+#define SYS_CLK			CONFIG_SYS_CLK_FREQ
+#define AHB_CLK			SYS_CLK
+#define APB_CLK			(SYS_CLK / 2)
+
+#define CONFIG_SYS_HZ		1000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+#define CONFIG_SYS_TEXT_BASE	0x03200000
+
+/*
+ * System Clock
+ * Suggested frequency lists:
+ *	16000000 -> 16.000000 MHz
+ *	18432000 -> 18.432000 MHz
+ *	22118400 -> 22.118400 MHz
+ *	83000000 -> 83.000000 MHz
+ *	33000000 -> 33.000000 MHz
+ *	36864000 -> 36.864000 MHz
+ *	48000000 -> 48.000000 MHz CONFIG_ADP_AG101
+ *	39062500 -> 39.062500 MHz CONFIG_ADP_AG101P
+ */
+#ifdef CONFIG_ADP_AG101
+#define  CONFIG_SYS_CLK_FREQ	48000000
+#endif
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#ifdef CONFIG_ADP_AG101
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+#endif
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE /* 0x99600000 */
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+
+#ifdef CONFIG_ADP_AG101
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+#endif
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+						 FTAHBC020S_SLAVE_BSR_SIZE(FTAHBC020S_SLAVE_BSR_SIZE_2G))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZEF(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x0CF00000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x00200000
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+
+#ifdef CONFIG_ADP_AG101
+/*
+ * There are 2 bank connected to FTSMC020 on ADP_AG101
+ * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+ *
+ * Note:
+ *  FLASH on ADP_AG101P (FPGA version of ADP_AG101) is connected to BANK1
+ *  Just disalbe the other BANK to avoid detection error.
+ */
+
+/* This FTSMC020_BANK1_SDRAM was used in lowlevel_init.S */
+#define FTSMC020_BANK1_SDRAM_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_SDRAM_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+
+#define FTSMC020_BANK1_CONFIG		FTSMC020_BANK1_SDRAM_CONFIG
+#define FTSMC020_BANK1_TIMING		FTSMC020_BANK1_SDRAM_TIMING
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0 (FLASH)
+ * PHYS_FLASH_1 should be 0x400000 (13 bits to store addr, 0x1000000)
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+#endif /* CONFIG_ADP_AG101 */
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#define PHYS_FLASH_1			0x80400000
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x1C0000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+/* relocation parameters */
+#define CONFIG_SYS_RELO_ADDR		0x10000000
+
+#endif	/* __CONFIG_H */
-- 
1.7.3.5

[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1302180333-25372-1-git-send-email-macpaul@andestech.com> you wrote:
> Add generic header files support for nds32 architecture.
> Cache, ptregs, data type and other definitions are included.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Checkpatch complains a lot about "do not add new typedefs".

...
> +#define PTREGS(reg)	[reg]

This also triggers an erro-r from checkpatch, and indeed this is a
strange define.

> +#define R0		uregs[1]	/* R0 */
> +#define R1		uregs[2]
> +#define R2		uregs[3]
> +#define R3		uregs[4]
> +#define R4		uregs[5]
> +#define R5		uregs[6]
> +#define R6		uregs[7]
> +#define R7		uregs[8]
> +#define R8		uregs[9]
> +#define R9		uregs[10]
> +#define R10		uregs[11]
> +#define R11		uregs[12]
> +#define R12		uregs[13]
> +#define R13		uregs[14]
> +#define R14		uregs[15]
> +#define R15		uregs[16]
> +#define R16		uregs[17]
> +#define R17		uregs[18]
> +#define R18		uregs[19]
> +#define R19		uregs[20]
> +#define R20		uregs[21]
> +#define R21		uregs[22]
> +#define R22		uregs[23]
> +#define R23		uregs[24]
> +#define R24		uregs[25]
> +#define R25		uregs[26]
> +#define R26		uregs[27]
> +#define R27		uregs[28]
> +#define FP		uregs[29]	/* R28 */
> +#define GP		uregs[30]	/* R29 */
> +#define RA		uregs[31]	/* R30 */
> +#define SP		uregs[32]	/* R31 */
> +#define D0HI		uregs[33]
> +#define D0LO		uregs[34]
> +#define D1HI		uregs[35]
> +#define D1LO		uregs[36]
> +#define PSW		uregs[37]	/* IR0 */
> +#define PC		uregs[38]	/* PC */

NAK.  Please use a C struct instead.

...
> diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
> new file mode 100644
> index 0000000..fafe4e4
> --- /dev/null
> +++ b/arch/nds32/include/asm/u-boot.h
> @@ -0,0 +1,63 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * Copyright (C) 2011 Andes Technology Corporation
> + * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
> + * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
...
> +#ifndef _U_BOOT_H_
> +#define _U_BOOT_H_	1
> +
> +#include <environment.h>
> +
> +typedef struct bd_info {
> +	int		bi_baudrate;	/* serial console baudrate */
> +	unsigned long	bi_ip_addr;	/* IP Address */
> +	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
> +
> +	env_t		*bi_env;
> +	unsigned long	bi_arch_number;	/* unique id for this board */
> +	unsigned long	bi_boot_params;	/* where this board expects params */
> +
> +	unsigned long	bi_memstart;	/* start of DRAM memory */
> +	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
> +	unsigned long	bi_flashstart;	/* start of FLASH memory */
> +	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
> +	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
> +
> +	struct				/* RAM configuration */
> +	{
> +		unsigned long start;
> +		unsigned long size;
> +	} bi_dram[CONFIG_NR_DRAM_BANKS];
> +} bd_t;

I wonder which part of this file would be (C) by any of the folks
listed above?


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Time is an illusion perpetrated by the manufacturers of space.

[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32

[Macpaul Lin]

Hi Wolfgang,

2011/4/7 Wolfgang Denk <wd@denx.de>:
Dear Macpaul Lin,

>> Add generic header files support for nds32 architecture.
>> Cache, ptregs, data type and other definitions are included.
>>
>> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
>
> Checkpatch complains a lot about "do not add new typedefs".

Indeed, but this seems is special for Linux Kernel,
I've checked some of the "typedefs" from other architecture code in u-boot.
Most of them are specific for u-boot only.
Even GD is one of them.
I did check typedefs one by one by myself in hand and eye checking.
If some thing is not suitable for using "typedefs" please let me know.

> ...
>> +#define PTREGS(reg) ?[reg]
>
> This also triggers an erro-r from checkpatch, and indeed this is a
> strange define.

It was strange for me, too.
However, it looks like I must use PTREGS define for ptregs for API
compatibility.
Please refer to the ARM code and MIPS, etc.

> +#define R0 ? ? ? ? ? uregs[1] ? ? ? ?/* R0 */
>> +#define R1 ? ? ? ? ? uregs[2]
>> +#define R2 ? ? ? ? ? uregs[3]
>> +#define R3 ? ? ? ? ? uregs[4]
>> +#define R4 ? ? ? ? ? uregs[5]
>> +#define R5 ? ? ? ? ? uregs[6]
>> +#define R6 ? ? ? ? ? uregs[7]
>> +#define R7 ? ? ? ? ? uregs[8]
>> +#define R8 ? ? ? ? ? uregs[9]
>> +#define R9 ? ? ? ? ? uregs[10]
>> +#define R10 ? ? ? ? ?uregs[11]
>> +#define R11 ? ? ? ? ?uregs[12]
>> +#define R12 ? ? ? ? ?uregs[13]
>> +#define R13 ? ? ? ? ?uregs[14]
>> +#define R14 ? ? ? ? ?uregs[15]
>> +#define R15 ? ? ? ? ?uregs[16]
>> +#define R16 ? ? ? ? ?uregs[17]
>> +#define R17 ? ? ? ? ?uregs[18]
>> +#define R18 ? ? ? ? ?uregs[19]
>> +#define R19 ? ? ? ? ?uregs[20]
>> +#define R20 ? ? ? ? ?uregs[21]
>> +#define R21 ? ? ? ? ?uregs[22]
>> +#define R22 ? ? ? ? ?uregs[23]
>> +#define R23 ? ? ? ? ?uregs[24]
>> +#define R24 ? ? ? ? ?uregs[25]
>> +#define R25 ? ? ? ? ?uregs[26]
>> +#define R26 ? ? ? ? ?uregs[27]
>> +#define R27 ? ? ? ? ?uregs[28]
>> +#define FP ? ? ? ? ? uregs[29] ? ? ? /* R28 */
>> +#define GP ? ? ? ? ? uregs[30] ? ? ? /* R29 */
>> +#define RA ? ? ? ? ? uregs[31] ? ? ? /* R30 */
>> +#define SP ? ? ? ? ? uregs[32] ? ? ? /* R31 */
>> +#define D0HI ? ? ? ? uregs[33]
>> +#define D0LO ? ? ? ? uregs[34]
>> +#define D1HI ? ? ? ? uregs[35]
>> +#define D1LO ? ? ? ? uregs[36]
>> +#define PSW ? ? ? ? ?uregs[37] ? ? ? /* IR0 */
>> +#define PC ? ? ? ? ? uregs[38] ? ? ? /* PC */
>
> NAK. ?Please use a C struct instead.

Other architecture use specific ARM_XXX_R0 or MIPS_XXX _R.
Since most of NDS32 registers could be used as general register, hence
we have such format in define.
If you have better idea, please give me a suggestion of the code to
the correspoded

And I think this part is specific for the API ?to ptregs.h.
Other architecture gose the similar format instead C structure.
If use C structure to present a set of CPU registers is adapable for
ptregs related API is workable, please give me such a hint and I will
try.
However, the define of PC or PSW for ptregs related feature I guess it
is required somehow.

Please give a suggestion if my knowledge of ptregs related APIs is wrong.

> ...
>> diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
>> new file mode 100644
>> index 0000000..fafe4e4
>> --- /dev/null
>> +++ b/arch/nds32/include/asm/u-boot.h
>> @@ -0,0 +1,63 @@
>> +/*
>> + * (C) Copyright 2002
>> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
>> + * Marius Groeger <mgroeger@sysgo.de>
>> + *
>> + * Copyright (C) 2011 Andes Technology Corporation
>> + * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
>> + * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
> ...
>> +#ifndef _U_BOOT_H_
>> +#define _U_BOOT_H_ ? 1
>> +
>> +#include <environment.h>
>> +
>> +typedef struct bd_info {
>> + ? ? int ? ? ? ? ? ? bi_baudrate; ? ?/* serial console baudrate */
>> + ? ? unsigned long ? bi_ip_addr; ? ? /* IP Address */
>> + ? ? unsigned char ? bi_enetaddr[6]; /* Ethernet adress */
>> +
>> + ? ? env_t ? ? ? ? ? *bi_env;
>> + ? ? unsigned long ? bi_arch_number; /* unique id for this board */
>> + ? ? unsigned long ? bi_boot_params; /* where this board expects params */
>> +
>> + ? ? unsigned long ? bi_memstart; ? ?/* start of DRAM memory */
>> + ? ? unsigned long ? bi_memsize; ? ? /* size ?of DRAM memory in bytes */
>> + ? ? unsigned long ? bi_flashstart; ?/* start of FLASH memory */
>> + ? ? unsigned long ? bi_flashsize; ? /* size ?of FLASH memory */
>> + ? ? unsigned long ? bi_flashoffset; /* reserved area for startup monitor */
>> +
>> + ? ? struct ? ? ? ? ? ? ? ? ? ? ? ? ?/* RAM configuration */
>> + ? ? {
>> + ? ? ? ? ? ? unsigned long start;
>> + ? ? ? ? ? ? unsigned long size;
>> + ? ? } bi_dram[CONFIG_NR_DRAM_BANKS];
>> +} bd_t;
>
> I wonder which part of this file would be (C) by any of the folks
> listed above?

Because I'm not in the office (this is not office hour in asia).
I'll check it in the office tommorrow.

Thanks a lot.

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32

[Wolfgang Denk]

Dear Macpaul Lin,

In message <BANLkTimhCuOcvMmFrSJGHxYRHyKFXJTc9g@mail.gmail.com> you wrote:
> 
> > Checkpatch complains a lot about "do not add new typedefs".
> 
> Indeed, but this seems is special for Linux Kernel,

Not really.  This is Linux CodingStyle policy, which we usually adapt.

> I've checked some of the "typedefs" from other architecture code in u-boot.

This does not mean much.  Yes, there are tons of typedef's in U-Boot,
but this is old code that has not been cleaned up yet.  At least we
now try not to add to that pool.

> I did check typedefs one by one by myself in hand and eye checking.
> If some thing is not suitable for using "typedefs" please let me know.

Please don't add any new typedef's.

> >> +#define PTREGS(reg)  [reg]
> >
> > This also triggers an erro-r from checkpatch, and indeed this is a
> > strange define.
> 
> It was strange for me, too.
> However, it looks like I must use PTREGS define for ptregs for API
> compatibility.
> Please refer to the ARM code and MIPS, etc.

I did check.  There is not any code anywhere that references anything
like "ptreg" or similar.

> > NAK.  Please use a C struct instead.
> 
> Other architecture use specific ARM_XXX_R0 or MIPS_XXX _R.

I'm not sure what you might be referring to.  The only other file
which I can find which has similar code is
arch/arm/include/asm/proc-armv/ptrace.h, and this indeed should be
cleaned up, too.

Sorry, sometimes such things slip through the reviews.

> And I think this part is specific for the API  to ptregs.h.

It appears this is something no other architecture needs in U-Boot?


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Every time history repeats itself the price goes up.

[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32

[Macpaul Lin]

Hi Wolfgang,

>> > Checkpatch complains a lot about "do not add new typedefs".
>>
>> Indeed, but this seems is special for Linux Kernel,
>
> Not really. ?This is Linux CodingStyle policy, which we usually adapt.
>
>> I've checked some of the "typedefs" from other architecture code in u-boot.
>
> This does not mean much. ?Yes, there are tons of typedef's in U-Boot,
> but this is old code that has not been cleaned up yet. ?At least we
> now try not to add to that pool.
>
>> I did check typedefs one by one by myself in hand and eye checking.
>> If some thing is not suitable for using "typedefs" please let me know.
>
> Please don't add any new typedef's.
>

I think we still have to discuss about the typedef's.
What does the "new" typedef means?

According to the checkpatch result, "typedef" warning exists in 4 files.
arch/nds32/include/asm/posix_types.h
arch/nds32/include/asm/types.h
arch/nds32/include/asm/global_data.h
arch/nds32/include/asm/u-boot.h.

File arch/nds32/include/asm/posix_types.h  and arch/nds32/include/asm/types.h
come from the Linux kernel. Which is usually used for posix
compatibility for Linux Kernel.
Which should be "old" features for posix and compatibility.
However, you cannot say for a new architecture to support posix and
other compatibility as
"new" typedef.
I've checked the latest kernel (2.6.38.1), arm, mips, avr32, powerpc
consist these posix_types.h and types.h with "typedef".

It looks the kernel is not going to fix the "old" typedef for
posix_types.h and types.h

I think they say "please do not add any new typedef" might mean to
those typedef
used in drivers or protocols.

In the other 2 files arch/nds32/include/asm/global_data.h and
arch/nds32/include/asm/u-boot.h,
typedef was used for
#449: FILE: arch/nds32/include/asm/global_data.h:46:
+typedef        struct global_data {
+} gd_t;
#1505: FILE: arch/nds32/include/asm/u-boot.h:41:
+typedef struct bd_info {
+} bd_t;

I don't know if you have any idea of fixing it in u-boot.

If you have an explicit way to fix it, for example,
"we must declare bd_t in each function before we use it",
I'll very glad to do it for fixing up the coding style.
Otherwise I'm afraid of the fixing "typedef" here in these 2 file might lead
function or other problem in u-boot build with nds32.

Thanks.

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32

[Macpaul Lin]

Hi Wolfgang,

>>> I did check typedefs one by one by myself in hand and eye checking.
>>> If some thing is not suitable for using "typedefs" please let me know.
>>
>> Please don't add any new typedef's.
>>
>
> I think we still have to discuss about the typedef's.
> What does the "new" typedef means?
>
> According to the checkpatch result, "typedef" warning exists in 4 files.
> arch/nds32/include/asm/posix_types.h
> arch/nds32/include/asm/types.h
> arch/nds32/include/asm/global_data.h
> arch/nds32/include/asm/u-boot.h.
>

I've found the origin purpose of adding typedef check to checkpatch.pl
from the author "apw".
Please refer to url
"http://lkml.indiana.edu/hypermail/linux/kernel/0801.0/0354.html"
I quote his words as below.

Andy Whitcroft (apw said..)
"It is checkpatch's role to point out things which are likely to be
wrong. There will always be exceptions. Lines which are much more
readable if they spill over 80 characters, typedefs which do make sense.
atomic_t's for example. This may well be a valid use of them. Note
that this is mentioned as a WARNING not an ERROR. As is stated in the
patch submission notes, you are meant to be comfortable with everything
which checkpatch is still reporting.

checkpatch is a style _guide_, not the be all and end all. It is meant
to carry a preferred style to try and maintain some consistency kernel
wide."

There is also a section of the coding style which related to "typedef" in Linux
Kernel's Documents.

Please also refer to "Chapter 5, typedef" in "Documentation/CodingStyle".

Hope this information is helping other patch submitters. Thanks.

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32

[Wolfgang Denk]

Dear Macpaul Lin,

In message <BANLkTi=haZVW17eNWYCmYf3McrGmbm-4Xw@mail.gmail.com> you wrote:
> 
> I think we still have to discuss about the typedef's.
> What does the "new" typedef means?

It means adding any new code to U-Boot which includes "typedef"s.

> According to the checkpatch result, "typedef" warning exists in 4 files.
> arch/nds32/include/asm/posix_types.h
> arch/nds32/include/asm/types.h
> arch/nds32/include/asm/global_data.h
> arch/nds32/include/asm/u-boot.h.
>
> File arch/nds32/include/asm/posix_types.h  and arch/nds32/include/asm/types.h
> come from the Linux kernel. Which is usually used for posix
> compatibility for Linux Kernel.

So these files should be fixed in Linux, too, because it is the Linux
checkpatch tool which throws this warning.

I don't think this affects POSIX compatibility. Which typedef's are
required by POSIX?

> Which should be "old" features for posix and compatibility.
> However, you cannot say for a new architecture to support posix and
> other compatibility as
> "new" typedef.
> I've checked the latest kernel (2.6.38.1), arm, mips, avr32, powerpc
> consist these posix_types.h and types.h with "typedef".

Maybe this is old code that was added before checkpatch existed?

> It looks the kernel is not going to fix the "old" typedef for
> posix_types.h and types.h

Eventually they would not add these files as is any more today.

> I think they say "please do not add any new typedef" might mean to
> those typedef
> used in drivers or protocols.

I mean all of them.

> In the other 2 files arch/nds32/include/asm/global_data.h and
> arch/nds32/include/asm/u-boot.h,
> typedef was used for
> #449: FILE: arch/nds32/include/asm/global_data.h:46:
> +typedef        struct global_data {
> +} gd_t;
> #1505: FILE: arch/nds32/include/asm/u-boot.h:41:
> +typedef struct bd_info {
> +} bd_t;

Ouch. You got me there... :-(

> I don't know if you have any idea of fixing it in u-boot.

Well, the fix is basicly straightforward - replace all ocurrences of
gd_t and bd_t in the U-Boot code.  But this is a bigger issue and more
work than I dare to push on you.  I'm grinding my teeth, but I will
accept these.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If ignorance is bliss, why aren't there more happy people?

[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32

[Chih-Min Chao]

On Sat, Apr 30, 2011 at 7:09 AM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Macpaul Lin,
>
> In message <BANLkTi=haZVW17eNWYCmYf3McrGmbm-4Xw@mail.gmail.com> you wrote:
>>
>> I think we still have to discuss about the typedef's.
>> What does the "new" typedef means?
>
> It means adding any new code to U-Boot which includes "typedef"s.
>
>> According to the checkpatch result, "typedef" warning exists in 4 files.
>> arch/nds32/include/asm/posix_types.h
>> arch/nds32/include/asm/types.h
>> arch/nds32/include/asm/global_data.h
>> arch/nds32/include/asm/u-boot.h.
>>
>> File arch/nds32/include/asm/posix_types.h ?and arch/nds32/include/asm/types.h
>> come from the Linux kernel. Which is usually used for posix
>> compatibility for Linux Kernel.
>
> So these files should be fixed in Linux, too, because it is the Linux
> checkpatch tool which throws this warning.
>
> I don't think this affects POSIX compatibility. Which typedef's are
> required by POSIX?
>
>> Which should be "old" features for posix and compatibility.
>> However, you cannot say for a new architecture to support posix and
>> other compatibility as
>> "new" typedef.
>> I've checked the latest kernel (2.6.38.1), arm, mips, avr32, powerpc
>> consist these posix_types.h and types.h with "typedef".
>
> Maybe this is old code that was added before checkpatch existed?
>
In Linux  "CodingStyle"

" Chapter 5: Typedefs

Please don't use things like "vps_t".

It's a _mistake_ to use typedef for structures and pointers."
[skip]
"Lots of people think that typedefs "help readability". Not so. They are
useful only for:"
[skip]
" (b) Clear integer types, where the abstraction _helps_ avoid confusion
     whether it is "int" or "long".

     u8/u16/u32 are perfectly fine typedefs, although they fit into
     category (d) better than here.

     NOTE! Again - there needs to be a _reason_ for this. If something is
     "unsigned long", then there's no reason to do

        typedef unsigned long myflags_t;

     but if there is a clear reason for why it under certain circumstances
     might be an "unsigned int" and under other configurations might be
     "unsigned long", then by all means go ahead and use a typedef."

I think posix_types may be an example of this case. nds32 have some
types different from
what has been defined in <asm-generic/posix_types.h>

As for commit time, the latest update for checkpatch.pl is in 2009-01-06
653d4876 (Andy Whitcroft     2007-06-23 17:16:34 -0700 1891)
 if ($line =~ /\btypedef\s/ &&
8054576d (Andy Whitcroft     2009-01-06 14:41:26 -0800 1892)
     $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ &&
c45dcabd (Andy Whitcroft     2008-06-05 22:46:01 -0700 1893)
     $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ &&
8ed22cad (Andy Whitcroft     2008-10-15 22:02:32 -0700 1894)
     $line !~ /\b$typeTypedefs\b/ &&
653d4876 (Andy Whitcroft     2007-06-23 17:16:34 -0700 1895)
     $line !~ /\b__bitwise(?:__|)\b/) {
de7d4f0e (Andy Whitcroft     2007-07-15 23:37:22 -0700 1896)
         WARN("do not add new typedefs\n" . $herecurr);
0a920b5b (Andy Whitcroft     2007-06-01 00:46:48 -0700 1897)            }

But Michal Simek's commit, which added posix_types.h is adapted in 2009-03-27.
You can reference it by 6d9c3f208580 in Linux repo



>> It looks the kernel is not going to fix the "old" typedef for
>> posix_types.h and types.h
>
> Eventually they would not add these files as is any more today.
>
>> I think they say "please do not add any new typedef" might mean to
>> those typedef
>> used in drivers or protocols.
>
> I mean all of them.
>
>> In the other 2 files arch/nds32/include/asm/global_data.h and
>> arch/nds32/include/asm/u-boot.h,
>> typedef was used for
>> #449: FILE: arch/nds32/include/asm/global_data.h:46:
>> +typedef ? ? ? ?struct global_data {
>> +} gd_t;
>> #1505: FILE: arch/nds32/include/asm/u-boot.h:41:
>> +typedef struct bd_info {
>> +} bd_t;
>
> Ouch. You got me there... :-(
>
>> I don't know if you have any idea of fixing it in u-boot.
>
> Well, the fix is basicly straightforward - replace all ocurrences of
> gd_t and bd_t in the U-Boot code. ?But this is a bigger issue and more
> work than I dare to push on you. ?I'm grinding my teeth, but I will
> accept these.
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> If ignorance is bliss, why aren't there more happy people?
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32

[Macpaul Lin]

Hi Wolfgang,

2011/4/30 Wolfgang Denk <wd@denx.de>:
> Dear Macpaul Lin,
>
> It means adding any new code to U-Boot which includes "typedef"s.
>
>> According to the checkpatch result, "typedef" warning exists in 4 files.
>> arch/nds32/include/asm/posix_types.h
>> arch/nds32/include/asm/types.h
>> arch/nds32/include/asm/global_data.h
>> arch/nds32/include/asm/u-boot.h.
>>
>> File arch/nds32/include/asm/posix_types.h ?and arch/nds32/include/asm/types.h
>> come from the Linux kernel. Which is usually used for posix
>> compatibility for Linux Kernel.
>
> So these files should be fixed in Linux, too, because it is the Linux
> checkpatch tool which throws this warning.
>
> I don't think this affects POSIX compatibility. Which typedef's are
> required by POSIX?

1. posix_types.h
I cannot say I'm sure that the posix_types.h is not necessary for u-boot.
If this posix_types.h won't be used any more, should we keep it in u-boot?

I listed the required typedef for POSIX compatibility in Linux kernel
as follows which
are also support by other architectures.
typedef unsigned short         __kernel_dev_t;
typedef unsigned long          __kernel_ino_t;
typedef unsigned short         __kernel_mode_t;
typedef unsigned short         __kernel_nlink_t;
typedef long                   __kernel_off_t;
typedef int                    __kernel_pid_t;
typedef unsigned short         __kernel_ipc_pid_t;
typedef unsigned short         __kernel_uid_t;
typedef unsigned short         __kernel_gid_t;
typedef unsigned int           __kernel_size_t;
typedef int                    __kernel_ssize_t;
typedef int                    __kernel_ptrdiff_t;
typedef long                   __kernel_time_t;
typedef long                   __kernel_suseconds_t;
typedef long                   __kernel_clock_t;
typedef int                    __kernel_daddr_t;
typedef char                   *__kernel_caddr_t;
typedef unsigned short         __kernel_uid16_t;
typedef unsigned short         __kernel_gid16_t;
typedef unsigned int           __kernel_uid32_t;
typedef unsigned int           __kernel_gid32_t;
typedef unsigned short         __kernel_old_uid_t;
typedef unsigned short         __kernel_old_gid_t;
typedef long long              __kernel_loff_t;
typedef struct {
#if defined(__KERNEL__) || defined(__USE_ALL)
        int     val[2];
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
        int     __val[2];
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;

> Maybe this is old code that was added before checkpatch existed?
>
>> It looks the kernel is not going to fix the "old" typedef for
>> posix_types.h and types.h
>
> Eventually they would not add these files as is any more today.
>

Even though kernel would not add these files with "typedef" for
implementing POSIX,
however, any new architecture want to be commit to Linux kernel must
implementing
the old "typedef" code for POSIX compatibility support unless they
want to rewrite all
POSIX interfaces.

2. types.h
typedef unsigned short umode_t;
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
Take phys_addr_t as example, the following code in u-boot will use it.
 include/common.h:223:phys_size_t initdram (int) will use such typedef.
../include/lmb.h:40:extern phys_addr_t lmb_alloc(struct lmb *lmb,
phys_size_t size, ulong align);
../include/addr_map.h:27:                               phys_size_t
size, int idx);
../include/image.h:455:phys_size_t getenv_bootm_size(void);

This file will use umode_t
../fs/ubifs/ubifs.h:115:        umode_t                 i_mode;

>> I think they say "please do not add any new typedef" might mean to
>> those typedef
>> used in drivers or protocols.
>
> I mean all of them.
>
>> In the other 2 files arch/nds32/include/asm/global_data.h and
>> arch/nds32/include/asm/u-boot.h,
>> typedef was used for
>> #449: FILE: arch/nds32/include/asm/global_data.h:46:
>> +typedef ? ? ? ?struct global_data {
>> +} gd_t;
>> #1505: FILE: arch/nds32/include/asm/u-boot.h:41:
>> +typedef struct bd_info {
>> +} bd_t;
>
> Ouch. You got me there... :-(
>
>> I don't know if you have any idea of fixing it in u-boot.
>
> Well, the fix is basicly straightforward - replace all ocurrences of
> gd_t and bd_t in the U-Boot code. ?But this is a bigger issue and more
> work than I dare to push on you. ?I'm grinding my teeth, but I will
> accept these.

Okay, well then, according to the list above I think the problem of typedefs in
global_data.h and u-boot.h is similar to types.h. I don't know if you
agree with it?

If posix_types.h won't be used in u-boot, I'll suggest u-boot remove it.
However, I've found that if I have removed posix_types.h in
arch/nds32/includes/asm
will lead the following compilation fail.

/home/macpaul/u-boot/u-boot-nds32/include/linux/posix_types.h:46:29:
asm/posix_types.h: No such file or directory
In file included from /home/macpaul/u-boot/u-boot-nds32/include/linux/types.h:8,
                 from /home/macpaul/u-boot/u-boot-nds32/include/common.h:40,
                 from lib/asm-offsets.c:18:
/home/macpaul/u-boot/u-boot-nds32/include/linux/posix_types.h:46:29:
asm/posix_types.h: No such file or directory
/home/macpaul/u-boot/u-boot-nds32/include/linux/types.h:14: error:
parse error before "dev_t"
/home/macpaul/u-boot/u-boot-nds32/include/linux/types.h:14: warning:
type defaults to `int' in declaration of `dev_t'
/home/macpaul/u-boot/u-boot-nds32/include/linux/types.h:14: warning:
data definition has no type or storage class
/home/macpaul/u-boot/u-boot-nds32/include/linux/types.h:15: error:
parse error before "ino_t"
/home/macpaul/u-boot/u-boot-nds32/include/linux/types.h:15: warning:
type defaults to `int' in declaration of `ino_t'
/home/macpaul/u-boot/u-boot-nds32/include/linux/types.h:15: warning:
data definition has no type or storage class
/home/macpaul/u-boot/u-boot-nds32/include/linux/types.h:16: error:
parse error before "mode_t"
... and more.

These are indeed related to typedef in posix_types.h

According to Chao's informations, I think the files of these typedef
we've send is comfort to Linux's coding styles.

Thanks.

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v9 01/10] nds32: add header files support for nds32

[Macpaul Lin]

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v4:
   - Code cleanup and style formatting.
Changes for v5-v6:
   - This patch also updated the following changes against the
     change after master tree (v2010.12-rc1).
   - fix upper case definitions in cache.h
   - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
   - Add readsb, writesb functions into io.h.
Changes for v7:
   - clean up
   - volatile:
    - types.h
     - remove typedef volatile unsigned char  vuchar;
     - remove typedef volatile unsigned long  vulong;
     - remove typedef volatile unsigned short vushort;
    - u-boot.h: remove bd_info_ext bi_ext
    - bitops.h: add accessor function to bit operation with volatile var.
    - system.h: add system.h for local_irq operation with flag.
Changes for v8:
   - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
   - ptregs.h: removed
Changes for v9:
   - No change.
---
 arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
 arch/nds32/include/asm/byteorder.h    |   36 +++
 arch/nds32/include/asm/cache.h        |   54 +++++
 arch/nds32/include/asm/config.h       |   26 ++
 arch/nds32/include/asm/global_data.h  |   82 +++++++
 arch/nds32/include/asm/io.h           |  410 +++++++++++++++++++++++++++++++++
 arch/nds32/include/asm/mach-types.h   |   29 +++
 arch/nds32/include/asm/memory.h       |   19 ++
 arch/nds32/include/asm/posix_types.h  |   84 +++++++
 arch/nds32/include/asm/processor.h    |   25 ++
 arch/nds32/include/asm/ptrace.h       |   88 +++++++
 arch/nds32/include/asm/string.h       |   57 +++++
 arch/nds32/include/asm/system.h       |   88 +++++++
 arch/nds32/include/asm/types.h        |   63 +++++
 arch/nds32/include/asm/u-boot-nds32.h |   50 ++++
 arch/nds32/include/asm/u-boot.h       |   63 +++++
 arch/nds32/include/asm/unaligned.h    |   31 +++
 17 files changed, 1391 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/bitops.h
 create mode 100644 arch/nds32/include/asm/byteorder.h
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/config.h
 create mode 100644 arch/nds32/include/asm/global_data.h
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/include/asm/mach-types.h
 create mode 100644 arch/nds32/include/asm/memory.h
 create mode 100644 arch/nds32/include/asm/posix_types.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/system.h
 create mode 100644 arch/nds32/include/asm/types.h
 create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
 create mode 100644 arch/nds32/include/asm/u-boot.h
 create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..c56f04b
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void *addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+extern void clear_bit(int nr, volatile void *addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, volatile void *addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, volatile void *addr);
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ	6	/* I-cache line size */
+#define ICM_CFG_MSK_ISZ	(0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
+#define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..23421b7
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..a3e5b4c
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+#ifdef CONFIG_VFD
+	unsigned char	vfd_type;	/* display type */
+#endif
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT		0x00004	/* Silent mode			*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	*/
+#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG8
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r8")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..be097ec
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,410 @@
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <asm/memory.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+#define writeb(v, a)			__arch_putb(v, a)
+#define writew(v, a)			__arch_putw(v, a)
+#define writel(v, a)			__arch_putl(v, a)
+
+#define readb(a)			__arch_getb(a)
+#define readw(a)			__arch_getw(a)
+#define readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache)				\
+({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
+	_ret;								\
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"), 0)
+#define readw(addr)			(__readwrite_bug("readw"), 0)
+#define readl(addr)			(__readwrite_bug("readl"), 0)
+#define writeb(v, addr)			__readwrite_bug("writeb")
+#define writew(v, addr)			__readwrite_bug("writew")
+#define writel(v, addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101             0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101()	(machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101()	(0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index 0000000..5bcc4e1
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/memory.h
+ *
+ * Copyright (C) 2000-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Note: this file should not be included by non-asm/.h files
+ */
+#ifndef __ASM_NDS_MEMORY_H
+#define __ASM_NDS_MEMORY_H
+
+#endif	/* __ASM_NDS_MEMORY_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..4336083
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+	NDS32_REG ir0;
+	NDS32_REG ipsw;
+	NDS32_REG ipc;
+	NDS32_REG sp;
+	NDS32_REG orig_r0;
+	NDS32_REG pipsw;
+	NDS32_REG pipc;
+	NDS32_REG pp0;
+	NDS32_REG pp1;
+	NDS32_REG d0hi;
+	NDS32_REG d0lo;
+	NDS32_REG d1hi;
+	NDS32_REG d1lo;
+	NDS32_REG r[26];	/* r0 - r25 */
+	NDS32_REG fp;		/* r28 */
+	NDS32_REG gp;		/* r29 */
+	NDS32_REG lp;		/* r30 */
+	NDS32_REG fucop_ctl;
+	NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+	(((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..2383e08
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong _andesboot_start;		/* code start */
+extern ulong _andesboot_end;		/* code end */
+extern ulong _andesboot_real_end;	/* first usable RAM address */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+/* cpu/.../timer.c */
+int	timer_init(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..fafe4e4
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <environment.h>
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+
+	env_t		*bi_env;
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..ffa7e30
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Andes Technology Corporation
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _ASM_NDS_UNALIGNED_H
+#define _ASM_NDS_UNALIGNED_H
+
+#include <compiler.h>
+/*
+ * Select endianness
+ */
+#ifndef __NDSEB__
+#define get_unaligned	__get_unaligned_le
+#define put_unaligned	__put_unaligned_le
+#else
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+#endif /* __NDSEB__ */
+
+#include <asm/byteorder.h>
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+#endif /* _ASM_NDS_UNALIGNED_H */
-- 
1.7.3.5

[U-Boot] [PATCH v9 02/10] nds32: add NDS32 support into common header file

[Macpaul Lin]

Add NDS32 support into common header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v7:
  - No change
Changes for v8:
  - Fix the patch according to dependency of x86's Fix
Changes for v9:
  - No change
---
 include/common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index 00e266e..aa1abe6 100644
--- a/include/common.h
+++ b/include/common.h
@@ -275,6 +275,10 @@ int	setenv	     (char *, char *);
 #ifdef CONFIG_X86		/* x86 version to be fixed! */
 # include <asm/u-boot-x86.h>
 #endif /* CONFIG_X86 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h>	/* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
-- 
1.7.3.5

[U-Boot] [PATCH v9 03/10] nds32/core N1213: NDS32 N12 core family N1213

[Macpaul Lin]

Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

NDS32 Core N1213 has the following hardware features.

 Core:
  - 16-/32-bit mixable instruction format
  - 32 general-purpose 32-bit registers
  - 8-stage pipeline
  - Dynamic branch prediction
  - 32/64/128/256 BTB
  - Return address stack (RAS)
  - Vector interrupts for internal/external
  - 3 HW-level nested interruptions
  - User and super-user mode support
  - Memory-mapped I/O
  - Address space up to 4GB

 Memory Management Unit:
  - TLB
  - Optional hardware page table walker
  - Two groups of page size support

 Memory Subsystem:
  - I & D cache
  - I & D local memory (LM)

 Bus Interface:
  - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes v1 to v6:
  - Style clean up and reorganize code
Changes v7-v9:
  - No Change.
---
 arch/nds32/cpu/n1213/Makefile   |   50 +++++
 arch/nds32/cpu/n1213/start.S    |  447 +++++++++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/u-boot.lds |   68 ++++++
 3 files changed, 565 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/Makefile
 create mode 100644 arch/nds32/cpu/n1213/start.S
 create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..111d14f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..b04f3a5
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,447 @@
+/*
+ *	Andesboot - Startup Code for Whitiger core
+ *
+ *	Copyright (C) 2006	Andes Technology Corporation
+ *	Copyright (C) 2006	Shawn Lin <nobuhiro@andestech.com>
+ *	Copyright (C) 2011	Macpaul <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC		2UL
+#define DIS_DCAC		~ENA_DCAC
+#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
+#define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
+#define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY	(0x07<<3)	! D cache ways
+#define DCAC_MEM_KBF_DSZ	(0x07<<6)	! D cache line size
+
+#define PSW			$ir0
+#define EIT_INTR_PSW		$ir1		! interruption $PSW
+#define EIT_PREV_IPSW		$ir2		! previous $IPSW
+#define EIT_IVB			$ir3		! intr vector base address
+#define EIT_EVA			$ir4		! MMU related Exception Virtual Address register */
+#define EIT_PREV_EVA		$ir5		! previous $eva
+#define EIT_ITYPE		$ir6		! interruption type
+#define EIT_PREV_ITYPE		$ir7		! prev intr type
+#define EIT_MACH_ERR		$ir8		! machine error log
+#define EIT_INTR_PC		$ir9		! Interruption PC
+#define EIT_PREV_IPC		$ir10		! previous $IPC
+#define EIT_OVL_INTR_PC		$ir11		! overflow interruption PC
+#define EIT_PREV_P0		$ir12		! prev $P0
+#define EIT_PREV_P1		$ir13		! prev $p1
+#define CR_ICAC_MEM		$cr1		! I-cache/memory config reg
+#define CR_DCAC_MEM		$cr2		! D-cache/memory config reg
+#define MR_CAC_CTL		$mr8
+
+.globl _start
+
+_start:	b	reset
+	b	tlb_fill
+	b	tlb_not_present
+	b	tlb_misc
+	b	tlb_vlpt_miss
+	b	cache_parity_error
+	b	debug
+	b	general_exception
+	b	internal_interrupt		! H0I
+	b	internal_interrupt		! H1I
+	b	internal_interrupt		! H2I
+	b	internal_interrupt		! H3I
+	b	internal_interrupt		! H4I
+	b	internal_interrupt		! H5I
+
+	.balign 16
+
+!========================================================================
+! Andesboot Startup Code (reset vector)
+!
+!	1.	bootstrap
+!		1.1 reset - start of Andesboot
+!		1.2 to superuser mode - as is when reset
+!		1.4 Do lowlevel_init
+!			- (this will jump out to lowlevel_init.S in SoC)
+!			- (lowlevel_init)
+!		1.3 Turn off watchdog timer
+!			- (this will jump out to watchdog.S in SoC)
+!			- (turnoff_watchdog)
+!	2.	Do critical init when reboot (not from mem)
+!	3.	Relocate andesboot to ram
+!	4.	Setup stack
+!	5.	Jump to second stage (start_andesboot)
+!========================================================================
+
+! Note: TEXT_BASE is defined by the (board-dependent) linker script
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+.globl _andesboot_start
+_andesboot_start:
+	.word _start
+
+! Note: andesboot_end is defined by the (board-dependent) linker script
+.globl _andesboot_end
+_andesboot_end:
+	.word andesboot_end
+
+! _andesboot_real_end is the first usable RAM address behind Andesboot
+! and the various stacks
+.globl _andesboot_real_end
+_andesboot_real_end:
+	.word 0x0badc0de
+
+!=============================================
+! The bootstrap code of Andesboot
+!=============================================
+
+reset:
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	jal	load_lowlevel_init
+	jral	$p0
+#endif
+
+! Set the Whitiger core to superuser mode
+! According to spec, it is already when reset
+
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+	jal	load_turnoff_watchdog
+	jral	$p0
+#endif
+
+! Do CPU critical regs init only at reboot, not when booting from ram
+#ifdef CONFIG_INIT_CRITICAL
+	bal	cpu_init_crit			! Do CPU critical regs init
+#endif
+
+	.align 2
+relocate:
+	! relocate andesboot to RAM
+	jal	2f
+	!la	$r0, _start			! $r0 = source start addr
+	!l.w	$r2, _andesboot_start		! Andesboot start address
+	!l.w	$r3, _andesboot_end		! Andesboot end address
+	!sub	$r2, $r3, $r2			! $r2 = size of Andesboot
+	!l.w	$r1, _TEXT_BASE			! $r1 = destination start addr
+	move	$r0, $lp
+	la	$p0, _start
+	la	$p1, relocate+4
+	sub	$p0, $p1, $p0
+	sub	$r0, $r0, $p0
+
+	la	$p0, _andesboot_end
+	sub	$p0, $p0, $p1
+	move	$r3, $lp
+	lw	$r3, [$r3+$p0]			! _andesboot_end
+	addi	$p0, $p0, -4
+	move	$r2, $lp
+	lw	$r2, [$r2+$p0]			! _andesboot_start
+	sub	$r2, $r3, $r2
+	addi	$p0, $p0, -4
+	move	$r1, $lp
+	lw	$r1, [$r1+$p0]			! _TEXT_BASE
+
+	! $r0 = source address
+	! $r1 = destination address
+	! $r2 = size to copy
+copy_loop:
+	lmw.bim $r3, [$r0], $r10
+	smw.bim $r3, [$r1], $r10
+	addi	$r2, $r2, -32
+	bgez	$r2, copy_loop
+
+	! Set up the stack
+	l.w	$p0, _andesboot_end		! Defined by board linker script
+	li	$p1, CONFIG_STACKSIZE		! (128*1024) defined in config.h
+	add	$sp, $p0, $p1
+
+	bal	flib_init_bss_memory
+
+	! Jump to start_andesboot (2nd phase)
+	l.w	$p0, __start_andesboot
+	br	$p0
+
+__start_andesboot:	.word start_andesboot
+
+!=========================================================================
+! Initialize CPU critical registers
+!
+!	1.	Setup control registers
+!		1.1 Mask all IRQs
+!		1.2 Flush cache and TLB
+!		1.3 Disable MMU and cache
+!	2.	Setup memory timing
+!=========================================================================
+
+cpu_init_crit:
+	!push	ra
+	move	$r0, $lp
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	! Flush caches and TLB
+
+	! Invalidate caches
+	bal	invalidate_icac
+	bal	invalidate_dcac
+
+	! Flush TLB
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	FlushAll			! Flush TLB
+
+1:
+	! Disable MMU, Dcache
+	! Whitiger is MMU disabled when reset
+	! Disable the D$
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Set DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! write back the $CACHE_CTL reg
+	isb
+
+	! RAM is initialized in the dram_init()(board/nds32/cpe.c)
+	! Remove the memsetup.S in the board directory.
+	!pop	ra
+
+	move	$lp, $r0
+2:
+	ret
+
+flib_init_bss_memory:
+	smw.adm $r4, [$sp], $r6, #0x1
+
+	la	$r4, __bss_start
+	la	$r5, __bss_end
+	move	$r6, #0
+1:
+	swi.p	 $r6, [$r4], #4
+	blt	 $r4, $r5, 1b			! Check if done..
+
+	lmw.bim $r4, [$sp], $r6, #0x1
+	ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+	la  $r6, lowlevel_init
+	la  $r7, load_lli + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+	la  $r6, turnoff_watchdog
+	la  $r7, turnoff_wtdog + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+
+!=======================================================
+! Invalidate I$
+!=======================================================
+invalidate_icac:
+	mfsr	$t0, CR_ICAC_MEM		! read $cr1(I CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, ICAC_MEM_KBF_ISZ 	! Get the ISZ field
+	beqz	$p0, end_flush_icache		! if $p0=0, then no I CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of I$ block
+	addi	$t1, $p0, 2			! $t1= bit width of I cache line size(ISZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, ICAC_MEM_KBF_ISET	! get the ISET field
+	addi	$t2, $p1, 6			! $t2= bit width of ISET
+	andi	$p1, $t0, ICAC_MEM_KBF_IWAY	! get bitfield of Iway
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is I way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+ICAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1I_IX_INVAL
+	bnez	$p1, ICAC_LOOP
+end_flush_icache:
+	ret
+
+!=======================================================
+! Invalidate D$
+!=======================================================
+invalidate_dcac:
+	mfsr	$t0, CR_DCAC_MEM		! read $cr2(D CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, DCAC_MEM_KBF_DSZ	! Get the DSZ field
+	beqz	$p0, end_flush_dcache		! if $p0=0, then no D CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of D$ block
+	addi	$t1, $p0, 2			! $t1= bit width of D cache line size(DSZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, DCAC_MEM_KBF_DSET	! get the DSET field
+	addi	$t2, $p1, 6			! $t2= bit width of DSET
+	andi	$p1, $t0, DCAC_MEM_KBF_DWAY	! get bitfield of D way
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is D way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+DCAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1D_IX_INVAL
+	bnez	$p1, DCAC_LOOP
+end_flush_dcache:
+	ret
+
+!========================================================================
+! Interrupt handling
+!========================================================================
+
+/*
+ * exception handlers
+ */
+	.align	5
+
+		.macro	SAVE_ALL
+	! FIXME: Other way to get PC?
+	! FIXME: Update according to the newest spec!!
+1:	la	 $r28, 1
+	push $r28
+		mfsr $r28, PSW			! $PSW
+		push $r28
+		mfsr $r28, EIT_EVA		! $ir1 $EVA
+		push $r28
+		mfsr $r28, EIT_ITYPE		! $ir2 $ITYPE
+		push $r28
+		mfsr $r28, EIT_MACH_ERR		! $ir3 Mach Error
+		push $r28
+		mfsr $r28, EIT_INTR_PSW		! $ir5 $IPSW
+		push $r28
+		mfsr $r28, EIT_PREV_IPSW	! $ir6 prev $IPSW
+		push $r28
+		mfsr $r28, EIT_PREV_EVA		! $ir7 prev $EVA
+		push $r28
+		mfsr $r28, EIT_PREV_ITYPE	! $ir8 prev $ITYPE
+		push $r28
+		mfsr $r28, EIT_INTR_PC		! $ir9 Interruption PC
+		push $r28
+		mfsr $r28, EIT_PREV_IPC		! $ir10 prev INTR_PC
+		push $r28
+		mfsr $r28, EIT_OVL_INTR_PC	! $ir11 Overflowed INTR_PC
+		push $r28
+		mfusr $r28, $d1.lo
+		push $r28
+		mfusr $r28, $d1.hi
+		push $r28
+		mfusr $r28, $d0.lo
+		push $r28
+		mfusr $r28, $d0.hi
+		push $r28
+		pushm $r0,$r30			/* we will also store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp */
+		addi	$sp, $sp, -4		! make room for implicit pt_regs parameters
+		.endm
+
+	.align	5
+tlb_fill:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 1				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_not_present:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 2				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_misc:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 3				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_vlpt_miss:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 4				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+cache_parity_error:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 5				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+debug:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 6				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+general_exception:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 7				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+internal_interrupt:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 8				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+
+!===========================================
+!void reset_cpu(ulong addr);
+!	$r0: input address to jump to
+!===========================================
+.globl reset_cpu
+reset_cpu:
+! No need to disable MMU because we never enable it!
+
+	bal	invalidate_icac
+	bal	invalidate_dcac
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	FlushAll			! Flush TLB
+1:
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Clear the DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! Write back the $CACHE_CTL reg
+	br	$r0				! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..824d05d
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		arch/nds32/cpu/n1213/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	andesboot_end = .;
+
+	. = 0x02000000;
+	.u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
-- 
1.7.3.5

[U-Boot] [PATCH v9 04/10] nds32/ag101: dev offset header of SoC ag101

[Macpaul Lin]

Add header file of device offset support for SoC ag101.

SoC ag101 is the first chip using NDS32 N1213 cpu core.

Note:
   Ag101 is actually use ftsdmc021 instead of ftsdmc020
   as dram controller, which is probably wrong in the datasheet.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v6:
  - Code clean up and style formatting.
Changes for v7-v9:
  - No change.
---
 arch/nds32/include/asm/arch-ag101/ag101.h |   68 +++++++++++++++++++++++++++++
 1 files changed, 68 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE		0x90100000	/* AHB Controller */
+#define CONFIG_FTSMC020_BASE		0x90200000	/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE		0x90300000	/* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000	/* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000	/* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE		0x90600000	/* LCD Controller */
+#define CONFIG_RESERVED_01_BASE		0x90700000	/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000	/* Reserved */
+#define CONFIG_FTMAC100_BASE		0x90900000	/* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000	/* External USB host */
+#define CONFIG_USB_DEV_BASE		0x90B00000	/* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000	/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE		0x90D00000	/* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000	/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000	/* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000	/* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC	/* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE		0x98100000	/* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE	0x98300000	/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE		0x98400000	/* Counter/Timers */
+#define CONFIG_FTWDT010_BASE		0x98500000	/* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE		0x98600000	/* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE		0x98700000	/* GPIO */
+#define CONFIG_FTINTC010_BASE		0x98800000	/* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE		0x98A00000	/* I2C */
+#define CONFIG_RESERVED_04_BASE		0x98C00000	/* Reserved */
+#define CONFIG_FTCFC010_BASE		0x98D00000	/* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000	/* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE		0x99400000	/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE	0x99600000	/* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE	0x98200000	/* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000	/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE		0x98900000	/* IrDA */
+#define CONFIG_PMW_BASE			0x99100000	/* PWM - Pulse Width Modulator Controller */
+
+#endif	/* __AG101_H */
-- 
1.7.3.5

[U-Boot] [PATCH v9 05/10] nds32/ag101: lowlevel_init.S of ag101

[Macpaul Lin]

lowlevel_init.S is a peripheral initial procedure of ag101.
It configures onboard dram, clock, and power settings.
It also prepars the dram environment before moving u-boot
from rom and flash into dram.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes from v1-v4:
  - Code clean up and formatting style.
Changes from v5-v6
  - Change hard code value into MARCO definitions.
  - ftsmc010
    - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
  - ftsdmc021
    - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
    - Fix the default configuration value of FTSDMC and FTSMC controller.
  - Remove some ftpmu010 and flash probe code to C functions.
Changes for v7-v9:
  - No change.
---
 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  160 ++++++++++++++++++++++++++++
 1 files changed, 160 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S

diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..96969ba
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+	jal	mem_init
+	jal	remap
+
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	li	$r0, (CONFIG_FTSMC020_BASE+FTSMC020_BANK0_CR)
+	li	$r1, (FTSMC020_BANK1_CONFIG)			! 0x10000052
+	swi	$r1, [$r0]
+	li	$r1, (FTSMC020_BANK1_TIMING)			! 0x00151151
+	swi	$r1, [$r0+FTSMC020_BANK0_TPR]
+
+	/*
+	 * config AHB Controller
+	 */
+	li	$r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+	li	$r1, (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6)
+	swi	$r1, [$r0]
+
+	/*
+	 * config PMU
+	 */
+	li	$r0, (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+	lwi	$r1, [$r0]
+	! ftpmu010_dlldis_disable, must do it in lowleve_init
+	li	$r2, FTPMU010_PDLLCR0_DLLDIS			! 0x00010000
+	or	$r1, $r1, $r2
+	swi	$r1, [$r0]
+
+	/*
+	 * config SDRAM controller
+	 */
+	li	$r0, (CONFIG_FTSDMC021_BASE)
+	li	$r1, (CONFIG_SYS_FTSDMC021_TP1) ! 0x00011312
+	swi	$r1, [$r0]
+	li	$r1, (CONFIG_SYS_FTSDMC021_TP2) ! 0x00480180
+	swi	$r1, [$r0+FTSDMC021_OFFSET_TP2]
+	li	$r1, (CONFIG_SYS_FTSDMC021_CR1)	! 0x00002326
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR1]
+	li	$r1, (FTSDMC021_CR2_IPREC)	! 0x00000010
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+1:
+	lwi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+	andi	$r1, $r1, (CONFIG_SYS_FTSDMC021_CR2)	! 0x1C
+	bnez	$r1, 1b
+
+	li	$r1, (FTSDMC021_CR2_ISMR)	! 0x00000004
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+2:
+	lwi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+	bnez	$r1, 2b
+
+	li	$r1, (FTSDMC021_CR2_IREF)	! 0x00000008
+	swi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+3:
+	lwi	$r1, [$r0+FTSDMC021_OFFSET_CR2]
+	bnez	$r1, 3b
+
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* AG101 */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif
+
+	/*
+	 * relocation, copy ROM code to SDRAM (current at 0x10000000)
+	 */
+	li	$r4, CONFIG_SYS_RELO_ADDR		! 0x10000000
+	li	$r5, 0x0
+	la	$r1, relo_base
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(andesboot_end)
+	ori	$r6, $r6, lo12(andesboot_end)
+	add	$r6, $r6, $r2
+1:
+	lwi	$r7, [$r5]
+	swi	$r7, [$r4]
+	addi	$r5, $r5, #4
+	addi	$r4, $r4, #4
+	blt	$r5, $r6, 1b
+
+	/*
+	 * Remapping
+	 */
+	li	$r0, (CONFIG_FTSDMC021_BASE + FTSDMC021_OFFSET_TP1)
+	li	$r1, (CONFIG_SYS_FTSDMC021_BANK0_BSR)	! 0x00001100
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK0_BSR]
+	li	$r1, 0x0
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK1_BSR]
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK2_BSR]
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK3_BSR]
+	li	$r1, (FTSDMC021_BANK_ENABLE)		! 0x00001000
+	swi	$r1, [$r0+FTSDMC021_OFFSET_BANK0_BSR]
+
+	li	$r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+	lwi	$r1, [$r0]
+	ori	$r1, $r1, FTAHBC020S_CR_REMAP		! 0x1
+	swi	$r1, [$r0]
+
+	li	$r0, (CONFIG_FTSMC020_BASE)
+
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif
-- 
1.7.3.5

[U-Boot] [PATCH v9 05/10] nds32/ag101: lowlevel_init.S of ag101

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1304342712-17120-5-git-send-email-macpaul@andestech.com> you wrote:
> lowlevel_init.S is a peripheral initial procedure of ag101.
> It configures onboard dram, clock, and power settings.
> It also prepars the dram environment before moving u-boot
> from rom and flash into dram.
> 
> This version of lowlevel_init.S also replace hardcode value
> by MARCO defines from the GPL version andesboot for better
> code quality.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> 
> Changes from v1-v4:
>   - Code clean up and formatting style.
> Changes from v5-v6
>   - Change hard code value into MARCO definitions.
>   - ftsmc010
>     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
>   - ftsdmc021
>     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
>     - Fix the default configuration value of FTSDMC and FTSMC controller.
>   - Remove some ftpmu010 and flash probe code to C functions.
> Changes for v7-v9:
>   - No change.
> ---

Patch changelog belongs _below_ the "---" line, not above.

>  arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  160 ++++++++++++++++++++++++++++
>  1 files changed, 160 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S

This file alone makes no sense.  Pluease submit as a single commit
together with the other board code.

...
> +	/*
> +	 * relocation, copy ROM code to SDRAM (current at 0x10000000)
> +	 */
> +	li	$r4, CONFIG_SYS_RELO_ADDR		! 0x10000000
> +	li	$r5, 0x0
> +	la	$r1, relo_base
> +	sub	$r2, $r0, $r1
> +	sethi	$r6, hi20(andesboot_end)
> +	ori	$r6, $r6, lo12(andesboot_end)
> +	add	$r6, $r6, $r2
> +1:
> +	lwi	$r7, [$r5]
> +	swi	$r7, [$r4]
> +	addi	$r5, $r5, #4
> +	addi	$r4, $r4, #4
> +	blt	$r5, $r6, 1b

You are using  non-standard and completely undocumented CONFIG option
here, CONFIG_SYS_RELO_ADDR.  Please don't.  I think when adding new
architecture support we should avaid errors done with other
architectures in the past (see ARM, MIPS, ...).

Please implement proper relocation to a dynamically determined
address at the upper end of RAM. Keep in mind that the intention is
to have only a single lib/board.c isnatead of a collection of
slightly different arch-specific arch/*/board.c versions.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
In an organization, each person rises to the level of his own  incom-
petency                                         - The Peter Principle

[U-Boot] [PATCH v9 05/10] nds32/ag101: lowlevel_init.S of ag101

[Macpaul Lin]

Hi Wolfgang,

> Patch changelog belongs _below_ the "---" line, not above.

Sorry for this mistaken, will fix in Patch v10

>> ?arch/nds32/cpu/n1213/ag101/lowlevel_init.S | ?160 ++++++++++++++++++++++++++++
>> ?1 files changed, 160 insertions(+), 0 deletions(-)
>> ?create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
>
> This file alone makes no sense. ?Pluease submit as a single commit
> together with the other board code.

The single file is intend to be reviewed and fix up easyly because I
know there must be some problem of this lowlevel_init.S.
I think this should go with the SoC. So I will merge it into ag101 SoC
level related code.

> ...
>> + ? ? /*
>> + ? ? ?* relocation, copy ROM code to SDRAM (current at 0x10000000)
>> + ? ? ?*/
>> + ? ? li ? ? ?$r4, CONFIG_SYS_RELO_ADDR ? ? ? ? ? ? ? ! 0x10000000
>> + ? ? li ? ? ?$r5, 0x0
>> + ? ? la ? ? ?$r1, relo_base
>> + ? ? sub ? ? $r2, $r0, $r1
>> + ? ? sethi ? $r6, hi20(andesboot_end)
>> + ? ? ori ? ? $r6, $r6, lo12(andesboot_end)
>> + ? ? add ? ? $r6, $r6, $r2
>> +1:
>> + ? ? lwi ? ? $r7, [$r5]
>> + ? ? swi ? ? $r7, [$r4]
>> + ? ? addi ? ?$r5, $r5, #4
>> + ? ? addi ? ?$r4, $r4, #4
>> + ? ? blt ? ? $r5, $r6, 1b
>
> You are using ?non-standard and completely undocumented CONFIG option
> here, CONFIG_SYS_RELO_ADDR. ?Please don't. ?I think when adding new
> architecture support we should avaid errors done with other
> architectures in the past (see ARM, MIPS, ...).

Sure.

> Please implement proper relocation to a dynamically determined
> address at the upper end of RAM. Keep in mind that the intention is
> to have only a single lib/board.c isnatead of a collection of
> slightly different arch-specific arch/*/board.c versions.
>
> Best regards,
>
> Wolfgang Denk

Will try to fix it soon.
Thanks.

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v9 06/10] nds32/ag101: cpu and init funcs of SoC ag101

[Macpaul Lin]

Add main function of SoC ag101 based on NDS32 n1213 core.

cpu.c
 According to the bootstrap procedure in n1213 Core,
 to turn off watchdog timer is suggested after the
 cpu is in superuser mdoe.

 1. bootstrap
 1.1 reset - start of Andesboot
 1.2 to superuser mode - as is when reset
 1.3 Turn off watchdog timer

 If you take look into the start.S in n1213, you will find that
 system will turn off watchdog after start.S has been retunred
 from lowlevel_init.

 Since the watchdog device is depends on the SoC is choosed.
 It should be belonged to the SoC (ag101) folder.

watchdog.S:
 If you've ran another bootloader before u-boot was started
 the watchdog might have been enabled already.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v4:
  - Code clean up.
Changes for v5-v6:
  - Split watchdog.S from lowlevel_init.S.
  - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
   - reset_cpu was remove inside do_reset().
Changes for v7:
  - clean up.
Changes for v8-v9:
  - No change.
---
 arch/nds32/cpu/n1213/ag101/Makefile   |   58 +++++++++
 arch/nds32/cpu/n1213/ag101/cpu.c      |  207 +++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/timer.c    |  204 ++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/watchdog.S |   48 ++++++++
 4 files changed, 517 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
 create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S

diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..e96b1e4
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..8e7eb0a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/* setup up stack if necessary */
+/* it makes no sense to use the caches if the MMU also isn't used */
+void cpu_init(void)
+{
+	_andesboot_real_end = _andesboot_end + CONFIG_STACKSIZE;
+}
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+	unsigned long i;
+#endif
+
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+	while (1)
+		;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr , addr + size);
+	icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..87275eb
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (APB_CLK);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / (APB_CLK);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * (APB_CLK / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl	turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+#endif
-- 
1.7.3.5

[U-Boot] [PATCH v9 07/10] nds32/lib: add generic funcs in NDS32 lib

[Macpaul Lin]

Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v4:
  - code clean up and formatting style.
Changes for v5-v6:
  - board.c
   - Do some clean up and add code
   - Remove display banner which hasn't support.
   - Add ftpmu010 related power management unit code.
   - Remove useless LED related code.
   - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
   - Remove CONFIG_SOFT_I2C which hasn't been support.
   - Remove CONFIG_FSL_ESDHC which hasn't been support.
   - clean up.
Changes for v7:
  - clean up.
  - move single file patch arch/nds32/config.mk to this commit.
  - interrupts.c refine origin interrupt enable and disable.
Changes for v8:
  - interrups.c: fix up for new ptraces.h.
Changes for v9:
  - support CONFIG_STANDALONE_LOAD_ADDR in config.mk

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
 arch/nds32/config.mk        |   35 +++++
 arch/nds32/lib/Makefile     |   52 +++++++
 arch/nds32/lib/board.c      |  346 +++++++++++++++++++++++++++++++++++++++++++
 arch/nds32/lib/bootm.c      |  241 ++++++++++++++++++++++++++++++
 arch/nds32/lib/interrupts.c |  131 ++++++++++++++++
 5 files changed, 805 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/config.mk
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/board.c
 create mode 100644 arch/nds32/lib/bootm.c
 create mode 100644 arch/nds32/lib/interrupts.c

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..3df2963
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common
+PLATFORM_RELFLAGS	+= -gdwarf-2
+PLATFORM_CPPFLAGS	+= -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-8
+
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..eca4324
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+OBJS	:= board.o bootm.o interrupts.o
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..6ed4194
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,346 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern ulong __bss_end;
+ulong monitor_flash_len;
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+const char version_string[] =
+	U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	char tmp[64];	/* long enough for environment variables */
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+			? (int) simple_strtoul(tmp, NULL, 10)
+			: CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+	pmu_init,
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init,
+#endif
+	display_dram_config,
+	NULL,
+};
+
+void start_andesboot(void)
+{
+	init_fnc_t **init_fnc_ptr;
+	char *s;
+#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
+	unsigned long addr;
+#endif
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)(_andesboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t));
+	/* compiler optimization barrier needed for GCC >= 3.4 */
+	__asm__ __volatile__("" : : : "memory");
+
+	memset((void *)gd, 0, sizeof(gd_t));
+	gd->bd = (bd_t *)((char *)gd - sizeof(bd_t));
+	memset(gd->bd, 0, sizeof(bd_t));
+
+	gd->flags |= GD_FLG_RELOC;
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	/* andesboot_start is defined in the board-specific linker script */
+	mem_malloc_init(_andesboot_start - CONFIG_SYS_MALLOC_LEN,
+			CONFIG_SYS_MALLOC_LEN);
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#ifdef CONFIG_VFD
+#	ifndef PAGE_SIZE
+#	  define PAGE_SIZE 4096
+#	endif
+	/*
+	 * reserve memory for VFD display (always full pages)
+	 */
+	/* bss_end is defined in the board-specific linker script */
+	addr = (__bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+	vfd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_VFD */
+
+#ifdef CONFIG_LCD
+	/* board init may have inited fb_base */
+	if (!gd->fb_base) {
+#		ifndef PAGE_SIZE
+#		  define PAGE_SIZE 4096
+#		endif
+		/*
+		 * reserve memory for LCD display (always full pages)
+		 */
+		/* bss_end is defined in the board-specific linker script */
+		addr = (__bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+		lcd_setmem(addr);
+		gd->fb_base = addr;
+	}
+#endif /* CONFIG_LCD */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+	onenand_init();
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#ifdef CONFIG_VFD
+	/* must do this after the framebuffer is allocated */
+	drv_vfd_init();
+#endif /* CONFIG_VFD */
+
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
+	/* IP Address */
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+	/* enable exceptions */
+	enable_interrupts();
+
+	/* Perform network card initialisation if necessary */
+
+	/* Initialize from environment */
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+	puts("Net:   ");
+#endif
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	show_boot_progress(15);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..c42ad2b
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+extern void reset_cpu(ulong addr);
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"lp : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}
-- 
1.7.3.5

[U-Boot] [PATCH v9 08/10] nds32: standalone support

[Macpaul Lin]

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v6:
  - code clean up.
Changes for v7-v9:
  - No change.
---
 examples/standalone/nds32.lds     |   64 +++++++++++++++++++++++++++++++++++++
 examples/standalone/stubs.c       |   17 +++++++++-
 examples/standalone/x86-testapp.c |   12 +++++++
 3 files changed, 92 insertions(+), 1 deletions(-)
 create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..c2ac107
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	_end = .;
+
+	. = 0x02000000;
+	.u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 507d38c..11c7565 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
 "	jmp %%g1\n"					\
 "	nop\n"						\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	lwi	$r16, [$gp + (%0)]\n"	\
+"	lwi	$r16, [$r16 + (%1)]\n"	\
+"	jr	$r16\n"			\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
 #else
+/*"	addi	$sp, $sp, -24\n"	\
+"	br	$r16\n"			\*/
+
 #error stubs definition missing for this architecture
 #endif
 
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile (						\
 "	lw	$25, %1($25)\n"				\
 "	jr	$25\n"					\
 	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x)					\
+asm volatile (						\
+"	.globl mon_" #x "\n"				\
+"mon_" #x ":\n"						\
+"	lwi	$r16, [$gp + (%0)]\n"			\
+"	lwi	$r16, [$r16 + (%1)]\n"			\
+"	jr	$r16\n"					\
+	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
+
 #else
 #error [No stub code for this arch]
 #endif
@@ -72,6 +82,8 @@ int main(void)
 	register volatile xxx_t *pq asm("r8");
 #elif defined(__mips__)
 	register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+	register volatile xxx_t *pq asm("$r16");
 #endif
 	char buf[32];
 
-- 
1.7.3.5

[U-Boot] [PATCH v9 09/10] nds32: common bdinfo, bootm, image support

[Macpaul Lin]

Add support of NDS32 to common commands bdinfo, bootm, and image format.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v6:
  - Code clean up
Changes for v7-v9:
  - No Change.
---
 common/cmd_bdinfo.c |   28 +++++++++++++++++++++++++++-
 common/cmd_bootm.c  |    2 ++
 common/image.c      |    1 +
 include/image.h     |    5 +++++
 4 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 1d76ffa..cfa7de6 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -411,13 +411,39 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num("arch_number",	bd->bi_arch_number);
+	print_num("env_t",		(ulong)bd->bi_env);
+	print_num("boot_params",	(ulong)bd->bi_boot_params);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
 
 static void print_num(const char *name, ulong value)
 {
-	printf ("%-12s= 0x%08lX\n", name, value);
+	printf("%-12s= 0x%08lX\n", name, value);
 }
 
 #if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 1966da4..79b9031 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -187,6 +187,8 @@ void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
   #define IH_INITRD_ARCH IH_ARCH_SH
 #elif defined(__sparc__)
   #define IH_INITRD_ARCH IH_ARCH_SPARC
+#elif defined(__nds32__)
+  #define IH_INITRD_ARCH IH_ARCH_NDS32
 #else
 # error Unknown CPU type
 #endif
diff --git a/common/image.c b/common/image.c
index e542a57..dac17c0 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	-1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index c31e862..5a619bc 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_NDS32	        19	/* ANDES Technology - NDS32  */
 
 /*
  * Image Types
@@ -504,6 +505,8 @@ static inline int image_check_target_arch (const image_header_t *hdr)
 	if (!image_check_arch (hdr, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!image_check_arch (hdr, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!image_check_arch(hdr, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
@@ -656,6 +659,8 @@ static inline int fit_image_check_target_arch (const void *fdt, int node)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!fit_image_check_arch(fdt, node, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
-- 
1.7.3.5

[U-Boot] [PATCH v9 10/10] adp-ag101: add board adp-ag101 support

[Macpaul Lin]

Add evaluation board "adp-ag101" aconfiguration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v4:
  - code clean up
Changes for v5-v6:
  - Refine the definitions and parameters about CLK,
    AHB controller, SDRAM controller, Static memory controllers.
  - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
  - ftahbc010:
    - Update include path of ftahbc010.
  - ftsdmc021:
    - Update include path of ftsdmc021.
  - ftsmc020:
    - Update include path of ftsmc020.
  - ftwdt010:
    - Fix WDT define and update include path.
    - Fix ftwdt010 for hardware reset.
  - ftpmu010:
    - Remove duplicate PMU definitions.
    - Add related configurations.
  - Fix MAX malloc len and fix saveenv.
  - clean up.
Changes for v7:
  - clean up.
  - Move CONFIG_SYS_TEXT_BASE from board/config.mk.
  - Fix Makefile and remove config.mk
Changes for v8:
  - No change.
Changes for v9:
  - Fix because other boards has been added into boards.cfg and
    broken this patch.
---
 MAINTAINERS                           |   11 +
 MAKEALL                               |    6 +
 board/AndesTech/adp-ag101/Makefile    |   57 +++++
 board/AndesTech/adp-ag101/adp-ag101.c |   81 +++++++
 boards.cfg                            |    1 +
 include/configs/adp-ag101.h           |  378 +++++++++++++++++++++++++++++++++
 6 files changed, 534 insertions(+), 0 deletions(-)
 create mode 100644 board/AndesTech/adp-ag101/Makefile
 create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
 create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e2a4ba9..37194ad 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1138,5 +1138,16 @@ Chong Huang <chuang@ucrobotics.com>
 	bf525-ucr2	BF525
 
 #########################################################################
+# NDS32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+	ADP-AG101	N1213 (AG101 SoC)
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index c3df657..fd1c63e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -612,6 +612,12 @@ LIST_sh="$(boards_by_arch sh)"
 
 LIST_sparc="$(boards_by_arch sparc)"
 
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
 #-----------------------------------------------------------------------
 
 build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..5a403b1
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,57 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= adp-ag101.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+ifdef CONFIG_SYS_LDSCRIPT
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else
+LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..b31b785
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->bd->bi_dram[0].start = sdram_base;
+	gd->bd->bi_dram[0].size  = actual_size;
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else
+		return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 2b0900a..1fd84ef 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -261,6 +261,7 @@ vct_platinumavc              mips        mips32      vct                 microna
 vct_platinumavc_small        mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
+adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..9e1d50e
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,378 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Timer
+ */
+
+/*
+ * ag101:	CONFIG_SYS_HZ:	APB_CLK (ag101 original timer clock frequency)
+ *
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+
+/*
+ * APB_CLK, AHB_CLK, SYS_CLK are from an old configuration
+ * in the earlist nds32 bootloader.
+ *
+ * CONFIG_SYS_HZ = APB_CLK = SYS_CLK = CONFIG_SYS_CLK_FREQ /2
+ *
+ * Since the power management (PWM) Timer 4 uses a counter of
+ * 15625 for 10 ms, so we need it to wrap 100 times
+ * (total 1562500) to get 1 sec.
+ *
+ * #define CONFIG_HZ		1562500
+ * 1562500*25=3906250
+ */
+#define SYS_CLK			CONFIG_SYS_CLK_FREQ
+#define AHB_CLK			SYS_CLK
+#define APB_CLK			(SYS_CLK / 2)
+
+#define CONFIG_SYS_HZ		1000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+#define CONFIG_SYS_TEXT_BASE	0x03200000
+
+/*
+ * System Clock
+ * Suggested frequency lists:
+ *	16000000 -> 16.000000 MHz
+ *	18432000 -> 18.432000 MHz
+ *	22118400 -> 22.118400 MHz
+ *	83000000 -> 83.000000 MHz
+ *	33000000 -> 33.000000 MHz
+ *	36864000 -> 36.864000 MHz
+ *	48000000 -> 48.000000 MHz CONFIG_ADP_AG101
+ *	39062500 -> 39.062500 MHz CONFIG_ADP_AG101P
+ */
+#ifdef CONFIG_ADP_AG101
+#define  CONFIG_SYS_CLK_FREQ	48000000
+#endif
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#ifdef CONFIG_ADP_AG101
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+#endif
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE /* 0x99600000 */
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+
+#ifdef CONFIG_ADP_AG101
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+#endif
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+						 FTAHBC020S_SLAVE_BSR_SIZE(FTAHBC020S_SLAVE_BSR_SIZE_2G))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZEF(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x0CF00000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x00200000
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+
+#ifdef CONFIG_ADP_AG101
+/*
+ * There are 2 bank connected to FTSMC020 on ADP_AG101
+ * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+ *
+ * Note:
+ *  FLASH on ADP_AG101P (FPGA version of ADP_AG101) is connected to BANK1
+ *  Just disalbe the other BANK to avoid detection error.
+ */
+
+/* This FTSMC020_BANK1_SDRAM was used in lowlevel_init.S */
+#define FTSMC020_BANK1_SDRAM_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_SDRAM_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+
+#define FTSMC020_BANK1_CONFIG		FTSMC020_BANK1_SDRAM_CONFIG
+#define FTSMC020_BANK1_TIMING		FTSMC020_BANK1_SDRAM_TIMING
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0 (FLASH)
+ * PHYS_FLASH_1 should be 0x400000 (13 bits to store addr, 0x1000000)
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+#endif /* CONFIG_ADP_AG101 */
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#define PHYS_FLASH_1			0x80400000
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x1C0000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+/* relocation parameters */
+#define CONFIG_SYS_RELO_ADDR		0x10000000
+
+#endif	/* __CONFIG_H */
-- 
1.7.3.5

[U-Boot] [PATCH v9 10/10] adp-ag101: add board adp-ag101 support

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1304342712-17120-10-git-send-email-macpaul@andestech.com> you wrote:
> Add evaluation board "adp-ag101" aconfiguration file adp-ag101.h.
> Add adp-ag101.c board config and related settings.
> Add board adp-ag101 into boards.cfg
...
> +	if (expected_size != actual_size)
> +		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
> +				actual_size >> 20, expected_size >> 20);

Please use braces around multi-line statements.

> +	if (banknum == 0) {	/* non-CFI boot flash */
> +		info->portwidth = FLASH_CFI_8BIT;
> +		info->chipwidth = FLASH_CFI_BY8;
> +		info->interface = FLASH_CFI_X8;
> +		return 1;
> +	} else
> +		return 0;

Use braces in both branches.

...
> +#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE /* 0x99600000 */

Line too long. Please fix globally.

...
> +#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
> +						 FTAHBC020S_SLAVE_BSR_SIZE(FTAHBC020S_SLAVE_BSR_SIZE_2G))

Ditto.

> +/* memtest works on 63 MB in DRAM */
> +#define CONFIG_SYS_MEMTEST_START	0x00000000
> +#define CONFIG_SYS_MEMTEST_END		0x00200000

Comments and code are not in sync.

> +/* relocation parameters */
> +#define CONFIG_SYS_RELO_ADDR		0x10000000

This should go, too.  See previous message.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"There are some good people in it, but the orchestra as  a  whole  is
equivalent to a gang bent on destruction."      - John Cage, composer

[U-Boot] [PATCH v10 1/8] nds32: add header files support for nds32

[Macpaul Lin]

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
   - Code cleanup and style formatting.
Changes for v5-v6:
   - This patch also updated the following changes against the
     change after master tree (v2010.12-rc1).
   - fix upper case definitions in cache.h
   - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
   - Add readsb, writesb functions into io.h.
Changes for v7:
   - clean up
   - volatile:
    - types.h
     - remove typedef volatile unsigned char  vuchar;
     - remove typedef volatile unsigned long  vulong;
     - remove typedef volatile unsigned short vushort;
    - u-boot.h: remove bd_info_ext bi_ext
    - bitops.h: add accessor function to bit operation with volatile var.
    - system.h: add system.h for local_irq operation with flag.
Changes for v8:
   - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
   - ptregs.h: removed
Changes for v9:
   - No change.
Changes for v10:
   - macro.h: add writel and setbf macros
   - u-boot-nds32.h:
    - Remove obsolete andesboot_* symbols for relocation.
    - Add _bss_*_offset symbols for relocation.
   - config.h: add manual relocation support as default.

 arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
 arch/nds32/include/asm/byteorder.h    |   36 +++
 arch/nds32/include/asm/cache.h        |   54 +++++
 arch/nds32/include/asm/config.h       |   28 +++
 arch/nds32/include/asm/global_data.h  |   89 +++++++
 arch/nds32/include/asm/io.h           |  410 +++++++++++++++++++++++++++++++++
 arch/nds32/include/asm/mach-types.h   |   29 +++
 arch/nds32/include/asm/macro.h        |   96 ++++++++
 arch/nds32/include/asm/memory.h       |   19 ++
 arch/nds32/include/asm/posix_types.h  |   84 +++++++
 arch/nds32/include/asm/processor.h    |   25 ++
 arch/nds32/include/asm/ptrace.h       |   88 +++++++
 arch/nds32/include/asm/string.h       |   57 +++++
 arch/nds32/include/asm/system.h       |   88 +++++++
 arch/nds32/include/asm/types.h        |   63 +++++
 arch/nds32/include/asm/u-boot-nds32.h |   53 +++++
 arch/nds32/include/asm/u-boot.h       |   63 +++++
 arch/nds32/include/asm/unaligned.h    |   31 +++
 18 files changed, 1499 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/bitops.h
 create mode 100644 arch/nds32/include/asm/byteorder.h
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/config.h
 create mode 100644 arch/nds32/include/asm/global_data.h
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/include/asm/mach-types.h
 create mode 100644 arch/nds32/include/asm/macro.h
 create mode 100644 arch/nds32/include/asm/memory.h
 create mode 100644 arch/nds32/include/asm/posix_types.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/system.h
 create mode 100644 arch/nds32/include/asm/types.h
 create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
 create mode 100644 arch/nds32/include/asm/u-boot.h
 create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..c56f04b
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void *addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+extern void clear_bit(int nr, volatile void *addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, volatile void *addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, volatile void *addr);
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ	6	/* I-cache line size */
+#define ICM_CFG_MSK_ISZ	(0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
+#define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..6f654d9
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_NEEDS_MANUAL_RELOC
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..665266b
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+
+	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t	ram_size;	/* RAM size */
+	unsigned long	mon_len;	/* monitor len */
+	unsigned long	irq_sp;		/* irq stack pointer */
+	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	unsigned long	tlb_addr;
+#endif
+
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT		0x00004	/* Silent mode			*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	*/
+#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r10")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..be097ec
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,410 @@
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <asm/memory.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+#define writeb(v, a)			__arch_putb(v, a)
+#define writew(v, a)			__arch_putw(v, a)
+#define writel(v, a)			__arch_putl(v, a)
+
+#define readb(a)			__arch_getb(a)
+#define readw(a)			__arch_getw(a)
+#define readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache)				\
+({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
+	_ret;								\
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"), 0)
+#define readw(addr)			(__readwrite_bug("readw"), 0)
+#define readl(addr)			(__readwrite_bug("readl"), 0)
+#define writeb(v, addr)			__readwrite_bug("writeb")
+#define writew(v, addr)			__readwrite_bug("writew")
+#define writel(v, addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101             0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101()	(machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101()	(0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/macro.h b/arch/nds32/include/asm/macro.h
new file mode 100644
index 0000000..acda060
--- /dev/null
+++ b/arch/nds32/include/asm/macro.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-nds32/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NDS_MACRO_H
+#define __ASM_NDS_MACRO_H
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to an "immediate address (address used by periphal)" only.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any NDS32 architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	li	$r4, addr
+	li	$r5, data
+	swi	$r5, [$r4]
+.endm
+
+.macro	write16, addr, data
+	li	$r4, addr
+	li	$r5, data
+	shi	$r5, [$r4]
+.endm
+
+.macro	write8, addr, data
+	li	$r4, addr
+	li	$r5, data
+	sbi	$r5, [$r4]
+.endm
+
+/*
+ * This macro read a value from a register, then do OR operation
+ * (set bit fields) to the value, and then store it back to the register.
+ * Note: Instruction 'ori' supports immediate value up to 15 bits.
+ */
+.macro	setbf32, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	li	$r6, data
+	or	$r5, $r5, $r6
+	swi	$r5, [$r4]
+.endm
+
+.macro	setbf15, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	ori	$r5, $r5, data
+	swi	$r5, [$r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any NDS32 architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	li	$r4, time
+1:
+	nop
+	addi	$r4, $r4, -1
+	bnez    $r4, 1b
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H */
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index 0000000..5bcc4e1
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/memory.h
+ *
+ * Copyright (C) 2000-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Note: this file should not be included by non-asm/.h files
+ */
+#ifndef __ASM_NDS_MEMORY_H
+#define __ASM_NDS_MEMORY_H
+
+#endif	/* __ASM_NDS_MEMORY_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..4336083
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+	NDS32_REG ir0;
+	NDS32_REG ipsw;
+	NDS32_REG ipc;
+	NDS32_REG sp;
+	NDS32_REG orig_r0;
+	NDS32_REG pipsw;
+	NDS32_REG pipc;
+	NDS32_REG pp0;
+	NDS32_REG pp1;
+	NDS32_REG d0hi;
+	NDS32_REG d0lo;
+	NDS32_REG d1hi;
+	NDS32_REG d1lo;
+	NDS32_REG r[26];	/* r0 - r25 */
+	NDS32_REG fp;		/* r28 */
+	NDS32_REG gp;		/* r29 */
+	NDS32_REG lp;		/* r30 */
+	NDS32_REG fucop_ctl;
+	NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+	(((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..30a8fc1
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong _bss_start_ofs;	/* BSS start relative to _start */
+extern ulong _bss_end_ofs;	/* BSS end relative to _start */
+extern ulong _end_ofs;		/* end of image relative to _start */
+extern ulong _TEXT_BASE;	/* code start */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+/* cpu/.../timer.c */
+int	timer_init(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..fafe4e4
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <environment.h>
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+
+	env_t		*bi_env;
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..ffa7e30
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Andes Technology Corporation
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _ASM_NDS_UNALIGNED_H
+#define _ASM_NDS_UNALIGNED_H
+
+#include <compiler.h>
+/*
+ * Select endianness
+ */
+#ifndef __NDSEB__
+#define get_unaligned	__get_unaligned_le
+#define put_unaligned	__put_unaligned_le
+#else
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+#endif /* __NDSEB__ */
+
+#include <asm/byteorder.h>
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+#endif /* _ASM_NDS_UNALIGNED_H */
-- 
1.7.3.5

[U-Boot] [PATCH v10 1/8] nds32: add header files support for nds32

[Mike Frysinger]

On Wednesday, August 31, 2011 06:25:53 Macpaul Lin wrote:
> --- /dev/null
> +++ b/arch/nds32/include/asm/unaligned.h
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright (C) 2016 Andes Technology Corporation
> + * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
> + *
> + * This file is subject to the terms and conditions of the GNU General
> Public + * License.  See the file "COPYING" in the main directory of this
> archive + * for more details.
> + */
> +
> +#ifndef _ASM_NDS_UNALIGNED_H
> +#define _ASM_NDS_UNALIGNED_H
> +
> +#include <compiler.h>
> +/*
> + * Select endianness
> + */
> +#ifndef __NDSEB__
> +#define get_unaligned	__get_unaligned_le
> +#define put_unaligned	__put_unaligned_le
> +#else
> +#define get_unaligned	__get_unaligned_be
> +#define put_unaligned	__put_unaligned_be
> +#endif /* __NDSEB__ */
> +
> +#include <asm/byteorder.h>
> +
> +#include <linux/unaligned/le_byteshift.h>
> +#include <linux/unaligned/be_byteshift.h>
> +#include <linux/unaligned/generic.h>
> +
> +#endif /* _ASM_NDS_UNALIGNED_H */

cant you just include asm-generic/unaligned.h ?
-mike
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[U-Boot] [PATCH v10 1/8] nds32: add header files support for nds32

[Mike Frysinger]

(just picking this e-mail because there is no patch summary to reply to)

your nds32 port doesnt update the top level README or doc/README.standalone or 
add a doc/README.nds32.  please add some documentation for your port ;).
-mike
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[U-Boot] [PATCH v10 2/8] nds32: add NDS32 support into common header file

[Macpaul Lin]

Add NDS32 support into common header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v7:
  - No change
Changes for v8:
  - Fix the patch according to dependency of x86's Fix
Changes for v9-v10:
  - No change

 include/common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index 12a1074..782933d 100644
--- a/include/common.h
+++ b/include/common.h
@@ -281,6 +281,10 @@ int	setenv	     (const char *, const char *);
 #ifdef CONFIG_X86		/* x86 version to be fixed! */
 # include <asm/u-boot-x86.h>
 #endif /* CONFIG_X86 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h>	/* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
-- 
1.7.3.5

[U-Boot] [PATCH v10 3/8] nds32/core N1213: NDS32 N12 core family N1213

[Macpaul Lin]

Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

NDS32 Core N1213 has the following hardware features.

 Core:
  - 16-/32-bit mixable instruction format
  - 32 general-purpose 32-bit registers
  - 8-stage pipeline
  - Dynamic branch prediction
  - 32/64/128/256 BTB
  - Return address stack (RAS)
  - Vector interrupts for internal/external
  - 3 HW-level nested interruptions
  - User and super-user mode support
  - Memory-mapped I/O
  - Address space up to 4GB

 Memory Management Unit:
  - TLB
  - Optional hardware page table walker
  - Two groups of page size support

 Memory Subsystem:
  - I & D cache
  - I & D local memory (LM)

 Bus Interface:
  - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes v1 to v6:
  - Style clean up and reorganize code
Changes v7-v9:
  - No Change.
Changes v10:
  - start.S of N1213 CPU has been rewrote for relocation support.
  - u-boot.lds:
   - Add got and *(.got.plt) section for support GCC 4 toolchain
   - Modified for relocation implementation.

 arch/nds32/cpu/n1213/Makefile   |   50 ++++
 arch/nds32/cpu/n1213/start.S    |  523 +++++++++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/u-boot.lds |   72 ++++++
 3 files changed, 645 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/Makefile
 create mode 100644 arch/nds32/cpu/n1213/start.S
 create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..111d14f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..602067e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,523 @@
+/*
+ *	Andesboot - Startup Code for Whitiger core
+ *
+ *	Copyright (C) 2006	Andes Technology Corporation
+ *	Copyright (C) 2006	Shawn Lin <nobuhiro@andestech.com>
+ *	Copyright (C) 2011	Macpaul <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <asm/macro.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC		2UL
+#define DIS_DCAC		~ENA_DCAC
+#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
+#define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
+#define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY	(0x07<<3)	! D cache ways
+#define DCAC_MEM_KBF_DSZ	(0x07<<6)	! D cache line size
+
+#define PSW			$ir0
+#define EIT_INTR_PSW		$ir1		! interruption $PSW
+#define EIT_PREV_IPSW		$ir2		! previous $IPSW
+#define EIT_IVB			$ir3		! intr vector base address
+#define EIT_EVA			$ir4		! MMU related Exception Virtual Address register
+#define EIT_PREV_EVA		$ir5		! previous $eva
+#define EIT_ITYPE		$ir6		! interruption type
+#define EIT_PREV_ITYPE		$ir7		! prev intr type
+#define EIT_MACH_ERR		$ir8		! machine error log
+#define EIT_INTR_PC		$ir9		! Interruption PC
+#define EIT_PREV_IPC		$ir10		! previous $IPC
+#define EIT_OVL_INTR_PC		$ir11		! overflow interruption PC
+#define EIT_PREV_P0		$ir12		! prev $P0
+#define EIT_PREV_P1		$ir13		! prev $p1
+#define CR_ICAC_MEM		$cr1		! I-cache/memory config reg
+#define CR_DCAC_MEM		$cr2		! D-cache/memory config reg
+#define MR_CAC_CTL		$mr8
+
+.globl _start
+
+_start:	b	reset
+	b	tlb_fill
+	b	tlb_not_present
+	b	tlb_misc
+	b	tlb_vlpt_miss
+	b	cache_parity_error
+	b	debug
+	b	general_exception
+	b	internal_interrupt		! H0I
+	b	internal_interrupt		! H1I
+	b	internal_interrupt		! H2I
+	b	internal_interrupt		! H3I
+	b	internal_interrupt		! H4I
+	b	internal_interrupt		! H5I
+
+	.balign 16
+
+/*
+ * Andesboot Startup Code (reset vector)
+ *
+ *	1.	bootstrap
+ *		1.1 reset - start of Andesboot
+ *		1.2 to superuser mode - as is when reset
+ *		1.4 Do lowlevel_init
+ *			- (this will jump out to lowlevel_init.S in SoC)
+ *			- (lowlevel_init)
+ *		1.3 Turn off watchdog timer
+ *			- (this will jump out to watchdog.S in SoC)
+ *			- (turnoff_watchdog)
+ *	2.	Do critical init when reboot (not from mem)
+ *	3.	Relocate andesboot to ram
+ *	4.	Setup stack
+ *	5.	Jump to second stage (start_andesboot)
+ */
+
+/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
+	.word _end - _start
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word 0x0badc0de
+
+/*
+ * The bootstrap code of nds32 core
+ */
+
+reset:
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	jal	load_lowlevel_init
+	jral	$p0
+#endif
+
+/*
+ * Set the N1213 (Whitiger) core to superuser mode
+ * According to spec, it is already when reset
+ */
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+	jal	load_turnoff_watchdog
+	jral	$p0
+#endif
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+	bal	cpu_init_crit		! Do CPU critical regs init
+#endif
+
+/*
+ * Set stackpointer in internal RAM to call board_init_f
+ * $sp must be 8-byte alignment for ABI compliance.
+ */
+call_board_init_f:
+	li	$sp, CONFIG_SYS_INIT_SP_ADDR
+	li	$r0, 0x00000000
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__
+/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
+	la	$r15, board_init_f	! store function address into $r15
+#endif
+#endif
+	j	board_init_f		! jump to board_init_f() in lib/board.c
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl	relocate_code
+relocate_code:
+	move	$r4, $r0		/* save addr_sp */
+	move	$r5, $r1		/* save addr of gd */
+	move	$r6, $r2		/* save addr of destination */
+
+/* Set up the stack */
+stack_setup:
+	move	$sp, $r4
+
+	la	$r0, _start
+
+	beq	$r0, $r6, clear_bss	/* skip relocation */
+
+	move	$r1, $r6		/* r1 <- scratch for copy_loop */
+	l.w	$r3, _bss_start_ofs
+	add	$r2, $r0, $r3		/* r2 <- source end address */
+
+copy_loop:
+	lwi.p	$r7, [$r0], #4
+	swi.p	$r7, [$r1], #4
+	blt	$r0, $r2, copy_loop
+
+/*
+ * fix relocations related issues
+ */
+fix_relocations:
+	l.w	$r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	$r9, $r6, $r0		/* r9 <- relocation offset */
+
+fix_got:
+/*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+	l.w	$r2, _rel_got_start_ofs	/* r2 <- rel got start ofs */
+	add	$r2, $r2, $r0		/* r2 <- rel got start in FLASH */
+	add	$r2, $r2, $r9		/* r2 <- rel got start in RAM */
+	l.w	$r3, _rel_got_end_ofs	/* r3 <- rel got end ofs */
+	add	$r3, $r3, $r0		/* r3 <- rel got end in FLASH */
+	add	$r3, $r3, $r9		/* r3 <- rel got end in RAM */
+	addi	$r2, $r2, #8		/* skipping first two entries */
+fix_got_loop:
+	lwi	$r0, [$r2]		/* r0 <- location in FLASH to fix up */
+	add	$r0, $r0, $r9		/* r0 <- location fix up to RAM */
+	swi.p	$r0, [$r2], #4		/* r0 <- store fix into .got in RAM */
+	blt	$r2, $r3, fix_got_loop
+
+clear_bss:
+	l.w	$r0, _bss_start_ofs
+	l.w	$r1, _bss_end_ofs
+	move	$r4, $r6		/* reloc addr */
+	add	$r0, $r0, $r4
+	add	$r1, $r1, $r4
+	li	$r2, 0x00000000		/* clear */
+
+clbss_l:
+	sw	$r2, [$r0]		/* clear loop... */
+	addi	$r0, $r0, #4
+	bne	$r0, $r1, clbss_l
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+	l.w	$r0, _board_init_r_ofs
+	la	$r1, _start
+	add	$lp, $r0, $r1		/* offset of board_init_f() */
+	add	$lp, $lp, $r9		/* real address of board_init_f() */
+	/* setup parameters for board_init_r */
+	move	$r0, $r5		/* gd_t */
+	move	$r1, $r6		/* dest_addr */
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__		/* NDS32 V0 ISA	*/
+	move	$r15, $lp		/* store function address into $r15 */
+#endif
+#endif
+
+	/* jump to it ... */
+	jr	$lp			/* jump to board_init_r() */
+
+_board_init_r_ofs:
+	.word board_init_r - _start
+_rel_got_start_ofs:
+	.word __got_start - _start
+_rel_got_end_ofs:
+	.word __got_end - _start
+
+/*
+ * Initialize CPU critical registers
+ *
+ *	1.	Setup control registers
+ *		1.1 Mask all IRQs
+ *		1.2 Flush cache and TLB
+ *		1.3 Disable MMU and cache
+ *	2.	Setup memory timing
+ */
+
+cpu_init_crit:
+
+	move	$r0, $lp		/* push	ra */
+
+	/* Disable Interrupts by clear GIE in $PSW reg */
+	setgie.d
+
+	/* Flush caches and TLB */
+	/* Invalidate caches */
+	bal	invalidate_icac
+	bal	invalidate_dcac
+
+	/* Flush TLB */
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+
+1:
+	! Disable MMU, Dcache
+	! Whitiger is MMU disabled when reset
+	! Disable the D$
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Set DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! write back the $CACHE_CTL reg
+	isb
+
+	move	$lp, $r0
+2:
+	ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+	la  $r6, lowlevel_init
+	la  $r7, load_lli + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+	la  $r6, turnoff_watchdog
+	la  $r7, turnoff_wtdog + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+/*
+ * Invalidate I$
+ */
+invalidate_icac:
+	mfsr	$t0, CR_ICAC_MEM		! read $cr1(I CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, ICAC_MEM_KBF_ISZ 	! Get the ISZ field
+	beqz	$p0, end_flush_icache		! if $p0=0, then no I CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of I$ block
+	addi	$t1, $p0, 2			! $t1= bit width of I cache line size(ISZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, ICAC_MEM_KBF_ISET	! get the ISET field
+	addi	$t2, $p1, 6			! $t2= bit width of ISET
+	andi	$p1, $t0, ICAC_MEM_KBF_IWAY	! get bitfield of Iway
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is I way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+ICAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1I_IX_INVAL
+	bnez	$p1, ICAC_LOOP
+end_flush_icache:
+	ret
+
+/*
+ * Invalidate D$
+ */
+invalidate_dcac:
+	mfsr	$t0, CR_DCAC_MEM		! read $cr2(D CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, DCAC_MEM_KBF_DSZ	! Get the DSZ field
+	beqz	$p0, end_flush_dcache		! if $p0=0, then no D CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of D$ block
+	addi	$t1, $p0, 2			! $t1= bit width of D cache line size(DSZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, DCAC_MEM_KBF_DSET	! get the DSET field
+	addi	$t2, $p1, 6			! $t2= bit width of DSET
+	andi	$p1, $t0, DCAC_MEM_KBF_DWAY	! get bitfield of D way
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is D way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+DCAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1D_IX_INVAL
+	bnez	$p1, DCAC_LOOP
+end_flush_dcache:
+	ret
+
+/*
+ * Interrupt handling
+ */
+
+/*
+ * exception handlers
+ */
+	.align	5
+
+.macro	SAVE_ALL
+	! FIXME: Other way to get PC?
+	! FIXME: Update according to the newest spec!!
+1:
+	la	 $r28, 1
+	push $r28
+	mfsr $r28, PSW			! $PSW
+	push $r28
+	mfsr $r28, EIT_EVA		! $ir1 $EVA
+	push $r28
+	mfsr $r28, EIT_ITYPE		! $ir2 $ITYPE
+	push $r28
+	mfsr $r28, EIT_MACH_ERR		! $ir3 Mach Error
+	push $r28
+	mfsr $r28, EIT_INTR_PSW		! $ir5 $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_IPSW	! $ir6 prev $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_EVA		! $ir7 prev $EVA
+	push $r28
+	mfsr $r28, EIT_PREV_ITYPE	! $ir8 prev $ITYPE
+	push $r28
+	mfsr $r28, EIT_INTR_PC		! $ir9 Interruption PC
+	push $r28
+	mfsr $r28, EIT_PREV_IPC		! $ir10 prev INTR_PC
+	push $r28
+	mfsr $r28, EIT_OVL_INTR_PC	! $ir11 Overflowed INTR_PC
+	push $r28
+	mfusr $r28, $d1.lo
+	push $r28
+	mfusr $r28, $d1.hi
+	push $r28
+	mfusr $r28, $d0.lo
+	push $r28
+	mfusr $r28, $d0.hi
+	push $r28
+	pushm $r0, $r30		! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
+	addi	$sp, $sp, -4	! make room for implicit pt_regs parameters
+.endm
+
+	.align	5
+tlb_fill:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 1				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_not_present:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 2				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_misc:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 3				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_vlpt_miss:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 4				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+cache_parity_error:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 5				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+debug:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 6				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+general_exception:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 7				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+internal_interrupt:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 8				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+
+/*
+ * void reset_cpu(ulong addr);
+ * $r0: input address to jump to
+ */
+.globl reset_cpu
+reset_cpu:
+/* No need to disable MMU because we never enable it */
+
+	bal	invalidate_icac
+	bal	invalidate_dcac
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+1:
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Clear the DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! Write back the $CACHE_CTL reg
+	br	$r0				! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..194f45a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		arch/nds32/cpu/n1213/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		 *(.got.plt) *(.got)
+		__got_end = .;
+	}
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+}
-- 
1.7.3.5

[U-Boot] [PATCH v10 3/8] nds32/core N1213: NDS32 N12 core family N1213

[Mike Frysinger]

On Wednesday, August 31, 2011 06:25:55 Macpaul Lin wrote:
> --- /dev/null
> +++ b/arch/nds32/cpu/n1213/Makefile
>
> +LIB	= $(obj)lib$(CPU).o
> +
> +$(LIB):	$(OBJS)
> +	$(AR) $(ARFLAGS) $@ $(OBJS)

all your makefiles that call $(AR) are broken.  they need to use $(call 
cmd_link_o_target,...).  i see this in multiple nds32 patches here.

see arch/blackfin/lib/Makefile as a simple example
-mike
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[U-Boot] [PATCH v10 4/8] nds32/ag101: cpu and init funcs of SoC ag101

[Macpaul Lin]

SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.

cpu.c
 According to the bootstrap procedure in n1213 Core,
 to turn off watchdog timer is suggested after the
 cpu is in superuser mdoe.

 1. bootstrap
 1.1 reset - start of Andesboot
 1.2 to superuser mode - as is when reset
 1.3 Turn off watchdog timer

 If you take look into the start.S in n1213, you will find that
 system will turn off watchdog after start.S has been retunred
 from lowlevel_init.

 Since the watchdog device is depends on the SoC is choosed.
 It should be belonged to the SoC (ag101) folder.

watchdog.S:
 If you've ran another bootloader before u-boot was started
 the watchdog might have been enabled already.

lowlevel_init.S is a peripheral initial procedure of ag101.
It configures onboard dram, clock, and power settings.
It also prepars the dram environment before moving u-boot
from rom and flash into dram.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code clean up.
Changes for v5-v6:
  - Split watchdog.S from lowlevel_init.S.
  - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
   - reset_cpu was remove inside do_reset().
  - lowlevel_init.S
   - Change hard code value into MARCO definitions.
   - ftsmc010
     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
   - ftsdmc021
     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
     - Fix the default configuration value of FTSDMC and FTSMC controller.
   - Remove some ftpmu010 and flash probe code to C functions.
Changes for v7:
  - clean up.
Changes for v8-v9:
  - No change.
Changes for v10:
  - asm-offset.c: file added for ag101 use only.
  - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
  - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
  - cpu.c: remove unused cpu_init().
  - lowlevel_init.S
   - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
   - Replace routings by macros to made code much easier to understand.
   - Add debug LED support.
   - Add CONFIG_MEM_REMAP for those boards must do memort remapping.

 Makefile                                   |    3 +-
 arch/nds32/cpu/n1213/ag101/Makefile        |   70 ++++++++
 arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
 arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/timer.c         |  204 ++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
 arch/nds32/include/asm/arch-ag101/ag101.h  |   68 ++++++++
 8 files changed, 873 insertions(+), 1 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
 create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
 create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/Makefile b/Makefile
index 03d80b7..89aebff 100644
--- a/Makefile
+++ b/Makefile
@@ -1019,7 +1019,8 @@ clean:
 	       $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds  \
 	       $(obj)u-boot.lds						  \
 	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]	  \
-	       $(obj)arch/blackfin/cpu/init.{lds,elf}
+	       $(obj)arch/blackfin/cpu/init.{lds,elf}			  \
+	       $(obj)arch/nds32/cpu/$(CPU)/$(SOC)/gen-asm-offsets.[chs]
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)lib/asm-offsets.s
 	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..40a0fa7
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,70 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+$(OBJS): $(obj)gen-asm-offsets.h
+$(obj)gen-asm-offsets.h:	$(TOPDIR)/include/autoconf.mk.dep \
+	$(obj)gen-asm-offsets.s
+	@echo Generating $@ ; \
+	$(SRCTREE)/tools/scripts/make-asm-offsets $(obj)gen-asm-offsets.s $@
+
+$(obj)gen-asm-offsets.s:	$(TOPDIR)/include/autoconf.mk.dep \
+	$(src)asm-offsets.c
+	@mkdir -p $(obj)b
+	$(CC) -DDO_DEPS_ONLY \
+		$(CFLAGS) -o $@ $(src)asm-offsets.c -c -S
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
new file mode 100644
index 0000000..92ada8a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
@@ -0,0 +1,43 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..0ab666e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+	unsigned long i;
+#endif
+
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+	while (1)
+		;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr , addr + size);
+	icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..94308a8
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+#include "gen-asm-offsets.h"
+
+#include <asm/macro.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+
+#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro	wait_sdram
+	li	$r0, CONFIG_FTSDMC021_BASE
+1:
+	lwi	$r1, [$r0+FTSDMC021_CR2]
+	bnez	$r1, 1b
+.endm
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+
+	led	0x0
+	jal	mem_init
+
+	led	0x10
+	jal	remap
+
+	led	0x20
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	led	0x01
+	write32	SMC_BANK0_CR_A, SMC_BANK0_CR_D			! 0x10000052
+	write32	SMC_BANK0_TPR_A, SMC_BANK0_TPR_D		! 0x00151151
+
+	/*
+	 * config AHB Controller
+	 */
+	led	0x02
+	write32	AHBC_BSR6_A, AHBC_BSR6_D
+
+	/*
+	 * config PMU controller
+	 */
+	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
+	led	0x03
+	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
+
+	/*
+	 * config SDRAM controller
+	 */
+	led	0x04
+	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
+	led	0x05
+	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
+	led	0x06
+	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
+
+	led	0x07
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
+	wait_sdram
+
+	led	0x08
+	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
+	wait_sdram
+
+	led	0x09
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
+	wait_sdram
+
+	led	0x0a
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+	/*
+	 * Remapping
+	 */
+	led	0x1a
+	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
+
+	/* clear empty BSR registers */
+	led	0x1b
+	li	$r4, CONFIG_FTSDMC021_BASE
+	li	$r5, 0x0
+	swi	$r5, [$r4 + FTSDMC021_BANK1_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
+
+#ifdef CONFIG_MEM_REMAP
+	/*
+	 * Copy ROM code to SDRAM base for memory remap layout.
+	 * This is not the real relocation, the real relocation is the function
+	 * relocate_code() is start.S which supports the systems is memory
+	 * remapped or not.
+	 */
+	/*
+	 * Doing memory remap is essential for preparing some non-OS or RTOS
+	 * applications.
+	 *
+	 * This is also a must on ADP-AG101 board.
+	 * The reason is because the ROM/FLASH circuit on PCB board.
+	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	 * ROM/FLASH is used to boot.
+	 *
+	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	 * and the FLASH is connected to BANK1.
+	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	 * and the FLASH is connected to BANK0.
+	 * It will occur problem when doing flash probing if the flash is at
+	 * BANK0 (0x00000000) while memory remapping was skipped.
+	 *
+	 * Other board like ADP-AG101P may not enable this since there is only
+	 * a FLASH connected to bank0.
+	 */
+	led	0x11
+	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
+	li	$r5, 0x0
+	la	$r1, relo_base				/* get $pc or $lp */
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(_end)
+	ori	$r6, $r6, lo12(_end)
+	add	$r6, $r6, $r2
+1:
+	lwi.p	$r7, [$r5], #4
+	swi.p	$r7, [$r4], #4
+	blt	$r5, $r6, 1b
+
+	/* set remap bit */
+	/*
+	 * MEM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
+	 */
+	led	0x1c
+	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..b689eab
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl	turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+#endif
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE		0x90100000	/* AHB Controller */
+#define CONFIG_FTSMC020_BASE		0x90200000	/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE		0x90300000	/* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000	/* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000	/* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE		0x90600000	/* LCD Controller */
+#define CONFIG_RESERVED_01_BASE		0x90700000	/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000	/* Reserved */
+#define CONFIG_FTMAC100_BASE		0x90900000	/* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000	/* External USB host */
+#define CONFIG_USB_DEV_BASE		0x90B00000	/* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000	/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE		0x90D00000	/* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000	/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000	/* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000	/* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC	/* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE		0x98100000	/* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE	0x98300000	/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE		0x98400000	/* Counter/Timers */
+#define CONFIG_FTWDT010_BASE		0x98500000	/* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE		0x98600000	/* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE		0x98700000	/* GPIO */
+#define CONFIG_FTINTC010_BASE		0x98800000	/* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE		0x98A00000	/* I2C */
+#define CONFIG_RESERVED_04_BASE		0x98C00000	/* Reserved */
+#define CONFIG_FTCFC010_BASE		0x98D00000	/* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000	/* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE		0x99400000	/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE	0x99600000	/* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE	0x98200000	/* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000	/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE		0x98900000	/* IrDA */
+#define CONFIG_PMW_BASE			0x99100000	/* PWM - Pulse Width Modulator Controller */
+
+#endif	/* __AG101_H */
-- 
1.7.3.5

[U-Boot] [PATCH v10 5/8] nds32/lib: add generic funcs in NDS32 lib

[Macpaul Lin]

Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up and formatting style.
Changes for v5-v6:
  - board.c
   - Do some clean up and add code
   - Remove display banner which hasn't support.
   - Add ftpmu010 related power management unit code.
   - Remove useless LED related code.
   - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
   - Remove CONFIG_SOFT_I2C which hasn't been support.
   - Remove CONFIG_FSL_ESDHC which hasn't been support.
   - clean up.
Changes for v7:
  - clean up.
  - move single file patch arch/nds32/config.mk to this commit.
  - interrupts.c refine origin interrupt enable and disable.
Changes for v8:
  - interrups.c: fix up for new ptraces.h.
Changes for v9:
  - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
Changes for v10:
  - config.mk:
   - add -fpie flag.
   - replace -ffixed-8 to -ffixed-10.
   - add -mrelax and --gc-sections to LDFLAG
  - board.c:
   - fix lib/board.c for relocation.
   - fix dram init for relocation.

 arch/nds32/config.mk        |   37 ++++
 arch/nds32/lib/Makefile     |   52 +++++
 arch/nds32/lib/board.c      |  453 +++++++++++++++++++++++++++++++++++++++++++
 arch/nds32/lib/bootm.c      |  241 +++++++++++++++++++++++
 arch/nds32/lib/interrupts.c |  131 +++++++++++++
 5 files changed, 914 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/config.mk
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/board.c
 create mode 100644 arch/nds32/lib/bootm.c
 create mode 100644 arch/nds32/lib/interrupts.c

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..78b4a23
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,37 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common -mrelax
+PLATFORM_RELFLAGS	+= -gdwarf-2
+PLATFORM_CPPFLAGS	+= -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-10 -fpie
+
+LDFLAGS_u-boot		= --gc-sections --relax
+
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..eca4324
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+OBJS	:= board.o bootm.o interrupts.o
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..1195e91
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,453 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern ulong __bss_end;
+ulong monitor_flash_len;
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+const char version_string[] =
+	U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	char tmp[64];	/* long enough for environment variables */
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+			? (int) simple_strtoul(tmp, NULL, 10)
+			: CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+void __dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size =  gd->ram_size;
+}
+void dram_init_banksize(void)
+	__attribute__((weak, alias("__dram_init_banksize")));
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	pmu_init,
+#endif
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init,
+#endif
+	display_dram_config,
+	NULL,
+};
+
+void board_init_f(ulong bootflag)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	gd_t *id;
+	ulong addr, addr_sp;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
+
+	/* compiler optimization barrier needed for GCC >= 3.4 */
+	__asm__ __volatile__("" : : : "memory");
+
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	gd->mon_len = _bss_end_ofs;
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	debug("monitor len: %08lX\n", gd->mon_len);
+	/*
+	 * Ram is setup, size stored in gd !!
+	 */
+	debug("ramsize: %08lX\n", gd->ram_size);
+
+	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	/* reserve TLB table */
+	addr -= (4096 * 4);
+
+	/* round down to next 64 kB limit */
+	addr &= ~(0x10000 - 1);
+
+	gd->tlb_addr = addr;
+	debug("TLB table at: %08lx\n", addr);
+#endif
+
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+	gd->fb_base = CONFIG_FB_ADDR;
+#else
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
+	/*
+	 * reserve memory for U-Boot code, data & bss
+	 * round down to next 4 kB limit
+	 */
+	addr -= gd->mon_len;
+	addr &= ~(4096 - 1);
+
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+
+	/*
+	 * reserve memory for malloc() arena
+	 */
+	addr_sp = addr - TOTAL_MALLOC_LEN;
+	debug("Reserving %dk for malloc() at: %08lx\n",
+			TOTAL_MALLOC_LEN >> 10, addr_sp);
+	/*
+	 * (permanently) allocate a Board Info struct
+	 * and a permanent copy of the "global" data
+	 */
+	addr_sp -= sizeof(bd_t);
+	bd = (bd_t *) addr_sp;
+	gd->bd = bd;
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+			sizeof(bd_t), addr_sp);
+
+	addr_sp -= sizeof(gd_t);
+	id = (gd_t *) addr_sp;
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			sizeof(gd_t), addr_sp);
+
+	/* setup stackpointer for exeptions */
+	gd->irq_sp = addr_sp;
+#ifdef CONFIG_USE_IRQ
+	addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
+#endif
+	/* leave 3 words for abort-stack    */
+	addr_sp -= 12;
+
+	/* 8-byte alignment for ABI compliance */
+	addr_sp &= ~0x07;
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
+
+	gd->bd->bi_baudrate = gd->baudrate;
+	/* Ram isn't board specific, so move it to board code ... */
+	dram_init_banksize();
+	display_dram_config();	/* and display it */
+
+	gd->relocaddr = addr;
+	gd->start_addr_sp = addr_sp;
+
+	gd->reloc_off = addr - _TEXT_BASE;
+
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	memcpy(id, (void *)gd, sizeof(gd_t));
+
+	relocate_code(addr_sp, id, addr);
+
+	/* NOTREACHED - relocate_code() does not return */
+}
+
+/*
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	char *s;
+	bd_t *bd;
+	ulong malloc_start;
+
+	extern void malloc_bin_reloc(void);
+
+	gd = id;
+	bd = gd->bd;
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	monitor_flash_len = _end_ofs;
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
+
+	board_init();	/* Setup chipselects */
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	/*
+	 * We have to relocate the command table manually
+	 */
+	fixup_cmdtable(&__u_boot_cmd_start,
+		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
+
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+	mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+	malloc_bin_reloc();
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init();
+#endif
+
+	/* IP Address */
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+#if defined(CONFIG_USE_IRQ)
+	/* set up exceptions */
+	interrupt_init();
+	/* enable exceptions */
+	enable_interrupts();
+#endif
+
+	/* Initialize from environment */
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+	puts("Net:   ");
+#endif
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	show_boot_progress(15);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..c42ad2b
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+extern void reset_cpu(ulong addr);
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"lp : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}
-- 
1.7.3.5

[U-Boot] [PATCH v10 6/8] nds32: standalone support

[Macpaul Lin]

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - code clean up.
Changes for v7-v10:
  - No change.

 examples/standalone/nds32.lds     |   64 +++++++++++++++++++++++++++++++++++++
 examples/standalone/stubs.c       |   17 +++++++++-
 examples/standalone/x86-testapp.c |   12 +++++++
 3 files changed, 92 insertions(+), 1 deletions(-)
 create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..c2ac107
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	_end = .;
+
+	. = 0x02000000;
+	.u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 507d38c..11c7565 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
 "	jmp %%g1\n"					\
 "	nop\n"						\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	lwi	$r16, [$gp + (%0)]\n"	\
+"	lwi	$r16, [$r16 + (%1)]\n"	\
+"	jr	$r16\n"			\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
 #else
+/*"	addi	$sp, $sp, -24\n"	\
+"	br	$r16\n"			\*/
+
 #error stubs definition missing for this architecture
 #endif
 
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile (						\
 "	lw	$25, %1($25)\n"				\
 "	jr	$25\n"					\
 	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x)					\
+asm volatile (						\
+"	.globl mon_" #x "\n"				\
+"mon_" #x ":\n"						\
+"	lwi	$r16, [$gp + (%0)]\n"			\
+"	lwi	$r16, [$r16 + (%1)]\n"			\
+"	jr	$r16\n"					\
+	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
+
 #else
 #error [No stub code for this arch]
 #endif
@@ -72,6 +82,8 @@ int main(void)
 	register volatile xxx_t *pq asm("r8");
 #elif defined(__mips__)
 	register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+	register volatile xxx_t *pq asm("$r16");
 #endif
 	char buf[32];
 
-- 
1.7.3.5

[U-Boot] [PATCH v10 7/8] nds32: common bdinfo, bootm, image support

[Macpaul Lin]

Add support of NDS32 to common commands bdinfo, bootm, and image format.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - Code clean up
Changes for v7-v9:
  - No Change.
Changes for v10:
  - fix up according to the changes in master tree.

 common/cmd_bdinfo.c |   26 ++++++++++++++++++++++++++
 common/cmd_bootm.c  |    2 ++
 common/image.c      |    1 +
 include/image.h     |    5 +++++
 4 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 6051120..52102db 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -413,6 +413,32 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num("arch_number",	bd->bi_arch_number);
+	print_num("env_t",		(ulong)bd->bi_env);
+	print_num("boot_params",	(ulong)bd->bi_boot_params);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 272d879..99ec547 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -187,6 +187,8 @@ void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
   #define IH_INITRD_ARCH IH_ARCH_SH
 #elif defined(__sparc__)
   #define IH_INITRD_ARCH IH_ARCH_SPARC
+#elif defined(__nds32__)
+  #define IH_INITRD_ARCH IH_ARCH_NDS32
 #else
 # error Unknown CPU type
 #endif
diff --git a/common/image.c b/common/image.c
index 5eea2a1..95e16b8 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	-1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index 352e4a0..dcbbc8b 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_NDS32	        19	/* ANDES Technology - NDS32  */
 
 /*
  * Image Types
@@ -506,6 +507,8 @@ static inline int image_check_target_arch (const image_header_t *hdr)
 	if (!image_check_arch (hdr, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!image_check_arch (hdr, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!image_check_arch(hdr, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
@@ -658,6 +661,8 @@ static inline int fit_image_check_target_arch (const void *fdt, int node)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!fit_image_check_arch(fdt, node, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
-- 
1.7.3.5

[U-Boot] [PATCH v10 8/8] adp-ag101: add board adp-ag101 support

[Macpaul Lin]

Add evaluation board "adp-ag101" configuration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up
Changes for v5-v6:
  - Refine the definitions and parameters about CLK,
    AHB controller, SDRAM controller, Static memory controllers.
  - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
  - ftahbc010:
    - Update include path of ftahbc010.
  - ftsdmc021:
    - Update include path of ftsdmc021.
  - ftsmc020:
    - Update include path of ftsmc020.
  - ftwdt010:
    - Fix WDT define and update include path.
    - Fix ftwdt010 for hardware reset.
  - ftpmu010:
    - Remove duplicate PMU definitions.
    - Add related configurations.
  - Fix MAX malloc len and fix saveenv.
  - clean up.
Changes for v7:
  - clean up.
  - Move CONFIG_SYS_TEXT_BASE from board/config.mk.
  - Fix Makefile and remove config.mk
Changes for v8:
  - No change.
Changes for v9:
  - Fix because other boards has been added into boards.cfg and
    broken this patch.
Changes for v10:
  - adp-ag101.h
   - Fix lines over 80 characters.
   - Fix for introducing gen-asm-offset.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix flash init.
   - fix ftsmc010 configuraion for flash probing.
   - Add SP_INIT related configurations for supporting relocation.
   - Fix CONFIG_TEXT_BASE for relocation.
   - Add CONFIG_MEM_REMAP for some hardware boards and non-OS application.
  - adp-ag101.c
   - Clean up for braces according to Wolfgang's suggestion.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix dram init(), made this more simpler.

 MAINTAINERS                           |   11 +
 MAKEALL                               |    6 +
 board/AndesTech/adp-ag101/Makefile    |   57 +++++
 board/AndesTech/adp-ag101/adp-ag101.c |   89 +++++++
 boards.cfg                            |    1 +
 include/configs/adp-ag101.h           |  411 +++++++++++++++++++++++++++++++++
 6 files changed, 575 insertions(+), 0 deletions(-)
 create mode 100644 board/AndesTech/adp-ag101/Makefile
 create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
 create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 7982c36..6b7c664 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1162,5 +1162,16 @@ Chong Huang <chuang@ucrobotics.com>
 	bf525-ucr2	BF525
 
 #########################################################################
+# NDS32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+	ADP-AG101	N1213 (AG101 SoC)
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 3b98f03..232ed3b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -600,6 +600,12 @@ LIST_sh="$(boards_by_arch sh)"
 
 LIST_sparc="$(boards_by_arch sparc)"
 
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
 #-----------------------------------------------------------------------
 
 build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..5a403b1
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,57 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= adp-ag101.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+ifdef CONFIG_SYS_LDSCRIPT
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else
+LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..82ce4c9
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	ftsdc010_mmc_init(0);
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index c253f03..ce01cda 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -308,6 +308,7 @@ vct_platinumavc_small        mips        mips32      vct                 microna
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
 nios2-generic                nios2       nios2       nios2-generic       altera
+adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..0108033
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x80500000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_CMD_FAT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#else
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#endif
+
+#ifdef CONFIG_ADP_AG101
+/*
+ * There are 2 bank connected to FTSMC020 on ADP-AG101.
+ * You can use jumper and switch to force it booted from ROM or FLASH.
+ * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
+ * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
+ */
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0 (FLASH)
+ * PHYS_FLASH_1 should be 0x400000 (13 bits to store addr, 0x1000000)
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
+				 FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M	|	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_RBE	|	\
+				 FTSMC020_TPR_AST(1)	|	\
+				 FTSMC020_TPR_CTW(1)	|	\
+				 FTSMC020_TPR_ATI(1)	|	\
+				 FTSMC020_TPR_AT2(1)	|	\
+				 FTSMC020_TPR_WTC(1)	|	\
+				 FTSMC020_TPR_AHT(1)	|	\
+				 FTSMC020_TPR_TRNA(1))
+
+#endif /* CONFIG_ADP_AG101 */
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif	/* CONFIG_MEM_REMAP */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif	/* __CONFIG_H */
-- 
1.7.3.5

[U-Boot] [PATCH v11 1/9] nds32: add header files support for nds32

[Macpaul Lin]

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
   - Code cleanup and style formatting.
Changes for v5-v6:
   - This patch also updated the following changes against the
     change after master tree (v2010.12-rc1).
   - fix upper case definitions in cache.h
   - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
   - Add readsb, writesb functions into io.h.
Changes for v7:
   - clean up
   - volatile:
    - types.h
     - remove typedef volatile unsigned char  vuchar;
     - remove typedef volatile unsigned long  vulong;
     - remove typedef volatile unsigned short vushort;
    - u-boot.h: remove bd_info_ext bi_ext
    - bitops.h: add accessor function to bit operation with volatile var.
    - system.h: add system.h for local_irq operation with flag.
Changes for v8:
   - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
   - ptregs.h: removed
Changes for v9:
   - No change.
Changes for v10:
   - macro.h: add writel and setbf macros
   - u-boot-nds32.h:
    - Remove obsolete andesboot_* symbols for relocation.
    - Add _bss_*_offset symbols for relocation.
   - config.h: add manual relocation support as default.
Changes for v11:
   - unaligned.h: replace asm/unaligned.h with asm-generic/unaligned.h

 arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
 arch/nds32/include/asm/byteorder.h    |   36 +++
 arch/nds32/include/asm/cache.h        |   54 +++++
 arch/nds32/include/asm/config.h       |   28 +++
 arch/nds32/include/asm/global_data.h  |   89 +++++++
 arch/nds32/include/asm/io.h           |  410 +++++++++++++++++++++++++++++++++
 arch/nds32/include/asm/mach-types.h   |   29 +++
 arch/nds32/include/asm/macro.h        |   96 ++++++++
 arch/nds32/include/asm/memory.h       |   19 ++
 arch/nds32/include/asm/posix_types.h  |   84 +++++++
 arch/nds32/include/asm/processor.h    |   25 ++
 arch/nds32/include/asm/ptrace.h       |   88 +++++++
 arch/nds32/include/asm/string.h       |   57 +++++
 arch/nds32/include/asm/system.h       |   88 +++++++
 arch/nds32/include/asm/types.h        |   63 +++++
 arch/nds32/include/asm/u-boot-nds32.h |   53 +++++
 arch/nds32/include/asm/u-boot.h       |   63 +++++
 arch/nds32/include/asm/unaligned.h    |    1 +
 18 files changed, 1469 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/bitops.h
 create mode 100644 arch/nds32/include/asm/byteorder.h
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/config.h
 create mode 100644 arch/nds32/include/asm/global_data.h
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/include/asm/mach-types.h
 create mode 100644 arch/nds32/include/asm/macro.h
 create mode 100644 arch/nds32/include/asm/memory.h
 create mode 100644 arch/nds32/include/asm/posix_types.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/system.h
 create mode 100644 arch/nds32/include/asm/types.h
 create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
 create mode 100644 arch/nds32/include/asm/u-boot.h
 create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..c56f04b
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void *addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+extern void clear_bit(int nr, volatile void *addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, volatile void *addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, volatile void *addr);
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ	6	/* I-cache line size */
+#define ICM_CFG_MSK_ISZ	(0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
+#define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..6f654d9
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_NEEDS_MANUAL_RELOC
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..665266b
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+
+	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t	ram_size;	/* RAM size */
+	unsigned long	mon_len;	/* monitor len */
+	unsigned long	irq_sp;		/* irq stack pointer */
+	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	unsigned long	tlb_addr;
+#endif
+
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT		0x00004	/* Silent mode			*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	*/
+#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r10")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..be097ec
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,410 @@
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <asm/memory.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+#define writeb(v, a)			__arch_putb(v, a)
+#define writew(v, a)			__arch_putw(v, a)
+#define writel(v, a)			__arch_putl(v, a)
+
+#define readb(a)			__arch_getb(a)
+#define readw(a)			__arch_getw(a)
+#define readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache)				\
+({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
+	_ret;								\
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"), 0)
+#define readw(addr)			(__readwrite_bug("readw"), 0)
+#define readl(addr)			(__readwrite_bug("readl"), 0)
+#define writeb(v, addr)			__readwrite_bug("writeb")
+#define writew(v, addr)			__readwrite_bug("writew")
+#define writel(v, addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101             0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101()	(machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101()	(0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/macro.h b/arch/nds32/include/asm/macro.h
new file mode 100644
index 0000000..acda060
--- /dev/null
+++ b/arch/nds32/include/asm/macro.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-nds32/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NDS_MACRO_H
+#define __ASM_NDS_MACRO_H
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to an "immediate address (address used by periphal)" only.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any NDS32 architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	li	$r4, addr
+	li	$r5, data
+	swi	$r5, [$r4]
+.endm
+
+.macro	write16, addr, data
+	li	$r4, addr
+	li	$r5, data
+	shi	$r5, [$r4]
+.endm
+
+.macro	write8, addr, data
+	li	$r4, addr
+	li	$r5, data
+	sbi	$r5, [$r4]
+.endm
+
+/*
+ * This macro read a value from a register, then do OR operation
+ * (set bit fields) to the value, and then store it back to the register.
+ * Note: Instruction 'ori' supports immediate value up to 15 bits.
+ */
+.macro	setbf32, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	li	$r6, data
+	or	$r5, $r5, $r6
+	swi	$r5, [$r4]
+.endm
+
+.macro	setbf15, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	ori	$r5, $r5, data
+	swi	$r5, [$r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any NDS32 architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	li	$r4, time
+1:
+	nop
+	addi	$r4, $r4, -1
+	bnez    $r4, 1b
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H */
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index 0000000..5bcc4e1
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/memory.h
+ *
+ * Copyright (C) 2000-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Note: this file should not be included by non-asm/.h files
+ */
+#ifndef __ASM_NDS_MEMORY_H
+#define __ASM_NDS_MEMORY_H
+
+#endif	/* __ASM_NDS_MEMORY_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..4336083
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+	NDS32_REG ir0;
+	NDS32_REG ipsw;
+	NDS32_REG ipc;
+	NDS32_REG sp;
+	NDS32_REG orig_r0;
+	NDS32_REG pipsw;
+	NDS32_REG pipc;
+	NDS32_REG pp0;
+	NDS32_REG pp1;
+	NDS32_REG d0hi;
+	NDS32_REG d0lo;
+	NDS32_REG d1hi;
+	NDS32_REG d1lo;
+	NDS32_REG r[26];	/* r0 - r25 */
+	NDS32_REG fp;		/* r28 */
+	NDS32_REG gp;		/* r29 */
+	NDS32_REG lp;		/* r30 */
+	NDS32_REG fucop_ctl;
+	NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+	(((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..30a8fc1
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong _bss_start_ofs;	/* BSS start relative to _start */
+extern ulong _bss_end_ofs;	/* BSS end relative to _start */
+extern ulong _end_ofs;		/* end of image relative to _start */
+extern ulong _TEXT_BASE;	/* code start */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+/* cpu/.../timer.c */
+int	timer_init(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..fafe4e4
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <environment.h>
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+
+	env_t		*bi_env;
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
-- 
1.7.3.5

[U-Boot] [PATCH v11 1/9] nds32: add header files support for nds32

[Mike Frysinger]

On Thursday, September 01, 2011 01:52:42 Macpaul Lin wrote:
> --- /dev/null
> +++ b/arch/nds32/include/asm/memory.h
> +#ifndef __ASM_NDS_MEMORY_H
> +#define __ASM_NDS_MEMORY_H
> +
> +#endif	/* __ASM_NDS_MEMORY_H */

this header doesnt define anything, and common code doesnt require 
asm/memory.h, so looks like you should just punt this

> --- /dev/null
> +++ b/arch/nds32/include/asm/u-boot.h
>
> +#include <environment.h>
> ...
> +typedef struct bd_info {
> ...
> +	env_t		*bi_env;

this is pretty unusual.  why do you need a board-specific point to the env ?  
no other arch needs this ...
-mike
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[U-Boot] [PATCH v11 2/9] nds32: add NDS32 support into common header file

[Macpaul Lin]

Add NDS32 support into common header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v7:
  - No change
Changes for v8:
  - Fix the patch according to dependency of x86's Fix
Changes for v9-v11:
  - No change

 include/common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index 12a1074..782933d 100644
--- a/include/common.h
+++ b/include/common.h
@@ -281,6 +281,10 @@ int	setenv	     (const char *, const char *);
 #ifdef CONFIG_X86		/* x86 version to be fixed! */
 # include <asm/u-boot-x86.h>
 #endif /* CONFIG_X86 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h>	/* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
-- 
1.7.3.5

[U-Boot] [PATCH v11 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Macpaul Lin]

Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

NDS32 Core N1213 has the following hardware features.

 Core:
  - 16-/32-bit mixable instruction format
  - 32 general-purpose 32-bit registers
  - 8-stage pipeline
  - Dynamic branch prediction
  - 32/64/128/256 BTB
  - Return address stack (RAS)
  - Vector interrupts for internal/external
  - 3 HW-level nested interruptions
  - User and super-user mode support
  - Memory-mapped I/O
  - Address space up to 4GB

 Memory Management Unit:
  - TLB
  - Optional hardware page table walker
  - Two groups of page size support

 Memory Subsystem:
  - I & D cache
  - I & D local memory (LM)

 Bus Interface:
  - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes v1 to v6:
  - Style clean up and reorganize code
Changes v7-v9:
  - No Change.
Changes v10:
  - start.S of N1213 CPU has been rewrote for relocation support.
  - u-boot.lds:
   - Add got and *(.got.plt) section for support GCC 4 toolchain
   - Modified for relocation implementation.
Changes v11:
  - arch/nds32/cpu/n1213/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)

 arch/nds32/cpu/n1213/Makefile   |   50 ++++
 arch/nds32/cpu/n1213/start.S    |  523 +++++++++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/u-boot.lds |   72 ++++++
 3 files changed, 645 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/Makefile
 create mode 100644 arch/nds32/cpu/n1213/start.S
 create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..da15574
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..602067e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,523 @@
+/*
+ *	Andesboot - Startup Code for Whitiger core
+ *
+ *	Copyright (C) 2006	Andes Technology Corporation
+ *	Copyright (C) 2006	Shawn Lin <nobuhiro@andestech.com>
+ *	Copyright (C) 2011	Macpaul <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <asm/macro.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC		2UL
+#define DIS_DCAC		~ENA_DCAC
+#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
+#define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
+#define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY	(0x07<<3)	! D cache ways
+#define DCAC_MEM_KBF_DSZ	(0x07<<6)	! D cache line size
+
+#define PSW			$ir0
+#define EIT_INTR_PSW		$ir1		! interruption $PSW
+#define EIT_PREV_IPSW		$ir2		! previous $IPSW
+#define EIT_IVB			$ir3		! intr vector base address
+#define EIT_EVA			$ir4		! MMU related Exception Virtual Address register
+#define EIT_PREV_EVA		$ir5		! previous $eva
+#define EIT_ITYPE		$ir6		! interruption type
+#define EIT_PREV_ITYPE		$ir7		! prev intr type
+#define EIT_MACH_ERR		$ir8		! machine error log
+#define EIT_INTR_PC		$ir9		! Interruption PC
+#define EIT_PREV_IPC		$ir10		! previous $IPC
+#define EIT_OVL_INTR_PC		$ir11		! overflow interruption PC
+#define EIT_PREV_P0		$ir12		! prev $P0
+#define EIT_PREV_P1		$ir13		! prev $p1
+#define CR_ICAC_MEM		$cr1		! I-cache/memory config reg
+#define CR_DCAC_MEM		$cr2		! D-cache/memory config reg
+#define MR_CAC_CTL		$mr8
+
+.globl _start
+
+_start:	b	reset
+	b	tlb_fill
+	b	tlb_not_present
+	b	tlb_misc
+	b	tlb_vlpt_miss
+	b	cache_parity_error
+	b	debug
+	b	general_exception
+	b	internal_interrupt		! H0I
+	b	internal_interrupt		! H1I
+	b	internal_interrupt		! H2I
+	b	internal_interrupt		! H3I
+	b	internal_interrupt		! H4I
+	b	internal_interrupt		! H5I
+
+	.balign 16
+
+/*
+ * Andesboot Startup Code (reset vector)
+ *
+ *	1.	bootstrap
+ *		1.1 reset - start of Andesboot
+ *		1.2 to superuser mode - as is when reset
+ *		1.4 Do lowlevel_init
+ *			- (this will jump out to lowlevel_init.S in SoC)
+ *			- (lowlevel_init)
+ *		1.3 Turn off watchdog timer
+ *			- (this will jump out to watchdog.S in SoC)
+ *			- (turnoff_watchdog)
+ *	2.	Do critical init when reboot (not from mem)
+ *	3.	Relocate andesboot to ram
+ *	4.	Setup stack
+ *	5.	Jump to second stage (start_andesboot)
+ */
+
+/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
+	.word _end - _start
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word 0x0badc0de
+
+/*
+ * The bootstrap code of nds32 core
+ */
+
+reset:
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	jal	load_lowlevel_init
+	jral	$p0
+#endif
+
+/*
+ * Set the N1213 (Whitiger) core to superuser mode
+ * According to spec, it is already when reset
+ */
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+	jal	load_turnoff_watchdog
+	jral	$p0
+#endif
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+	bal	cpu_init_crit		! Do CPU critical regs init
+#endif
+
+/*
+ * Set stackpointer in internal RAM to call board_init_f
+ * $sp must be 8-byte alignment for ABI compliance.
+ */
+call_board_init_f:
+	li	$sp, CONFIG_SYS_INIT_SP_ADDR
+	li	$r0, 0x00000000
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__
+/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
+	la	$r15, board_init_f	! store function address into $r15
+#endif
+#endif
+	j	board_init_f		! jump to board_init_f() in lib/board.c
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl	relocate_code
+relocate_code:
+	move	$r4, $r0		/* save addr_sp */
+	move	$r5, $r1		/* save addr of gd */
+	move	$r6, $r2		/* save addr of destination */
+
+/* Set up the stack */
+stack_setup:
+	move	$sp, $r4
+
+	la	$r0, _start
+
+	beq	$r0, $r6, clear_bss	/* skip relocation */
+
+	move	$r1, $r6		/* r1 <- scratch for copy_loop */
+	l.w	$r3, _bss_start_ofs
+	add	$r2, $r0, $r3		/* r2 <- source end address */
+
+copy_loop:
+	lwi.p	$r7, [$r0], #4
+	swi.p	$r7, [$r1], #4
+	blt	$r0, $r2, copy_loop
+
+/*
+ * fix relocations related issues
+ */
+fix_relocations:
+	l.w	$r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	$r9, $r6, $r0		/* r9 <- relocation offset */
+
+fix_got:
+/*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+	l.w	$r2, _rel_got_start_ofs	/* r2 <- rel got start ofs */
+	add	$r2, $r2, $r0		/* r2 <- rel got start in FLASH */
+	add	$r2, $r2, $r9		/* r2 <- rel got start in RAM */
+	l.w	$r3, _rel_got_end_ofs	/* r3 <- rel got end ofs */
+	add	$r3, $r3, $r0		/* r3 <- rel got end in FLASH */
+	add	$r3, $r3, $r9		/* r3 <- rel got end in RAM */
+	addi	$r2, $r2, #8		/* skipping first two entries */
+fix_got_loop:
+	lwi	$r0, [$r2]		/* r0 <- location in FLASH to fix up */
+	add	$r0, $r0, $r9		/* r0 <- location fix up to RAM */
+	swi.p	$r0, [$r2], #4		/* r0 <- store fix into .got in RAM */
+	blt	$r2, $r3, fix_got_loop
+
+clear_bss:
+	l.w	$r0, _bss_start_ofs
+	l.w	$r1, _bss_end_ofs
+	move	$r4, $r6		/* reloc addr */
+	add	$r0, $r0, $r4
+	add	$r1, $r1, $r4
+	li	$r2, 0x00000000		/* clear */
+
+clbss_l:
+	sw	$r2, [$r0]		/* clear loop... */
+	addi	$r0, $r0, #4
+	bne	$r0, $r1, clbss_l
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+	l.w	$r0, _board_init_r_ofs
+	la	$r1, _start
+	add	$lp, $r0, $r1		/* offset of board_init_f() */
+	add	$lp, $lp, $r9		/* real address of board_init_f() */
+	/* setup parameters for board_init_r */
+	move	$r0, $r5		/* gd_t */
+	move	$r1, $r6		/* dest_addr */
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__		/* NDS32 V0 ISA	*/
+	move	$r15, $lp		/* store function address into $r15 */
+#endif
+#endif
+
+	/* jump to it ... */
+	jr	$lp			/* jump to board_init_r() */
+
+_board_init_r_ofs:
+	.word board_init_r - _start
+_rel_got_start_ofs:
+	.word __got_start - _start
+_rel_got_end_ofs:
+	.word __got_end - _start
+
+/*
+ * Initialize CPU critical registers
+ *
+ *	1.	Setup control registers
+ *		1.1 Mask all IRQs
+ *		1.2 Flush cache and TLB
+ *		1.3 Disable MMU and cache
+ *	2.	Setup memory timing
+ */
+
+cpu_init_crit:
+
+	move	$r0, $lp		/* push	ra */
+
+	/* Disable Interrupts by clear GIE in $PSW reg */
+	setgie.d
+
+	/* Flush caches and TLB */
+	/* Invalidate caches */
+	bal	invalidate_icac
+	bal	invalidate_dcac
+
+	/* Flush TLB */
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+
+1:
+	! Disable MMU, Dcache
+	! Whitiger is MMU disabled when reset
+	! Disable the D$
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Set DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! write back the $CACHE_CTL reg
+	isb
+
+	move	$lp, $r0
+2:
+	ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+	la  $r6, lowlevel_init
+	la  $r7, load_lli + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+	la  $r6, turnoff_watchdog
+	la  $r7, turnoff_wtdog + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+/*
+ * Invalidate I$
+ */
+invalidate_icac:
+	mfsr	$t0, CR_ICAC_MEM		! read $cr1(I CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, ICAC_MEM_KBF_ISZ 	! Get the ISZ field
+	beqz	$p0, end_flush_icache		! if $p0=0, then no I CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of I$ block
+	addi	$t1, $p0, 2			! $t1= bit width of I cache line size(ISZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, ICAC_MEM_KBF_ISET	! get the ISET field
+	addi	$t2, $p1, 6			! $t2= bit width of ISET
+	andi	$p1, $t0, ICAC_MEM_KBF_IWAY	! get bitfield of Iway
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is I way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+ICAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1I_IX_INVAL
+	bnez	$p1, ICAC_LOOP
+end_flush_icache:
+	ret
+
+/*
+ * Invalidate D$
+ */
+invalidate_dcac:
+	mfsr	$t0, CR_DCAC_MEM		! read $cr2(D CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, DCAC_MEM_KBF_DSZ	! Get the DSZ field
+	beqz	$p0, end_flush_dcache		! if $p0=0, then no D CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of D$ block
+	addi	$t1, $p0, 2			! $t1= bit width of D cache line size(DSZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, DCAC_MEM_KBF_DSET	! get the DSET field
+	addi	$t2, $p1, 6			! $t2= bit width of DSET
+	andi	$p1, $t0, DCAC_MEM_KBF_DWAY	! get bitfield of D way
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is D way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+DCAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1D_IX_INVAL
+	bnez	$p1, DCAC_LOOP
+end_flush_dcache:
+	ret
+
+/*
+ * Interrupt handling
+ */
+
+/*
+ * exception handlers
+ */
+	.align	5
+
+.macro	SAVE_ALL
+	! FIXME: Other way to get PC?
+	! FIXME: Update according to the newest spec!!
+1:
+	la	 $r28, 1
+	push $r28
+	mfsr $r28, PSW			! $PSW
+	push $r28
+	mfsr $r28, EIT_EVA		! $ir1 $EVA
+	push $r28
+	mfsr $r28, EIT_ITYPE		! $ir2 $ITYPE
+	push $r28
+	mfsr $r28, EIT_MACH_ERR		! $ir3 Mach Error
+	push $r28
+	mfsr $r28, EIT_INTR_PSW		! $ir5 $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_IPSW	! $ir6 prev $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_EVA		! $ir7 prev $EVA
+	push $r28
+	mfsr $r28, EIT_PREV_ITYPE	! $ir8 prev $ITYPE
+	push $r28
+	mfsr $r28, EIT_INTR_PC		! $ir9 Interruption PC
+	push $r28
+	mfsr $r28, EIT_PREV_IPC		! $ir10 prev INTR_PC
+	push $r28
+	mfsr $r28, EIT_OVL_INTR_PC	! $ir11 Overflowed INTR_PC
+	push $r28
+	mfusr $r28, $d1.lo
+	push $r28
+	mfusr $r28, $d1.hi
+	push $r28
+	mfusr $r28, $d0.lo
+	push $r28
+	mfusr $r28, $d0.hi
+	push $r28
+	pushm $r0, $r30		! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
+	addi	$sp, $sp, -4	! make room for implicit pt_regs parameters
+.endm
+
+	.align	5
+tlb_fill:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 1				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_not_present:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 2				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_misc:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 3				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_vlpt_miss:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 4				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+cache_parity_error:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 5				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+debug:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 6				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+general_exception:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 7				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+internal_interrupt:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 8				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+
+/*
+ * void reset_cpu(ulong addr);
+ * $r0: input address to jump to
+ */
+.globl reset_cpu
+reset_cpu:
+/* No need to disable MMU because we never enable it */
+
+	bal	invalidate_icac
+	bal	invalidate_dcac
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+1:
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Clear the DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! Write back the $CACHE_CTL reg
+	br	$r0				! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..194f45a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		arch/nds32/cpu/n1213/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		 *(.got.plt) *(.got)
+		__got_end = .;
+	}
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+}
-- 
1.7.3.5

[U-Boot] [PATCH v11 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Mike Frysinger]

On Thursday, September 01, 2011 01:52:44 Macpaul Lin wrote:
> --- /dev/null
> +++ b/arch/nds32/cpu/n1213/u-boot.lds
>
> +SECTIONS
> +{
> +	. = 0x00000000;

shouldnt this be CONFIG_SYS_TEXT_BASE or CONFIG_SYS_MONITOR_BASE or something 
other than 0 ?
-mike
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[U-Boot] [PATCH v11 3/9] nds32/core N1213: NDS32 N12 core family N1213

[馬克泡]

Hi Mike and Albert,

2011/9/1 Mike Frysinger <vapier@gentoo.org>:
> On Thursday, September 01, 2011 01:52:44 Macpaul Lin wrote:
>> --- /dev/null
>> +++ b/arch/nds32/cpu/n1213/u-boot.lds
>>
>> +SECTIONS
>> +{
>> + ? ? . = 0x00000000;
>
> shouldnt this be CONFIG_SYS_TEXT_BASE or CONFIG_SYS_MONITOR_BASE or something
> other than 0 ?
> -mike

After checking the binary with NDS32 architecture, I've found the
dominate parameter is
CONFIG_SYS_TEXT_BASE or CONFIG_SYS_MONITOR_BASE.
So this line is not necessary.
However I also found there are the same configurations in ARM's linker script.
I just curios about is this a necessity for ARM?

I'll remove this in PATCH v12. Thanks.

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v11 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Mike Frysinger]

On Thursday, September 01, 2011 01:52:42 you wrote:
> --- /dev/null
> +++ b/arch/nds32/include/asm/u-boot-nds32.h
>
> +/* cpu/.../timer.c */
> +int	timer_init(void);

this is taken care of by common.h already, so you can just delete this
-mike
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[U-Boot] [PATCH v11 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Macpaul Lin]

SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.

cpu.c
 According to the bootstrap procedure in n1213 Core,
 to turn off watchdog timer is suggested after the
 cpu is in superuser mdoe.

 1. bootstrap
 1.1 reset - start of Andesboot
 1.2 to superuser mode - as is when reset
 1.3 Turn off watchdog timer

 If you take look into the start.S in n1213, you will find that
 system will turn off watchdog after start.S has been retunred
 from lowlevel_init.

 Since the watchdog device is depends on the SoC is choosed.
 It should be belonged to the SoC (ag101) folder.

watchdog.S:
 If you've ran another bootloader before u-boot was started
 the watchdog might have been enabled already.

lowlevel_init.S is a peripheral initial procedure of ag101.
It configures onboard dram, clock, and power settings.
It also prepars the dram environment before moving u-boot
from rom and flash into dram.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code clean up.
Changes for v5-v6:
  - Split watchdog.S from lowlevel_init.S.
  - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
   - reset_cpu was remove inside do_reset().
  - lowlevel_init.S
   - Change hard code value into MARCO definitions.
   - ftsmc010
     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
   - ftsdmc021
     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
     - Fix the default configuration value of FTSDMC and FTSMC controller.
   - Remove some ftpmu010 and flash probe code to C functions.
Changes for v7:
  - clean up.
Changes for v8-v9:
  - No change.
Changes for v10:
  - asm-offset.c: file added for ag101 use only.
  - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
  - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
  - cpu.c: remove unused cpu_init().
  - lowlevel_init.S
   - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
   - Replace routings by macros to made code much easier to understand.
   - Add debug LED support.
   - Add CONFIG_MEM_REMAP for those boards must do memort remapping.
Changes for v11:
  - arch/nds32/cpu/n1213/ag101/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)

 Makefile                                   |    3 +-
 arch/nds32/cpu/n1213/ag101/Makefile        |   70 ++++++++
 arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
 arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/timer.c         |  204 ++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
 arch/nds32/include/asm/arch-ag101/ag101.h  |   68 ++++++++
 8 files changed, 873 insertions(+), 1 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
 create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
 create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/Makefile b/Makefile
index 03d80b7..89aebff 100644
--- a/Makefile
+++ b/Makefile
@@ -1019,7 +1019,8 @@ clean:
 	       $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds  \
 	       $(obj)u-boot.lds						  \
 	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]	  \
-	       $(obj)arch/blackfin/cpu/init.{lds,elf}
+	       $(obj)arch/blackfin/cpu/init.{lds,elf}			  \
+	       $(obj)arch/nds32/cpu/$(CPU)/$(SOC)/gen-asm-offsets.[chs]
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)lib/asm-offsets.s
 	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..02e36b7
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,70 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+$(OBJS): $(obj)gen-asm-offsets.h
+$(obj)gen-asm-offsets.h:	$(TOPDIR)/include/autoconf.mk.dep \
+	$(obj)gen-asm-offsets.s
+	@echo Generating $@ ; \
+	$(SRCTREE)/tools/scripts/make-asm-offsets $(obj)gen-asm-offsets.s $@
+
+$(obj)gen-asm-offsets.s:	$(TOPDIR)/include/autoconf.mk.dep \
+	$(src)asm-offsets.c
+	@mkdir -p $(obj)b
+	$(CC) -DDO_DEPS_ONLY \
+		$(CFLAGS) -o $@ $(src)asm-offsets.c -c -S
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
new file mode 100644
index 0000000..92ada8a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
@@ -0,0 +1,43 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..0ab666e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+	unsigned long i;
+#endif
+
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+	while (1)
+		;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr , addr + size);
+	icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..94308a8
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+#include "gen-asm-offsets.h"
+
+#include <asm/macro.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+
+#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro	wait_sdram
+	li	$r0, CONFIG_FTSDMC021_BASE
+1:
+	lwi	$r1, [$r0+FTSDMC021_CR2]
+	bnez	$r1, 1b
+.endm
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+
+	led	0x0
+	jal	mem_init
+
+	led	0x10
+	jal	remap
+
+	led	0x20
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	led	0x01
+	write32	SMC_BANK0_CR_A, SMC_BANK0_CR_D			! 0x10000052
+	write32	SMC_BANK0_TPR_A, SMC_BANK0_TPR_D		! 0x00151151
+
+	/*
+	 * config AHB Controller
+	 */
+	led	0x02
+	write32	AHBC_BSR6_A, AHBC_BSR6_D
+
+	/*
+	 * config PMU controller
+	 */
+	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
+	led	0x03
+	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
+
+	/*
+	 * config SDRAM controller
+	 */
+	led	0x04
+	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
+	led	0x05
+	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
+	led	0x06
+	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
+
+	led	0x07
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
+	wait_sdram
+
+	led	0x08
+	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
+	wait_sdram
+
+	led	0x09
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
+	wait_sdram
+
+	led	0x0a
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+	/*
+	 * Remapping
+	 */
+	led	0x1a
+	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
+
+	/* clear empty BSR registers */
+	led	0x1b
+	li	$r4, CONFIG_FTSDMC021_BASE
+	li	$r5, 0x0
+	swi	$r5, [$r4 + FTSDMC021_BANK1_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
+
+#ifdef CONFIG_MEM_REMAP
+	/*
+	 * Copy ROM code to SDRAM base for memory remap layout.
+	 * This is not the real relocation, the real relocation is the function
+	 * relocate_code() is start.S which supports the systems is memory
+	 * remapped or not.
+	 */
+	/*
+	 * Doing memory remap is essential for preparing some non-OS or RTOS
+	 * applications.
+	 *
+	 * This is also a must on ADP-AG101 board.
+	 * The reason is because the ROM/FLASH circuit on PCB board.
+	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	 * ROM/FLASH is used to boot.
+	 *
+	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	 * and the FLASH is connected to BANK1.
+	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	 * and the FLASH is connected to BANK0.
+	 * It will occur problem when doing flash probing if the flash is at
+	 * BANK0 (0x00000000) while memory remapping was skipped.
+	 *
+	 * Other board like ADP-AG101P may not enable this since there is only
+	 * a FLASH connected to bank0.
+	 */
+	led	0x11
+	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
+	li	$r5, 0x0
+	la	$r1, relo_base				/* get $pc or $lp */
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(_end)
+	ori	$r6, $r6, lo12(_end)
+	add	$r6, $r6, $r2
+1:
+	lwi.p	$r7, [$r5], #4
+	swi.p	$r7, [$r4], #4
+	blt	$r5, $r6, 1b
+
+	/* set remap bit */
+	/*
+	 * MEM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
+	 */
+	led	0x1c
+	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..b689eab
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl	turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+#endif
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE		0x90100000	/* AHB Controller */
+#define CONFIG_FTSMC020_BASE		0x90200000	/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE		0x90300000	/* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000	/* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000	/* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE		0x90600000	/* LCD Controller */
+#define CONFIG_RESERVED_01_BASE		0x90700000	/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000	/* Reserved */
+#define CONFIG_FTMAC100_BASE		0x90900000	/* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000	/* External USB host */
+#define CONFIG_USB_DEV_BASE		0x90B00000	/* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000	/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE		0x90D00000	/* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000	/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000	/* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000	/* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC	/* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE		0x98100000	/* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE	0x98300000	/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE		0x98400000	/* Counter/Timers */
+#define CONFIG_FTWDT010_BASE		0x98500000	/* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE		0x98600000	/* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE		0x98700000	/* GPIO */
+#define CONFIG_FTINTC010_BASE		0x98800000	/* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE		0x98A00000	/* I2C */
+#define CONFIG_RESERVED_04_BASE		0x98C00000	/* Reserved */
+#define CONFIG_FTCFC010_BASE		0x98D00000	/* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000	/* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE		0x99400000	/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE	0x99600000	/* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE	0x98200000	/* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000	/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE		0x98900000	/* IrDA */
+#define CONFIG_PMW_BASE			0x99100000	/* PWM - Pulse Width Modulator Controller */
+
+#endif	/* __AG101_H */
-- 
1.7.3.5

[U-Boot] [PATCH v11 5/9] nds32/lib: add generic funcs in NDS32 lib

[Macpaul Lin]

Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up and formatting style.
Changes for v5-v6:
  - board.c
   - Do some clean up and add code
   - Remove display banner which hasn't support.
   - Add ftpmu010 related power management unit code.
   - Remove useless LED related code.
   - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
   - Remove CONFIG_SOFT_I2C which hasn't been support.
   - Remove CONFIG_FSL_ESDHC which hasn't been support.
   - clean up.
Changes for v7:
  - clean up.
  - move single file patch arch/nds32/config.mk to this commit.
  - interrupts.c refine origin interrupt enable and disable.
Changes for v8:
  - interrups.c: fix up for new ptraces.h.
Changes for v9:
  - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
Changes for v10:
  - config.mk:
   - add -fpie flag.
   - replace -ffixed-8 to -ffixed-10.
   - add -mrelax and --gc-sections to LDFLAG
  - board.c:
   - fix lib/board.c for relocation.
   - fix dram init for relocation.
Changes for v11:
  - arch/nds32/lib/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)

 arch/nds32/config.mk        |   37 ++++
 arch/nds32/lib/Makefile     |   52 +++++
 arch/nds32/lib/board.c      |  453 +++++++++++++++++++++++++++++++++++++++++++
 arch/nds32/lib/bootm.c      |  241 +++++++++++++++++++++++
 arch/nds32/lib/interrupts.c |  131 +++++++++++++
 5 files changed, 914 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/config.mk
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/board.c
 create mode 100644 arch/nds32/lib/bootm.c
 create mode 100644 arch/nds32/lib/interrupts.c

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..78b4a23
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,37 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common -mrelax
+PLATFORM_RELFLAGS	+= -gdwarf-2
+PLATFORM_CPPFLAGS	+= -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-10 -fpie
+
+LDFLAGS_u-boot		= --gc-sections --relax
+
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..0475c7f
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+OBJS	:= board.o bootm.o interrupts.o
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..1195e91
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,453 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern ulong __bss_end;
+ulong monitor_flash_len;
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+const char version_string[] =
+	U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	char tmp[64];	/* long enough for environment variables */
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+			? (int) simple_strtoul(tmp, NULL, 10)
+			: CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+void __dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size =  gd->ram_size;
+}
+void dram_init_banksize(void)
+	__attribute__((weak, alias("__dram_init_banksize")));
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	pmu_init,
+#endif
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init,
+#endif
+	display_dram_config,
+	NULL,
+};
+
+void board_init_f(ulong bootflag)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	gd_t *id;
+	ulong addr, addr_sp;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
+
+	/* compiler optimization barrier needed for GCC >= 3.4 */
+	__asm__ __volatile__("" : : : "memory");
+
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	gd->mon_len = _bss_end_ofs;
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	debug("monitor len: %08lX\n", gd->mon_len);
+	/*
+	 * Ram is setup, size stored in gd !!
+	 */
+	debug("ramsize: %08lX\n", gd->ram_size);
+
+	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	/* reserve TLB table */
+	addr -= (4096 * 4);
+
+	/* round down to next 64 kB limit */
+	addr &= ~(0x10000 - 1);
+
+	gd->tlb_addr = addr;
+	debug("TLB table at: %08lx\n", addr);
+#endif
+
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+	gd->fb_base = CONFIG_FB_ADDR;
+#else
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
+	/*
+	 * reserve memory for U-Boot code, data & bss
+	 * round down to next 4 kB limit
+	 */
+	addr -= gd->mon_len;
+	addr &= ~(4096 - 1);
+
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+
+	/*
+	 * reserve memory for malloc() arena
+	 */
+	addr_sp = addr - TOTAL_MALLOC_LEN;
+	debug("Reserving %dk for malloc() at: %08lx\n",
+			TOTAL_MALLOC_LEN >> 10, addr_sp);
+	/*
+	 * (permanently) allocate a Board Info struct
+	 * and a permanent copy of the "global" data
+	 */
+	addr_sp -= sizeof(bd_t);
+	bd = (bd_t *) addr_sp;
+	gd->bd = bd;
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+			sizeof(bd_t), addr_sp);
+
+	addr_sp -= sizeof(gd_t);
+	id = (gd_t *) addr_sp;
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			sizeof(gd_t), addr_sp);
+
+	/* setup stackpointer for exeptions */
+	gd->irq_sp = addr_sp;
+#ifdef CONFIG_USE_IRQ
+	addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
+#endif
+	/* leave 3 words for abort-stack    */
+	addr_sp -= 12;
+
+	/* 8-byte alignment for ABI compliance */
+	addr_sp &= ~0x07;
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
+
+	gd->bd->bi_baudrate = gd->baudrate;
+	/* Ram isn't board specific, so move it to board code ... */
+	dram_init_banksize();
+	display_dram_config();	/* and display it */
+
+	gd->relocaddr = addr;
+	gd->start_addr_sp = addr_sp;
+
+	gd->reloc_off = addr - _TEXT_BASE;
+
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	memcpy(id, (void *)gd, sizeof(gd_t));
+
+	relocate_code(addr_sp, id, addr);
+
+	/* NOTREACHED - relocate_code() does not return */
+}
+
+/*
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	char *s;
+	bd_t *bd;
+	ulong malloc_start;
+
+	extern void malloc_bin_reloc(void);
+
+	gd = id;
+	bd = gd->bd;
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	monitor_flash_len = _end_ofs;
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
+
+	board_init();	/* Setup chipselects */
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	/*
+	 * We have to relocate the command table manually
+	 */
+	fixup_cmdtable(&__u_boot_cmd_start,
+		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
+
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+	mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+	malloc_bin_reloc();
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init();
+#endif
+
+	/* IP Address */
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+#if defined(CONFIG_USE_IRQ)
+	/* set up exceptions */
+	interrupt_init();
+	/* enable exceptions */
+	enable_interrupts();
+#endif
+
+	/* Initialize from environment */
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+	puts("Net:   ");
+#endif
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	show_boot_progress(15);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..c42ad2b
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+extern void reset_cpu(ulong addr);
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"lp : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}
-- 
1.7.3.5

[U-Boot] [PATCH v11 5/9] nds32/lib: add generic funcs in NDS32 lib

[Mike Frysinger]

On Thursday, September 01, 2011 01:52:46 Macpaul Lin wrote:
> --- /dev/null
> +++ b/arch/nds32/config.mk
>
> +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds

the top level logic tries hard to find a good LDSCRIPT default.  do you need 
to set this yourself anymore ?

> --- /dev/null
> +++ b/arch/nds32/lib/board.c
>
> +extern ulong __bss_end;

if this is coming from the linker script, then it should be:
extern char __bss_end[];

> +#ifndef CONFIG_IDENT_STRING
> +#define CONFIG_IDENT_STRING ""
> +#endif
> +
> +const char version_string[] =
> +	U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING;

pretty sure you dont need this anymore as common/cmd_version.c takes care of 
it.  so just delete this code.

> +void board_init_f(ulong bootflag)
> +{
> ...
> +	/* Pointer is writable since we allocated a register for it */
> +	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
> +
> +	/* compiler optimization barrier needed for GCC >= 3.4 */
> +	__asm__ __volatile__("" : : : "memory");
> +
> +	memset((void *)gd, 0, sizeof(gd_t));

err, is that barrier really needed ?  sounds like a bug in your compiler.

as for the memset, it should be:
memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);

> +	addr_sp -= sizeof(bd_t);

sizeof(bd_t) -> GENERATED_BD_INFO_SIZE

this shows up multiple times

also, did i miss something, or do you not zero out your board info ?

> +	addr_sp -= sizeof(gd_t);

sizeof(gd_t) -> GENERATED_GBL_DATA_SIZE

this shows up multiple times
-mike
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[U-Boot] [PATCH v11 5/9] nds32/lib: add generic funcs in NDS32 lib

[馬克泡]

Hi, Mike and Wolfgang,

2011/9/1 Mike Frysinger <vapier@gentoo.org>:
> On Thursday, September 01, 2011 01:52:46 Macpaul Lin wrote:

[... skipped and will discuss these later]

>> +void board_init_f(ulong bootflag)
>> +{
>> ...
>> + ? ? /* Pointer is writable since we allocated a register for it */
>> + ? ? gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
>> +
>> + ? ? /* compiler optimization barrier needed for GCC >= 3.4 */
>> + ? ? __asm__ __volatile__("" : : : "memory");
>> +
>> + ? ? memset((void *)gd, 0, sizeof(gd_t));
>
> err, is that barrier really needed ? ?sounds like a bug in your compiler.

I'm not sure if this is really a bug which has been fixed or this is
still a common problem.
I've found there are architectures x86, mips, m68k, nios2, powerpc
have this code to do
optimization barrier.
I'll try to verify this with our toolchain department, but I think
this might be a common problem.
Could someone give a comment on this?

> as for the memset, it should be:
> memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);

It's the similar case.
Since we have generated header file for global data, this code might be good.
However, there are other architecture remain the same code which do
memset with sizeof(gd_t).
Included m68k, sparc, arm, avr32 and powerpc.
Do I miss something of the discussion before in the mailing list?
Should these also be a clean up for other architectures, too?

>
>> + ? ? addr_sp -= sizeof(bd_t);
>
> sizeof(bd_t) -> GENERATED_BD_INFO_SIZE
>
> this shows up multiple times
>
> also, did i miss something, or do you not zero out your board info ?
>
>> + ? ? addr_sp -= sizeof(gd_t);
>
> sizeof(gd_t) -> GENERATED_GBL_DATA_SIZE
>
> this shows up multiple times
> -mike
>

No, I didn't zero out the board info just like the implementation of
other architecture.
Dose this lead a problem?

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v11 5/9] nds32/lib: add generic funcs in NDS32 lib

[Mike Frysinger]

On Tuesday, September 06, 2011 02:41:47 ??? wrote:
> 2011/9/1 Mike Frysinger <vapier@gentoo.org>:
> > On Thursday, September 01, 2011 01:52:46 Macpaul Lin wrote:
> >> +void board_init_f(ulong bootflag)
> >> +{
> >> ...
> >> +     /* Pointer is writable since we allocated a register for it */
> >> +     gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
> >> +
> >> +     /* compiler optimization barrier needed for GCC >= 3.4 */
> >> +     __asm__ __volatile__("" : : : "memory");
> >> +
> >> +     memset((void *)gd, 0, sizeof(gd_t));
> > 
> > err, is that barrier really needed ?  sounds like a bug in your compiler.
> 
> I'm not sure if this is really a bug which has been fixed or this is
> still a common problem.
> I've found there are architectures x86, mips, m68k, nios2, powerpc
> have this code to do
> optimization barrier.
> I'll try to verify this with our toolchain department, but I think
> this might be a common problem.
> Could someone give a comment on this?

unless you know you need it, i'd refrain from copying warts from other people.  
might want to look at `git log` to see why the other arches actually have it.

> > as for the memset, it should be:
> > memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
> 
> It's the similar case.
> Since we have generated header file for global data, this code might be
> good. However, there are other architecture remain the same code which do
> memset with sizeof(gd_t).
> Included m68k, sparc, arm, avr32 and powerpc.
> Do I miss something of the discussion before in the mailing list?
> Should these also be a clean up for other architectures, too?

i think it's a matter of those arches havent updated.  the generated header is 
a new feature compared to these arches.

> > also, did i miss something, or do you not zero out your board info ?
> 
> No, I didn't zero out the board info just like the implementation of
> other architecture.
> Dose this lead a problem?

i think it depends purely on the arch/board setup.  if the arch knows the 
board data is going to be coming from a zeroed location (like bss), or it 
knows it initializes all the members, then you can skip it.  otherwise, you 
should be calling memset() on it to make sure things are in a sane state.
-mike
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[U-Boot] [PATCH v12 1/9] nds32: add header files support for nds32

[Macpaul Lin]

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
   - Code cleanup and style formatting.
Changes for v5-v6:
   - This patch also updated the following changes against the
     change after master tree (v2010.12-rc1).
   - fix upper case definitions in cache.h
   - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
   - Add readsb, writesb functions into io.h.
Changes for v7:
   - clean up
   - volatile:
    - types.h
     - remove typedef volatile unsigned char  vuchar;
     - remove typedef volatile unsigned long  vulong;
     - remove typedef volatile unsigned short vushort;
    - u-boot.h: remove bd_info_ext bi_ext
    - bitops.h: add accessor function to bit operation with volatile var.
    - system.h: add system.h for local_irq operation with flag.
Changes for v8:
   - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
   - ptregs.h: removed
Changes for v9:
   - No change.
Changes for v10:
   - macro.h: add writel and setbf macros
   - u-boot-nds32.h:
    - Remove obsolete andesboot_* symbols for relocation.
    - Add _bss_*_offset symbols for relocation.
   - config.h: add manual relocation support as default.
Changes for v11:
   - unaligned.h: replace asm/unaligned.h with asm-generic/unaligned.h
Changes for v12:
   - remove no used memory.h
   - remove seldom used bi_env parameter
   - u-boot-nds32.h:
    - remove duplicate timer_init()

 arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
 arch/nds32/include/asm/byteorder.h    |   36 +++
 arch/nds32/include/asm/cache.h        |   54 +++++
 arch/nds32/include/asm/config.h       |   28 +++
 arch/nds32/include/asm/global_data.h  |   89 +++++++
 arch/nds32/include/asm/io.h           |  409 +++++++++++++++++++++++++++++++++
 arch/nds32/include/asm/mach-types.h   |   29 +++
 arch/nds32/include/asm/macro.h        |   96 ++++++++
 arch/nds32/include/asm/posix_types.h  |   84 +++++++
 arch/nds32/include/asm/processor.h    |   25 ++
 arch/nds32/include/asm/ptrace.h       |   88 +++++++
 arch/nds32/include/asm/string.h       |   57 +++++
 arch/nds32/include/asm/system.h       |   88 +++++++
 arch/nds32/include/asm/types.h        |   63 +++++
 arch/nds32/include/asm/u-boot-nds32.h |   51 ++++
 arch/nds32/include/asm/u-boot.h       |   60 +++++
 arch/nds32/include/asm/unaligned.h    |    1 +
 17 files changed, 1444 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/bitops.h
 create mode 100644 arch/nds32/include/asm/byteorder.h
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/config.h
 create mode 100644 arch/nds32/include/asm/global_data.h
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/include/asm/mach-types.h
 create mode 100644 arch/nds32/include/asm/macro.h
 create mode 100644 arch/nds32/include/asm/posix_types.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/system.h
 create mode 100644 arch/nds32/include/asm/types.h
 create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
 create mode 100644 arch/nds32/include/asm/u-boot.h
 create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..c56f04b
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void *addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+extern void clear_bit(int nr, volatile void *addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, volatile void *addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, volatile void *addr);
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ	6	/* I-cache line size */
+#define ICM_CFG_MSK_ISZ	(0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
+#define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..6f654d9
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_NEEDS_MANUAL_RELOC
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..665266b
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+
+	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t	ram_size;	/* RAM size */
+	unsigned long	mon_len;	/* monitor len */
+	unsigned long	irq_sp;		/* irq stack pointer */
+	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	unsigned long	tlb_addr;
+#endif
+
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT		0x00004	/* Silent mode			*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	*/
+#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r10")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..45b9c2e
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,409 @@
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+#define writeb(v, a)			__arch_putb(v, a)
+#define writew(v, a)			__arch_putw(v, a)
+#define writel(v, a)			__arch_putl(v, a)
+
+#define readb(a)			__arch_getb(a)
+#define readw(a)			__arch_getw(a)
+#define readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache)				\
+({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
+	_ret;								\
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"), 0)
+#define readw(addr)			(__readwrite_bug("readw"), 0)
+#define readl(addr)			(__readwrite_bug("readl"), 0)
+#define writeb(v, addr)			__readwrite_bug("writeb")
+#define writew(v, addr)			__readwrite_bug("writew")
+#define writel(v, addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101             0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101()	(machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101()	(0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/macro.h b/arch/nds32/include/asm/macro.h
new file mode 100644
index 0000000..acda060
--- /dev/null
+++ b/arch/nds32/include/asm/macro.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-nds32/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NDS_MACRO_H
+#define __ASM_NDS_MACRO_H
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to an "immediate address (address used by periphal)" only.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any NDS32 architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	li	$r4, addr
+	li	$r5, data
+	swi	$r5, [$r4]
+.endm
+
+.macro	write16, addr, data
+	li	$r4, addr
+	li	$r5, data
+	shi	$r5, [$r4]
+.endm
+
+.macro	write8, addr, data
+	li	$r4, addr
+	li	$r5, data
+	sbi	$r5, [$r4]
+.endm
+
+/*
+ * This macro read a value from a register, then do OR operation
+ * (set bit fields) to the value, and then store it back to the register.
+ * Note: Instruction 'ori' supports immediate value up to 15 bits.
+ */
+.macro	setbf32, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	li	$r6, data
+	or	$r5, $r5, $r6
+	swi	$r5, [$r4]
+.endm
+
+.macro	setbf15, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	ori	$r5, $r5, data
+	swi	$r5, [$r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any NDS32 architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	li	$r4, time
+1:
+	nop
+	addi	$r4, $r4, -1
+	bnez    $r4, 1b
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..4336083
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+	NDS32_REG ir0;
+	NDS32_REG ipsw;
+	NDS32_REG ipc;
+	NDS32_REG sp;
+	NDS32_REG orig_r0;
+	NDS32_REG pipsw;
+	NDS32_REG pipc;
+	NDS32_REG pp0;
+	NDS32_REG pp1;
+	NDS32_REG d0hi;
+	NDS32_REG d0lo;
+	NDS32_REG d1hi;
+	NDS32_REG d1lo;
+	NDS32_REG r[26];	/* r0 - r25 */
+	NDS32_REG fp;		/* r28 */
+	NDS32_REG gp;		/* r29 */
+	NDS32_REG lp;		/* r30 */
+	NDS32_REG fucop_ctl;
+	NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+	(((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..ae1918d
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong __bss_start;	/* BSS start relative to _start */
+extern ulong __bss_end__;	/* BSS end relative to _start */
+extern ulong _end;		/* end of image relative to _start */
+extern ulong _start;		/* start of image relative to _start */
+extern ulong _TEXT_BASE;	/* code start */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..fe4bfcb
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <environment.h>
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
-- 
1.7.3.5

[U-Boot] [PATCH v12 2/9] nds32: add NDS32 support into common header file

[Macpaul Lin]

Add NDS32 support into common header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v7:
  - No change
Changes for v8:
  - Fix the patch according to dependency of x86's Fix
Changes for v9-v12:
  - No change

 include/common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index bd10f31..bf36b2f 100644
--- a/include/common.h
+++ b/include/common.h
@@ -281,6 +281,10 @@ int	setenv	     (const char *, const char *);
 #ifdef CONFIG_X86		/* x86 version to be fixed! */
 # include <asm/u-boot-x86.h>
 #endif /* CONFIG_X86 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h>	/* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
-- 
1.7.3.5

[U-Boot] [PATCH v12 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Macpaul Lin]

Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes v1 to v6:
  - Style clean up and reorganize code
Changes v7-v9:
  - No Change.
Changes v10:
  - start.S of N1213 CPU has been rewrote for relocation support.
  - u-boot.lds:
   - Add got and *(.got.plt) section for support GCC 4 toolchain
   - Modified for relocation implementation.
Changes v11:
  - arch/nds32/cpu/n1213/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes v12:
  - u-boot.lds
   - Remove the 0x00000000 base address in linker script.
     The base address of the binary will be determined by CONFIG_SYS_TEXT_BASE
  - Remove the CPU features in commit log and add to README in later patches.

 arch/nds32/cpu/n1213/Makefile   |   50 ++++
 arch/nds32/cpu/n1213/start.S    |  501 +++++++++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/u-boot.lds |   70 ++++++
 3 files changed, 621 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/Makefile
 create mode 100644 arch/nds32/cpu/n1213/start.S
 create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..da15574
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..6fe30cc
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,501 @@
+/*
+ *	Andesboot - Startup Code for Whitiger core
+ *
+ *	Copyright (C) 2006	Andes Technology Corporation
+ *	Copyright (C) 2006	Shawn Lin <nobuhiro@andestech.com>
+ *	Copyright (C) 2011	Macpaul <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <asm/macro.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC		2UL
+#define DIS_DCAC		~ENA_DCAC
+#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
+#define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
+#define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY	(0x07<<3)	! D cache ways
+#define DCAC_MEM_KBF_DSZ	(0x07<<6)	! D cache line size
+
+#define PSW			$ir0
+#define EIT_INTR_PSW		$ir1		! interruption $PSW
+#define EIT_PREV_IPSW		$ir2		! previous $IPSW
+#define EIT_IVB			$ir3		! intr vector base address
+#define EIT_EVA			$ir4		! MMU related Exception Virtual Address register
+#define EIT_PREV_EVA		$ir5		! previous $eva
+#define EIT_ITYPE		$ir6		! interruption type
+#define EIT_PREV_ITYPE		$ir7		! prev intr type
+#define EIT_MACH_ERR		$ir8		! machine error log
+#define EIT_INTR_PC		$ir9		! Interruption PC
+#define EIT_PREV_IPC		$ir10		! previous $IPC
+#define EIT_OVL_INTR_PC		$ir11		! overflow interruption PC
+#define EIT_PREV_P0		$ir12		! prev $P0
+#define EIT_PREV_P1		$ir13		! prev $p1
+#define CR_ICAC_MEM		$cr1		! I-cache/memory config reg
+#define CR_DCAC_MEM		$cr2		! D-cache/memory config reg
+#define MR_CAC_CTL		$mr8
+
+.globl _start
+
+_start:	b	reset
+	b	tlb_fill
+	b	tlb_not_present
+	b	tlb_misc
+	b	tlb_vlpt_miss
+	b	cache_parity_error
+	b	debug
+	b	general_exception
+	b	internal_interrupt		! H0I
+	b	internal_interrupt		! H1I
+	b	internal_interrupt		! H2I
+	b	internal_interrupt		! H3I
+	b	internal_interrupt		! H4I
+	b	internal_interrupt		! H5I
+
+	.balign 16
+
+/*
+ * Andesboot Startup Code (reset vector)
+ *
+ *	1.	bootstrap
+ *		1.1 reset - start of u-boot
+ *		1.2 to superuser mode - as is when reset
+ *		1.4 Do lowlevel_init
+ *			- (this will jump out to lowlevel_init.S in SoC)
+ *			- (lowlevel_init)
+ *		1.3 Turn off watchdog timer
+ *			- (this will jump out to watchdog.S in SoC)
+ *			- (turnoff_watchdog)
+ *	2.	Do critical init when reboot (not from mem)
+ *	3.	Relocate andesboot to ram
+ *	4.	Setup stack
+ *	5.	Jump to second stage (board_init_r)
+ */
+
+/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word 0x0badc0de
+
+/*
+ * The bootstrap code of nds32 core
+ */
+
+reset:
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	jal	load_lowlevel_init
+	jral	$p0
+#endif
+
+/*
+ * Set the N1213 (Whitiger) core to superuser mode
+ * According to spec, it is already when reset
+ */
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+	jal	load_turnoff_watchdog
+	jral	$p0
+#endif
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+	bal	cpu_init_crit		! Do CPU critical regs init
+#endif
+
+/*
+ * Set stackpointer in internal RAM to call board_init_f
+ * $sp must be 8-byte alignment for ABI compliance.
+ */
+call_board_init_f:
+	li	$sp, CONFIG_SYS_INIT_SP_ADDR
+	li	$r0, 0x00000000
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__
+/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
+	la	$r15, board_init_f	! store function address into $r15
+#endif
+#endif
+	j	board_init_f		! jump to board_init_f() in lib/board.c
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl	relocate_code
+relocate_code:
+	move	$r4, $r0		/* save addr_sp */
+	move	$r5, $r1		/* save addr of gd */
+	move	$r6, $r2		/* save addr of destination */
+
+/* Set up the stack */
+stack_setup:
+	move	$sp, $r4
+
+	la	$r0, _start
+
+	beq	$r0, $r6, clear_bss	/* skip relocation */
+
+	move	$r1, $r6		/* r1 <- scratch for copy_loop */
+	la	$r3, __bss_start
+	sub	$r3, $r3, $r0		/* r3 <- __bss_start_ofs */
+	add	$r2, $r0, $r3		/* r2 <- source end address */
+
+copy_loop:
+	lwi.p	$r7, [$r0], #4
+	swi.p	$r7, [$r1], #4
+	blt	$r0, $r2, copy_loop
+
+/*
+ * fix relocations related issues
+ */
+fix_relocations:
+	l.w	$r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	$r9, $r6, $r0		/* r9 <- relocation offset */
+
+fix_got:
+/*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+	la	$r2, __got_start	/* r2 <- rel __got_start in FLASH */
+	add	$r2, $r2, $r9		/* r2 <- rel __got_start in RAM */
+	la	$r3, __got_end		/* r3 <- rel __got_end in FLASH */
+	add	$r3, $r3, $r9		/* r3 <- rel __got_end in RAM */
+	addi	$r2, $r2, #8		/* skipping first two entries */
+fix_got_loop:
+	lwi	$r0, [$r2]		/* r0 <- location in FLASH to fix up */
+	add	$r0, $r0, $r9		/* r0 <- location fix up to RAM */
+	swi.p	$r0, [$r2], #4		/* r0 <- store fix into .got in RAM */
+	blt	$r2, $r3, fix_got_loop
+
+clear_bss:
+	la	$r0, __bss_start	/* r0 <- rel __bss_start in FLASH */
+	add	$r0, $r0, $r9		/* r0 <- rel __bss_start in FLASH */
+	la	$r1, __bss_end__	/* r1 <- rel __bss_end in RAM */
+	add	$r1, $r1, $r9		/* r0 <- rel __bss_end in RAM */
+	li	$r2, 0x00000000		/* clear */
+
+clbss_l:
+	sw	$r2, [$r0]		/* clear loop... */
+	addi	$r0, $r0, #4
+	bne	$r0, $r1, clbss_l
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+	la	$r0, board_init_r
+	move	$lp, $r0		/* offset of board_init_r() */
+	add	$lp, $lp, $r9		/* real address of board_init_r() */
+	/* setup parameters for board_init_r */
+	move	$r0, $r5		/* gd_t */
+	move	$r1, $r6		/* dest_addr */
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__		/* NDS32 V0 ISA	*/
+	move	$r15, $lp		/* store function address into $r15 */
+#endif
+#endif
+
+	/* jump to it ... */
+	jr	$lp			/* jump to board_init_r() */
+
+/*
+ * Initialize CPU critical registers
+ *
+ *	1.	Setup control registers
+ *		1.1 Mask all IRQs
+ *		1.2 Flush cache and TLB
+ *		1.3 Disable MMU and cache
+ *	2.	Setup memory timing
+ */
+
+cpu_init_crit:
+
+	move	$r0, $lp		/* push	ra */
+
+	/* Disable Interrupts by clear GIE in $PSW reg */
+	setgie.d
+
+	/* Flush caches and TLB */
+	/* Invalidate caches */
+	bal	invalidate_icac
+	bal	invalidate_dcac
+
+	/* Flush TLB */
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+
+1:
+	! Disable MMU, Dcache
+	! Whitiger is MMU disabled when reset
+	! Disable the D$
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Set DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! write back the $CACHE_CTL reg
+	isb
+
+	move	$lp, $r0
+2:
+	ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+	la  $r6, lowlevel_init
+	la  $r7, load_lli + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+	la  $r6, turnoff_watchdog
+	la  $r7, turnoff_wtdog + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+/*
+ * Invalidate I$
+ */
+invalidate_icac:
+	mfsr	$t0, CR_ICAC_MEM		! read $cr1(I CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, ICAC_MEM_KBF_ISZ 	! Get the ISZ field
+	beqz	$p0, end_flush_icache		! if $p0=0, then no I CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of I$ block
+	addi	$t1, $p0, 2			! $t1= bit width of I cache line size(ISZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, ICAC_MEM_KBF_ISET	! get the ISET field
+	addi	$t2, $p1, 6			! $t2= bit width of ISET
+	andi	$p1, $t0, ICAC_MEM_KBF_IWAY	! get bitfield of Iway
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is I way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+ICAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1I_IX_INVAL
+	bnez	$p1, ICAC_LOOP
+end_flush_icache:
+	ret
+
+/*
+ * Invalidate D$
+ */
+invalidate_dcac:
+	mfsr	$t0, CR_DCAC_MEM		! read $cr2(D CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, DCAC_MEM_KBF_DSZ	! Get the DSZ field
+	beqz	$p0, end_flush_dcache		! if $p0=0, then no D CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of D$ block
+	addi	$t1, $p0, 2			! $t1= bit width of D cache line size(DSZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, DCAC_MEM_KBF_DSET	! get the DSET field
+	addi	$t2, $p1, 6			! $t2= bit width of DSET
+	andi	$p1, $t0, DCAC_MEM_KBF_DWAY	! get bitfield of D way
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is D way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+DCAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1D_IX_INVAL
+	bnez	$p1, DCAC_LOOP
+end_flush_dcache:
+	ret
+
+/*
+ * Interrupt handling
+ */
+
+/*
+ * exception handlers
+ */
+	.align	5
+
+.macro	SAVE_ALL
+	! FIXME: Other way to get PC?
+	! FIXME: Update according to the newest spec!!
+1:
+	la	 $r28, 1
+	push $r28
+	mfsr $r28, PSW			! $PSW
+	push $r28
+	mfsr $r28, EIT_EVA		! $ir1 $EVA
+	push $r28
+	mfsr $r28, EIT_ITYPE		! $ir2 $ITYPE
+	push $r28
+	mfsr $r28, EIT_MACH_ERR		! $ir3 Mach Error
+	push $r28
+	mfsr $r28, EIT_INTR_PSW		! $ir5 $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_IPSW	! $ir6 prev $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_EVA		! $ir7 prev $EVA
+	push $r28
+	mfsr $r28, EIT_PREV_ITYPE	! $ir8 prev $ITYPE
+	push $r28
+	mfsr $r28, EIT_INTR_PC		! $ir9 Interruption PC
+	push $r28
+	mfsr $r28, EIT_PREV_IPC		! $ir10 prev INTR_PC
+	push $r28
+	mfsr $r28, EIT_OVL_INTR_PC	! $ir11 Overflowed INTR_PC
+	push $r28
+	mfusr $r28, $d1.lo
+	push $r28
+	mfusr $r28, $d1.hi
+	push $r28
+	mfusr $r28, $d0.lo
+	push $r28
+	mfusr $r28, $d0.hi
+	push $r28
+	pushm $r0, $r30		! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
+	addi	$sp, $sp, -4	! make room for implicit pt_regs parameters
+.endm
+
+	.align	5
+tlb_fill:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 1				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_not_present:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 2				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_misc:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 3				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_vlpt_miss:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 4				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+cache_parity_error:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 5				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+debug:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 6				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+general_exception:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 7				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+internal_interrupt:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 8				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+
+/*
+ * void reset_cpu(ulong addr);
+ * $r0: input address to jump to
+ */
+.globl reset_cpu
+reset_cpu:
+/* No need to disable MMU because we never enable it */
+
+	bal	invalidate_icac
+	bal	invalidate_dcac
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+1:
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Clear the DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! Write back the $CACHE_CTL reg
+	br	$r0				! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..45221ee
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		arch/nds32/cpu/n1213/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		 *(.got.plt) *(.got)
+		__got_end = .;
+	}
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+}
-- 
1.7.3.5

[U-Boot] [PATCH v12 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Macpaul Lin]

SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
Add lowlevel_init.S and other periphal related code.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code clean up.
Changes for v5-v6:
  - Split watchdog.S from lowlevel_init.S.
  - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
   - reset_cpu was remove inside do_reset().
  - lowlevel_init.S
   - Change hard code value into MARCO definitions.
   - ftsmc010
     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
   - ftsdmc021
     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
     - Fix the default configuration value of FTSDMC and FTSMC controller.
   - Remove some ftpmu010 and flash probe code to C functions.
Changes for v7:
  - clean up.
Changes for v8-v9:
  - No change.
Changes for v10:
  - asm-offset.c: file added for ag101 use only.
  - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
  - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
  - cpu.c: remove unused cpu_init().
  - lowlevel_init.S
   - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
   - Replace routings by macros to made code much easier to understand.
   - Add debug LED support.
   - Add CONFIG_MEM_REMAP for those boards must do memort remapping.
Changes for v11:
  - arch/nds32/cpu/n1213/ag101/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - Simplify the commit log about the part of lowlevel_init.S.

 Makefile                                   |    3 +-
 arch/nds32/cpu/n1213/ag101/Makefile        |   70 ++++++++
 arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
 arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/timer.c         |  204 ++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
 arch/nds32/include/asm/arch-ag101/ag101.h  |   68 ++++++++
 8 files changed, 873 insertions(+), 1 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
 create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
 create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/Makefile b/Makefile
index d5a1f0a..d938fce 100644
--- a/Makefile
+++ b/Makefile
@@ -936,7 +936,8 @@ clean:
 	       $(obj)board/voiceblue/eeprom 				  \
 	       $(obj)u-boot.lds						  \
 	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]	  \
-	       $(obj)arch/blackfin/cpu/init.{lds,elf}
+	       $(obj)arch/blackfin/cpu/init.{lds,elf}			  \
+	       $(obj)arch/nds32/cpu/$(CPU)/$(SOC)/gen-asm-offsets.[chs]
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)lib/asm-offsets.s
 	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..02e36b7
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,70 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+$(OBJS): $(obj)gen-asm-offsets.h
+$(obj)gen-asm-offsets.h:	$(TOPDIR)/include/autoconf.mk.dep \
+	$(obj)gen-asm-offsets.s
+	@echo Generating $@ ; \
+	$(SRCTREE)/tools/scripts/make-asm-offsets $(obj)gen-asm-offsets.s $@
+
+$(obj)gen-asm-offsets.s:	$(TOPDIR)/include/autoconf.mk.dep \
+	$(src)asm-offsets.c
+	@mkdir -p $(obj)b
+	$(CC) -DDO_DEPS_ONLY \
+		$(CFLAGS) -o $@ $(src)asm-offsets.c -c -S
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
new file mode 100644
index 0000000..92ada8a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
@@ -0,0 +1,43 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..0ab666e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+	unsigned long i;
+#endif
+
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+	while (1)
+		;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr , addr + size);
+	icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..94308a8
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+#include "gen-asm-offsets.h"
+
+#include <asm/macro.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+
+#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro	wait_sdram
+	li	$r0, CONFIG_FTSDMC021_BASE
+1:
+	lwi	$r1, [$r0+FTSDMC021_CR2]
+	bnez	$r1, 1b
+.endm
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+
+	led	0x0
+	jal	mem_init
+
+	led	0x10
+	jal	remap
+
+	led	0x20
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	led	0x01
+	write32	SMC_BANK0_CR_A, SMC_BANK0_CR_D			! 0x10000052
+	write32	SMC_BANK0_TPR_A, SMC_BANK0_TPR_D		! 0x00151151
+
+	/*
+	 * config AHB Controller
+	 */
+	led	0x02
+	write32	AHBC_BSR6_A, AHBC_BSR6_D
+
+	/*
+	 * config PMU controller
+	 */
+	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
+	led	0x03
+	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
+
+	/*
+	 * config SDRAM controller
+	 */
+	led	0x04
+	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
+	led	0x05
+	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
+	led	0x06
+	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
+
+	led	0x07
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
+	wait_sdram
+
+	led	0x08
+	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
+	wait_sdram
+
+	led	0x09
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
+	wait_sdram
+
+	led	0x0a
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+	/*
+	 * Remapping
+	 */
+	led	0x1a
+	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
+
+	/* clear empty BSR registers */
+	led	0x1b
+	li	$r4, CONFIG_FTSDMC021_BASE
+	li	$r5, 0x0
+	swi	$r5, [$r4 + FTSDMC021_BANK1_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
+
+#ifdef CONFIG_MEM_REMAP
+	/*
+	 * Copy ROM code to SDRAM base for memory remap layout.
+	 * This is not the real relocation, the real relocation is the function
+	 * relocate_code() is start.S which supports the systems is memory
+	 * remapped or not.
+	 */
+	/*
+	 * Doing memory remap is essential for preparing some non-OS or RTOS
+	 * applications.
+	 *
+	 * This is also a must on ADP-AG101 board.
+	 * The reason is because the ROM/FLASH circuit on PCB board.
+	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	 * ROM/FLASH is used to boot.
+	 *
+	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	 * and the FLASH is connected to BANK1.
+	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	 * and the FLASH is connected to BANK0.
+	 * It will occur problem when doing flash probing if the flash is at
+	 * BANK0 (0x00000000) while memory remapping was skipped.
+	 *
+	 * Other board like ADP-AG101P may not enable this since there is only
+	 * a FLASH connected to bank0.
+	 */
+	led	0x11
+	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
+	li	$r5, 0x0
+	la	$r1, relo_base				/* get $pc or $lp */
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(_end)
+	ori	$r6, $r6, lo12(_end)
+	add	$r6, $r6, $r2
+1:
+	lwi.p	$r7, [$r5], #4
+	swi.p	$r7, [$r4], #4
+	blt	$r5, $r6, 1b
+
+	/* set remap bit */
+	/*
+	 * MEM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
+	 */
+	led	0x1c
+	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..b689eab
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl	turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+#endif
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE		0x90100000	/* AHB Controller */
+#define CONFIG_FTSMC020_BASE		0x90200000	/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE		0x90300000	/* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000	/* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000	/* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE		0x90600000	/* LCD Controller */
+#define CONFIG_RESERVED_01_BASE		0x90700000	/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000	/* Reserved */
+#define CONFIG_FTMAC100_BASE		0x90900000	/* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000	/* External USB host */
+#define CONFIG_USB_DEV_BASE		0x90B00000	/* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000	/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE		0x90D00000	/* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000	/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000	/* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000	/* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC	/* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE		0x98100000	/* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE	0x98300000	/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE		0x98400000	/* Counter/Timers */
+#define CONFIG_FTWDT010_BASE		0x98500000	/* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE		0x98600000	/* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE		0x98700000	/* GPIO */
+#define CONFIG_FTINTC010_BASE		0x98800000	/* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE		0x98A00000	/* I2C */
+#define CONFIG_RESERVED_04_BASE		0x98C00000	/* Reserved */
+#define CONFIG_FTCFC010_BASE		0x98D00000	/* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000	/* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE		0x99400000	/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE	0x99600000	/* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE	0x98200000	/* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000	/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE		0x98900000	/* IrDA */
+#define CONFIG_PMW_BASE			0x99100000	/* PWM - Pulse Width Modulator Controller */
+
+#endif	/* __AG101_H */
-- 
1.7.3.5

[U-Boot] [PATCH v12 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Mike Frysinger]

On Tuesday, September 06, 2011 22:27:15 Macpaul Lin wrote:
> --- a/Makefile
> +++ b/Makefile
> @@ -936,7 +936,8 @@ clean:
>  	       $(obj)board/voiceblue/eeprom 				  \
>  	       $(obj)u-boot.lds						  \
>  	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]	  \
> -	       $(obj)arch/blackfin/cpu/init.{lds,elf}
> +	       $(obj)arch/blackfin/cpu/init.{lds,elf}			  \
> +	       $(obj)arch/nds32/cpu/$(CPU)/$(SOC)/gen-asm-offsets.[chs]

i think the recently merged asm-offsets unification patch takes care of this 
for you, so you can drop this change

> --- /dev/null
> +++ b/arch/nds32/cpu/n1213/ag101/Makefile
> 
> +ifndef CONFIG_SKIP_LOWLEVEL_INIT
> +SOBJS	:= lowlevel_init.o
> +endif
> +
> +ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
> +SOBJS	+= watchdog.o
> +endif

the CONFIG_SKIP_xxx is a bit backwards.  seems like you should invert the 
logic, have your arch asm/config.h define them by default, and then have the 
boards which want to skip it do an #undef on them.

otherwise, you can unify this with:
SOBJS- :=
SOBJS-$(CONFIG_SKIP_LOWLEVEL_INIT) += lowlevel_init.o
SOBJS-$(CONFIG_SKIP_TRUNOFF_WATCHDOG) += watchdog.o

and then use $(SOBJS-) ...

> +$(OBJS): $(obj)gen-asm-offsets.h
> +$(obj)gen-asm-offsets.h:	$(TOPDIR)/include/autoconf.mk.dep \
> +	$(obj)gen-asm-offsets.s
> +	@echo Generating $@ ; \
> +	$(SRCTREE)/tools/scripts/make-asm-offsets $(obj)gen-asm-offsets.s $@
> +
> +$(obj)gen-asm-offsets.s:	$(TOPDIR)/include/autoconf.mk.dep \
> +	$(src)asm-offsets.c
> +	@mkdir -p $(obj)b
> +	$(CC) -DDO_DEPS_ONLY \
> +		$(CFLAGS) -o $@ $(src)asm-offsets.c -c -S

pretty sure the recent unification of this in the top level Makefile means you 
can drop this now
-mike
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[U-Boot] [PATCH v12 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[馬克泡]

Hi Mike,

2011/9/9 Mike Frysinger <vapier@gentoo.org>

> On Tuesday, September 06, 2011 22:27:15 Macpaul Lin wrote:
> > --- a/Makefile
> > +++ b/Makefile
>

Thanks for your reviewing.
I'll be on vacation for 1 week.
So I'll continue on this after the vacation is finished.

Thanks!

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v12 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[馬克泡]

Hi Mike,

> --- /dev/null
> > +++ b/arch/nds32/cpu/n1213/ag101/Makefile
> >
> > +ifndef CONFIG_SKIP_LOWLEVEL_INIT
> > +SOBJS        := lowlevel_init.o
> > +endif
> > +
> > +ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
> > +SOBJS        += watchdog.o
> > +endif
>
> the CONFIG_SKIP_xxx is a bit backwards.  seems like you should invert the
> logic, have your arch asm/config.h define them by default, and then have
> the
> boards which want to skip it do an #undef on them.
>

Our evaluation boards has an another boot loader loaded before u-boot is
loaded.
However, we do not suggest our customer use this boot loader on their
product if 2 different boot loaders was required.
Which means, only u-boot with lowlevel_init should be shipped on customers'
own platforms.
This kind of switchable definition is designed for helping customers to get
familiar with the
evaluation boards.

Hence CONFIG_SKIP_LOWLEVEL_INIT shouldn't be exist on customers' platforms.
Which means lowlevel_init should be executed by default.
This also means
"SOBJS-$(CONFIG_SKIP_LOWLEVEL_INIT) += lowlevel_init.o" won't work under
this case.
If we defined CONFIG_SKIP_LOWLEVEL_INIT as yes, then lowlevel_init.o will be
included
which is not the correct result.

The same situation is also applied on CONFIG_SKIP_TRUNOFF_WATCHDOG.


> otherwise, you can unify this with:
> SOBJS- :=
> SOBJS-$(CONFIG_SKIP_LOWLEVEL_INIT) += lowlevel_init.o
> SOBJS-$(CONFIG_SKIP_TRUNOFF_WATCHDOG) += watchdog.o
>
> and then use $(SOBJS-) ...
>
>
Hence I disagree with this. If SOBJS- could work with NOT (inverse) logic
for object files, I'll
glad to make this stuffs to get more simple.


>  > +$(OBJS): $(obj)gen-asm-offsets.h
> > +$(obj)gen-asm-offsets.h:     $(TOPDIR)/include/autoconf.mk.dep \
> > +     $(obj)gen-asm-offsets.s
> > +     @echo Generating $@ ; \
> > +     $(SRCTREE)/tools/scripts/make-asm-offsets $(obj)gen-asm-offsets.s
> $@
> > +
> > +$(obj)gen-asm-offsets.s:     $(TOPDIR)/include/autoconf.mk.dep \
> > +     $(src)asm-offsets.c
> > +     @mkdir -p $(obj)b
> > +     $(CC) -DDO_DEPS_ONLY \
> > +             $(CFLAGS) -o $@ $(src)asm-offsets.c -c -S
>
> pretty sure the recent unification of this in the top level Makefile means
> you
> can drop this now
> -mike
>

Other suggestion for changes are agreed and tested to be adopted in PATCH
v13
Thanks!


-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v13 1/9] nds32: add header files support for nds32

[Macpaul Lin]

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
   - Code cleanup and style formatting.
Changes for v5-v6:
   - This patch also updated the following changes against the
     change after master tree (v2010.12-rc1).
   - fix upper case definitions in cache.h
   - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
   - Add readsb, writesb functions into io.h.
Changes for v7:
   - clean up
   - volatile:
    - types.h
     - remove typedef volatile unsigned char  vuchar;
     - remove typedef volatile unsigned long  vulong;
     - remove typedef volatile unsigned short vushort;
    - u-boot.h: remove bd_info_ext bi_ext
    - bitops.h: add accessor function to bit operation with volatile var.
    - system.h: add system.h for local_irq operation with flag.
Changes for v8:
   - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
   - ptregs.h: removed
Changes for v9:
   - No change.
Changes for v10:
   - macro.h: add writel and setbf macros
   - u-boot-nds32.h:
    - Remove obsolete andesboot_* symbols for relocation.
    - Add _bss_*_offset symbols for relocation.
   - config.h: add manual relocation support as default.
Changes for v11:
   - unaligned.h: replace asm/unaligned.h with asm-generic/unaligned.h
Changes for v12:
   - remove no used memory.h
   - remove seldom used bi_env parameter
   - u-boot-nds32.h:
    - remove duplicate timer_init()
Changes for v13:
   - No change.

 arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
 arch/nds32/include/asm/byteorder.h    |   36 +++
 arch/nds32/include/asm/cache.h        |   54 +++++
 arch/nds32/include/asm/config.h       |   28 +++
 arch/nds32/include/asm/global_data.h  |   89 +++++++
 arch/nds32/include/asm/io.h           |  409 +++++++++++++++++++++++++++++++++
 arch/nds32/include/asm/mach-types.h   |   29 +++
 arch/nds32/include/asm/macro.h        |   96 ++++++++
 arch/nds32/include/asm/posix_types.h  |   84 +++++++
 arch/nds32/include/asm/processor.h    |   25 ++
 arch/nds32/include/asm/ptrace.h       |   88 +++++++
 arch/nds32/include/asm/string.h       |   57 +++++
 arch/nds32/include/asm/system.h       |   88 +++++++
 arch/nds32/include/asm/types.h        |   63 +++++
 arch/nds32/include/asm/u-boot-nds32.h |   51 ++++
 arch/nds32/include/asm/u-boot.h       |   60 +++++
 arch/nds32/include/asm/unaligned.h    |    1 +
 17 files changed, 1444 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/bitops.h
 create mode 100644 arch/nds32/include/asm/byteorder.h
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/config.h
 create mode 100644 arch/nds32/include/asm/global_data.h
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/include/asm/mach-types.h
 create mode 100644 arch/nds32/include/asm/macro.h
 create mode 100644 arch/nds32/include/asm/posix_types.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/system.h
 create mode 100644 arch/nds32/include/asm/types.h
 create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
 create mode 100644 arch/nds32/include/asm/u-boot.h
 create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..c56f04b
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void *addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+extern void clear_bit(int nr, volatile void *addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, volatile void *addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, volatile void *addr);
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ	6	/* I-cache line size */
+#define ICM_CFG_MSK_ISZ	(0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
+#define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..6f654d9
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_NEEDS_MANUAL_RELOC
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..665266b
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+
+	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t	ram_size;	/* RAM size */
+	unsigned long	mon_len;	/* monitor len */
+	unsigned long	irq_sp;		/* irq stack pointer */
+	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	unsigned long	tlb_addr;
+#endif
+
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT		0x00004	/* Silent mode			*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	*/
+#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r10")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..45b9c2e
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,409 @@
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+#define writeb(v, a)			__arch_putb(v, a)
+#define writew(v, a)			__arch_putw(v, a)
+#define writel(v, a)			__arch_putl(v, a)
+
+#define readb(a)			__arch_getb(a)
+#define readw(a)			__arch_getw(a)
+#define readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache)				\
+({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
+	_ret;								\
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"), 0)
+#define readw(addr)			(__readwrite_bug("readw"), 0)
+#define readl(addr)			(__readwrite_bug("readl"), 0)
+#define writeb(v, addr)			__readwrite_bug("writeb")
+#define writew(v, addr)			__readwrite_bug("writew")
+#define writel(v, addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101             0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101()	(machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101()	(0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/macro.h b/arch/nds32/include/asm/macro.h
new file mode 100644
index 0000000..acda060
--- /dev/null
+++ b/arch/nds32/include/asm/macro.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-nds32/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NDS_MACRO_H
+#define __ASM_NDS_MACRO_H
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to an "immediate address (address used by periphal)" only.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any NDS32 architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	li	$r4, addr
+	li	$r5, data
+	swi	$r5, [$r4]
+.endm
+
+.macro	write16, addr, data
+	li	$r4, addr
+	li	$r5, data
+	shi	$r5, [$r4]
+.endm
+
+.macro	write8, addr, data
+	li	$r4, addr
+	li	$r5, data
+	sbi	$r5, [$r4]
+.endm
+
+/*
+ * This macro read a value from a register, then do OR operation
+ * (set bit fields) to the value, and then store it back to the register.
+ * Note: Instruction 'ori' supports immediate value up to 15 bits.
+ */
+.macro	setbf32, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	li	$r6, data
+	or	$r5, $r5, $r6
+	swi	$r5, [$r4]
+.endm
+
+.macro	setbf15, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	ori	$r5, $r5, data
+	swi	$r5, [$r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any NDS32 architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	li	$r4, time
+1:
+	nop
+	addi	$r4, $r4, -1
+	bnez    $r4, 1b
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..4336083
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+	NDS32_REG ir0;
+	NDS32_REG ipsw;
+	NDS32_REG ipc;
+	NDS32_REG sp;
+	NDS32_REG orig_r0;
+	NDS32_REG pipsw;
+	NDS32_REG pipc;
+	NDS32_REG pp0;
+	NDS32_REG pp1;
+	NDS32_REG d0hi;
+	NDS32_REG d0lo;
+	NDS32_REG d1hi;
+	NDS32_REG d1lo;
+	NDS32_REG r[26];	/* r0 - r25 */
+	NDS32_REG fp;		/* r28 */
+	NDS32_REG gp;		/* r29 */
+	NDS32_REG lp;		/* r30 */
+	NDS32_REG fucop_ctl;
+	NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+	(((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..ae1918d
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong __bss_start;	/* BSS start relative to _start */
+extern ulong __bss_end__;	/* BSS end relative to _start */
+extern ulong _end;		/* end of image relative to _start */
+extern ulong _start;		/* start of image relative to _start */
+extern ulong _TEXT_BASE;	/* code start */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..fe4bfcb
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <environment.h>
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
-- 
1.7.3.5

[U-Boot] [PATCH v13 1/9] nds32: add header files support for nds32

[馬克泡]

HI all,

2011/9/21 Macpaul Lin <macpaul@andestech.com>

> Add generic header files support for nds32 architecture.
> Cache, ptregs, data type and other definitions are included.
>
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
>

Sorry, it is my fault.
I've forgot to fix only a single line from PATCH v12 to PATCH v13.
Hence please forget PATCH v13 away.
I'll fix it later and send PATCH v14 ASAP.
So you will see both PATCH v13 and PATCH v14 in your mailbox, please forget
PATCH v13.
Please review PATCH v14 only.

Thanks.

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v14 1/9] nds32: add header files support for nds32

[Macpaul Lin]

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
   - Code cleanup and style formatting.
Changes for v5-v6:
   - This patch also updated the following changes against the
     change after master tree (v2010.12-rc1).
   - fix upper case definitions in cache.h
   - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
   - Add readsb, writesb functions into io.h.
Changes for v7:
   - clean up
   - volatile:
    - types.h
     - remove typedef volatile unsigned char  vuchar;
     - remove typedef volatile unsigned long  vulong;
     - remove typedef volatile unsigned short vushort;
    - u-boot.h: remove bd_info_ext bi_ext
    - bitops.h: add accessor function to bit operation with volatile var.
    - system.h: add system.h for local_irq operation with flag.
Changes for v8:
   - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
   - ptregs.h: removed
Changes for v9:
   - No change.
Changes for v10:
   - macro.h: add writel and setbf macros
   - u-boot-nds32.h:
    - Remove obsolete andesboot_* symbols for relocation.
    - Add _bss_*_offset symbols for relocation.
   - config.h: add manual relocation support as default.
Changes for v11:
   - unaligned.h: replace asm/unaligned.h with asm-generic/unaligned.h
Changes for v12:
   - remove no used memory.h
   - remove seldom used bi_env parameter
   - u-boot-nds32.h:
    - remove duplicate timer_init()
Changes for v13-v14:
   - No change.

 arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
 arch/nds32/include/asm/byteorder.h    |   36 +++
 arch/nds32/include/asm/cache.h        |   54 +++++
 arch/nds32/include/asm/config.h       |   28 +++
 arch/nds32/include/asm/global_data.h  |   89 +++++++
 arch/nds32/include/asm/io.h           |  409 +++++++++++++++++++++++++++++++++
 arch/nds32/include/asm/mach-types.h   |   29 +++
 arch/nds32/include/asm/macro.h        |   96 ++++++++
 arch/nds32/include/asm/posix_types.h  |   84 +++++++
 arch/nds32/include/asm/processor.h    |   25 ++
 arch/nds32/include/asm/ptrace.h       |   88 +++++++
 arch/nds32/include/asm/string.h       |   57 +++++
 arch/nds32/include/asm/system.h       |   88 +++++++
 arch/nds32/include/asm/types.h        |   63 +++++
 arch/nds32/include/asm/u-boot-nds32.h |   51 ++++
 arch/nds32/include/asm/u-boot.h       |   60 +++++
 arch/nds32/include/asm/unaligned.h    |    1 +
 17 files changed, 1444 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/bitops.h
 create mode 100644 arch/nds32/include/asm/byteorder.h
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/config.h
 create mode 100644 arch/nds32/include/asm/global_data.h
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/include/asm/mach-types.h
 create mode 100644 arch/nds32/include/asm/macro.h
 create mode 100644 arch/nds32/include/asm/posix_types.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/system.h
 create mode 100644 arch/nds32/include/asm/types.h
 create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
 create mode 100644 arch/nds32/include/asm/u-boot.h
 create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..c56f04b
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void *addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+extern void clear_bit(int nr, volatile void *addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, volatile void *addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, volatile void *addr);
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ	6	/* I-cache line size */
+#define ICM_CFG_MSK_ISZ	(0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
+#define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..6f654d9
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_NEEDS_MANUAL_RELOC
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..665266b
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+
+	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t	ram_size;	/* RAM size */
+	unsigned long	mon_len;	/* monitor len */
+	unsigned long	irq_sp;		/* irq stack pointer */
+	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	unsigned long	tlb_addr;
+#endif
+
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT		0x00004	/* Silent mode			*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	*/
+#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r10")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..45b9c2e
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,409 @@
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+#define writeb(v, a)			__arch_putb(v, a)
+#define writew(v, a)			__arch_putw(v, a)
+#define writel(v, a)			__arch_putl(v, a)
+
+#define readb(a)			__arch_getb(a)
+#define readw(a)			__arch_getw(a)
+#define readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache)				\
+({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
+	_ret;								\
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"), 0)
+#define readw(addr)			(__readwrite_bug("readw"), 0)
+#define readl(addr)			(__readwrite_bug("readl"), 0)
+#define writeb(v, addr)			__readwrite_bug("writeb")
+#define writew(v, addr)			__readwrite_bug("writew")
+#define writel(v, addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101             0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101()	(machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101()	(0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/macro.h b/arch/nds32/include/asm/macro.h
new file mode 100644
index 0000000..acda060
--- /dev/null
+++ b/arch/nds32/include/asm/macro.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-nds32/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NDS_MACRO_H
+#define __ASM_NDS_MACRO_H
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to an "immediate address (address used by periphal)" only.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any NDS32 architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	li	$r4, addr
+	li	$r5, data
+	swi	$r5, [$r4]
+.endm
+
+.macro	write16, addr, data
+	li	$r4, addr
+	li	$r5, data
+	shi	$r5, [$r4]
+.endm
+
+.macro	write8, addr, data
+	li	$r4, addr
+	li	$r5, data
+	sbi	$r5, [$r4]
+.endm
+
+/*
+ * This macro read a value from a register, then do OR operation
+ * (set bit fields) to the value, and then store it back to the register.
+ * Note: Instruction 'ori' supports immediate value up to 15 bits.
+ */
+.macro	setbf32, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	li	$r6, data
+	or	$r5, $r5, $r6
+	swi	$r5, [$r4]
+.endm
+
+.macro	setbf15, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	ori	$r5, $r5, data
+	swi	$r5, [$r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any NDS32 architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	li	$r4, time
+1:
+	nop
+	addi	$r4, $r4, -1
+	bnez    $r4, 1b
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..4336083
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+	NDS32_REG ir0;
+	NDS32_REG ipsw;
+	NDS32_REG ipc;
+	NDS32_REG sp;
+	NDS32_REG orig_r0;
+	NDS32_REG pipsw;
+	NDS32_REG pipc;
+	NDS32_REG pp0;
+	NDS32_REG pp1;
+	NDS32_REG d0hi;
+	NDS32_REG d0lo;
+	NDS32_REG d1hi;
+	NDS32_REG d1lo;
+	NDS32_REG r[26];	/* r0 - r25 */
+	NDS32_REG fp;		/* r28 */
+	NDS32_REG gp;		/* r29 */
+	NDS32_REG lp;		/* r30 */
+	NDS32_REG fucop_ctl;
+	NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+	(((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..ae1918d
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong __bss_start;	/* BSS start relative to _start */
+extern ulong __bss_end__;	/* BSS end relative to _start */
+extern ulong _end;		/* end of image relative to _start */
+extern ulong _start;		/* start of image relative to _start */
+extern ulong _TEXT_BASE;	/* code start */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..fe4bfcb
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <environment.h>
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
-- 
1.7.3.5

[U-Boot] [PATCH v14 1/9] nds32: add header files support for nds32

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1316574638-20460-1-git-send-email-macpaul@andestech.com> you wrote:
> Add generic header files support for nds32 architecture.
> Cache, ptregs, data type and other definitions are included.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v4:
>    - Code cleanup and style formatting.
> Changes for v5-v6:
>    - This patch also updated the following changes against the
>      change after master tree (v2010.12-rc1).
>    - fix upper case definitions in cache.h
>    - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
>    - Add readsb, writesb functions into io.h.
> Changes for v7:
>    - clean up
>    - volatile:
>     - types.h
>      - remove typedef volatile unsigned char  vuchar;
>      - remove typedef volatile unsigned long  vulong;
>      - remove typedef volatile unsigned short vushort;
>     - u-boot.h: remove bd_info_ext bi_ext
>     - bitops.h: add accessor function to bit operation with volatile var.
>     - system.h: add system.h for local_irq operation with flag.
> Changes for v8:
>    - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
>    - ptregs.h: removed
> Changes for v9:
>    - No change.
> Changes for v10:
>    - macro.h: add writel and setbf macros
>    - u-boot-nds32.h:
>     - Remove obsolete andesboot_* symbols for relocation.
>     - Add _bss_*_offset symbols for relocation.
>    - config.h: add manual relocation support as default.
> Changes for v11:
>    - unaligned.h: replace asm/unaligned.h with asm-generic/unaligned.h
> Changes for v12:
>    - remove no used memory.h
>    - remove seldom used bi_env parameter
>    - u-boot-nds32.h:
>     - remove duplicate timer_init()
> Changes for v13-v14:
>    - No change.
> 
>  arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
>  arch/nds32/include/asm/byteorder.h    |   36 +++
>  arch/nds32/include/asm/cache.h        |   54 +++++
>  arch/nds32/include/asm/config.h       |   28 +++
>  arch/nds32/include/asm/global_data.h  |   89 +++++++
>  arch/nds32/include/asm/io.h           |  409 +++++++++++++++++++++++++++++++++
>  arch/nds32/include/asm/mach-types.h   |   29 +++
>  arch/nds32/include/asm/macro.h        |   96 ++++++++
>  arch/nds32/include/asm/posix_types.h  |   84 +++++++
>  arch/nds32/include/asm/processor.h    |   25 ++
>  arch/nds32/include/asm/ptrace.h       |   88 +++++++
>  arch/nds32/include/asm/string.h       |   57 +++++
>  arch/nds32/include/asm/system.h       |   88 +++++++
>  arch/nds32/include/asm/types.h        |   63 +++++
>  arch/nds32/include/asm/u-boot-nds32.h |   51 ++++
>  arch/nds32/include/asm/u-boot.h       |   60 +++++
>  arch/nds32/include/asm/unaligned.h    |    1 +
>  17 files changed, 1444 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/include/asm/bitops.h
>  create mode 100644 arch/nds32/include/asm/byteorder.h
>  create mode 100644 arch/nds32/include/asm/cache.h
>  create mode 100644 arch/nds32/include/asm/config.h
>  create mode 100644 arch/nds32/include/asm/global_data.h
>  create mode 100644 arch/nds32/include/asm/io.h
>  create mode 100644 arch/nds32/include/asm/mach-types.h
>  create mode 100644 arch/nds32/include/asm/macro.h
>  create mode 100644 arch/nds32/include/asm/posix_types.h
>  create mode 100644 arch/nds32/include/asm/processor.h
>  create mode 100644 arch/nds32/include/asm/ptrace.h
>  create mode 100644 arch/nds32/include/asm/string.h
>  create mode 100644 arch/nds32/include/asm/system.h
>  create mode 100644 arch/nds32/include/asm/types.h
>  create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
>  create mode 100644 arch/nds32/include/asm/u-boot.h
>  create mode 100644 arch/nds32/include/asm/unaligned.h

Checkpatch says:

total: 8 errors, 58 warnings, 1444 lines checked

Please clean up and resubmit.  Thanks.

[U-Boot] [PATCH v14 2/9] nds32: add NDS32 support into common header file

[Macpaul Lin]

Add NDS32 support into common header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v7:
  - No change
Changes for v8:
  - Fix the patch according to dependency of x86's Fix
Changes for v9-v14:
  - No change

 include/common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index d244bd4..8a90354 100644
--- a/include/common.h
+++ b/include/common.h
@@ -302,6 +302,10 @@ int	setenv	     (const char *, const char *);
 #ifdef CONFIG_X86		/* x86 version to be fixed! */
 # include <asm/u-boot-x86.h>
 #endif /* CONFIG_X86 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h>	/* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
-- 
1.7.3.5

[U-Boot] [PATCH v14 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Macpaul Lin]

Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes v1 to v6:
  - Style clean up and reorganize code
Changes v7-v9:
  - No Change.
Changes v10:
  - start.S of N1213 CPU has been rewrote for relocation support.
  - u-boot.lds:
   - Add got and *(.got.plt) section for support GCC 4 toolchain
   - Modified for relocation implementation.
Changes v11:
  - arch/nds32/cpu/n1213/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes v12:
  - u-boot.lds
   - Remove the 0x00000000 base address in linker script.
     The base address of the binary will be determined by CONFIG_SYS_TEXT_BASE
  - Remove the CPU features in commit log and add to README in later patches.
Changes v13-v14:
  - No change.

 arch/nds32/cpu/n1213/Makefile   |   50 ++++
 arch/nds32/cpu/n1213/start.S    |  501 +++++++++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/u-boot.lds |   70 ++++++
 3 files changed, 621 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/Makefile
 create mode 100644 arch/nds32/cpu/n1213/start.S
 create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..da15574
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..6fe30cc
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,501 @@
+/*
+ *	Andesboot - Startup Code for Whitiger core
+ *
+ *	Copyright (C) 2006	Andes Technology Corporation
+ *	Copyright (C) 2006	Shawn Lin <nobuhiro@andestech.com>
+ *	Copyright (C) 2011	Macpaul <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <asm/macro.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC		2UL
+#define DIS_DCAC		~ENA_DCAC
+#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
+#define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
+#define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY	(0x07<<3)	! D cache ways
+#define DCAC_MEM_KBF_DSZ	(0x07<<6)	! D cache line size
+
+#define PSW			$ir0
+#define EIT_INTR_PSW		$ir1		! interruption $PSW
+#define EIT_PREV_IPSW		$ir2		! previous $IPSW
+#define EIT_IVB			$ir3		! intr vector base address
+#define EIT_EVA			$ir4		! MMU related Exception Virtual Address register
+#define EIT_PREV_EVA		$ir5		! previous $eva
+#define EIT_ITYPE		$ir6		! interruption type
+#define EIT_PREV_ITYPE		$ir7		! prev intr type
+#define EIT_MACH_ERR		$ir8		! machine error log
+#define EIT_INTR_PC		$ir9		! Interruption PC
+#define EIT_PREV_IPC		$ir10		! previous $IPC
+#define EIT_OVL_INTR_PC		$ir11		! overflow interruption PC
+#define EIT_PREV_P0		$ir12		! prev $P0
+#define EIT_PREV_P1		$ir13		! prev $p1
+#define CR_ICAC_MEM		$cr1		! I-cache/memory config reg
+#define CR_DCAC_MEM		$cr2		! D-cache/memory config reg
+#define MR_CAC_CTL		$mr8
+
+.globl _start
+
+_start:	b	reset
+	b	tlb_fill
+	b	tlb_not_present
+	b	tlb_misc
+	b	tlb_vlpt_miss
+	b	cache_parity_error
+	b	debug
+	b	general_exception
+	b	internal_interrupt		! H0I
+	b	internal_interrupt		! H1I
+	b	internal_interrupt		! H2I
+	b	internal_interrupt		! H3I
+	b	internal_interrupt		! H4I
+	b	internal_interrupt		! H5I
+
+	.balign 16
+
+/*
+ * Andesboot Startup Code (reset vector)
+ *
+ *	1.	bootstrap
+ *		1.1 reset - start of u-boot
+ *		1.2 to superuser mode - as is when reset
+ *		1.4 Do lowlevel_init
+ *			- (this will jump out to lowlevel_init.S in SoC)
+ *			- (lowlevel_init)
+ *		1.3 Turn off watchdog timer
+ *			- (this will jump out to watchdog.S in SoC)
+ *			- (turnoff_watchdog)
+ *	2.	Do critical init when reboot (not from mem)
+ *	3.	Relocate andesboot to ram
+ *	4.	Setup stack
+ *	5.	Jump to second stage (board_init_r)
+ */
+
+/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word 0x0badc0de
+
+/*
+ * The bootstrap code of nds32 core
+ */
+
+reset:
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	jal	load_lowlevel_init
+	jral	$p0
+#endif
+
+/*
+ * Set the N1213 (Whitiger) core to superuser mode
+ * According to spec, it is already when reset
+ */
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+	jal	load_turnoff_watchdog
+	jral	$p0
+#endif
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+	bal	cpu_init_crit		! Do CPU critical regs init
+#endif
+
+/*
+ * Set stackpointer in internal RAM to call board_init_f
+ * $sp must be 8-byte alignment for ABI compliance.
+ */
+call_board_init_f:
+	li	$sp, CONFIG_SYS_INIT_SP_ADDR
+	li	$r0, 0x00000000
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__
+/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
+	la	$r15, board_init_f	! store function address into $r15
+#endif
+#endif
+	j	board_init_f		! jump to board_init_f() in lib/board.c
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl	relocate_code
+relocate_code:
+	move	$r4, $r0		/* save addr_sp */
+	move	$r5, $r1		/* save addr of gd */
+	move	$r6, $r2		/* save addr of destination */
+
+/* Set up the stack */
+stack_setup:
+	move	$sp, $r4
+
+	la	$r0, _start
+
+	beq	$r0, $r6, clear_bss	/* skip relocation */
+
+	move	$r1, $r6		/* r1 <- scratch for copy_loop */
+	la	$r3, __bss_start
+	sub	$r3, $r3, $r0		/* r3 <- __bss_start_ofs */
+	add	$r2, $r0, $r3		/* r2 <- source end address */
+
+copy_loop:
+	lwi.p	$r7, [$r0], #4
+	swi.p	$r7, [$r1], #4
+	blt	$r0, $r2, copy_loop
+
+/*
+ * fix relocations related issues
+ */
+fix_relocations:
+	l.w	$r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	$r9, $r6, $r0		/* r9 <- relocation offset */
+
+fix_got:
+/*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+	la	$r2, __got_start	/* r2 <- rel __got_start in FLASH */
+	add	$r2, $r2, $r9		/* r2 <- rel __got_start in RAM */
+	la	$r3, __got_end		/* r3 <- rel __got_end in FLASH */
+	add	$r3, $r3, $r9		/* r3 <- rel __got_end in RAM */
+	addi	$r2, $r2, #8		/* skipping first two entries */
+fix_got_loop:
+	lwi	$r0, [$r2]		/* r0 <- location in FLASH to fix up */
+	add	$r0, $r0, $r9		/* r0 <- location fix up to RAM */
+	swi.p	$r0, [$r2], #4		/* r0 <- store fix into .got in RAM */
+	blt	$r2, $r3, fix_got_loop
+
+clear_bss:
+	la	$r0, __bss_start	/* r0 <- rel __bss_start in FLASH */
+	add	$r0, $r0, $r9		/* r0 <- rel __bss_start in FLASH */
+	la	$r1, __bss_end__	/* r1 <- rel __bss_end in RAM */
+	add	$r1, $r1, $r9		/* r0 <- rel __bss_end in RAM */
+	li	$r2, 0x00000000		/* clear */
+
+clbss_l:
+	sw	$r2, [$r0]		/* clear loop... */
+	addi	$r0, $r0, #4
+	bne	$r0, $r1, clbss_l
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+	la	$r0, board_init_r
+	move	$lp, $r0		/* offset of board_init_r() */
+	add	$lp, $lp, $r9		/* real address of board_init_r() */
+	/* setup parameters for board_init_r */
+	move	$r0, $r5		/* gd_t */
+	move	$r1, $r6		/* dest_addr */
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__		/* NDS32 V0 ISA	*/
+	move	$r15, $lp		/* store function address into $r15 */
+#endif
+#endif
+
+	/* jump to it ... */
+	jr	$lp			/* jump to board_init_r() */
+
+/*
+ * Initialize CPU critical registers
+ *
+ *	1.	Setup control registers
+ *		1.1 Mask all IRQs
+ *		1.2 Flush cache and TLB
+ *		1.3 Disable MMU and cache
+ *	2.	Setup memory timing
+ */
+
+cpu_init_crit:
+
+	move	$r0, $lp		/* push	ra */
+
+	/* Disable Interrupts by clear GIE in $PSW reg */
+	setgie.d
+
+	/* Flush caches and TLB */
+	/* Invalidate caches */
+	bal	invalidate_icac
+	bal	invalidate_dcac
+
+	/* Flush TLB */
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+
+1:
+	! Disable MMU, Dcache
+	! Whitiger is MMU disabled when reset
+	! Disable the D$
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Set DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! write back the $CACHE_CTL reg
+	isb
+
+	move	$lp, $r0
+2:
+	ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+	la  $r6, lowlevel_init
+	la  $r7, load_lli + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+	la  $r6, turnoff_watchdog
+	la  $r7, turnoff_wtdog + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+/*
+ * Invalidate I$
+ */
+invalidate_icac:
+	mfsr	$t0, CR_ICAC_MEM		! read $cr1(I CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, ICAC_MEM_KBF_ISZ 	! Get the ISZ field
+	beqz	$p0, end_flush_icache		! if $p0=0, then no I CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of I$ block
+	addi	$t1, $p0, 2			! $t1= bit width of I cache line size(ISZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, ICAC_MEM_KBF_ISET	! get the ISET field
+	addi	$t2, $p1, 6			! $t2= bit width of ISET
+	andi	$p1, $t0, ICAC_MEM_KBF_IWAY	! get bitfield of Iway
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is I way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+ICAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1I_IX_INVAL
+	bnez	$p1, ICAC_LOOP
+end_flush_icache:
+	ret
+
+/*
+ * Invalidate D$
+ */
+invalidate_dcac:
+	mfsr	$t0, CR_DCAC_MEM		! read $cr2(D CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, DCAC_MEM_KBF_DSZ	! Get the DSZ field
+	beqz	$p0, end_flush_dcache		! if $p0=0, then no D CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of D$ block
+	addi	$t1, $p0, 2			! $t1= bit width of D cache line size(DSZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, DCAC_MEM_KBF_DSET	! get the DSET field
+	addi	$t2, $p1, 6			! $t2= bit width of DSET
+	andi	$p1, $t0, DCAC_MEM_KBF_DWAY	! get bitfield of D way
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is D way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+DCAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1D_IX_INVAL
+	bnez	$p1, DCAC_LOOP
+end_flush_dcache:
+	ret
+
+/*
+ * Interrupt handling
+ */
+
+/*
+ * exception handlers
+ */
+	.align	5
+
+.macro	SAVE_ALL
+	! FIXME: Other way to get PC?
+	! FIXME: Update according to the newest spec!!
+1:
+	la	 $r28, 1
+	push $r28
+	mfsr $r28, PSW			! $PSW
+	push $r28
+	mfsr $r28, EIT_EVA		! $ir1 $EVA
+	push $r28
+	mfsr $r28, EIT_ITYPE		! $ir2 $ITYPE
+	push $r28
+	mfsr $r28, EIT_MACH_ERR		! $ir3 Mach Error
+	push $r28
+	mfsr $r28, EIT_INTR_PSW		! $ir5 $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_IPSW	! $ir6 prev $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_EVA		! $ir7 prev $EVA
+	push $r28
+	mfsr $r28, EIT_PREV_ITYPE	! $ir8 prev $ITYPE
+	push $r28
+	mfsr $r28, EIT_INTR_PC		! $ir9 Interruption PC
+	push $r28
+	mfsr $r28, EIT_PREV_IPC		! $ir10 prev INTR_PC
+	push $r28
+	mfsr $r28, EIT_OVL_INTR_PC	! $ir11 Overflowed INTR_PC
+	push $r28
+	mfusr $r28, $d1.lo
+	push $r28
+	mfusr $r28, $d1.hi
+	push $r28
+	mfusr $r28, $d0.lo
+	push $r28
+	mfusr $r28, $d0.hi
+	push $r28
+	pushm $r0, $r30		! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
+	addi	$sp, $sp, -4	! make room for implicit pt_regs parameters
+.endm
+
+	.align	5
+tlb_fill:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 1				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_not_present:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 2				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_misc:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 3				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_vlpt_miss:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 4				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+cache_parity_error:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 5				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+debug:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 6				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+general_exception:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 7				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+internal_interrupt:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 8				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+
+/*
+ * void reset_cpu(ulong addr);
+ * $r0: input address to jump to
+ */
+.globl reset_cpu
+reset_cpu:
+/* No need to disable MMU because we never enable it */
+
+	bal	invalidate_icac
+	bal	invalidate_dcac
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+1:
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Clear the DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! Write back the $CACHE_CTL reg
+	br	$r0				! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..45221ee
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		arch/nds32/cpu/n1213/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		 *(.got.plt) *(.got)
+		__got_end = .;
+	}
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+}
-- 
1.7.3.5

[U-Boot] [PATCH v14 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1316574638-20460-3-git-send-email-macpaul@andestech.com> you wrote:
> Add N1213 cpu core (N12 Core family) support for NDS32 arch.
> This patch includes start.S for the initialize procedure of N1213.
> 
> Start procedure:
>  start.S will start up the N1213 CPU core at first,
>  then jump to SoC dependent "lowlevel_init.S" and
>  "watchdog.S" to configure peripheral devices.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes v1 to v6:
>   - Style clean up and reorganize code
> Changes v7-v9:
>   - No Change.
> Changes v10:
>   - start.S of N1213 CPU has been rewrote for relocation support.
>   - u-boot.lds:
>    - Add got and *(.got.plt) section for support GCC 4 toolchain
>    - Modified for relocation implementation.
> Changes v11:
>   - arch/nds32/cpu/n1213/Makefile
>    - replace $(AR) $(call cmd_link_o_target,...)
> Changes v12:
>   - u-boot.lds
>    - Remove the 0x00000000 base address in linker script.
>      The base address of the binary will be determined by CONFIG_SYS_TEXT_BASE
>   - Remove the CPU features in commit log and add to README in later patches.
> Changes v13-v14:
>   - No change.
> 
>  arch/nds32/cpu/n1213/Makefile   |   50 ++++
>  arch/nds32/cpu/n1213/start.S    |  501 +++++++++++++++++++++++++++++++++++++++
>  arch/nds32/cpu/n1213/u-boot.lds |   70 ++++++
>  3 files changed, 621 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/cpu/n1213/Makefile
>  create mode 100644 arch/nds32/cpu/n1213/start.S
>  create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

Checkpatch says:

total: 0 errors, 7 warnings, 621 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Niklaus Wirth has lamented that, whereas Europeans pronounce his name
correctly  (Ni-klows  Virt),  Americans  invariably  mangle  it  into
(Nick-les  Worth).  Which  is to say that Europeans call him by name,
but Americans call him by value.

[U-Boot] [PATCH v14 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Macpaul Lin]

SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
Add lowlevel_init.S and other periphal related code.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code clean up.
Changes for v5-v6:
  - Split watchdog.S from lowlevel_init.S.
  - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
   - reset_cpu was remove inside do_reset().
  - lowlevel_init.S
   - Change hard code value into MARCO definitions.
   - ftsmc010
     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
   - ftsdmc021
     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
     - Fix the default configuration value of FTSDMC and FTSMC controller.
   - Remove some ftpmu010 and flash probe code to C functions.
Changes for v7:
  - clean up.
Changes for v8-v9:
  - No change.
Changes for v10:
  - asm-offset.c: file added for ag101 use only.
  - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
  - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
  - cpu.c: remove unused cpu_init().
  - lowlevel_init.S
   - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
   - Replace routings by macros to made code much easier to understand.
   - Add debug LED support.
   - Add CONFIG_MEM_REMAP for those boards must do memort remapping.
Changes for v11:
  - arch/nds32/cpu/n1213/ag101/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - Simplify the commit log about the part of lowlevel_init.S.
Changes for v13:
  - arch/nds32/cpu/n1213/ag101/Makefile: remove unused gen-asm-offset.
  - Makefile: remove unused gen-asm-offset because merged asm-offsets.
Changes for v14:
  - lowlevel_init.S: fix include path of <generated/asm-offsets.h>

 arch/nds32/cpu/n1213/ag101/Makefile        |   58 +++++++
 arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
 arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/timer.c         |  204 ++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
 arch/nds32/include/asm/arch-ag101/ag101.h  |   68 ++++++++
 7 files changed, 859 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
 create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
 create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..8716c4e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
new file mode 100644
index 0000000..92ada8a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
@@ -0,0 +1,43 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..0ab666e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+	unsigned long i;
+#endif
+
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+	while (1)
+		;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr , addr + size);
+	icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..e349118
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#include <asm/macro.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+
+#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro	wait_sdram
+	li	$r0, CONFIG_FTSDMC021_BASE
+1:
+	lwi	$r1, [$r0+FTSDMC021_CR2]
+	bnez	$r1, 1b
+.endm
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+
+	led	0x0
+	jal	mem_init
+
+	led	0x10
+	jal	remap
+
+	led	0x20
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	led	0x01
+	write32	SMC_BANK0_CR_A, SMC_BANK0_CR_D			! 0x10000052
+	write32	SMC_BANK0_TPR_A, SMC_BANK0_TPR_D		! 0x00151151
+
+	/*
+	 * config AHB Controller
+	 */
+	led	0x02
+	write32	AHBC_BSR6_A, AHBC_BSR6_D
+
+	/*
+	 * config PMU controller
+	 */
+	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
+	led	0x03
+	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
+
+	/*
+	 * config SDRAM controller
+	 */
+	led	0x04
+	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
+	led	0x05
+	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
+	led	0x06
+	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
+
+	led	0x07
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
+	wait_sdram
+
+	led	0x08
+	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
+	wait_sdram
+
+	led	0x09
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
+	wait_sdram
+
+	led	0x0a
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+	/*
+	 * Remapping
+	 */
+	led	0x1a
+	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
+
+	/* clear empty BSR registers */
+	led	0x1b
+	li	$r4, CONFIG_FTSDMC021_BASE
+	li	$r5, 0x0
+	swi	$r5, [$r4 + FTSDMC021_BANK1_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
+
+#ifdef CONFIG_MEM_REMAP
+	/*
+	 * Copy ROM code to SDRAM base for memory remap layout.
+	 * This is not the real relocation, the real relocation is the function
+	 * relocate_code() is start.S which supports the systems is memory
+	 * remapped or not.
+	 */
+	/*
+	 * Doing memory remap is essential for preparing some non-OS or RTOS
+	 * applications.
+	 *
+	 * This is also a must on ADP-AG101 board.
+	 * The reason is because the ROM/FLASH circuit on PCB board.
+	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	 * ROM/FLASH is used to boot.
+	 *
+	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	 * and the FLASH is connected to BANK1.
+	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	 * and the FLASH is connected to BANK0.
+	 * It will occur problem when doing flash probing if the flash is at
+	 * BANK0 (0x00000000) while memory remapping was skipped.
+	 *
+	 * Other board like ADP-AG101P may not enable this since there is only
+	 * a FLASH connected to bank0.
+	 */
+	led	0x11
+	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
+	li	$r5, 0x0
+	la	$r1, relo_base				/* get $pc or $lp */
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(_end)
+	ori	$r6, $r6, lo12(_end)
+	add	$r6, $r6, $r2
+1:
+	lwi.p	$r7, [$r5], #4
+	swi.p	$r7, [$r4], #4
+	blt	$r5, $r6, 1b
+
+	/* set remap bit */
+	/*
+	 * MEM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
+	 */
+	led	0x1c
+	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..b689eab
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl	turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+#endif
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE		0x90100000	/* AHB Controller */
+#define CONFIG_FTSMC020_BASE		0x90200000	/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE		0x90300000	/* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000	/* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000	/* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE		0x90600000	/* LCD Controller */
+#define CONFIG_RESERVED_01_BASE		0x90700000	/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000	/* Reserved */
+#define CONFIG_FTMAC100_BASE		0x90900000	/* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000	/* External USB host */
+#define CONFIG_USB_DEV_BASE		0x90B00000	/* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000	/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE		0x90D00000	/* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000	/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000	/* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000	/* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC	/* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE		0x98100000	/* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE	0x98300000	/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE		0x98400000	/* Counter/Timers */
+#define CONFIG_FTWDT010_BASE		0x98500000	/* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE		0x98600000	/* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE		0x98700000	/* GPIO */
+#define CONFIG_FTINTC010_BASE		0x98800000	/* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE		0x98A00000	/* I2C */
+#define CONFIG_RESERVED_04_BASE		0x98C00000	/* Reserved */
+#define CONFIG_FTCFC010_BASE		0x98D00000	/* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000	/* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE		0x99400000	/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE	0x99600000	/* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE	0x98200000	/* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000	/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE		0x98900000	/* IrDA */
+#define CONFIG_PMW_BASE			0x99100000	/* PWM - Pulse Width Modulator Controller */
+
+#endif	/* __AG101_H */
-- 
1.7.3.5

[U-Boot] [PATCH v14 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1316574638-20460-4-git-send-email-macpaul@andestech.com> you wrote:
> SoC ag101 is the first chip using NDS32 N1213 cpu core.
> Add header file of device offset support for SoC ag101.
> Add main function of SoC ag101 based on NDS32 n1213 core.
> Add lowlevel_init.S and other periphal related code.
> 
> This version of lowlevel_init.S also replace hardcode value
> by MARCO defines from the GPL version andesboot for better
> code quality.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v4:
>   - Code clean up.
> Changes for v5-v6:
>   - Split watchdog.S from lowlevel_init.S.
>   - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
>    - reset_cpu was remove inside do_reset().
>   - lowlevel_init.S
>    - Change hard code value into MARCO definitions.
>    - ftsmc010
>      - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
>    - ftsdmc021
>      - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
>      - Fix the default configuration value of FTSDMC and FTSMC controller.
>    - Remove some ftpmu010 and flash probe code to C functions.
> Changes for v7:
>   - clean up.
> Changes for v8-v9:
>   - No change.
> Changes for v10:
>   - asm-offset.c: file added for ag101 use only.
>   - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
>   - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
>   - cpu.c: remove unused cpu_init().
>   - lowlevel_init.S
>    - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
>    - Replace routings by macros to made code much easier to understand.
>    - Add debug LED support.
>    - Add CONFIG_MEM_REMAP for those boards must do memort remapping.
> Changes for v11:
>   - arch/nds32/cpu/n1213/ag101/Makefile
>    - replace $(AR) $(call cmd_link_o_target,...)
> Changes for v12:
>   - Simplify the commit log about the part of lowlevel_init.S.
> Changes for v13:
>   - arch/nds32/cpu/n1213/ag101/Makefile: remove unused gen-asm-offset.
>   - Makefile: remove unused gen-asm-offset because merged asm-offsets.
> Changes for v14:
>   - lowlevel_init.S: fix include path of <generated/asm-offsets.h>
> 
>  arch/nds32/cpu/n1213/ag101/Makefile        |   58 +++++++
>  arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
>  arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
>  arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
>  arch/nds32/cpu/n1213/ag101/timer.c         |  204 ++++++++++++++++++++++++
>  arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
>  arch/nds32/include/asm/arch-ag101/ag101.h  |   68 ++++++++
>  7 files changed, 859 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
>  create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
>  create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
>  create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
>  create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
>  create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
>  create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

Checkpatch says:

total: 0 errors, 15 warnings, 859 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Real programmers can write assembly code in any language.   :-)
                      - Larry Wall in  <8571@jpl-devvax.JPL.NASA.GOV>

[U-Boot] [PATCH v14 5/9] nds32/lib: add generic funcs in NDS32 lib

[Macpaul Lin]

Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up and formatting style.
Changes for v5-v6:
  - board.c
   - Do some clean up and add code
   - Remove display banner which hasn't support.
   - Add ftpmu010 related power management unit code.
   - Remove useless LED related code.
   - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
   - Remove CONFIG_SOFT_I2C which hasn't been support.
   - Remove CONFIG_FSL_ESDHC which hasn't been support.
   - clean up.
Changes for v7:
  - clean up.
  - move single file patch arch/nds32/config.mk to this commit.
  - interrupts.c refine origin interrupt enable and disable.
Changes for v8:
  - interrups.c: fix up for new ptraces.h.
Changes for v9:
  - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
Changes for v10:
  - config.mk:
   - add -fpie flag.
   - replace -ffixed-8 to -ffixed-10.
   - add -mrelax and --gc-sections to LDFLAG
  - board.c:
   - fix lib/board.c for relocation.
   - fix dram init for relocation.
Changes for v11:
  - arch/nds32/lib/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - config.mk
   - remove $(SRCTREE)/$(CPUDIR)/u-boot.lds
  - board.c:
   - remove obsolelte version_string.
   - remove declaration "extern __bss_end" which is not need.
   - replace sizeof(gd_t) and sizeof(bd_t) to
     GENERATED_GBL_DATA_SIZE and GENERATED_BD_INFO_SIZE
   - add memset to board info (bd)
   - remove compiler optimization barrier which is not need.
Changes for v13:
  - board.c: remove unused CONFIG_IDENT_STRING.
  - arch/nds32/lib/Makefile: remove unused clean and distclean.
Changes for v14:
  - No change.

 arch/nds32/config.mk        |   35 ++++
 arch/nds32/lib/Makefile     |   46 +++++
 arch/nds32/lib/board.c      |  443 +++++++++++++++++++++++++++++++++++++++++++
 arch/nds32/lib/bootm.c      |  241 +++++++++++++++++++++++
 arch/nds32/lib/interrupts.c |  131 +++++++++++++
 5 files changed, 896 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/config.mk
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/board.c
 create mode 100644 arch/nds32/lib/bootm.c
 create mode 100644 arch/nds32/lib/interrupts.c

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..c589829
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common -mrelax
+PLATFORM_RELFLAGS	+= -gdwarf-2
+PLATFORM_CPPFLAGS	+= -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-10 -fpie
+
+LDFLAGS_u-boot		= --gc-sections --relax
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..e5c31c3
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+OBJS	:= board.o bootm.o interrupts.o
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..f6774e1
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,443 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong monitor_flash_len;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	char tmp[64];	/* long enough for environment variables */
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+			? (int) simple_strtoul(tmp, NULL, 10)
+			: CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+void __dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size =  gd->ram_size;
+}
+void dram_init_banksize(void)
+	__attribute__((weak, alias("__dram_init_banksize")));
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	pmu_init,
+#endif
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init,
+#endif
+	display_dram_config,
+	NULL,
+};
+
+void board_init_f(ulong bootflag)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	gd_t *id;
+	ulong addr, addr_sp;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
+
+	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+
+	gd->mon_len = (unsigned int)(&__bss_end__) - (unsigned int)(&_start);
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	debug("monitor len: %08lX\n", gd->mon_len);
+	/*
+	 * Ram is setup, size stored in gd !!
+	 */
+	debug("ramsize: %08lX\n", gd->ram_size);
+
+	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	/* reserve TLB table */
+	addr -= (4096 * 4);
+
+	/* round down to next 64 kB limit */
+	addr &= ~(0x10000 - 1);
+
+	gd->tlb_addr = addr;
+	debug("TLB table at: %08lx\n", addr);
+#endif
+
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+	gd->fb_base = CONFIG_FB_ADDR;
+#else
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
+	/*
+	 * reserve memory for U-Boot code, data & bss
+	 * round down to next 4 kB limit
+	 */
+	addr -= gd->mon_len;
+	addr &= ~(4096 - 1);
+
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+
+	/*
+	 * reserve memory for malloc() arena
+	 */
+	addr_sp = addr - TOTAL_MALLOC_LEN;
+	debug("Reserving %dk for malloc() at: %08lx\n",
+			TOTAL_MALLOC_LEN >> 10, addr_sp);
+	/*
+	 * (permanently) allocate a Board Info struct
+	 * and a permanent copy of the "global" data
+	 */
+	addr_sp -= GENERATED_BD_INFO_SIZE;
+	bd = (bd_t *) addr_sp;
+	gd->bd = bd;
+	memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+			GENERATED_BD_INFO_SIZE, addr_sp);
+
+	addr_sp -= GENERATED_GBL_DATA_SIZE;
+	id = (gd_t *) addr_sp;
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			GENERATED_GBL_DATA_SIZE, addr_sp);
+
+	/* setup stackpointer for exeptions */
+	gd->irq_sp = addr_sp;
+#ifdef CONFIG_USE_IRQ
+	addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
+#endif
+	/* leave 3 words for abort-stack    */
+	addr_sp -= 12;
+
+	/* 8-byte alignment for ABI compliance */
+	addr_sp &= ~0x07;
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
+
+	gd->bd->bi_baudrate = gd->baudrate;
+	/* Ram isn't board specific, so move it to board code ... */
+	dram_init_banksize();
+	display_dram_config();	/* and display it */
+
+	gd->relocaddr = addr;
+	gd->start_addr_sp = addr_sp;
+
+	gd->reloc_off = addr - _TEXT_BASE;
+
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	memcpy(id, (void *)gd, GENERATED_GBL_DATA_SIZE);
+
+	relocate_code(addr_sp, id, addr);
+
+	/* NOTREACHED - relocate_code() does not return */
+}
+
+/*
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	char *s;
+	bd_t *bd;
+	ulong malloc_start;
+
+	extern void malloc_bin_reloc(void);
+
+	gd = id;
+	bd = gd->bd;
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	monitor_flash_len = &_end - &_start;
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
+
+	board_init();	/* Setup chipselects */
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	/*
+	 * We have to relocate the command table manually
+	 */
+	fixup_cmdtable(&__u_boot_cmd_start,
+		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
+
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+	mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+	malloc_bin_reloc();
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init();
+#endif
+
+	/* IP Address */
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+#if defined(CONFIG_USE_IRQ)
+	/* set up exceptions */
+	interrupt_init();
+	/* enable exceptions */
+	enable_interrupts();
+#endif
+
+	/* Initialize from environment */
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+	puts("Net:   ");
+#endif
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	show_boot_progress(15);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..c42ad2b
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+extern void reset_cpu(ulong addr);
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"lp : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}
-- 
1.7.3.5

[U-Boot] [PATCH v14 5/9] nds32/lib: add generic funcs in NDS32 lib

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1316574638-20460-5-git-send-email-macpaul@andestech.com> you wrote:
> Add Makefile, board.c, interrupts.c and bootm.c functions
> to nds32 architecture.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v4:
>   - code clean up and formatting style.
> Changes for v5-v6:
>   - board.c
>    - Do some clean up and add code
>    - Remove display banner which hasn't support.
>    - Add ftpmu010 related power management unit code.
>    - Remove useless LED related code.
>    - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
>    - Remove CONFIG_SOFT_I2C which hasn't been support.
>    - Remove CONFIG_FSL_ESDHC which hasn't been support.
>    - clean up.
> Changes for v7:
>   - clean up.
>   - move single file patch arch/nds32/config.mk to this commit.
>   - interrupts.c refine origin interrupt enable and disable.
> Changes for v8:
>   - interrups.c: fix up for new ptraces.h.
> Changes for v9:
>   - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
> Changes for v10:
>   - config.mk:
>    - add -fpie flag.
>    - replace -ffixed-8 to -ffixed-10.
>    - add -mrelax and --gc-sections to LDFLAG
>   - board.c:
>    - fix lib/board.c for relocation.
>    - fix dram init for relocation.
> Changes for v11:
>   - arch/nds32/lib/Makefile
>    - replace $(AR) $(call cmd_link_o_target,...)
> Changes for v12:
>   - config.mk
>    - remove $(SRCTREE)/$(CPUDIR)/u-boot.lds
>   - board.c:
>    - remove obsolelte version_string.
>    - remove declaration "extern __bss_end" which is not need.
>    - replace sizeof(gd_t) and sizeof(bd_t) to
>      GENERATED_GBL_DATA_SIZE and GENERATED_BD_INFO_SIZE
>    - add memset to board info (bd)
>    - remove compiler optimization barrier which is not need.
> Changes for v13:
>   - board.c: remove unused CONFIG_IDENT_STRING.
>   - arch/nds32/lib/Makefile: remove unused clean and distclean.
> Changes for v14:
>   - No change.
> 
>  arch/nds32/config.mk        |   35 ++++
>  arch/nds32/lib/Makefile     |   46 +++++
>  arch/nds32/lib/board.c      |  443 +++++++++++++++++++++++++++++++++++++++++++
>  arch/nds32/lib/bootm.c      |  241 +++++++++++++++++++++++
>  arch/nds32/lib/interrupts.c |  131 +++++++++++++
>  5 files changed, 896 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/config.mk
>  create mode 100644 arch/nds32/lib/Makefile
>  create mode 100644 arch/nds32/lib/board.c
>  create mode 100644 arch/nds32/lib/bootm.c
>  create mode 100644 arch/nds32/lib/interrupts.c

Checkpatch says:

total: 0 errors, 8 warnings, 896 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Accident: A condition in which presence of mind is good, but  absence
of body is better.

[U-Boot] [PATCH v14 6/9] nds32: standalone support

[Macpaul Lin]

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - code clean up.
Changes for v7-v11:
  - No change.
Changes for v12:
  - clean up for linker script.
Changes for v13-v14:
  - No change.

 examples/standalone/nds32.lds     |   56 +++++++++++++++++++++++++++++++++++++
 examples/standalone/stubs.c       |   17 ++++++++++-
 examples/standalone/x86-testapp.c |   12 ++++++++
 3 files changed, 84 insertions(+), 1 deletions(-)
 create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..50b4c4b
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	_end = .;
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 507d38c..11c7565 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
 "	jmp %%g1\n"					\
 "	nop\n"						\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	lwi	$r16, [$gp + (%0)]\n"	\
+"	lwi	$r16, [$r16 + (%1)]\n"	\
+"	jr	$r16\n"			\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
 #else
+/*"	addi	$sp, $sp, -24\n"	\
+"	br	$r16\n"			\*/
+
 #error stubs definition missing for this architecture
 #endif
 
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile (						\
 "	lw	$25, %1($25)\n"				\
 "	jr	$25\n"					\
 	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x)					\
+asm volatile (						\
+"	.globl mon_" #x "\n"				\
+"mon_" #x ":\n"						\
+"	lwi	$r16, [$gp + (%0)]\n"			\
+"	lwi	$r16, [$r16 + (%1)]\n"			\
+"	jr	$r16\n"					\
+	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
+
 #else
 #error [No stub code for this arch]
 #endif
@@ -72,6 +82,8 @@ int main(void)
 	register volatile xxx_t *pq asm("r8");
 #elif defined(__mips__)
 	register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+	register volatile xxx_t *pq asm("$r16");
 #endif
 	char buf[32];
 
-- 
1.7.3.5

[U-Boot] [PATCH v14 6/9] nds32: standalone support

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1316574638-20460-6-git-send-email-macpaul@andestech.com> you wrote:
> Add standalone program related support for nds32 architecture.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v6:
>   - code clean up.
> Changes for v7-v11:
>   - No change.
> Changes for v12:
>   - clean up for linker script.
> Changes for v13-v14:
>   - No change.
> 
>  examples/standalone/nds32.lds     |   56 +++++++++++++++++++++++++++++++++++++
>  examples/standalone/stubs.c       |   17 ++++++++++-
>  examples/standalone/x86-testapp.c |   12 ++++++++
>  3 files changed, 84 insertions(+), 1 deletions(-)
>  create mode 100644 examples/standalone/nds32.lds

Checkpatch says:

total: 0 errors, 2 warnings, 104 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Software entities are more complex for their size  than  perhaps  any
other human construct because no two parts are alike. If they are, we
make  the  two  similar parts into a subroutine -- open or closed. In
this respect, software  systems  differ  profoundly  from  computers,
buildings, or automobiles, where repeated elements abound.
                                                   - Fred Brooks, Jr.

[U-Boot] [PATCH v14 7/9] nds32: common bdinfo, bootm, image support

[Macpaul Lin]

Add support of NDS32 to common commands bdinfo, bootm, and image format.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - Code clean up
Changes for v7-v9:
  - No Change.
Changes for v10:
  - fix up according to the changes in master tree.
Changes for v11:
  - No Change.
Changes for v12:
  - remove seldom used bi_env parameter.
Changes for v13-v14:
  - No change.

 common/cmd_bdinfo.c |   25 +++++++++++++++++++++++++
 common/cmd_bootm.c  |    2 ++
 common/image.c      |    1 +
 include/image.h     |    5 +++++
 4 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 6051120..b3e506f 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -413,6 +413,31 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num("arch_number",	bd->bi_arch_number);
+	print_num("boot_params",	(ulong)bd->bi_boot_params);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 8909ee7..844be80 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -187,6 +187,8 @@ void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
   #define IH_INITRD_ARCH IH_ARCH_SH
 #elif defined(__sparc__)
   #define IH_INITRD_ARCH IH_ARCH_SPARC
+#elif defined(__nds32__)
+  #define IH_INITRD_ARCH IH_ARCH_NDS32
 #else
 # error Unknown CPU type
 #endif
diff --git a/common/image.c b/common/image.c
index d38ce4a..d620b85 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	-1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index 352e4a0..dcbbc8b 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_NDS32	        19	/* ANDES Technology - NDS32  */
 
 /*
  * Image Types
@@ -506,6 +507,8 @@ static inline int image_check_target_arch (const image_header_t *hdr)
 	if (!image_check_arch (hdr, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!image_check_arch (hdr, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!image_check_arch(hdr, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
@@ -658,6 +661,8 @@ static inline int fit_image_check_target_arch (const void *fdt, int node)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!fit_image_check_arch(fdt, node, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
-- 
1.7.3.5

[U-Boot] [PATCH v14 8/9] adp-ag101: add board adp-ag101 support

[Macpaul Lin]

Add evaluation board "adp-ag101" configuration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up
Changes for v5-v6:
  - Refine the definitions and parameters about CLK,
    AHB controller, SDRAM controller, Static memory controllers.
  - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
  - ftahbc010:
    - Update include path of ftahbc010.
  - ftsdmc021:
    - Update include path of ftsdmc021.
  - ftsmc020:
    - Update include path of ftsmc020.
  - ftwdt010:
    - Fix WDT define and update include path.
    - Fix ftwdt010 for hardware reset.
  - ftpmu010:
    - Remove duplicate PMU definitions.
    - Add related configurations.
  - Fix MAX malloc len and fix saveenv.
  - clean up.
Changes for v7:
  - clean up.
  - Move CONFIG_SYS_TEXT_BASE from board/config.mk.
  - Fix Makefile and remove config.mk
Changes for v8:
  - No change.
Changes for v9:
  - Fix because other boards has been added into boards.cfg and
    broken this patch.
Changes for v10:
  - adp-ag101.h
   - Fix lines over 80 characters.
   - Fix for introducing gen-asm-offset.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix flash init.
   - fix ftsmc010 configuraion for flash probing.
   - Add SP_INIT related configurations for supporting relocation.
   - Fix CONFIG_TEXT_BASE for relocation.
   - Add CONFIG_MEM_REMAP for some hardware boards and non-OS application.
  - adp-ag101.c
   - Clean up for braces according to Wolfgang's suggestion.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix dram init(), made this more simpler.
Changes for v11:
  - No change.
Changes for v12:
  - adp-ag101.h
   - fix address when enable CONFIG_SKIP_LOWLEVEL_INIT
Changes for v13:
  - board/AndesTech/adp-ag101/Makefile: remove unused clean and distclean.
Changes for v14:
  - No change.

 MAINTAINERS                           |   11 +
 MAKEALL                               |    6 +
 board/AndesTech/adp-ag101/Makefile    |   45 ++++
 board/AndesTech/adp-ag101/adp-ag101.c |   89 +++++++
 boards.cfg                            |    1 +
 include/configs/adp-ag101.h           |  407 +++++++++++++++++++++++++++++++++
 6 files changed, 559 insertions(+), 0 deletions(-)
 create mode 100644 board/AndesTech/adp-ag101/Makefile
 create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
 create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 2f60a60..61df1f8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1126,5 +1126,16 @@ Chong Huang <chuang@ucrobotics.com>
 	bf525-ucr2	BF525
 
 #########################################################################
+# NDS32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+	ADP-AG101	N1213 (AG101 SoC)
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 4d18c11..fb034c5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -480,6 +480,12 @@ LIST_sh="$(boards_by_arch sh)"
 
 LIST_sparc="$(boards_by_arch sparc)"
 
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
 #-----------------------------------------------------------------------
 
 build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..8a042d6
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= adp-ag101.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..82ce4c9
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	ftsdc010_mmc_init(0);
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 8a5bfc1..9cf4d63 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -298,6 +298,7 @@ vct_platinumavc_small        mips        mips32      vct                 microna
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
 nios2-generic                nios2       nios2       nios2-generic       altera
+adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..3544412
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,407 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x03200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_CMD_FAT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#else
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#endif
+
+/*
+ * There are 2 bank connected to FTSMC020 on ADP-AG101.
+ * You can use jumper and switch to force it booted from ROM or FLASH.
+ * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
+ * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
+ * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
+ *    Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
+ * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
+				 FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M	|	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_RBE	|	\
+				 FTSMC020_TPR_AST(1)	|	\
+				 FTSMC020_TPR_CTW(1)	|	\
+				 FTSMC020_TPR_ATI(1)	|	\
+				 FTSMC020_TPR_AT2(1)	|	\
+				 FTSMC020_TPR_WTC(1)	|	\
+				 FTSMC020_TPR_AHT(1)	|	\
+				 FTSMC020_TPR_TRNA(1))
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif	/* CONFIG_MEM_REMAP */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif	/* __CONFIG_H */
-- 
1.7.3.5

[U-Boot] [PATCH v14 9/9] doc/README: documents and readme for NDS32 arch

[Macpaul Lin]

Documents and READMEs for NDS32 architecture.
It patch also provides usage of SoC AG101 and board ADP-AG101.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v10:
  - The patch of documentation was not included.
Changes for v11:
  - Add the documents of NDS32, ag101, N1213.
Changes for v12-v14:
  - No change.

 README                |   24 ++++++++++++++--
 doc/README.N1213      |   55 ++++++++++++++++++++++++++++++++++++
 doc/README.NDS32      |   41 +++++++++++++++++++++++++++
 doc/README.ag101      |   74 +++++++++++++++++++++++++++++++++++++++++++++++++
 doc/README.standalone |    1 +
 5 files changed, 192 insertions(+), 3 deletions(-)
 create mode 100644 doc/README.N1213
 create mode 100644 doc/README.NDS32
 create mode 100644 doc/README.ag101

diff --git a/README b/README
index a43da97..8d0dffe 100644
--- a/README
+++ b/README
@@ -182,6 +182,10 @@ Directory Hierarchy:
     /cpu		CPU specific files
       /mips32		Files specific to MIPS32 CPUs
     /lib		Architecture specific library files
+  /nds32		Files generic to NDS32 architecture
+    /cpu		CPU specific files
+      /n1213		Files specific to Andes Technology N1213 CPUs
+    /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
@@ -3103,7 +3107,7 @@ Low Level (hardware related) configuration options:
 		globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-		[ARM, MIPS only] If this variable is defined, then certain
+		[ARM, NDS32, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
@@ -3653,8 +3657,8 @@ details; basically, the header defines the following image properties:
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
-  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
+  IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -4347,6 +4351,20 @@ On Nios II, the ABI is documented here:
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 
+On NDS32, the following registers are used:
+
+	R0-R1:	argument/return
+	R2-R5:	argument
+	R15:	temporary register for assembler
+	R16:	trampoline register
+	R28:	frame pointer (FP)
+	R29:	global pointer (GP)
+	R30:	link register (LP)
+	R31:	stack pointer (SP)
+	PC:	program counter (PC)
+
+    ==> U-Boot will use R10 to hold a pointer to the global data
+
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 
diff --git a/doc/README.N1213 b/doc/README.N1213
new file mode 100644
index 0000000..e107166
--- /dev/null
+++ b/doc/README.N1213
@@ -0,0 +1,55 @@
+N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
+
+Features
+========
+
+CPU Core
+ - 16-/32-bit mixable instruction format.
+ - 32 general-purpose 32-bit registers.
+ - 8-stage pipeline.
+ - Dynamic branch prediction.
+ - 32/64/128/256 BTB.
+ - Return address stack (RAS).
+ - Vector interrupts for internal/external.
+   interrupt controller with 6 hardware interrupt signals.
+ - 3 HW-level nested interruptions.
+ - User and super-user mode support.
+ - Memory-mapped I/O.
+ - Address space up to 4GB.
+
+Memory Management Unit
+ - TLB
+   - 4/8-entry fully associative iTLB/dTLB.
+   - 32/64/128-entry 4-way set-associati.ve main TLB.
+   - TLB locking support
+ - Optional hardware page table walker.
+ - Two groups of page size support.
+  - 4KB & 1MB.
+  - 8KB & 1MB.
+
+Memory Subsystem
+ - I & D cache.
+   - Virtually indexed and physically tagged.
+   - Cache size: 8KB/16KB/32KB/64KB.
+   - Cache line size: 16B/32B.
+   - Set associativity: 2-way, 4-way or direct-mapped.
+   - Cache locking support.
+ - I & D local memory (LM).
+   - Size: 4KB to 1MB.
+   - Bank numbers: 1 or 2.
+   - Optional 1D/2D DMA engine.
+   - Internal or external to CPU core.
+
+Bus Interface
+ - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
+ - Synchronous High speed memory port.
+   (HSMP): 0, 1 or 2 ports.
+
+Debug
+ - JTAG debug interface.
+ - Embedded debug module (EDM).
+ - Optional embedded program tracer interface.
+
+Miscellaneous
+ - Programmable data endian control.
+ - Performance monitoring mechanism.
diff --git a/doc/README.NDS32 b/doc/README.NDS32
new file mode 100644
index 0000000..b2b58fc
--- /dev/null
+++ b/doc/README.NDS32
@@ -0,0 +1,41 @@
+NDS32 is a new high-performance 32-bit RISC microprocessor core.
+
+http://www.andestech.com/
+
+AndeStar ISA
+============
+AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
+achieve optimal system performance, code density, and power efficiency.
+
+It contains the following features:
+ - Intermixable 32-bit and 16-bit instruction sets without the need for
+   mode switch.
+ - 16-bit instructions as a frequently used subset of 32-bit instructions.
+ - RISC-style register-based instruction set.
+ - 32 32-bit General Purpose Registers (GPR).
+ - Upto 1024 User Special Registers (USR) for existing and extension
+   instructions.
+ - Rich load/store instructions for...
+   - Single memory access with base address update.
+   - Multiple aligned and unaligned memory accesses for memory copy and stack
+     operations.
+   - Data prefetch to improve data cache performance.
+   - Non-bus locking synchronization instructions.
+ - PC relative jump and PC read instructions for efficient position independent
+   code.
+ - Multiply-add and multiple-sub with 64-bit accumulator.
+ - Instruction for efficient power management.
+ - Bi-endian support.
+ - Three instruction extension space for application acceleration:
+   - Performance extension.
+   - Andes future extensions (for floating-point, multimedia, etc.)
+   - Customer extensions.
+
+AndesCore CPU
+=============
+Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
+
+For details about N12 CPU family, please check doc/README.N1213.
+
+The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
+other associated software are actively supported by Andes Technology Corporation.
diff --git a/doc/README.ag101 b/doc/README.ag101
new file mode 100644
index 0000000..46fc637
--- /dev/null
+++ b/doc/README.ag101
@@ -0,0 +1,74 @@
+Andes Technology SoC AG101
+==========================
+
+AG101 is the first SoC produced by Andes Technology using N1213 CPU core.
+AG101 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG101
+=========
+
+ADP-AG101 is the SoC with AG101 hardcore CPU.
+
+Please check http://www.andestech.com/p2-4.htm for detail of this SoC.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+	This is also a must on ADP-AG101 board.
+	(While other boards may not have this problem).
+
+	The reason is because the ROM/FLASH circuit on PCB board.
+	AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	ROM/FLASH is used to boot.
+
+	When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	and the FLASH is connected to BANK1.
+	When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	and the FLASH is connected to BANK0.
+	It will occur problem when doing flash probing if the flash is at
+	BANK0 (0x00000000) while memory remapping was skipped.
+
+	Other board like ADP-AG101P may not enable this since there is only
+	a FLASH connected to bank0.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from FLASH and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag101.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101` in u-boot root to build the image.
+
+burn u-boot to flash:
+1. Make sure the MA17 (J16) is Lo.
+2. Make sure the dip switch SW5 is set to "0101".
+3. Power On. Press button "S1", then press button "SW1", then you will found the
+   debug LED show 67 means the system successfully booted into e-bios.
+   Now you can control the e-bios boot loader from your console.
+4. Under "Command>>" prompt, enter "97" (CopyImageFromCard)
+5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c".
+6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you
+   just build. It is usually "u-boot.bin".
+7. Under "Enter Dest. Address =>" prompt, enter the memory address where you
+   want to put the binary from SD card to RAM.
+   Address "0x500000" is our suggestion.
+8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command
+   environment.
+9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the
+   binary from RAM to FLASH.
+10. Under "CLI>" prompt, enter "exit" to finish the burn process.
+
+boot u-boot from flash:
+1. Make sure the MA17 (J16) is Hi).
+2. Make sure the dip switch SW5 is set to "1010".
+3. Power On. Press button "S1", then you will see the debug LED count to 20.
+4. Now you can use u-boot on ADP-AG101 board.
diff --git a/doc/README.standalone b/doc/README.standalone
index 6e6b65f..2be5f27 100644
--- a/doc/README.standalone
+++ b/doc/README.standalone
@@ -56,6 +56,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
 	ARM		0x0c100000	0x0c100000
 	MIPS		0x80200000	0x80200000
 	Blackfin	0x00001000	0x00001000
+	NDS32		0x00300000	0x00300000
 	Nios II		0x02000000	0x02000000
 
    For example, the "hello world" application may be loaded and
-- 
1.7.3.5

[U-Boot] [PATCH v13 2/9] nds32: add NDS32 support into common header file

[Macpaul Lin]

Add NDS32 support into common header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v7:
  - No change
Changes for v8:
  - Fix the patch according to dependency of x86's Fix
Changes for v9-v13:
  - No change

 include/common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index d244bd4..8a90354 100644
--- a/include/common.h
+++ b/include/common.h
@@ -302,6 +302,10 @@ int	setenv	     (const char *, const char *);
 #ifdef CONFIG_X86		/* x86 version to be fixed! */
 # include <asm/u-boot-x86.h>
 #endif /* CONFIG_X86 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h>	/* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
-- 
1.7.3.5

[U-Boot] [PATCH v13 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Macpaul Lin]

Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes v1 to v6:
  - Style clean up and reorganize code
Changes v7-v9:
  - No Change.
Changes v10:
  - start.S of N1213 CPU has been rewrote for relocation support.
  - u-boot.lds:
   - Add got and *(.got.plt) section for support GCC 4 toolchain
   - Modified for relocation implementation.
Changes v11:
  - arch/nds32/cpu/n1213/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes v12:
  - u-boot.lds
   - Remove the 0x00000000 base address in linker script.
     The base address of the binary will be determined by CONFIG_SYS_TEXT_BASE
  - Remove the CPU features in commit log and add to README in later patches.
Changes v13:
  - No change.

 arch/nds32/cpu/n1213/Makefile   |   50 ++++
 arch/nds32/cpu/n1213/start.S    |  501 +++++++++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/u-boot.lds |   70 ++++++
 3 files changed, 621 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/Makefile
 create mode 100644 arch/nds32/cpu/n1213/start.S
 create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..da15574
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..6fe30cc
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,501 @@
+/*
+ *	Andesboot - Startup Code for Whitiger core
+ *
+ *	Copyright (C) 2006	Andes Technology Corporation
+ *	Copyright (C) 2006	Shawn Lin <nobuhiro@andestech.com>
+ *	Copyright (C) 2011	Macpaul <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <asm/macro.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC		2UL
+#define DIS_DCAC		~ENA_DCAC
+#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
+#define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
+#define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY	(0x07<<3)	! D cache ways
+#define DCAC_MEM_KBF_DSZ	(0x07<<6)	! D cache line size
+
+#define PSW			$ir0
+#define EIT_INTR_PSW		$ir1		! interruption $PSW
+#define EIT_PREV_IPSW		$ir2		! previous $IPSW
+#define EIT_IVB			$ir3		! intr vector base address
+#define EIT_EVA			$ir4		! MMU related Exception Virtual Address register
+#define EIT_PREV_EVA		$ir5		! previous $eva
+#define EIT_ITYPE		$ir6		! interruption type
+#define EIT_PREV_ITYPE		$ir7		! prev intr type
+#define EIT_MACH_ERR		$ir8		! machine error log
+#define EIT_INTR_PC		$ir9		! Interruption PC
+#define EIT_PREV_IPC		$ir10		! previous $IPC
+#define EIT_OVL_INTR_PC		$ir11		! overflow interruption PC
+#define EIT_PREV_P0		$ir12		! prev $P0
+#define EIT_PREV_P1		$ir13		! prev $p1
+#define CR_ICAC_MEM		$cr1		! I-cache/memory config reg
+#define CR_DCAC_MEM		$cr2		! D-cache/memory config reg
+#define MR_CAC_CTL		$mr8
+
+.globl _start
+
+_start:	b	reset
+	b	tlb_fill
+	b	tlb_not_present
+	b	tlb_misc
+	b	tlb_vlpt_miss
+	b	cache_parity_error
+	b	debug
+	b	general_exception
+	b	internal_interrupt		! H0I
+	b	internal_interrupt		! H1I
+	b	internal_interrupt		! H2I
+	b	internal_interrupt		! H3I
+	b	internal_interrupt		! H4I
+	b	internal_interrupt		! H5I
+
+	.balign 16
+
+/*
+ * Andesboot Startup Code (reset vector)
+ *
+ *	1.	bootstrap
+ *		1.1 reset - start of u-boot
+ *		1.2 to superuser mode - as is when reset
+ *		1.4 Do lowlevel_init
+ *			- (this will jump out to lowlevel_init.S in SoC)
+ *			- (lowlevel_init)
+ *		1.3 Turn off watchdog timer
+ *			- (this will jump out to watchdog.S in SoC)
+ *			- (turnoff_watchdog)
+ *	2.	Do critical init when reboot (not from mem)
+ *	3.	Relocate andesboot to ram
+ *	4.	Setup stack
+ *	5.	Jump to second stage (board_init_r)
+ */
+
+/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word 0x0badc0de
+
+/*
+ * The bootstrap code of nds32 core
+ */
+
+reset:
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	jal	load_lowlevel_init
+	jral	$p0
+#endif
+
+/*
+ * Set the N1213 (Whitiger) core to superuser mode
+ * According to spec, it is already when reset
+ */
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+	jal	load_turnoff_watchdog
+	jral	$p0
+#endif
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+	bal	cpu_init_crit		! Do CPU critical regs init
+#endif
+
+/*
+ * Set stackpointer in internal RAM to call board_init_f
+ * $sp must be 8-byte alignment for ABI compliance.
+ */
+call_board_init_f:
+	li	$sp, CONFIG_SYS_INIT_SP_ADDR
+	li	$r0, 0x00000000
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__
+/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
+	la	$r15, board_init_f	! store function address into $r15
+#endif
+#endif
+	j	board_init_f		! jump to board_init_f() in lib/board.c
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl	relocate_code
+relocate_code:
+	move	$r4, $r0		/* save addr_sp */
+	move	$r5, $r1		/* save addr of gd */
+	move	$r6, $r2		/* save addr of destination */
+
+/* Set up the stack */
+stack_setup:
+	move	$sp, $r4
+
+	la	$r0, _start
+
+	beq	$r0, $r6, clear_bss	/* skip relocation */
+
+	move	$r1, $r6		/* r1 <- scratch for copy_loop */
+	la	$r3, __bss_start
+	sub	$r3, $r3, $r0		/* r3 <- __bss_start_ofs */
+	add	$r2, $r0, $r3		/* r2 <- source end address */
+
+copy_loop:
+	lwi.p	$r7, [$r0], #4
+	swi.p	$r7, [$r1], #4
+	blt	$r0, $r2, copy_loop
+
+/*
+ * fix relocations related issues
+ */
+fix_relocations:
+	l.w	$r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	$r9, $r6, $r0		/* r9 <- relocation offset */
+
+fix_got:
+/*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+	la	$r2, __got_start	/* r2 <- rel __got_start in FLASH */
+	add	$r2, $r2, $r9		/* r2 <- rel __got_start in RAM */
+	la	$r3, __got_end		/* r3 <- rel __got_end in FLASH */
+	add	$r3, $r3, $r9		/* r3 <- rel __got_end in RAM */
+	addi	$r2, $r2, #8		/* skipping first two entries */
+fix_got_loop:
+	lwi	$r0, [$r2]		/* r0 <- location in FLASH to fix up */
+	add	$r0, $r0, $r9		/* r0 <- location fix up to RAM */
+	swi.p	$r0, [$r2], #4		/* r0 <- store fix into .got in RAM */
+	blt	$r2, $r3, fix_got_loop
+
+clear_bss:
+	la	$r0, __bss_start	/* r0 <- rel __bss_start in FLASH */
+	add	$r0, $r0, $r9		/* r0 <- rel __bss_start in FLASH */
+	la	$r1, __bss_end__	/* r1 <- rel __bss_end in RAM */
+	add	$r1, $r1, $r9		/* r0 <- rel __bss_end in RAM */
+	li	$r2, 0x00000000		/* clear */
+
+clbss_l:
+	sw	$r2, [$r0]		/* clear loop... */
+	addi	$r0, $r0, #4
+	bne	$r0, $r1, clbss_l
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+	la	$r0, board_init_r
+	move	$lp, $r0		/* offset of board_init_r() */
+	add	$lp, $lp, $r9		/* real address of board_init_r() */
+	/* setup parameters for board_init_r */
+	move	$r0, $r5		/* gd_t */
+	move	$r1, $r6		/* dest_addr */
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__		/* NDS32 V0 ISA	*/
+	move	$r15, $lp		/* store function address into $r15 */
+#endif
+#endif
+
+	/* jump to it ... */
+	jr	$lp			/* jump to board_init_r() */
+
+/*
+ * Initialize CPU critical registers
+ *
+ *	1.	Setup control registers
+ *		1.1 Mask all IRQs
+ *		1.2 Flush cache and TLB
+ *		1.3 Disable MMU and cache
+ *	2.	Setup memory timing
+ */
+
+cpu_init_crit:
+
+	move	$r0, $lp		/* push	ra */
+
+	/* Disable Interrupts by clear GIE in $PSW reg */
+	setgie.d
+
+	/* Flush caches and TLB */
+	/* Invalidate caches */
+	bal	invalidate_icac
+	bal	invalidate_dcac
+
+	/* Flush TLB */
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+
+1:
+	! Disable MMU, Dcache
+	! Whitiger is MMU disabled when reset
+	! Disable the D$
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Set DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! write back the $CACHE_CTL reg
+	isb
+
+	move	$lp, $r0
+2:
+	ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+	la  $r6, lowlevel_init
+	la  $r7, load_lli + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+	la  $r6, turnoff_watchdog
+	la  $r7, turnoff_wtdog + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+/*
+ * Invalidate I$
+ */
+invalidate_icac:
+	mfsr	$t0, CR_ICAC_MEM		! read $cr1(I CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, ICAC_MEM_KBF_ISZ 	! Get the ISZ field
+	beqz	$p0, end_flush_icache		! if $p0=0, then no I CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of I$ block
+	addi	$t1, $p0, 2			! $t1= bit width of I cache line size(ISZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, ICAC_MEM_KBF_ISET	! get the ISET field
+	addi	$t2, $p1, 6			! $t2= bit width of ISET
+	andi	$p1, $t0, ICAC_MEM_KBF_IWAY	! get bitfield of Iway
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is I way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+ICAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1I_IX_INVAL
+	bnez	$p1, ICAC_LOOP
+end_flush_icache:
+	ret
+
+/*
+ * Invalidate D$
+ */
+invalidate_dcac:
+	mfsr	$t0, CR_DCAC_MEM		! read $cr2(D CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, DCAC_MEM_KBF_DSZ	! Get the DSZ field
+	beqz	$p0, end_flush_dcache		! if $p0=0, then no D CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of D$ block
+	addi	$t1, $p0, 2			! $t1= bit width of D cache line size(DSZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, DCAC_MEM_KBF_DSET	! get the DSET field
+	addi	$t2, $p1, 6			! $t2= bit width of DSET
+	andi	$p1, $t0, DCAC_MEM_KBF_DWAY	! get bitfield of D way
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is D way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+DCAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1D_IX_INVAL
+	bnez	$p1, DCAC_LOOP
+end_flush_dcache:
+	ret
+
+/*
+ * Interrupt handling
+ */
+
+/*
+ * exception handlers
+ */
+	.align	5
+
+.macro	SAVE_ALL
+	! FIXME: Other way to get PC?
+	! FIXME: Update according to the newest spec!!
+1:
+	la	 $r28, 1
+	push $r28
+	mfsr $r28, PSW			! $PSW
+	push $r28
+	mfsr $r28, EIT_EVA		! $ir1 $EVA
+	push $r28
+	mfsr $r28, EIT_ITYPE		! $ir2 $ITYPE
+	push $r28
+	mfsr $r28, EIT_MACH_ERR		! $ir3 Mach Error
+	push $r28
+	mfsr $r28, EIT_INTR_PSW		! $ir5 $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_IPSW	! $ir6 prev $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_EVA		! $ir7 prev $EVA
+	push $r28
+	mfsr $r28, EIT_PREV_ITYPE	! $ir8 prev $ITYPE
+	push $r28
+	mfsr $r28, EIT_INTR_PC		! $ir9 Interruption PC
+	push $r28
+	mfsr $r28, EIT_PREV_IPC		! $ir10 prev INTR_PC
+	push $r28
+	mfsr $r28, EIT_OVL_INTR_PC	! $ir11 Overflowed INTR_PC
+	push $r28
+	mfusr $r28, $d1.lo
+	push $r28
+	mfusr $r28, $d1.hi
+	push $r28
+	mfusr $r28, $d0.lo
+	push $r28
+	mfusr $r28, $d0.hi
+	push $r28
+	pushm $r0, $r30		! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
+	addi	$sp, $sp, -4	! make room for implicit pt_regs parameters
+.endm
+
+	.align	5
+tlb_fill:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 1				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_not_present:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 2				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_misc:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 3				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_vlpt_miss:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 4				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+cache_parity_error:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 5				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+debug:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 6				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+general_exception:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 7				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+internal_interrupt:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 8				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+
+/*
+ * void reset_cpu(ulong addr);
+ * $r0: input address to jump to
+ */
+.globl reset_cpu
+reset_cpu:
+/* No need to disable MMU because we never enable it */
+
+	bal	invalidate_icac
+	bal	invalidate_dcac
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+1:
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Clear the DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! Write back the $CACHE_CTL reg
+	br	$r0				! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..45221ee
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		arch/nds32/cpu/n1213/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		 *(.got.plt) *(.got)
+		__got_end = .;
+	}
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+}
-- 
1.7.3.5

[U-Boot] [PATCH v13 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Macpaul Lin]

SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
Add lowlevel_init.S and other periphal related code.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code clean up.
Changes for v5-v6:
  - Split watchdog.S from lowlevel_init.S.
  - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
   - reset_cpu was remove inside do_reset().
  - lowlevel_init.S
   - Change hard code value into MARCO definitions.
   - ftsmc010
     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
   - ftsdmc021
     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
     - Fix the default configuration value of FTSDMC and FTSMC controller.
   - Remove some ftpmu010 and flash probe code to C functions.
Changes for v7:
  - clean up.
Changes for v8-v9:
  - No change.
Changes for v10:
  - asm-offset.c: file added for ag101 use only.
  - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
  - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
  - cpu.c: remove unused cpu_init().
  - lowlevel_init.S
   - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
   - Replace routings by macros to made code much easier to understand.
   - Add debug LED support.
   - Add CONFIG_MEM_REMAP for those boards must do memort remapping.
Changes for v11:
  - arch/nds32/cpu/n1213/ag101/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - Simplify the commit log about the part of lowlevel_init.S.
Changes for v13:
  - arch/nds32/cpu/n1213/ag101/Makefile: remove unused gen-asm-offset.
  - Makefile: remove unused gen-asm-offset because merged asm-offsets.

 arch/nds32/cpu/n1213/ag101/Makefile        |   58 +++++++
 arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
 arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/timer.c         |  204 ++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
 arch/nds32/include/asm/arch-ag101/ag101.h  |   68 ++++++++
 7 files changed, 859 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
 create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
 create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..8716c4e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
new file mode 100644
index 0000000..92ada8a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
@@ -0,0 +1,43 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..0ab666e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+	unsigned long i;
+#endif
+
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+	while (1)
+		;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr , addr + size);
+	icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..94308a8
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+#include "gen-asm-offsets.h"
+
+#include <asm/macro.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+
+#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro	wait_sdram
+	li	$r0, CONFIG_FTSDMC021_BASE
+1:
+	lwi	$r1, [$r0+FTSDMC021_CR2]
+	bnez	$r1, 1b
+.endm
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+
+	led	0x0
+	jal	mem_init
+
+	led	0x10
+	jal	remap
+
+	led	0x20
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	led	0x01
+	write32	SMC_BANK0_CR_A, SMC_BANK0_CR_D			! 0x10000052
+	write32	SMC_BANK0_TPR_A, SMC_BANK0_TPR_D		! 0x00151151
+
+	/*
+	 * config AHB Controller
+	 */
+	led	0x02
+	write32	AHBC_BSR6_A, AHBC_BSR6_D
+
+	/*
+	 * config PMU controller
+	 */
+	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
+	led	0x03
+	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
+
+	/*
+	 * config SDRAM controller
+	 */
+	led	0x04
+	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
+	led	0x05
+	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
+	led	0x06
+	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
+
+	led	0x07
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
+	wait_sdram
+
+	led	0x08
+	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
+	wait_sdram
+
+	led	0x09
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
+	wait_sdram
+
+	led	0x0a
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+	/*
+	 * Remapping
+	 */
+	led	0x1a
+	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
+
+	/* clear empty BSR registers */
+	led	0x1b
+	li	$r4, CONFIG_FTSDMC021_BASE
+	li	$r5, 0x0
+	swi	$r5, [$r4 + FTSDMC021_BANK1_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
+
+#ifdef CONFIG_MEM_REMAP
+	/*
+	 * Copy ROM code to SDRAM base for memory remap layout.
+	 * This is not the real relocation, the real relocation is the function
+	 * relocate_code() is start.S which supports the systems is memory
+	 * remapped or not.
+	 */
+	/*
+	 * Doing memory remap is essential for preparing some non-OS or RTOS
+	 * applications.
+	 *
+	 * This is also a must on ADP-AG101 board.
+	 * The reason is because the ROM/FLASH circuit on PCB board.
+	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	 * ROM/FLASH is used to boot.
+	 *
+	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	 * and the FLASH is connected to BANK1.
+	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	 * and the FLASH is connected to BANK0.
+	 * It will occur problem when doing flash probing if the flash is at
+	 * BANK0 (0x00000000) while memory remapping was skipped.
+	 *
+	 * Other board like ADP-AG101P may not enable this since there is only
+	 * a FLASH connected to bank0.
+	 */
+	led	0x11
+	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
+	li	$r5, 0x0
+	la	$r1, relo_base				/* get $pc or $lp */
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(_end)
+	ori	$r6, $r6, lo12(_end)
+	add	$r6, $r6, $r2
+1:
+	lwi.p	$r7, [$r5], #4
+	swi.p	$r7, [$r4], #4
+	blt	$r5, $r6, 1b
+
+	/* set remap bit */
+	/*
+	 * MEM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
+	 */
+	led	0x1c
+	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..b689eab
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl	turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+#endif
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE		0x90100000	/* AHB Controller */
+#define CONFIG_FTSMC020_BASE		0x90200000	/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE		0x90300000	/* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000	/* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000	/* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE		0x90600000	/* LCD Controller */
+#define CONFIG_RESERVED_01_BASE		0x90700000	/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000	/* Reserved */
+#define CONFIG_FTMAC100_BASE		0x90900000	/* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000	/* External USB host */
+#define CONFIG_USB_DEV_BASE		0x90B00000	/* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000	/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE		0x90D00000	/* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000	/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000	/* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000	/* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC	/* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE		0x98100000	/* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE	0x98300000	/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE		0x98400000	/* Counter/Timers */
+#define CONFIG_FTWDT010_BASE		0x98500000	/* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE		0x98600000	/* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE		0x98700000	/* GPIO */
+#define CONFIG_FTINTC010_BASE		0x98800000	/* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE		0x98A00000	/* I2C */
+#define CONFIG_RESERVED_04_BASE		0x98C00000	/* Reserved */
+#define CONFIG_FTCFC010_BASE		0x98D00000	/* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000	/* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE		0x99400000	/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE	0x99600000	/* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE	0x98200000	/* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000	/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE		0x98900000	/* IrDA */
+#define CONFIG_PMW_BASE			0x99100000	/* PWM - Pulse Width Modulator Controller */
+
+#endif	/* __AG101_H */
-- 
1.7.3.5

[U-Boot] [PATCH v13 5/9] nds32/lib: add generic funcs in NDS32 lib

[Macpaul Lin]

Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v4:
  - code clean up and formatting style.
Changes for v5-v6:
  - board.c
   - Do some clean up and add code
   - Remove display banner which hasn't support.
   - Add ftpmu010 related power management unit code.
   - Remove useless LED related code.
   - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
   - Remove CONFIG_SOFT_I2C which hasn't been support.
   - Remove CONFIG_FSL_ESDHC which hasn't been support.
   - clean up.
Changes for v7:
  - clean up.
  - move single file patch arch/nds32/config.mk to this commit.
  - interrupts.c refine origin interrupt enable and disable.
Changes for v8:
  - interrups.c: fix up for new ptraces.h.
Changes for v9:
  - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
Changes for v10:
  - config.mk:
   - add -fpie flag.
   - replace -ffixed-8 to -ffixed-10.
   - add -mrelax and --gc-sections to LDFLAG
  - board.c:
   - fix lib/board.c for relocation.
   - fix dram init for relocation.
Changes for v11:
  - arch/nds32/lib/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - config.mk
   - remove $(SRCTREE)/$(CPUDIR)/u-boot.lds
  - board.c:
   - remove obsolelte version_string.
   - remove declaration "extern __bss_end" which is not need.
   - replace sizeof(gd_t) and sizeof(bd_t) to
     GENERATED_GBL_DATA_SIZE and GENERATED_BD_INFO_SIZE
   - add memset to board info (bd)
   - remove compiler optimization barrier which is not need.
Changes for v13:
  - board.c: remove unused CONFIG_IDENT_STRING.
  - arch/nds32/lib/Makefile: remove unused clean and distclean.
---
 arch/nds32/config.mk        |   35 ++++
 arch/nds32/lib/Makefile     |   46 +++++
 arch/nds32/lib/board.c      |  443 +++++++++++++++++++++++++++++++++++++++++++
 arch/nds32/lib/bootm.c      |  241 +++++++++++++++++++++++
 arch/nds32/lib/interrupts.c |  131 +++++++++++++
 5 files changed, 896 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/config.mk
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/board.c
 create mode 100644 arch/nds32/lib/bootm.c
 create mode 100644 arch/nds32/lib/interrupts.c

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..c589829
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common -mrelax
+PLATFORM_RELFLAGS	+= -gdwarf-2
+PLATFORM_CPPFLAGS	+= -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-10 -fpie
+
+LDFLAGS_u-boot		= --gc-sections --relax
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..e5c31c3
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+OBJS	:= board.o bootm.o interrupts.o
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..f6774e1
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,443 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong monitor_flash_len;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	char tmp[64];	/* long enough for environment variables */
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+			? (int) simple_strtoul(tmp, NULL, 10)
+			: CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+void __dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size =  gd->ram_size;
+}
+void dram_init_banksize(void)
+	__attribute__((weak, alias("__dram_init_banksize")));
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	pmu_init,
+#endif
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init,
+#endif
+	display_dram_config,
+	NULL,
+};
+
+void board_init_f(ulong bootflag)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	gd_t *id;
+	ulong addr, addr_sp;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
+
+	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+
+	gd->mon_len = (unsigned int)(&__bss_end__) - (unsigned int)(&_start);
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	debug("monitor len: %08lX\n", gd->mon_len);
+	/*
+	 * Ram is setup, size stored in gd !!
+	 */
+	debug("ramsize: %08lX\n", gd->ram_size);
+
+	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	/* reserve TLB table */
+	addr -= (4096 * 4);
+
+	/* round down to next 64 kB limit */
+	addr &= ~(0x10000 - 1);
+
+	gd->tlb_addr = addr;
+	debug("TLB table at: %08lx\n", addr);
+#endif
+
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+	gd->fb_base = CONFIG_FB_ADDR;
+#else
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
+	/*
+	 * reserve memory for U-Boot code, data & bss
+	 * round down to next 4 kB limit
+	 */
+	addr -= gd->mon_len;
+	addr &= ~(4096 - 1);
+
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+
+	/*
+	 * reserve memory for malloc() arena
+	 */
+	addr_sp = addr - TOTAL_MALLOC_LEN;
+	debug("Reserving %dk for malloc() at: %08lx\n",
+			TOTAL_MALLOC_LEN >> 10, addr_sp);
+	/*
+	 * (permanently) allocate a Board Info struct
+	 * and a permanent copy of the "global" data
+	 */
+	addr_sp -= GENERATED_BD_INFO_SIZE;
+	bd = (bd_t *) addr_sp;
+	gd->bd = bd;
+	memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+			GENERATED_BD_INFO_SIZE, addr_sp);
+
+	addr_sp -= GENERATED_GBL_DATA_SIZE;
+	id = (gd_t *) addr_sp;
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			GENERATED_GBL_DATA_SIZE, addr_sp);
+
+	/* setup stackpointer for exeptions */
+	gd->irq_sp = addr_sp;
+#ifdef CONFIG_USE_IRQ
+	addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
+#endif
+	/* leave 3 words for abort-stack    */
+	addr_sp -= 12;
+
+	/* 8-byte alignment for ABI compliance */
+	addr_sp &= ~0x07;
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
+
+	gd->bd->bi_baudrate = gd->baudrate;
+	/* Ram isn't board specific, so move it to board code ... */
+	dram_init_banksize();
+	display_dram_config();	/* and display it */
+
+	gd->relocaddr = addr;
+	gd->start_addr_sp = addr_sp;
+
+	gd->reloc_off = addr - _TEXT_BASE;
+
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	memcpy(id, (void *)gd, GENERATED_GBL_DATA_SIZE);
+
+	relocate_code(addr_sp, id, addr);
+
+	/* NOTREACHED - relocate_code() does not return */
+}
+
+/*
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	char *s;
+	bd_t *bd;
+	ulong malloc_start;
+
+	extern void malloc_bin_reloc(void);
+
+	gd = id;
+	bd = gd->bd;
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	monitor_flash_len = &_end - &_start;
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
+
+	board_init();	/* Setup chipselects */
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	/*
+	 * We have to relocate the command table manually
+	 */
+	fixup_cmdtable(&__u_boot_cmd_start,
+		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
+
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+	mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+	malloc_bin_reloc();
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init();
+#endif
+
+	/* IP Address */
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+#if defined(CONFIG_USE_IRQ)
+	/* set up exceptions */
+	interrupt_init();
+	/* enable exceptions */
+	enable_interrupts();
+#endif
+
+	/* Initialize from environment */
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+	puts("Net:   ");
+#endif
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	show_boot_progress(15);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..c42ad2b
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+extern void reset_cpu(ulong addr);
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"lp : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}
-- 
1.7.3.5

[U-Boot] [PATCH v13 6/9] nds32: standalone support

[Macpaul Lin]

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v6:
  - code clean up.
Changes for v7-v11:
  - No change.
Changes for v12:
  - clean up for linker script.
Changes for v13:
  - No change.
---
 examples/standalone/nds32.lds     |   56 +++++++++++++++++++++++++++++++++++++
 examples/standalone/stubs.c       |   17 ++++++++++-
 examples/standalone/x86-testapp.c |   12 ++++++++
 3 files changed, 84 insertions(+), 1 deletions(-)
 create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..50b4c4b
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	_end = .;
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 507d38c..11c7565 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
 "	jmp %%g1\n"					\
 "	nop\n"						\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	lwi	$r16, [$gp + (%0)]\n"	\
+"	lwi	$r16, [$r16 + (%1)]\n"	\
+"	jr	$r16\n"			\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
 #else
+/*"	addi	$sp, $sp, -24\n"	\
+"	br	$r16\n"			\*/
+
 #error stubs definition missing for this architecture
 #endif
 
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile (						\
 "	lw	$25, %1($25)\n"				\
 "	jr	$25\n"					\
 	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x)					\
+asm volatile (						\
+"	.globl mon_" #x "\n"				\
+"mon_" #x ":\n"						\
+"	lwi	$r16, [$gp + (%0)]\n"			\
+"	lwi	$r16, [$r16 + (%1)]\n"			\
+"	jr	$r16\n"					\
+	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
+
 #else
 #error [No stub code for this arch]
 #endif
@@ -72,6 +82,8 @@ int main(void)
 	register volatile xxx_t *pq asm("r8");
 #elif defined(__mips__)
 	register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+	register volatile xxx_t *pq asm("$r16");
 #endif
 	char buf[32];
 
-- 
1.7.3.5

[U-Boot] [PATCH v13 7/9] nds32: common bdinfo, bootm, image support

[Macpaul Lin]

Add support of NDS32 to common commands bdinfo, bootm, and image format.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v6:
  - Code clean up
Changes for v7-v9:
  - No Change.
Changes for v10:
  - fix up according to the changes in master tree.
Changes for v11:
  - No Change.
Changes for v12:
  - remove seldom used bi_env parameter.
Changes for v13:
  - No change.
---
 common/cmd_bdinfo.c |   25 +++++++++++++++++++++++++
 common/cmd_bootm.c  |    2 ++
 common/image.c      |    1 +
 include/image.h     |    5 +++++
 4 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 6051120..b3e506f 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -413,6 +413,31 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num("arch_number",	bd->bi_arch_number);
+	print_num("boot_params",	(ulong)bd->bi_boot_params);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 8909ee7..844be80 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -187,6 +187,8 @@ void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
   #define IH_INITRD_ARCH IH_ARCH_SH
 #elif defined(__sparc__)
   #define IH_INITRD_ARCH IH_ARCH_SPARC
+#elif defined(__nds32__)
+  #define IH_INITRD_ARCH IH_ARCH_NDS32
 #else
 # error Unknown CPU type
 #endif
diff --git a/common/image.c b/common/image.c
index d38ce4a..d620b85 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	-1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index 352e4a0..dcbbc8b 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_NDS32	        19	/* ANDES Technology - NDS32  */
 
 /*
  * Image Types
@@ -506,6 +507,8 @@ static inline int image_check_target_arch (const image_header_t *hdr)
 	if (!image_check_arch (hdr, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!image_check_arch (hdr, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!image_check_arch(hdr, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
@@ -658,6 +661,8 @@ static inline int fit_image_check_target_arch (const void *fdt, int node)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!fit_image_check_arch(fdt, node, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
-- 
1.7.3.5

[U-Boot] [PATCH v13 8/9] adp-ag101: add board adp-ag101 support

[Macpaul Lin]

Add evaluation board "adp-ag101" configuration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v4:
  - code clean up
Changes for v5-v6:
  - Refine the definitions and parameters about CLK,
    AHB controller, SDRAM controller, Static memory controllers.
  - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
  - ftahbc010:
    - Update include path of ftahbc010.
  - ftsdmc021:
    - Update include path of ftsdmc021.
  - ftsmc020:
    - Update include path of ftsmc020.
  - ftwdt010:
    - Fix WDT define and update include path.
    - Fix ftwdt010 for hardware reset.
  - ftpmu010:
    - Remove duplicate PMU definitions.
    - Add related configurations.
  - Fix MAX malloc len and fix saveenv.
  - clean up.
Changes for v7:
  - clean up.
  - Move CONFIG_SYS_TEXT_BASE from board/config.mk.
  - Fix Makefile and remove config.mk
Changes for v8:
  - No change.
Changes for v9:
  - Fix because other boards has been added into boards.cfg and
    broken this patch.
Changes for v10:
  - adp-ag101.h
   - Fix lines over 80 characters.
   - Fix for introducing gen-asm-offset.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix flash init.
   - fix ftsmc010 configuraion for flash probing.
   - Add SP_INIT related configurations for supporting relocation.
   - Fix CONFIG_TEXT_BASE for relocation.
   - Add CONFIG_MEM_REMAP for some hardware boards and non-OS application.
  - adp-ag101.c
   - Clean up for braces according to Wolfgang's suggestion.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix dram init(), made this more simpler.
Changes for v11:
  - No Change.
Changes for v12:
  - adp-ag101.h
   - fix address when enable CONFIG_SKIP_LOWLEVEL_INIT
Changes for v13:
  - board/AndesTech/adp-ag101/Makefile: remove unused clean and distclean.
---
 MAINTAINERS                           |   11 +
 MAKEALL                               |    6 +
 board/AndesTech/adp-ag101/Makefile    |   45 ++++
 board/AndesTech/adp-ag101/adp-ag101.c |   89 +++++++
 boards.cfg                            |    1 +
 include/configs/adp-ag101.h           |  407 +++++++++++++++++++++++++++++++++
 6 files changed, 559 insertions(+), 0 deletions(-)
 create mode 100644 board/AndesTech/adp-ag101/Makefile
 create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
 create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 2f60a60..61df1f8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1126,5 +1126,16 @@ Chong Huang <chuang@ucrobotics.com>
 	bf525-ucr2	BF525
 
 #########################################################################
+# NDS32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+	ADP-AG101	N1213 (AG101 SoC)
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 4d18c11..fb034c5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -480,6 +480,12 @@ LIST_sh="$(boards_by_arch sh)"
 
 LIST_sparc="$(boards_by_arch sparc)"
 
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
 #-----------------------------------------------------------------------
 
 build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..8a042d6
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= adp-ag101.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..82ce4c9
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	ftsdc010_mmc_init(0);
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 8a5bfc1..9cf4d63 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -298,6 +298,7 @@ vct_platinumavc_small        mips        mips32      vct                 microna
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
 nios2-generic                nios2       nios2       nios2-generic       altera
+adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..3544412
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,407 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x03200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_CMD_FAT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#else
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#endif
+
+/*
+ * There are 2 bank connected to FTSMC020 on ADP-AG101.
+ * You can use jumper and switch to force it booted from ROM or FLASH.
+ * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
+ * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
+ * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
+ *    Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
+ * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
+				 FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M	|	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_RBE	|	\
+				 FTSMC020_TPR_AST(1)	|	\
+				 FTSMC020_TPR_CTW(1)	|	\
+				 FTSMC020_TPR_ATI(1)	|	\
+				 FTSMC020_TPR_AT2(1)	|	\
+				 FTSMC020_TPR_WTC(1)	|	\
+				 FTSMC020_TPR_AHT(1)	|	\
+				 FTSMC020_TPR_TRNA(1))
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif	/* CONFIG_MEM_REMAP */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif	/* __CONFIG_H */
-- 
1.7.3.5

[U-Boot] [PATCH v13 9/9] doc/README: documents and readme for NDS32 arch

[Macpaul Lin]

Documents and READMEs for NDS32 architecture.
It patch also provides usage of SoC AG101 and board ADP-AG101.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Changes for v1-v10:
  - The patch of documentation was not included.
Changes for v11:
  - Add the documents of NDS32, ag101, N1213.
Changes for v12-v13:
  - No change.
---
 README                |   24 ++++++++++++++--
 doc/README.N1213      |   55 ++++++++++++++++++++++++++++++++++++
 doc/README.NDS32      |   41 +++++++++++++++++++++++++++
 doc/README.ag101      |   74 +++++++++++++++++++++++++++++++++++++++++++++++++
 doc/README.standalone |    1 +
 5 files changed, 192 insertions(+), 3 deletions(-)
 create mode 100644 doc/README.N1213
 create mode 100644 doc/README.NDS32
 create mode 100644 doc/README.ag101

diff --git a/README b/README
index a43da97..8d0dffe 100644
--- a/README
+++ b/README
@@ -182,6 +182,10 @@ Directory Hierarchy:
     /cpu		CPU specific files
       /mips32		Files specific to MIPS32 CPUs
     /lib		Architecture specific library files
+  /nds32		Files generic to NDS32 architecture
+    /cpu		CPU specific files
+      /n1213		Files specific to Andes Technology N1213 CPUs
+    /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
@@ -3103,7 +3107,7 @@ Low Level (hardware related) configuration options:
 		globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-		[ARM, MIPS only] If this variable is defined, then certain
+		[ARM, NDS32, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
@@ -3653,8 +3657,8 @@ details; basically, the header defines the following image properties:
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
-  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
+  IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -4347,6 +4351,20 @@ On Nios II, the ABI is documented here:
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 
+On NDS32, the following registers are used:
+
+	R0-R1:	argument/return
+	R2-R5:	argument
+	R15:	temporary register for assembler
+	R16:	trampoline register
+	R28:	frame pointer (FP)
+	R29:	global pointer (GP)
+	R30:	link register (LP)
+	R31:	stack pointer (SP)
+	PC:	program counter (PC)
+
+    ==> U-Boot will use R10 to hold a pointer to the global data
+
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 
diff --git a/doc/README.N1213 b/doc/README.N1213
new file mode 100644
index 0000000..e107166
--- /dev/null
+++ b/doc/README.N1213
@@ -0,0 +1,55 @@
+N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
+
+Features
+========
+
+CPU Core
+ - 16-/32-bit mixable instruction format.
+ - 32 general-purpose 32-bit registers.
+ - 8-stage pipeline.
+ - Dynamic branch prediction.
+ - 32/64/128/256 BTB.
+ - Return address stack (RAS).
+ - Vector interrupts for internal/external.
+   interrupt controller with 6 hardware interrupt signals.
+ - 3 HW-level nested interruptions.
+ - User and super-user mode support.
+ - Memory-mapped I/O.
+ - Address space up to 4GB.
+
+Memory Management Unit
+ - TLB
+   - 4/8-entry fully associative iTLB/dTLB.
+   - 32/64/128-entry 4-way set-associati.ve main TLB.
+   - TLB locking support
+ - Optional hardware page table walker.
+ - Two groups of page size support.
+  - 4KB & 1MB.
+  - 8KB & 1MB.
+
+Memory Subsystem
+ - I & D cache.
+   - Virtually indexed and physically tagged.
+   - Cache size: 8KB/16KB/32KB/64KB.
+   - Cache line size: 16B/32B.
+   - Set associativity: 2-way, 4-way or direct-mapped.
+   - Cache locking support.
+ - I & D local memory (LM).
+   - Size: 4KB to 1MB.
+   - Bank numbers: 1 or 2.
+   - Optional 1D/2D DMA engine.
+   - Internal or external to CPU core.
+
+Bus Interface
+ - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
+ - Synchronous High speed memory port.
+   (HSMP): 0, 1 or 2 ports.
+
+Debug
+ - JTAG debug interface.
+ - Embedded debug module (EDM).
+ - Optional embedded program tracer interface.
+
+Miscellaneous
+ - Programmable data endian control.
+ - Performance monitoring mechanism.
diff --git a/doc/README.NDS32 b/doc/README.NDS32
new file mode 100644
index 0000000..b2b58fc
--- /dev/null
+++ b/doc/README.NDS32
@@ -0,0 +1,41 @@
+NDS32 is a new high-performance 32-bit RISC microprocessor core.
+
+http://www.andestech.com/
+
+AndeStar ISA
+============
+AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
+achieve optimal system performance, code density, and power efficiency.
+
+It contains the following features:
+ - Intermixable 32-bit and 16-bit instruction sets without the need for
+   mode switch.
+ - 16-bit instructions as a frequently used subset of 32-bit instructions.
+ - RISC-style register-based instruction set.
+ - 32 32-bit General Purpose Registers (GPR).
+ - Upto 1024 User Special Registers (USR) for existing and extension
+   instructions.
+ - Rich load/store instructions for...
+   - Single memory access with base address update.
+   - Multiple aligned and unaligned memory accesses for memory copy and stack
+     operations.
+   - Data prefetch to improve data cache performance.
+   - Non-bus locking synchronization instructions.
+ - PC relative jump and PC read instructions for efficient position independent
+   code.
+ - Multiply-add and multiple-sub with 64-bit accumulator.
+ - Instruction for efficient power management.
+ - Bi-endian support.
+ - Three instruction extension space for application acceleration:
+   - Performance extension.
+   - Andes future extensions (for floating-point, multimedia, etc.)
+   - Customer extensions.
+
+AndesCore CPU
+=============
+Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
+
+For details about N12 CPU family, please check doc/README.N1213.
+
+The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
+other associated software are actively supported by Andes Technology Corporation.
diff --git a/doc/README.ag101 b/doc/README.ag101
new file mode 100644
index 0000000..46fc637
--- /dev/null
+++ b/doc/README.ag101
@@ -0,0 +1,74 @@
+Andes Technology SoC AG101
+==========================
+
+AG101 is the first SoC produced by Andes Technology using N1213 CPU core.
+AG101 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG101
+=========
+
+ADP-AG101 is the SoC with AG101 hardcore CPU.
+
+Please check http://www.andestech.com/p2-4.htm for detail of this SoC.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+	This is also a must on ADP-AG101 board.
+	(While other boards may not have this problem).
+
+	The reason is because the ROM/FLASH circuit on PCB board.
+	AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	ROM/FLASH is used to boot.
+
+	When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	and the FLASH is connected to BANK1.
+	When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	and the FLASH is connected to BANK0.
+	It will occur problem when doing flash probing if the flash is at
+	BANK0 (0x00000000) while memory remapping was skipped.
+
+	Other board like ADP-AG101P may not enable this since there is only
+	a FLASH connected to bank0.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from FLASH and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag101.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101` in u-boot root to build the image.
+
+burn u-boot to flash:
+1. Make sure the MA17 (J16) is Lo.
+2. Make sure the dip switch SW5 is set to "0101".
+3. Power On. Press button "S1", then press button "SW1", then you will found the
+   debug LED show 67 means the system successfully booted into e-bios.
+   Now you can control the e-bios boot loader from your console.
+4. Under "Command>>" prompt, enter "97" (CopyImageFromCard)
+5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c".
+6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you
+   just build. It is usually "u-boot.bin".
+7. Under "Enter Dest. Address =>" prompt, enter the memory address where you
+   want to put the binary from SD card to RAM.
+   Address "0x500000" is our suggestion.
+8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command
+   environment.
+9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the
+   binary from RAM to FLASH.
+10. Under "CLI>" prompt, enter "exit" to finish the burn process.
+
+boot u-boot from flash:
+1. Make sure the MA17 (J16) is Hi).
+2. Make sure the dip switch SW5 is set to "1010".
+3. Power On. Press button "S1", then you will see the debug LED count to 20.
+4. Now you can use u-boot on ADP-AG101 board.
diff --git a/doc/README.standalone b/doc/README.standalone
index 6e6b65f..2be5f27 100644
--- a/doc/README.standalone
+++ b/doc/README.standalone
@@ -56,6 +56,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
 	ARM		0x0c100000	0x0c100000
 	MIPS		0x80200000	0x80200000
 	Blackfin	0x00001000	0x00001000
+	NDS32		0x00300000	0x00300000
 	Nios II		0x02000000	0x02000000
 
    For example, the "hello world" application may be loaded and
-- 
1.7.3.5

[U-Boot] [PATCH v15 1/9] nds32: add header files support for nds32

[Macpaul Lin]

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code cleanup and style formatting.
Changes for v5-v6:
  - This patch also updated the following changes against the
    change after master tree (v2010.12-rc1).
  - fix upper case definitions in cache.h
  - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
  - Add readsb, writesb functions into io.h.
Changes for v7:
  - clean up
  - volatile:
   - types.h
    - remove typedef volatile unsigned char  vuchar;
    - remove typedef volatile unsigned long  vulong;
    - remove typedef volatile unsigned short vushort;
   - u-boot.h: remove bd_info_ext bi_ext
   - bitops.h: add accessor function to bit operation with volatile var.
   - system.h: add system.h for local_irq operation with flag.
Changes for v8:
  - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
  - ptregs.h: removed
Changes for v9:
  - No change.
Changes for v10:
  - macro.h: add writel and setbf macros
  - u-boot-nds32.h:
   - Remove obsolete andesboot_* symbols for relocation.
   - Add _bss_*_offset symbols for relocation.
  - config.h: add manual relocation support as default.
Changes for v11:
  - unaligned.h: replace asm/unaligned.h with asm-generic/unaligned.h
Changes for v12:
  - remove no used memory.h
  - remove seldom used bi_env parameter
  - u-boot-nds32.h:
   - remove duplicate timer_init()
Changes for v13-v14:
  - No change.
Changes for v15:
  - u-boot.h: fix for new image.h according to Mike's contribution.

 arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
 arch/nds32/include/asm/byteorder.h    |   36 +++
 arch/nds32/include/asm/cache.h        |   54 +++++
 arch/nds32/include/asm/config.h       |   28 +++
 arch/nds32/include/asm/global_data.h  |   89 +++++++
 arch/nds32/include/asm/io.h           |  409 +++++++++++++++++++++++++++++++++
 arch/nds32/include/asm/mach-types.h   |   29 +++
 arch/nds32/include/asm/macro.h        |   96 ++++++++
 arch/nds32/include/asm/posix_types.h  |   84 +++++++
 arch/nds32/include/asm/processor.h    |   25 ++
 arch/nds32/include/asm/ptrace.h       |   88 +++++++
 arch/nds32/include/asm/string.h       |   57 +++++
 arch/nds32/include/asm/system.h       |   88 +++++++
 arch/nds32/include/asm/types.h        |   63 +++++
 arch/nds32/include/asm/u-boot-nds32.h |   51 ++++
 arch/nds32/include/asm/u-boot.h       |   63 +++++
 arch/nds32/include/asm/unaligned.h    |    1 +
 17 files changed, 1447 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/bitops.h
 create mode 100644 arch/nds32/include/asm/byteorder.h
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/config.h
 create mode 100644 arch/nds32/include/asm/global_data.h
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/include/asm/mach-types.h
 create mode 100644 arch/nds32/include/asm/macro.h
 create mode 100644 arch/nds32/include/asm/posix_types.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/system.h
 create mode 100644 arch/nds32/include/asm/types.h
 create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
 create mode 100644 arch/nds32/include/asm/u-boot.h
 create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..c56f04b
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void *addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+extern void clear_bit(int nr, volatile void *addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, volatile void *addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, volatile void *addr);
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ	6	/* I-cache line size */
+#define ICM_CFG_MSK_ISZ	(0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
+#define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..6f654d9
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_NEEDS_MANUAL_RELOC
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..665266b
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+
+	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t	ram_size;	/* RAM size */
+	unsigned long	mon_len;	/* monitor len */
+	unsigned long	irq_sp;		/* irq stack pointer */
+	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	unsigned long	tlb_addr;
+#endif
+
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT		0x00004	/* Silent mode			*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	*/
+#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r10")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..45b9c2e
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,409 @@
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+#define writeb(v, a)			__arch_putb(v, a)
+#define writew(v, a)			__arch_putw(v, a)
+#define writel(v, a)			__arch_putl(v, a)
+
+#define readb(a)			__arch_getb(a)
+#define readw(a)			__arch_getw(a)
+#define readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache)				\
+({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
+	_ret;								\
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"), 0)
+#define readw(addr)			(__readwrite_bug("readw"), 0)
+#define readl(addr)			(__readwrite_bug("readl"), 0)
+#define writeb(v, addr)			__readwrite_bug("writeb")
+#define writew(v, addr)			__readwrite_bug("writew")
+#define writel(v, addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101             0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101()	(machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101()	(0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/macro.h b/arch/nds32/include/asm/macro.h
new file mode 100644
index 0000000..acda060
--- /dev/null
+++ b/arch/nds32/include/asm/macro.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-nds32/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NDS_MACRO_H
+#define __ASM_NDS_MACRO_H
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to an "immediate address (address used by periphal)" only.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any NDS32 architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	li	$r4, addr
+	li	$r5, data
+	swi	$r5, [$r4]
+.endm
+
+.macro	write16, addr, data
+	li	$r4, addr
+	li	$r5, data
+	shi	$r5, [$r4]
+.endm
+
+.macro	write8, addr, data
+	li	$r4, addr
+	li	$r5, data
+	sbi	$r5, [$r4]
+.endm
+
+/*
+ * This macro read a value from a register, then do OR operation
+ * (set bit fields) to the value, and then store it back to the register.
+ * Note: Instruction 'ori' supports immediate value up to 15 bits.
+ */
+.macro	setbf32, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	li	$r6, data
+	or	$r5, $r5, $r6
+	swi	$r5, [$r4]
+.endm
+
+.macro	setbf15, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	ori	$r5, $r5, data
+	swi	$r5, [$r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any NDS32 architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	li	$r4, time
+1:
+	nop
+	addi	$r4, $r4, -1
+	bnez    $r4, 1b
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..4336083
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+	NDS32_REG ir0;
+	NDS32_REG ipsw;
+	NDS32_REG ipc;
+	NDS32_REG sp;
+	NDS32_REG orig_r0;
+	NDS32_REG pipsw;
+	NDS32_REG pipc;
+	NDS32_REG pp0;
+	NDS32_REG pp1;
+	NDS32_REG d0hi;
+	NDS32_REG d0lo;
+	NDS32_REG d1hi;
+	NDS32_REG d1lo;
+	NDS32_REG r[26];	/* r0 - r25 */
+	NDS32_REG fp;		/* r28 */
+	NDS32_REG gp;		/* r29 */
+	NDS32_REG lp;		/* r30 */
+	NDS32_REG fucop_ctl;
+	NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+	(((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..ae1918d
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong __bss_start;	/* BSS start relative to _start */
+extern ulong __bss_end__;	/* BSS end relative to _start */
+extern ulong _end;		/* end of image relative to _start */
+extern ulong _start;		/* start of image relative to _start */
+extern ulong _TEXT_BASE;	/* code start */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..9a69750
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <environment.h>
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_NDS32
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
-- 
1.7.3.5

[U-Boot] [PATCH v15 1/9] nds32: add header files support for nds32

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1317896723-9284-1-git-send-email-macpaul@andestech.com> you wrote:
> Add generic header files support for nds32 architecture.
> Cache, ptregs, data type and other definitions are included.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v4:
>   - Code cleanup and style formatting.
> Changes for v5-v6:
>   - This patch also updated the following changes against the
>     change after master tree (v2010.12-rc1).
>   - fix upper case definitions in cache.h
>   - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
>   - Add readsb, writesb functions into io.h.
> Changes for v7:
>   - clean up
>   - volatile:
>    - types.h
>     - remove typedef volatile unsigned char  vuchar;
>     - remove typedef volatile unsigned long  vulong;
>     - remove typedef volatile unsigned short vushort;
>    - u-boot.h: remove bd_info_ext bi_ext
>    - bitops.h: add accessor function to bit operation with volatile var.
>    - system.h: add system.h for local_irq operation with flag.
> Changes for v8:
>   - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
>   - ptregs.h: removed
> Changes for v9:
>   - No change.
> Changes for v10:
>   - macro.h: add writel and setbf macros
>   - u-boot-nds32.h:
>    - Remove obsolete andesboot_* symbols for relocation.
>    - Add _bss_*_offset symbols for relocation.
>   - config.h: add manual relocation support as default.
> Changes for v11:
>   - unaligned.h: replace asm/unaligned.h with asm-generic/unaligned.h
> Changes for v12:
>   - remove no used memory.h
>   - remove seldom used bi_env parameter
>   - u-boot-nds32.h:
>    - remove duplicate timer_init()
> Changes for v13-v14:
>   - No change.
> Changes for v15:
>   - u-boot.h: fix for new image.h according to Mike's contribution.
> 
>  arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
>  arch/nds32/include/asm/byteorder.h    |   36 +++
>  arch/nds32/include/asm/cache.h        |   54 +++++
>  arch/nds32/include/asm/config.h       |   28 +++
>  arch/nds32/include/asm/global_data.h  |   89 +++++++
>  arch/nds32/include/asm/io.h           |  409 +++++++++++++++++++++++++++++++++
>  arch/nds32/include/asm/mach-types.h   |   29 +++
>  arch/nds32/include/asm/macro.h        |   96 ++++++++
>  arch/nds32/include/asm/posix_types.h  |   84 +++++++
>  arch/nds32/include/asm/processor.h    |   25 ++
>  arch/nds32/include/asm/ptrace.h       |   88 +++++++
>  arch/nds32/include/asm/string.h       |   57 +++++
>  arch/nds32/include/asm/system.h       |   88 +++++++
>  arch/nds32/include/asm/types.h        |   63 +++++
>  arch/nds32/include/asm/u-boot-nds32.h |   51 ++++
>  arch/nds32/include/asm/u-boot.h       |   63 +++++
>  arch/nds32/include/asm/unaligned.h    |    1 +
>  17 files changed, 1447 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/include/asm/bitops.h
>  create mode 100644 arch/nds32/include/asm/byteorder.h
>  create mode 100644 arch/nds32/include/asm/cache.h
>  create mode 100644 arch/nds32/include/asm/config.h
>  create mode 100644 arch/nds32/include/asm/global_data.h
>  create mode 100644 arch/nds32/include/asm/io.h
>  create mode 100644 arch/nds32/include/asm/mach-types.h
>  create mode 100644 arch/nds32/include/asm/macro.h
>  create mode 100644 arch/nds32/include/asm/posix_types.h
>  create mode 100644 arch/nds32/include/asm/processor.h
>  create mode 100644 arch/nds32/include/asm/ptrace.h
>  create mode 100644 arch/nds32/include/asm/string.h
>  create mode 100644 arch/nds32/include/asm/system.h
>  create mode 100644 arch/nds32/include/asm/types.h
>  create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
>  create mode 100644 arch/nds32/include/asm/u-boot.h
>  create mode 100644 arch/nds32/include/asm/unaligned.h

Checkpatch says:

total: 8 errors, 58 warnings, 1447 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The easiest way to figure the cost of living is to take  your  income
and add ten percent.

[U-Boot] [PATCH v15 1/9] nds32: add header files support for nds32

[馬克泡]

Dear Wolfgang,

2011/10/7 Wolfgang Denk <wd@denx.de>:
> Dear Macpaul Lin,
>
> In message <1317896723-9284-1-git-send-email-macpaul@andestech.com> you wrote:
>> Add generic header files support for nds32 architecture.
>> Cache, ptregs, data type and other definitions are included.
>>
>> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
...
>> Changes for v15:
>> ? - u-boot.h: fix for new image.h according to Mike's contribution.

I believe you must be exhausted for reviewing these patches again and again.

However, we've discussed before, to support a new architecture, there
are some definitions
and codes which the checkpatch rules cannot be adapted.
For example, some typedefs definitions, special asm syntax, and those
special cases described
in Linux documents, and u-boot's typedef global structures.
ex: http://www.mail-archive.com/u-boot at lists.denx.de/msg52083.html

We've also discussed that Linux documents said checkpatch is just a
reference rule,
you still need to have human examination.
I guess you just forget that because the patch "works" is too heavy
and patch check
automation didn't help on special case much.

When we discuss about those was about NDS32 patch v7, and now is patch v15.
We've to a lot of fix, includes relocation.

So, could you please tell me now, should I resend the patch v16 or you
still have my v15
patches and kindly tell me which part need to be fixed? Thanks!

>
> Checkpatch says:
>
> total: 8 errors, 58 warnings, 1447 lines checked
>
> Please clean up and resubmit. ?Thanks.
>
> Best regards,
>
> Wolfgang Denk
>

Note:
The 8 errors is due to the new assembly march.h added.
Only 2 new cases introduced.

ERROR: space prohibited before open square bracket '['
#1032: FILE: arch/nds32/include/asm/macro.h:66:
+       lwi     $r5, [$r4]
This is to load a 32bit from the address x, while the value of
address x is stored in $r4, and load it into $r5

ERROR: spaces required around that ':' (ctx:VxE)
#1055: FILE: arch/nds32/include/asm/macro.h:89:
+1:
  ^
The original form is like this:

.macro  wait_timer, time
        li      $r4, time
1: <--------Checkpatch indicates error here. However this should be
checkpatch's fault.
        nop
        addi    $r4, $r4, -1
        bnez    $r4, 1b
.endm


Thanks!

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v15 1/9] nds32: add header files support for nds32

[Wolfgang Denk]

Dear =?UTF-8?B?6aas5YWL5rOh?=,

In message <CACCg+XM0r0z0Xm1C9zu9Zc4bJ+sX5b2Gv3w_v5eBjOVX9AsTbA@mail.gmail.com> you wrote:
> 
> I believe you must be exhausted for reviewing these patches again and again.

Not yet - actually I'm playing with doing such things in a mostly
automated way.

> However, we've discussed before, to support a new architecture, there
> are some definitions
> and codes which the checkpatch rules cannot be adapted.

First, we can adapt chackpatch rules.  It just needs to be done.

> We've also discussed that Linux documents said checkpatch is just a
> reference rule,

I'dlike to see checkpatch customized for our needs.  The tools to do
that are in place now.

> you still need to have human examination.

Indeed.

> I guess you just forget that because the patch "works" is too heavy
> and patch check
> automation didn't help on special case much.

I manually inspected all output before actually sending any messages
out.

> When we discuss about those was about NDS32 patch v7, and now is patch v15.
> We've to a lot of fix, includes relocation.
>
> So, could you please tell me now, should I resend the patch v16 or you
> still have my v15
> patches and kindly tell me which part need to be fixed? Thanks!

There is a large number of WARNING: Use of volatile is usually wrong;
I think you bit macros and I/O accessors should be cleaned up. I don;t
want to see volatile there.

WARNING: line over 80 characters needs to be fixed, obviously.


> The 8 errors is due to the new assembly march.h added.
> Only 2 new cases introduced.
>
> ERROR: space prohibited before open square bracket '['
> #1032: FILE: arch/nds32/include/asm/macro.h:66:
> +       lwi     $r5, [$r4]
> This is to load a 32bit from the address x, while the value of
> address x is stored in $r4, and load it into $r5
>
> ERROR: spaces required around that ':' (ctx:VxE)
> #1055: FILE: arch/nds32/include/asm/macro.h:89:
> +1:
>   ^

I agree that we can ignore these (or rather try and add exception
rules).


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"The number  of  Unix  installations  has  grown  to  10,  with  more
expected."    - The Unix Programmer's Manual, 2nd Edition, June, 1972

[U-Boot] [PATCH v15 1/9] nds32: add header files support for nds32

[馬克泡]

Dear Wolfgang,

2011/10/7 Wolfgang Denk <wd@denx.de>:
> Dear =?UTF-8?B?6aas5YWL5rOh?=,
>
>> However, we've discussed before, to support a new architecture, there
>> are some definitions
>> and codes which the checkpatch rules cannot be adapted.
>
> First, we can adapt chackpatch rules. ?It just needs to be done.
>
>> We've also discussed that Linux documents said checkpatch is just a
>> reference rule,
>
> I'dlike to see checkpatch customized for our needs. ?The tools to do
> that are in place now.
>

Agreed.

>> you still need to have human examination.
>
> Indeed.
>
>> I guess you just forget that because the patch "works" is too heavy
>> and patch check
>> automation didn't help on special case much.
>
> I manually inspected all output before actually sending any messages
> out.
>
>> When we discuss about those was about NDS32 patch v7, and now is patch v15.
>> We've to a lot of fix, includes relocation.
>>
>> So, could you please tell me now, should I resend the patch v16 or you
>> still have my v15
>> patches and kindly tell me which part need to be fixed? Thanks!
>
> There is a large number of WARNING: Use of volatile is usually wrong;
> I think you bit macros and I/O accessors should be cleaned up. I don;t
> want to see volatile there.

About the volatiles and IO accessors, as said and we've discussed
before according to
"Documentation/volatile-considered-harmful.txt". There are still four
kinds of volatiles are still
necessary. Let me copy the exceptions from
"Documentation/volatile-considered-harmful.txt" as follows.

Please give comment on volatiles which are need and should not be get
rid of these. Thanks!

"There are still a few rare situations where volatile makes sense in the
kernel:
- The above-mentioned accessor functions might use volatile on
  architectures where direct I/O memory access does work.  Essentially,
  each accessor call becomes a little critical section on its own and
  ensures that the access happens as expected by the programmer.

- Inline assembly code which changes memory, but which has no other
  visible side effects, risks being deleted by GCC.  Adding the volatile
  keyword to asm statements will prevent this removal.

- The jiffies variable is special in that it can have a different value
  every time it is referenced, but it can be read without any special
  locking.  So jiffies can be volatile, but the addition of other
  variables of this type is strongly frowned upon.  Jiffies is considered
  to be a "stupid legacy" issue (Linus's words) in this regard; fixing it
  would be more trouble than it is worth.

- Pointers to data structures in coherent memory which might be modified
  by I/O devices can, sometimes, legitimately be volatile.  A ring buffer
  used by a network adapter, where that adapter changes pointers to
  indicate which descriptors have been processed, is an example of this
  type of situation."

I think volatiles which like the following should be necessary
according to the 4 exceptions listed in the document
"Documentation/volatile-considered-harmful.txt".

WARNING: Use of volatile is usually wrong: see
Documentation/volatile-considered-harmful.txt
#124: FILE: arch/nds32/include/asm/bitops.h:31:
+extern void set_bit(int nr, volatile void *addr);

WARNING: Use of volatile is usually wrong: see
Documentation/volatile-considered-harmful.txt
#126: FILE: arch/nds32/include/asm/bitops.h:33:
+static inline void __set_bit(int nr, volatile void *addr)

WARNING: Use of volatile is usually wrong: see
Documentation/volatile-considered-harmful.txt
#594: FILE: arch/nds32/include/asm/io.h:78:
+#define __arch_getw(a)                 (*(volatile unsigned short *)(a))

WARNING: Use of volatile is usually wrong: see
Documentation/volatile-considered-harmful.txt
#142: FILE: examples/standalone/x86-testapp.c:86:
+       register volatile xxx_t *pq asm("$r16");

> WARNING: line over 80 characters needs to be fixed, obviously.
>

Sorry about this, but the 80 characters formatting is for human
reading. To fix some of the lines exceeds
80 characters made me feel the code has become less human readable.
For example:
WARNING: line over 80 characters
#824: FILE: arch/nds32/include/asm/io.h:308:
+#define readw(c) ({ unsigned int __v =
le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })

WARNING: line over 80 characters
#932: FILE: arch/nds32/include/asm/arch-ag101/ag101.h:26:
+#define CONFIG_FTSMC020_BASE           0x90200000      /* Static
Memory Controller (SRAM) */

WARNING: line over 80 characters (Comment and offset for a SoC).
#933: FILE: arch/nds32/include/asm/arch-ag101/ag101.h:27:
+#define CONFIG_FTSDMC021_BASE          0x90300000      /*
FTSDMC020/021 SDRAM Controller */

WARNING: line over 80 characters (to made this align with other architectures).
#132: FILE: examples/standalone/x86-testapp.c:63:
+       : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void
*)) : "$r16");

I can do fix for these lines over 80 characters but I think the add-on
codes might be less readable.

>> The 8 errors is due to the new assembly march.h added.
>> Only 2 new cases introduced.
>>
>> ERROR: space prohibited before open square bracket '['
>> #1032: FILE: arch/nds32/include/asm/macro.h:66:
>> + ? ? ? lwi ? ? $r5, [$r4]
>> This is to load a 32bit from the address x, while the value of
>> address x is stored in $r4, and load it into $r5
>>
>> ERROR: spaces required around that ':' (ctx:VxE)
>> #1055: FILE: arch/nds32/include/asm/macro.h:89:
>> +1:
>> ? ^
>
> I agree that we can ignore these (or rather try and add exception
> rules).
>
>
> Best regards,
>
> Wolfgang Denk

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v15 1/9] nds32: add header files support for nds32

[Wolfgang Denk]

Dear =?UTF-8?B?6aas5YWL5rOh?=,

In message <CACCg+XMDNyxa5-rAdvj=oG8yhmFAkiD8OZzhZE+-ThFXcT6sfQ@mail.gmail.com> you wrote:
>
> I think volatiles which like the following should be necessary
> according to the 4 exceptions listed in the document
> "Documentation/volatile-considered-harmful.txt".
> 
> WARNING: Use of volatile is usually wrong: see
> Documentation/volatile-considered-harmful.txt
> #124: FILE: arch/nds32/include/asm/bitops.h:31:
> +extern void set_bit(int nr, volatile void *addr);
> 
> WARNING: Use of volatile is usually wrong: see
> Documentation/volatile-considered-harmful.txt
> #126: FILE: arch/nds32/include/asm/bitops.h:33:
> +static inline void __set_bit(int nr, volatile void *addr)

If you look at the implementations of these functions, they need
explicit casts to actually get rid of the "volatile" attribute.
So why would there be any need to pass it in the first place?

> WARNING: Use of volatile is usually wrong: see
> Documentation/volatile-considered-harmful.txt
> #594: FILE: arch/nds32/include/asm/io.h:78:
> +#define __arch_getw(a)                 (*(volatile unsigned short *)(a))

I disagree with this code for several reasons.

First, it should be turned into a (inline) function, so the compiler
can actually verify the type of the argument and make sure it is
indeed a 16 bit pointer.

Second, please check and re-check if there is really no kind of memry
barrier instruction needed here.  And even if there is no such need, I
tend belive that adding some __iormb(); similar to whay is done for
example in "arch/arm/include/asm/io.h" would still be a good idea.

If the actual access goes through dereferencing a volatile pointer,
this should be hidden at the lowest level of the implementation.

> WARNING: Use of volatile is usually wrong: see
> Documentation/volatile-considered-harmful.txt
> #142: FILE: examples/standalone/x86-testapp.c:86:
> +       register volatile xxx_t *pq asm("$r16");

I don;t know this code, so I cannot comment onthis.

> > WARNING: line over 80 characters needs to be fixed, obviously.
> 
> Sorry about this, but the 80 characters formatting is for human
> reading. To fix some of the lines exceeds
> 80 characters made me feel the code has become less human readable.

If you don't fix it, then the text will wrap around in a completely
uncontrolled way depending on the window width.  This is even worse.

> For example:
> WARNING: line over 80 characters
> #824: FILE: arch/nds32/include/asm/io.h:308:
> +#define readw(c) ({ unsigned int __v =
> le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })

#define readw(c) ({					\
	unsigned int __v				\
							\
	__v = le16_to_cpu(__raw_readw(__mem_pci(c)))	\
})

> WARNING: line over 80 characters
> #932: FILE: arch/nds32/include/asm/arch-ag101/ag101.h:26:
> +#define CONFIG_FTSMC020_BASE           0x90200000      /* Static
> Memory Controller (SRAM) */

/* Static Memory Controller (SRAM) */
#define CONFIG_FTSMC020_BASE		0x90200000

etc.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It's certainly  convenient  the  way  the  crime  (or  condition)  of
stupidity   carries   with   it  its  own  punishment,  automatically
admisistered without remorse, pity, or prejudice. :-)
         -- Tom Christiansen in <559seq$ag1$1@csnews.cs.colorado.edu>

[U-Boot] [PATCH v15 1/9] nds32: add header files support for nds32

[馬克泡]

Hi Wolfgang,

2011/10/11 Wolfgang Denk <wd@denx.de>:
> Dear =?UTF-8?B?6aas5YWL5rOh?=,
>
> In message <CACCg+XMDNyxa5-rAdvj=oG8yhmFAkiD8OZzhZE+-ThFXcT6sfQ@mail.gmail.com> you wrote:
>>
>> I think volatiles which like the following should be necessary
>> according to the 4 exceptions listed in the document
>> "Documentation/volatile-considered-harmful.txt".
>>
>> WARNING: Use of volatile is usually wrong: see
>> Documentation/volatile-considered-harmful.txt
>> #124: FILE: arch/nds32/include/asm/bitops.h:31:
>> +extern void set_bit(int nr, volatile void *addr);
>>
>> WARNING: Use of volatile is usually wrong: see
>> Documentation/volatile-considered-harmful.txt
>> #126: FILE: arch/nds32/include/asm/bitops.h:33:
>> +static inline void __set_bit(int nr, volatile void *addr)
>
> If you look at the implementations of these functions, they need
> explicit casts to actually get rid of the "volatile" attribute.
> So why would there be any need to pass it in the first place?
>

[deleted]

Understood, will fix them in the next series of patches.
Thanks.


-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v16 1/9] nds32: add header files support for nds32

[Macpaul Lin]

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code cleanup and style formatting.
Changes for v5-v6:
  - This patch also updated the following changes against the
    change after master tree (v2010.12-rc1).
  - fix upper case definitions in cache.h
  - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
  - Add readsb, writesb functions into io.h.
Changes for v7:
  - clean up
  - volatile:
   - types.h
    - remove typedef volatile unsigned char  vuchar;
    - remove typedef volatile unsigned long  vulong;
    - remove typedef volatile unsigned short vushort;
   - u-boot.h: remove bd_info_ext bi_ext
   - bitops.h: add accessor function to bit operation with volatile var.
   - system.h: add system.h for local_irq operation with flag.
Changes for v8:
  - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
  - ptregs.h: removed
Changes for v9:
  - No change.
Changes for v10:
  - macro.h: add writel and setbf macros
  - u-boot-nds32.h:
   - Remove obsolete andesboot_* symbols for relocation.
   - Add _bss_*_offset symbols for relocation.
  - config.h: add manual relocation support as default.
Changes for v11:
  - unaligned.h: replace asm/unaligned.h with asm-generic/unaligned.h
Changes for v12:
  - remove no used memory.h
  - remove seldom used bi_env parameter
  - u-boot-nds32.h:
   - remove duplicate timer_init()
Changes for v13-v14:
  - No change.
Changes for v15:
  - u-boot.h: fix for new image.h according to Mike's contribution.
Changes for v16:
  - asm/io.h:
   - fix line over 80 characters.
   - remove volatiles for __arch_getb
  - asm/bitops.h: remove volatiles for inline __set_bit()
  - asm/global_data.h: fix line over 80 characters.

 arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
 arch/nds32/include/asm/byteorder.h    |   36 +++
 arch/nds32/include/asm/cache.h        |   54 +++++
 arch/nds32/include/asm/config.h       |   28 +++
 arch/nds32/include/asm/global_data.h  |   89 +++++++
 arch/nds32/include/asm/io.h           |  412 +++++++++++++++++++++++++++++++++
 arch/nds32/include/asm/mach-types.h   |   29 +++
 arch/nds32/include/asm/macro.h        |   96 ++++++++
 arch/nds32/include/asm/posix_types.h  |   84 +++++++
 arch/nds32/include/asm/processor.h    |   25 ++
 arch/nds32/include/asm/ptrace.h       |   88 +++++++
 arch/nds32/include/asm/string.h       |   57 +++++
 arch/nds32/include/asm/system.h       |   88 +++++++
 arch/nds32/include/asm/types.h        |   63 +++++
 arch/nds32/include/asm/u-boot-nds32.h |   51 ++++
 arch/nds32/include/asm/u-boot.h       |   63 +++++
 arch/nds32/include/asm/unaligned.h    |    1 +
 17 files changed, 1450 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/bitops.h
 create mode 100644 arch/nds32/include/asm/byteorder.h
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/config.h
 create mode 100644 arch/nds32/include/asm/global_data.h
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/include/asm/mach-types.h
 create mode 100644 arch/nds32/include/asm/macro.h
 create mode 100644 arch/nds32/include/asm/posix_types.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/system.h
 create mode 100644 arch/nds32/include/asm/types.h
 create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
 create mode 100644 arch/nds32/include/asm/u-boot.h
 create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..f1aa9a3
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, void *addr);
+
+static inline void __set_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+extern void clear_bit(int nr, void *addr);
+
+static inline void __clear_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, void *addr);
+
+static inline void __change_bit(int nr, void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, void *addr);
+
+static inline int __test_and_set_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, void *addr);
+
+static inline int __test_and_clear_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, void *addr);
+
+static inline int __test_and_change_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ	6	/* I-cache line size */
+#define ICM_CFG_MSK_ISZ	(0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
+#define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..6f654d9
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_NEEDS_MANUAL_RELOC
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..de20a0a
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+
+	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t	ram_size;	/* RAM size */
+	unsigned long	mon_len;	/* monitor len */
+	unsigned long	irq_sp;		/* irq stack pointer */
+	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	unsigned long	tlb_addr;
+#endif
+
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT		0x00004	/* Silent mode			*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	*/
+#define GD_FLG_ENV_READY	0x00080	/* Envs imported into hash table */
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r10")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..2504c2b
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,412 @@
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(unsigned char *)(a))
+#define __arch_getw(a)			(*(unsigned short *)(a))
+#define __arch_getl(a)			(*(unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+#define writeb(v, a)			__arch_putb(v, a)
+#define writew(v, a)			__arch_putw(v, a)
+#define writel(v, a)			__arch_putl(v, a)
+
+#define readb(a)			__arch_getb(a)
+#define readw(a)			__arch_getw(a)
+#define readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache)				\
+({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
+	_ret;								\
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = \
+			__raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = \
+			le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = \
+			le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"), 0)
+#define readw(addr)			(__readwrite_bug("readw"), 0)
+#define readl(addr)			(__readwrite_bug("readl"), 0)
+#define writeb(v, addr)			__readwrite_bug("writeb")
+#define writew(v, addr)			__readwrite_bug("writew")
+#define writel(v, addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101             0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101()	(machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101()	(0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/macro.h b/arch/nds32/include/asm/macro.h
new file mode 100644
index 0000000..acda060
--- /dev/null
+++ b/arch/nds32/include/asm/macro.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-nds32/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NDS_MACRO_H
+#define __ASM_NDS_MACRO_H
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to an "immediate address (address used by periphal)" only.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any NDS32 architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	li	$r4, addr
+	li	$r5, data
+	swi	$r5, [$r4]
+.endm
+
+.macro	write16, addr, data
+	li	$r4, addr
+	li	$r5, data
+	shi	$r5, [$r4]
+.endm
+
+.macro	write8, addr, data
+	li	$r4, addr
+	li	$r5, data
+	sbi	$r5, [$r4]
+.endm
+
+/*
+ * This macro read a value from a register, then do OR operation
+ * (set bit fields) to the value, and then store it back to the register.
+ * Note: Instruction 'ori' supports immediate value up to 15 bits.
+ */
+.macro	setbf32, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	li	$r6, data
+	or	$r5, $r5, $r6
+	swi	$r5, [$r4]
+.endm
+
+.macro	setbf15, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	ori	$r5, $r5, data
+	swi	$r5, [$r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any NDS32 architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	li	$r4, time
+1:
+	nop
+	addi	$r4, $r4, -1
+	bnez    $r4, 1b
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..4336083
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+	NDS32_REG ir0;
+	NDS32_REG ipsw;
+	NDS32_REG ipc;
+	NDS32_REG sp;
+	NDS32_REG orig_r0;
+	NDS32_REG pipsw;
+	NDS32_REG pipc;
+	NDS32_REG pp0;
+	NDS32_REG pp1;
+	NDS32_REG d0hi;
+	NDS32_REG d0lo;
+	NDS32_REG d1hi;
+	NDS32_REG d1lo;
+	NDS32_REG r[26];	/* r0 - r25 */
+	NDS32_REG fp;		/* r28 */
+	NDS32_REG gp;		/* r29 */
+	NDS32_REG lp;		/* r30 */
+	NDS32_REG fucop_ctl;
+	NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+	(((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..ae1918d
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong __bss_start;	/* BSS start relative to _start */
+extern ulong __bss_end__;	/* BSS end relative to _start */
+extern ulong _end;		/* end of image relative to _start */
+extern ulong _start;		/* start of image relative to _start */
+extern ulong _TEXT_BASE;	/* code start */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..9a69750
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <environment.h>
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_NDS32
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
-- 
1.7.3.5

[U-Boot] [PATCH v16 1/9] nds32: add header files support for nds32

[馬克泡]

Hi Wolfgang,

2011/10/12 Macpaul Lin <macpaul@andestech.com>:
> Add generic header files support for nds32 architecture.
> Cache, ptregs, data type and other definitions are included.
>
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Just wondering if you have comment to these patch v16.
I've fixed volatiles which complained  by checkpatch.pl in v16.
However, now I have to fix patch v16 to patch v17 because architecture
Sandbox has
been add into mainline. And now I'm waiting for if Sandbox if they
have more thing need
to be added in common/image.c.

Hope you can give comment for patch v16 hence I can to fix within patch v17.

Thanks!

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v16 1/9] nds32: add header files support for nds32

[Simon Glass]

Hi,

On Tue, Oct 18, 2011 at 1:36 AM, ??? <macpaul@gmail.com> wrote:
> Hi Wolfgang,
>
> 2011/10/12 Macpaul Lin <macpaul@andestech.com>:
>> Add generic header files support for nds32 architecture.
>> Cache, ptregs, data type and other definitions are included.
>>
>> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
>
> Just wondering if you have comment to these patch v16.
> I've fixed volatiles which complained ?by checkpatch.pl in v16.
> However, now I have to fix patch v16 to patch v17 because architecture
> Sandbox has
> been add into mainline. And now I'm waiting for if Sandbox if they
> have more thing need
> to be added in common/image.c.

No plans to do so at present - please go ahead.

Regards,
Simon

>
> Hope you can give comment for patch v16 hence I can to fix within patch v17.
>
> Thanks!
>
> --
> Best regards,
> Macpaul Lin
>

[U-Boot] [PATCH v16 2/9] nds32: add NDS32 support into common header file

[Macpaul Lin]

Add NDS32 support into common header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v7:
  - No change
Changes for v8:
  - Fix the patch according to dependency of x86's Fix
Changes for v9-v16:
  - No change

 include/common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index bcc00e8..42b00a0 100644
--- a/include/common.h
+++ b/include/common.h
@@ -302,6 +302,10 @@ int	setenv	     (const char *, const char *);
 #ifdef CONFIG_X86		/* x86 version to be fixed! */
 # include <asm/u-boot-x86.h>
 #endif /* CONFIG_X86 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h>	/* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
-- 
1.7.3.5

[U-Boot] [PATCH v16 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Macpaul Lin]

Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
Changes v1 to v6:
  - Style clean up and reorganize code
Changes v7-v9:
  - No Change.
Changes v10:
  - start.S of N1213 CPU has been rewrote for relocation support.
  - u-boot.lds:
   - Add got and *(.got.plt) section for support GCC 4 toolchain
   - Modified for relocation implementation.
Changes v11:
  - arch/nds32/cpu/n1213/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes v12:
  - u-boot.lds
   - Remove the 0x00000000 base address in linker script.
     The base address of the binary will be determined by CONFIG_SYS_TEXT_BASE
  - Remove the CPU features in commit log and add to README in later patches.
Changes v13-v14:
  - No change.
Changes v15:
  - start.S: fix exception vector aligment (add setivb in reset vector).
Changes v16:
  - start.S: remove lines over 80 characters.

 arch/nds32/cpu/n1213/Makefile   |   50 ++++
 arch/nds32/cpu/n1213/start.S    |  529 +++++++++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/u-boot.lds |   70 +++++
 3 files changed, 649 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/Makefile
 create mode 100644 arch/nds32/cpu/n1213/start.S
 create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..da15574
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..e778e65
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,529 @@
+/*
+ *	Andesboot - Startup Code for Whitiger core
+ *
+ *	Copyright (C) 2006	Andes Technology Corporation
+ *	Copyright (C) 2006	Shawn Lin <nobuhiro@andestech.com>
+ *	Copyright (C) 2011	Macpaul Lin <macpaul@andestech.com>
+ *				Greentime Hu <greentime@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <asm/macro.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC		2UL
+#define DIS_DCAC		~ENA_DCAC
+#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
+#define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
+#define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY	(0x07<<3)	! D cache ways
+#define DCAC_MEM_KBF_DSZ	(0x07<<6)	! D cache line size
+
+#define PSW			$ir0
+#define EIT_INTR_PSW		$ir1		! interruption $PSW
+#define EIT_PREV_IPSW		$ir2		! previous $IPSW
+#define EIT_IVB			$ir3		! intr vector base address
+#define EIT_EVA			$ir4		! MMU related Exception VA reg
+#define EIT_PREV_EVA		$ir5		! previous $eva
+#define EIT_ITYPE		$ir6		! interruption type
+#define EIT_PREV_ITYPE		$ir7		! prev intr type
+#define EIT_MACH_ERR		$ir8		! machine error log
+#define EIT_INTR_PC		$ir9		! Interruption PC
+#define EIT_PREV_IPC		$ir10		! previous $IPC
+#define EIT_OVL_INTR_PC		$ir11		! overflow interruption PC
+#define EIT_PREV_P0		$ir12		! prev $P0
+#define EIT_PREV_P1		$ir13		! prev $p1
+#define CR_ICAC_MEM		$cr1		! I-cache/memory config reg
+#define CR_DCAC_MEM		$cr2		! D-cache/memory config reg
+#define MR_CAC_CTL		$mr8
+
+.globl _start
+
+_start:	j	reset
+	j	tlb_fill
+	j	tlb_not_present
+	j	tlb_misc
+	j	tlb_vlpt_miss
+	j	cache_parity_error
+	j	debug
+	j	general_exception
+	j	internal_interrupt		! H0I
+	j	internal_interrupt		! H1I
+	j	internal_interrupt		! H2I
+	j	internal_interrupt		! H3I
+	j	internal_interrupt		! H4I
+	j	internal_interrupt		! H5I
+
+	.balign 16
+
+/*
+ * Andesboot Startup Code (reset vector)
+ *
+ *	1.	bootstrap
+ *		1.1 reset - start of u-boot
+ *		1.2 to superuser mode - as is when reset
+ *		1.4 Do lowlevel_init
+ *			- (this will jump out to lowlevel_init.S in SoC)
+ *			- (lowlevel_init)
+ *		1.3 Turn off watchdog timer
+ *			- (this will jump out to watchdog.S in SoC)
+ *			- (turnoff_watchdog)
+ *	2.	Do critical init when reboot (not from mem)
+ *	3.	Relocate andesboot to ram
+ *	4.	Setup stack
+ *	5.	Jump to second stage (board_init_r)
+ */
+
+/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word 0x0badc0de
+
+/*
+ * The bootstrap code of nds32 core
+ */
+
+reset:
+set_ivb:
+	li	$r0, 0x0
+
+	/* turn on BTB */
+	mtsr	$r0, $misc_ctl
+	/* set IVIC, vector size: 4 bytes, base: 0x0 */
+	mtsr	$r0, $ivb
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	jal	load_lowlevel_init
+	jral	$p0
+#endif
+
+/*
+ * Set the N1213 (Whitiger) core to superuser mode
+ * According to spec, it is already when reset
+ */
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+	jal	load_turnoff_watchdog
+	jral	$p0
+#endif
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+	bal	cpu_init_crit		! Do CPU critical regs init
+#endif
+
+/*
+ * Set stackpointer in internal RAM to call board_init_f
+ * $sp must be 8-byte alignment for ABI compliance.
+ */
+call_board_init_f:
+	li	$sp, CONFIG_SYS_INIT_SP_ADDR
+	li	$r0, 0x00000000
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__
+/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
+	la	$r15, board_init_f	! store function address into $r15
+#endif
+#endif
+	j	board_init_f		! jump to board_init_f() in lib/board.c
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl	relocate_code
+relocate_code:
+	move	$r4, $r0		/* save addr_sp */
+	move	$r5, $r1		/* save addr of gd */
+	move	$r6, $r2		/* save addr of destination */
+
+/* Set up the stack */
+stack_setup:
+	move	$sp, $r4
+
+	la	$r0, _start
+
+	beq	$r0, $r6, clear_bss	/* skip relocation */
+
+	move	$r1, $r6		/* r1 <- scratch for copy_loop */
+	la	$r3, __bss_start
+	sub	$r3, $r3, $r0		/* r3 <- __bss_start_ofs */
+	add	$r2, $r0, $r3		/* r2 <- source end address */
+
+copy_loop:
+	lwi.p	$r7, [$r0], #4
+	swi.p	$r7, [$r1], #4
+	blt	$r0, $r2, copy_loop
+
+/*
+ * fix relocations related issues
+ */
+fix_relocations:
+	l.w	$r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	$r9, $r6, $r0		/* r9 <- relocation offset */
+
+fix_got:
+/*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+	la	$r2, __got_start	/* r2 <- rel __got_start in FLASH */
+	add	$r2, $r2, $r9		/* r2 <- rel __got_start in RAM */
+	la	$r3, __got_end		/* r3 <- rel __got_end in FLASH */
+	add	$r3, $r3, $r9		/* r3 <- rel __got_end in RAM */
+	addi	$r2, $r2, #8		/* skipping first two entries */
+fix_got_loop:
+	lwi	$r0, [$r2]		/* r0 <- location in FLASH to fix up */
+	add	$r0, $r0, $r9		/* r0 <- location fix up to RAM */
+	swi.p	$r0, [$r2], #4		/* r0 <- store fix into .got in RAM */
+	blt	$r2, $r3, fix_got_loop
+
+clear_bss:
+	la	$r0, __bss_start	/* r0 <- rel __bss_start in FLASH */
+	add	$r0, $r0, $r9		/* r0 <- rel __bss_start in FLASH */
+	la	$r1, __bss_end__	/* r1 <- rel __bss_end in RAM */
+	add	$r1, $r1, $r9		/* r0 <- rel __bss_end in RAM */
+	li	$r2, 0x00000000		/* clear */
+
+clbss_l:
+	sw	$r2, [$r0]		/* clear loop... */
+	addi	$r0, $r0, #4
+	bne	$r0, $r1, clbss_l
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+	la	$r0, board_init_r
+	move	$lp, $r0		/* offset of board_init_r() */
+	add	$lp, $lp, $r9		/* real address of board_init_r() */
+	/* setup parameters for board_init_r */
+	move	$r0, $r5		/* gd_t */
+	move	$r1, $r6		/* dest_addr */
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__		/* NDS32 V0 ISA	*/
+	move	$r15, $lp		/* store function address into $r15 */
+#endif
+#endif
+
+	/* jump to it ... */
+	jr	$lp			/* jump to board_init_r() */
+
+/*
+ * Initialize CPU critical registers
+ *
+ *	1.	Setup control registers
+ *		1.1 Mask all IRQs
+ *		1.2 Flush cache and TLB
+ *		1.3 Disable MMU and cache
+ *	2.	Setup memory timing
+ */
+
+cpu_init_crit:
+
+	move	$r0, $lp		/* push	ra */
+
+	/* Disable Interrupts by clear GIE in $PSW reg */
+	setgie.d
+
+	/* Flush caches and TLB */
+	/* Invalidate caches */
+	bal	invalidate_icac
+	bal	invalidate_dcac
+
+	/* Flush TLB */
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+
+1:
+	! Disable MMU, Dcache
+	! Whitiger is MMU disabled when reset
+	! Disable the D$
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Set DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! write back the $CACHE_CTL reg
+	isb
+
+	move	$lp, $r0
+2:
+	ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+	la  $r6, lowlevel_init
+	la  $r7, load_lli + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+	la  $r6, turnoff_watchdog
+	la  $r7, turnoff_wtdog + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+/*
+ * Invalidate I$
+ */
+invalidate_icac:
+	! read $cr1(I CAC/MEM cfg. reg.) configuration
+	mfsr	$t0, CR_ICAC_MEM
+
+ 	! Get the ISZ field
+	andi	$p0, $t0, ICAC_MEM_KBF_ISZ
+
+	! if $p0=0, then no I CAC existed
+	beqz	$p0, end_flush_icache
+
+	! get $p0 the index of I$ block
+	srli	$p0, $p0, 6
+
+	! $t1= bit width of I cache line size(ISZ)
+	addi	$t1, $p0, 2
+
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, ICAC_MEM_KBF_ISET	! get the ISET field
+	addi	$t2, $p1, 6			! $t2= bit width of ISET
+	andi	$p1, $t0, ICAC_MEM_KBF_IWAY	! get bitfield of Iway
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is I way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+ICAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1I_IX_INVAL
+	bnez	$p1, ICAC_LOOP
+end_flush_icache:
+	ret
+
+/*
+ * Invalidate D$
+ */
+invalidate_dcac:
+	! read $cr2(D CAC/MEM cfg. reg.) configuration
+	mfsr	$t0, CR_DCAC_MEM
+
+	! Get the DSZ field
+	andi	$p0, $t0, DCAC_MEM_KBF_DSZ
+
+	! if $p0=0, then no D CAC existed
+	beqz	$p0, end_flush_dcache
+
+	! get $p0 the index of D$ block
+	srli	$p0, $p0, 6
+
+	! $t1= bit width of D cache line size(DSZ)
+	addi	$t1, $p0, 2
+
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, DCAC_MEM_KBF_DSET	! get the DSET field
+	addi	$t2, $p1, 6			! $t2= bit width of DSET
+	andi	$p1, $t0, DCAC_MEM_KBF_DWAY	! get bitfield of D way
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is D way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+DCAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1D_IX_INVAL
+	bnez	$p1, DCAC_LOOP
+end_flush_dcache:
+	ret
+
+/*
+ * Interrupt handling
+ */
+
+/*
+ * exception handlers
+ */
+	.align	5
+
+.macro	SAVE_ALL
+	! FIXME: Other way to get PC?
+	! FIXME: Update according to the newest spec!!
+1:
+	la	 $r28, 1
+	push $r28
+	mfsr $r28, PSW			! $PSW
+	push $r28
+	mfsr $r28, EIT_EVA		! $ir1 $EVA
+	push $r28
+	mfsr $r28, EIT_ITYPE		! $ir2 $ITYPE
+	push $r28
+	mfsr $r28, EIT_MACH_ERR		! $ir3 Mach Error
+	push $r28
+	mfsr $r28, EIT_INTR_PSW		! $ir5 $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_IPSW	! $ir6 prev $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_EVA		! $ir7 prev $EVA
+	push $r28
+	mfsr $r28, EIT_PREV_ITYPE	! $ir8 prev $ITYPE
+	push $r28
+	mfsr $r28, EIT_INTR_PC		! $ir9 Interruption PC
+	push $r28
+	mfsr $r28, EIT_PREV_IPC		! $ir10 prev INTR_PC
+	push $r28
+	mfsr $r28, EIT_OVL_INTR_PC	! $ir11 Overflowed INTR_PC
+	push $r28
+	mfusr $r28, $d1.lo
+	push $r28
+	mfusr $r28, $d1.hi
+	push $r28
+	mfusr $r28, $d0.lo
+	push $r28
+	mfusr $r28, $d0.hi
+	push $r28
+	pushm $r0, $r30		! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
+	addi	$sp, $sp, -4	! make room for implicit pt_regs parameters
+.endm
+
+	.align	5
+tlb_fill:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 1				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_not_present:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 2				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_misc:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 3				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_vlpt_miss:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 4				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+cache_parity_error:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 5				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+debug:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 6				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+general_exception:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 7				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+internal_interrupt:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 8				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+
+/*
+ * void reset_cpu(ulong addr);
+ * $r0: input address to jump to
+ */
+.globl reset_cpu
+reset_cpu:
+/* No need to disable MMU because we never enable it */
+
+	bal	invalidate_icac
+	bal	invalidate_dcac
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+1:
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Clear the DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! Write back the $CACHE_CTL reg
+	br	$r0				! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..45221ee
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		arch/nds32/cpu/n1213/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		 *(.got.plt) *(.got)
+		__got_end = .;
+	}
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+}
-- 
1.7.3.5

[U-Boot] [PATCH v16 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Macpaul Lin]

SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
Add lowlevel_init.S and other periphal related code.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code clean up.
Changes for v5-v6:
  - Split watchdog.S from lowlevel_init.S.
  - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
   - reset_cpu was remove inside do_reset().
  - lowlevel_init.S
   - Change hard code value into MARCO definitions.
   - ftsmc010
     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
   - ftsdmc021
     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
     - Fix the default configuration value of FTSDMC and FTSMC controller.
   - Remove some ftpmu010 and flash probe code to C functions.
Changes for v7:
  - clean up.
Changes for v8-v9:
  - No change.
Changes for v10:
  - asm-offset.c: file added for ag101 use only.
  - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
  - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
  - cpu.c: remove unused cpu_init().
  - lowlevel_init.S
   - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
   - Replace routings by macros to made code much easier to understand.
   - Add debug LED support.
   - Add CONFIG_MEM_REMAP for those boards must do memort remapping.
Changes for v11:
  - arch/nds32/cpu/n1213/ag101/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - Simplify the commit log about the part of lowlevel_init.S.
Changes for v13:
  - arch/nds32/cpu/n1213/ag101/Makefile: remove unused gen-asm-offset.
  - Makefile: remove unused gen-asm-offset because merged asm-offsets.
Changes for v14:
  - lowlevel_init.S: fix include path of <generated/asm-offsets.h>
Changes for v15:
  - fix sleep delay.
Changes for v16:
  - arch/nds32/include/asm/arch-ag101/ag101.h: fix lines over 80 characters
  - arch/nds32/cpu/n1213/ag101/lowlevel_init.S: fix lines over 80 characters
  - arch/nds32/cpu/n1213/ag101/timer.c: fix line over 80 characters

 arch/nds32/cpu/n1213/ag101/Makefile        |   58 +++++++
 arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
 arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/timer.c         |  205 ++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
 arch/nds32/include/asm/arch-ag101/ag101.h  |  103 ++++++++++++
 7 files changed, 895 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
 create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
 create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..8716c4e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
new file mode 100644
index 0000000..92ada8a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
@@ -0,0 +1,43 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..0ab666e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+	unsigned long i;
+#endif
+
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+	while (1)
+		;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr , addr + size);
+	icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..29c93fe
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#include <asm/macro.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+
+#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro	wait_sdram
+	li	$r0, CONFIG_FTSDMC021_BASE
+1:
+	lwi	$r1, [$r0+FTSDMC021_CR2]
+	bnez	$r1, 1b
+.endm
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+
+	led	0x0
+	jal	mem_init
+
+	led	0x10
+	jal	remap
+
+	led	0x20
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	led	0x01
+	write32	SMC_BANK0_CR_A, SMC_BANK0_CR_D			! 0x10000052
+	write32	SMC_BANK0_TPR_A, SMC_BANK0_TPR_D		! 0x00151151
+
+	/*
+	 * config AHB Controller
+	 */
+	led	0x02
+	write32	AHBC_BSR6_A, AHBC_BSR6_D
+
+	/*
+	 * config PMU controller
+	 */
+	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
+	led	0x03
+	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
+
+	/*
+	 * config SDRAM controller
+	 */
+	led	0x04
+	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
+	led	0x05
+	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
+	led	0x06
+	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
+
+	led	0x07
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
+	wait_sdram
+
+	led	0x08
+	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
+	wait_sdram
+
+	led	0x09
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
+	wait_sdram
+
+	led	0x0a
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+	/*
+	 * Remapping
+	 */
+	led	0x1a
+	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
+
+	/* clear empty BSR registers */
+	led	0x1b
+	li	$r4, CONFIG_FTSDMC021_BASE
+	li	$r5, 0x0
+	swi	$r5, [$r4 + FTSDMC021_BANK1_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
+
+#ifdef CONFIG_MEM_REMAP
+	/*
+	 * Copy ROM code to SDRAM base for memory remap layout.
+	 * This is not the real relocation, the real relocation is the function
+	 * relocate_code() is start.S which supports the systems is memory
+	 * remapped or not.
+	 */
+	/*
+	 * Doing memory remap is essential for preparing some non-OS or RTOS
+	 * applications.
+	 *
+	 * This is also a must on ADP-AG101 board.
+	 * The reason is because the ROM/FLASH circuit on PCB board.
+	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	 * ROM/FLASH is used to boot.
+	 *
+	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	 * and the FLASH is connected to BANK1.
+	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	 * and the FLASH is connected to BANK0.
+	 * It will occur problem when doing flash probing if the flash is at
+	 * BANK0 (0x00000000) while memory remapping was skipped.
+	 *
+	 * Other board like ADP-AG101P may not enable this since there is only
+	 * a FLASH connected to bank0.
+	 */
+	led	0x11
+	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
+	li	$r5, 0x0
+	la	$r1, relo_base				/* get $pc or $lp */
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(_end)
+	ori	$r6, $r6, lo12(_end)
+	add	$r6, $r6, $r2
+1:
+	lwi.p	$r7, [$r5], #4
+	swi.p	$r7, [$r4], #4
+	blt	$r5, $r6, 1b
+
+	/* set remap bit */
+	/*
+	 * MEM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
+	 */
+	led	0x1c
+	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..c099c33
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / \
+			(CONFIG_SYS_CLK_FREQ / 2 / 1024);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl	turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+#endif
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..141ba2a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+
+/* AHB Controller */
+#define CONFIG_FTAHBC020S_BASE		0x90100000
+/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSMC020_BASE		0x90200000
+/* FTSDMC021 SDRAM Controller */
+#define CONFIG_FTSDMC021_BASE		0x90300000
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000
+/* AHB-to-APB Bridge */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000
+/* LCD Controller */
+#define CONFIG_FTLCDC100_BASE		0x90600000
+/* Reserved */
+#define CONFIG_RESERVED_01_BASE		0x90700000
+/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000
+/* Ethernet */
+#define CONFIG_FTMAC100_BASE		0x90900000
+/* External USB host */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000
+/* USB Device */
+#define CONFIG_USB_DEV_BASE		0x90B00000
+/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000
+/* Reserved */
+#define CONFIG_RESERVED_03_BASE		0x90D00000
+/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000
+/* External AHB slave1 (LCD) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000
+/* External AHB slave2 (FUSBH200) */
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC
+
+/* APB Device definitions */
+
+/* Power Management Unit */
+#define CONFIG_FTPMU010_BASE		0x98100000
+/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTUART010_01_BASE	0x98300000
+/* Counter/Timers */
+#define CONFIG_FTTMR010_BASE		0x98400000
+/* Watchdog Timer */
+#define CONFIG_FTWDT010_BASE		0x98500000
+/* Real Time Clock */
+#define CONFIG_FTRTC010_BASE		0x98600000
+/* GPIO */
+#define CONFIG_FTGPIO010_BASE		0x98700000
+/* Interrupt Controller */
+#define CONFIG_FTINTC010_BASE		0x98800000
+/* I2C */
+#define CONFIG_FTIIC010_BASE		0x98A00000
+/* Reserved */
+#define CONFIG_RESERVED_04_BASE		0x98C00000
+/* Compat Flash Controller */
+#define CONFIG_FTCFC010_BASE		0x98D00000
+/* SD Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000
+
+/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTSSP010_02_BASE		0x99400000
+/* ST UART ? SSP 02 (UART 02 in Linux) */
+#define CONFIG_FTUART010_02_BASE	0x99600000
+
+/* The following address was not defined in Linux */
+
+/* FF UART 3 */
+#define CONFIG_FTUART010_03_BASE	0x98200000
+/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000
+/* IrDA */
+#define CONFIG_IRDA_BASE		0x98900000
+/* PWM - Pulse Width Modulator Controller */
+#define CONFIG_PMW_BASE			0x99100000
+
+#endif	/* __AG101_H */
-- 
1.7.3.5

[U-Boot] [PATCH v16 5/9] nds32/lib: add generic funcs in NDS32 lib

[Macpaul Lin]

Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up and formatting style.
Changes for v5-v6:
  - board.c
   - Do some clean up and add code
   - Remove display banner which hasn't support.
   - Add ftpmu010 related power management unit code.
   - Remove useless LED related code.
   - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
   - Remove CONFIG_SOFT_I2C which hasn't been support.
   - Remove CONFIG_FSL_ESDHC which hasn't been support.
   - clean up.
Changes for v7:
  - clean up.
  - move single file patch arch/nds32/config.mk to this commit.
  - interrupts.c refine origin interrupt enable and disable.
Changes for v8:
  - interrups.c: fix up for new ptraces.h.
Changes for v9:
  - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
Changes for v10:
  - config.mk:
   - add -fpie flag.
   - replace -ffixed-8 to -ffixed-10.
   - add -mrelax and --gc-sections to LDFLAG
  - board.c:
   - fix lib/board.c for relocation.
   - fix dram init for relocation.
Changes for v11:
  - arch/nds32/lib/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - config.mk
   - remove $(SRCTREE)/$(CPUDIR)/u-boot.lds
  - board.c:
   - remove obsolelte version_string.
   - remove declaration "extern __bss_end" which is not need.
   - replace sizeof(gd_t) and sizeof(bd_t) to
     GENERATED_GBL_DATA_SIZE and GENERATED_BD_INFO_SIZE
   - add memset to board info (bd)
   - remove compiler optimization barrier which is not need.
Changes for v13:
  - board.c: remove unused CONFIG_IDENT_STRING.
  - arch/nds32/lib/Makefile: remove unused clean and distclean.
Changes for v14:
  - No change.
Changes for v15:
  - lib/board.c:
   - remove duplicate pci init
   - drop NET_MULTI
Changes for v16:
  - No changes.

 arch/nds32/config.mk        |   35 ++++
 arch/nds32/lib/Makefile     |   46 +++++
 arch/nds32/lib/board.c      |  439 +++++++++++++++++++++++++++++++++++++++++++
 arch/nds32/lib/bootm.c      |  241 ++++++++++++++++++++++++
 arch/nds32/lib/interrupts.c |  129 +++++++++++++
 5 files changed, 890 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/config.mk
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/board.c
 create mode 100644 arch/nds32/lib/bootm.c
 create mode 100644 arch/nds32/lib/interrupts.c

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..c589829
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common -mrelax
+PLATFORM_RELFLAGS	+= -gdwarf-2
+PLATFORM_CPPFLAGS	+= -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-10 -fpie
+
+LDFLAGS_u-boot		= --gc-sections --relax
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..e5c31c3
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+OBJS	:= board.o bootm.o interrupts.o
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..1776a72
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,439 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong monitor_flash_len;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	char tmp[64];	/* long enough for environment variables */
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+			? (int) simple_strtoul(tmp, NULL, 10)
+			: CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+void __dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size =  gd->ram_size;
+}
+void dram_init_banksize(void)
+	__attribute__((weak, alias("__dram_init_banksize")));
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	pmu_init,
+#endif
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+	display_dram_config,
+	NULL,
+};
+
+void board_init_f(ulong bootflag)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	gd_t *id;
+	ulong addr, addr_sp;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
+
+	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+
+	gd->mon_len = (unsigned int)(&__bss_end__) - (unsigned int)(&_start);
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	debug("monitor len: %08lX\n", gd->mon_len);
+	/*
+	 * Ram is setup, size stored in gd !!
+	 */
+	debug("ramsize: %08lX\n", gd->ram_size);
+
+	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	/* reserve TLB table */
+	addr -= (4096 * 4);
+
+	/* round down to next 64 kB limit */
+	addr &= ~(0x10000 - 1);
+
+	gd->tlb_addr = addr;
+	debug("TLB table at: %08lx\n", addr);
+#endif
+
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+	gd->fb_base = CONFIG_FB_ADDR;
+#else
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
+	/*
+	 * reserve memory for U-Boot code, data & bss
+	 * round down to next 4 kB limit
+	 */
+	addr -= gd->mon_len;
+	addr &= ~(4096 - 1);
+
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+
+	/*
+	 * reserve memory for malloc() arena
+	 */
+	addr_sp = addr - TOTAL_MALLOC_LEN;
+	debug("Reserving %dk for malloc() at: %08lx\n",
+			TOTAL_MALLOC_LEN >> 10, addr_sp);
+	/*
+	 * (permanently) allocate a Board Info struct
+	 * and a permanent copy of the "global" data
+	 */
+	addr_sp -= GENERATED_BD_INFO_SIZE;
+	bd = (bd_t *) addr_sp;
+	gd->bd = bd;
+	memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+			GENERATED_BD_INFO_SIZE, addr_sp);
+
+	addr_sp -= GENERATED_GBL_DATA_SIZE;
+	id = (gd_t *) addr_sp;
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			GENERATED_GBL_DATA_SIZE, addr_sp);
+
+	/* setup stackpointer for exeptions */
+	gd->irq_sp = addr_sp;
+#ifdef CONFIG_USE_IRQ
+	addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
+#endif
+	/* leave 3 words for abort-stack    */
+	addr_sp -= 12;
+
+	/* 8-byte alignment for ABI compliance */
+	addr_sp &= ~0x07;
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
+
+	gd->bd->bi_baudrate = gd->baudrate;
+	/* Ram isn't board specific, so move it to board code ... */
+	dram_init_banksize();
+	display_dram_config();	/* and display it */
+
+	gd->relocaddr = addr;
+	gd->start_addr_sp = addr_sp;
+
+	gd->reloc_off = addr - _TEXT_BASE;
+
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	memcpy(id, (void *)gd, GENERATED_GBL_DATA_SIZE);
+
+	relocate_code(addr_sp, id, addr);
+
+	/* NOTREACHED - relocate_code() does not return */
+}
+
+/*
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	char *s;
+	bd_t *bd;
+	ulong malloc_start;
+
+	extern void malloc_bin_reloc(void);
+
+	gd = id;
+	bd = gd->bd;
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	monitor_flash_len = &_end - &_start;
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
+
+	board_init();	/* Setup chipselects */
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	/*
+	 * We have to relocate the command table manually
+	 */
+	fixup_cmdtable(&__u_boot_cmd_start,
+		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
+
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+	mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+	malloc_bin_reloc();
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init();
+#endif
+
+	/* IP Address */
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+#if defined(CONFIG_USE_IRQ)
+	/* set up exceptions */
+	interrupt_init();
+	/* enable exceptions */
+	enable_interrupts();
+#endif
+
+	/* Initialize from environment */
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#if defined(CONFIG_CMD_NET)
+	puts("Net:   ");
+
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	show_boot_progress(15);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..974d52a
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"lp : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}
-- 
1.7.3.5

[U-Boot] [PATCH v16 6/9] nds32: standalone support

[Macpaul Lin]

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - code clean up.
Changes for v7-v11:
  - No change.
Changes for v12:
  - clean up for linker script.
Changes for v13-v15:
  - No change.
Changes for v16:
  - x86-testapp.c: fix line over 80 characters.

 examples/standalone/nds32.lds     |   56 +++++++++++++++++++++++++++++++++++++
 examples/standalone/stubs.c       |   17 ++++++++++-
 examples/standalone/x86-testapp.c |   13 ++++++++
 3 files changed, 85 insertions(+), 1 deletions(-)
 create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..50b4c4b
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	_end = .;
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 507d38c..11c7565 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
 "	jmp %%g1\n"					\
 "	nop\n"						\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	lwi	$r16, [$gp + (%0)]\n"	\
+"	lwi	$r16, [$r16 + (%1)]\n"	\
+"	jr	$r16\n"			\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
 #else
+/*"	addi	$sp, $sp, -24\n"	\
+"	br	$r16\n"			\*/
+
 #error stubs definition missing for this architecture
 #endif
 
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..1e16ec7 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,17 @@ asm volatile (						\
 "	lw	$25, %1($25)\n"				\
 "	jr	$25\n"					\
 	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x)					\
+asm volatile (						\
+"	.globl mon_" #x "\n"				\
+"mon_" #x ":\n"						\
+"	lwi	$r16, [$gp + (%0)]\n"			\
+"	lwi	$r16, [$r16 + (%1)]\n"			\
+"	jr	$r16\n"					\
+: : "i"(offsetof(xxx_t, pfunc)),			\
+"i"(XF_ ## x * sizeof(void *)) : "$r16");
+
 #else
 #error [No stub code for this arch]
 #endif
@@ -72,6 +83,8 @@ int main(void)
 	register volatile xxx_t *pq asm("r8");
 #elif defined(__mips__)
 	register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+	register volatile xxx_t *pq asm("$r16");
 #endif
 	char buf[32];
 
-- 
1.7.3.5

[U-Boot] [PATCH v16 7/9] nds32: common bdinfo, bootm, image support

[Macpaul Lin]

Add support of NDS32 to common commands bdinfo, bootm, and image format.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - Code clean up
Changes for v7-v9:
  - No Change.
Changes for v10:
  - fix up according to the changes in master tree.
Changes for v11:
  - No Change.
Changes for v12:
  - remove seldom used bi_env parameter.
Changes for v13-v14:
  - No change.
Changes for v15:
  - cmd_bootm.c and image.h
    - Fix for new image.h according to Mike's Contribute.
Changes for v16:
  - No change.

 common/cmd_bdinfo.c |   25 +++++++++++++++++++++++++
 common/image.c      |    1 +
 include/image.h     |    1 +
 3 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 6051120..b3e506f 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -413,6 +413,31 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num("arch_number",	bd->bi_arch_number);
+	print_num("boot_params",	(ulong)bd->bi_boot_params);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
diff --git a/common/image.c b/common/image.c
index d38ce4a..d620b85 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	-1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index cca1cc5..e4c7ab9 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_NDS32	        19	/* ANDES Technology - NDS32  */
 
 /*
  * Image Types
-- 
1.7.3.5

[U-Boot] [PATCH v16 8/9] adp-ag101: add board adp-ag101 support

[Macpaul Lin]

Add evaluation board "adp-ag101" configuration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up
Changes for v5-v6:
  - Refine the definitions and parameters about CLK,
    AHB controller, SDRAM controller, Static memory controllers.
  - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
  - ftahbc010:
    - Update include path of ftahbc010.
  - ftsdmc021:
    - Update include path of ftsdmc021.
  - ftsmc020:
    - Update include path of ftsmc020.
  - ftwdt010:
    - Fix WDT define and update include path.
    - Fix ftwdt010 for hardware reset.
  - ftpmu010:
    - Remove duplicate PMU definitions.
    - Add related configurations.
  - Fix MAX malloc len and fix saveenv.
  - clean up.
Changes for v7:
  - clean up.
  - Move CONFIG_SYS_TEXT_BASE from board/config.mk.
  - Fix Makefile and remove config.mk
Changes for v8:
  - No change.
Changes for v9:
  - Fix because other boards has been added into boards.cfg and
    broken this patch.
Changes for v10:
  - adp-ag101.h
   - Fix lines over 80 characters.
   - Fix for introducing gen-asm-offset.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix flash init.
   - fix ftsmc010 configuraion for flash probing.
   - Add SP_INIT related configurations for supporting relocation.
   - Fix CONFIG_TEXT_BASE for relocation.
   - Add CONFIG_MEM_REMAP for some hardware boards and non-OS application.
  - adp-ag101.c
   - Clean up for braces according to Wolfgang's suggestion.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix dram init(), made this more simpler.
Changes for v11:
  - No change.
Changes for v12:
  - adp-ag101.h
   - fix address when enable CONFIG_SKIP_LOWLEVEL_INIT
Changes for v13:
  - board/AndesTech/adp-ag101/Makefile: remove unused clean and distclean.
Changes for v14:
  - No change.
Changes for v15:
  - adp-ag101.h: drop NET_MULTI
  - Makefile: clean up Makefile
Changes for v16:
  - No change.

 MAINTAINERS                           |   11 +
 MAKEALL                               |    6 +
 board/AndesTech/adp-ag101/Makefile    |   44 ++++
 board/AndesTech/adp-ag101/adp-ag101.c |   89 +++++++
 boards.cfg                            |    1 +
 include/configs/adp-ag101.h           |  406 +++++++++++++++++++++++++++++++++
 6 files changed, 557 insertions(+), 0 deletions(-)
 create mode 100644 board/AndesTech/adp-ag101/Makefile
 create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
 create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 3ab38fa..7009e38 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1120,5 +1120,16 @@ Chong Huang <chuang@ucrobotics.com>
 	bf525-ucr2	BF525
 
 #########################################################################
+# NDS32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+	ADP-AG101	N1213 (AG101 SoC)
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 52bc355..755e9b7 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -481,6 +481,12 @@ LIST_sh="$(boards_by_arch sh)"
 
 LIST_sparc="$(boards_by_arch sparc)"
 
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
 #-----------------------------------------------------------------------
 
 build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..d55a799
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= adp-ag101.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..82ce4c9
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	ftsdc010_mmc_init(0);
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 65482ac..f3685c5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -303,6 +303,7 @@ vct_platinumavc_small        mips        mips32      vct                 microna
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
 nios2-generic                nios2       nios2       nios2-generic       altera
+adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..8421c79
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,406 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x03200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_CMD_FAT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#else
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#endif
+
+/*
+ * There are 2 bank connected to FTSMC020 on ADP-AG101.
+ * You can use jumper and switch to force it booted from ROM or FLASH.
+ * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
+ * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
+ * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
+ *    Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
+ * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
+				 FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M	|	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_RBE	|	\
+				 FTSMC020_TPR_AST(1)	|	\
+				 FTSMC020_TPR_CTW(1)	|	\
+				 FTSMC020_TPR_ATI(1)	|	\
+				 FTSMC020_TPR_AT2(1)	|	\
+				 FTSMC020_TPR_WTC(1)	|	\
+				 FTSMC020_TPR_AHT(1)	|	\
+				 FTSMC020_TPR_TRNA(1))
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif	/* CONFIG_MEM_REMAP */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif	/* __CONFIG_H */
-- 
1.7.3.5

[U-Boot] [PATCH v16 9/9] doc/README: documents and readme for NDS32 arch

[Macpaul Lin]

Documents and READMEs for NDS32 architecture.
It patch also provides usage of SoC AG101 and board ADP-AG101.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v10:
  - The patch of documentation was not included.
Changes for v11:
  - Add the documents of NDS32, ag101, N1213.
Changes for v12-v16:
  - No change.

 README                |   24 ++++++++++++++--
 doc/README.N1213      |   55 ++++++++++++++++++++++++++++++++++++
 doc/README.NDS32      |   41 +++++++++++++++++++++++++++
 doc/README.ag101      |   74 +++++++++++++++++++++++++++++++++++++++++++++++++
 doc/README.standalone |    1 +
 5 files changed, 192 insertions(+), 3 deletions(-)
 create mode 100644 doc/README.N1213
 create mode 100644 doc/README.NDS32
 create mode 100644 doc/README.ag101

diff --git a/README b/README
index 0868531..2fd7acc 100644
--- a/README
+++ b/README
@@ -182,6 +182,10 @@ Directory Hierarchy:
     /cpu		CPU specific files
       /mips32		Files specific to MIPS32 CPUs
     /lib		Architecture specific library files
+  /nds32		Files generic to NDS32 architecture
+    /cpu		CPU specific files
+      /n1213		Files specific to Andes Technology N1213 CPUs
+    /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
@@ -3154,7 +3158,7 @@ Low Level (hardware related) configuration options:
 		globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-		[ARM, MIPS only] If this variable is defined, then certain
+		[ARM, NDS32, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
@@ -3702,8 +3706,8 @@ details; basically, the header defines the following image properties:
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
-  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
+  IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -4396,6 +4400,20 @@ On Nios II, the ABI is documented here:
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 
+On NDS32, the following registers are used:
+
+	R0-R1:	argument/return
+	R2-R5:	argument
+	R15:	temporary register for assembler
+	R16:	trampoline register
+	R28:	frame pointer (FP)
+	R29:	global pointer (GP)
+	R30:	link register (LP)
+	R31:	stack pointer (SP)
+	PC:	program counter (PC)
+
+    ==> U-Boot will use R10 to hold a pointer to the global data
+
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 
diff --git a/doc/README.N1213 b/doc/README.N1213
new file mode 100644
index 0000000..e107166
--- /dev/null
+++ b/doc/README.N1213
@@ -0,0 +1,55 @@
+N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
+
+Features
+========
+
+CPU Core
+ - 16-/32-bit mixable instruction format.
+ - 32 general-purpose 32-bit registers.
+ - 8-stage pipeline.
+ - Dynamic branch prediction.
+ - 32/64/128/256 BTB.
+ - Return address stack (RAS).
+ - Vector interrupts for internal/external.
+   interrupt controller with 6 hardware interrupt signals.
+ - 3 HW-level nested interruptions.
+ - User and super-user mode support.
+ - Memory-mapped I/O.
+ - Address space up to 4GB.
+
+Memory Management Unit
+ - TLB
+   - 4/8-entry fully associative iTLB/dTLB.
+   - 32/64/128-entry 4-way set-associati.ve main TLB.
+   - TLB locking support
+ - Optional hardware page table walker.
+ - Two groups of page size support.
+  - 4KB & 1MB.
+  - 8KB & 1MB.
+
+Memory Subsystem
+ - I & D cache.
+   - Virtually indexed and physically tagged.
+   - Cache size: 8KB/16KB/32KB/64KB.
+   - Cache line size: 16B/32B.
+   - Set associativity: 2-way, 4-way or direct-mapped.
+   - Cache locking support.
+ - I & D local memory (LM).
+   - Size: 4KB to 1MB.
+   - Bank numbers: 1 or 2.
+   - Optional 1D/2D DMA engine.
+   - Internal or external to CPU core.
+
+Bus Interface
+ - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
+ - Synchronous High speed memory port.
+   (HSMP): 0, 1 or 2 ports.
+
+Debug
+ - JTAG debug interface.
+ - Embedded debug module (EDM).
+ - Optional embedded program tracer interface.
+
+Miscellaneous
+ - Programmable data endian control.
+ - Performance monitoring mechanism.
diff --git a/doc/README.NDS32 b/doc/README.NDS32
new file mode 100644
index 0000000..b2b58fc
--- /dev/null
+++ b/doc/README.NDS32
@@ -0,0 +1,41 @@
+NDS32 is a new high-performance 32-bit RISC microprocessor core.
+
+http://www.andestech.com/
+
+AndeStar ISA
+============
+AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
+achieve optimal system performance, code density, and power efficiency.
+
+It contains the following features:
+ - Intermixable 32-bit and 16-bit instruction sets without the need for
+   mode switch.
+ - 16-bit instructions as a frequently used subset of 32-bit instructions.
+ - RISC-style register-based instruction set.
+ - 32 32-bit General Purpose Registers (GPR).
+ - Upto 1024 User Special Registers (USR) for existing and extension
+   instructions.
+ - Rich load/store instructions for...
+   - Single memory access with base address update.
+   - Multiple aligned and unaligned memory accesses for memory copy and stack
+     operations.
+   - Data prefetch to improve data cache performance.
+   - Non-bus locking synchronization instructions.
+ - PC relative jump and PC read instructions for efficient position independent
+   code.
+ - Multiply-add and multiple-sub with 64-bit accumulator.
+ - Instruction for efficient power management.
+ - Bi-endian support.
+ - Three instruction extension space for application acceleration:
+   - Performance extension.
+   - Andes future extensions (for floating-point, multimedia, etc.)
+   - Customer extensions.
+
+AndesCore CPU
+=============
+Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
+
+For details about N12 CPU family, please check doc/README.N1213.
+
+The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
+other associated software are actively supported by Andes Technology Corporation.
diff --git a/doc/README.ag101 b/doc/README.ag101
new file mode 100644
index 0000000..46fc637
--- /dev/null
+++ b/doc/README.ag101
@@ -0,0 +1,74 @@
+Andes Technology SoC AG101
+==========================
+
+AG101 is the first SoC produced by Andes Technology using N1213 CPU core.
+AG101 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG101
+=========
+
+ADP-AG101 is the SoC with AG101 hardcore CPU.
+
+Please check http://www.andestech.com/p2-4.htm for detail of this SoC.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+	This is also a must on ADP-AG101 board.
+	(While other boards may not have this problem).
+
+	The reason is because the ROM/FLASH circuit on PCB board.
+	AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	ROM/FLASH is used to boot.
+
+	When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	and the FLASH is connected to BANK1.
+	When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	and the FLASH is connected to BANK0.
+	It will occur problem when doing flash probing if the flash is at
+	BANK0 (0x00000000) while memory remapping was skipped.
+
+	Other board like ADP-AG101P may not enable this since there is only
+	a FLASH connected to bank0.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from FLASH and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag101.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101` in u-boot root to build the image.
+
+burn u-boot to flash:
+1. Make sure the MA17 (J16) is Lo.
+2. Make sure the dip switch SW5 is set to "0101".
+3. Power On. Press button "S1", then press button "SW1", then you will found the
+   debug LED show 67 means the system successfully booted into e-bios.
+   Now you can control the e-bios boot loader from your console.
+4. Under "Command>>" prompt, enter "97" (CopyImageFromCard)
+5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c".
+6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you
+   just build. It is usually "u-boot.bin".
+7. Under "Enter Dest. Address =>" prompt, enter the memory address where you
+   want to put the binary from SD card to RAM.
+   Address "0x500000" is our suggestion.
+8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command
+   environment.
+9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the
+   binary from RAM to FLASH.
+10. Under "CLI>" prompt, enter "exit" to finish the burn process.
+
+boot u-boot from flash:
+1. Make sure the MA17 (J16) is Hi).
+2. Make sure the dip switch SW5 is set to "1010".
+3. Power On. Press button "S1", then you will see the debug LED count to 20.
+4. Now you can use u-boot on ADP-AG101 board.
diff --git a/doc/README.standalone b/doc/README.standalone
index 6e6b65f..2be5f27 100644
--- a/doc/README.standalone
+++ b/doc/README.standalone
@@ -56,6 +56,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
 	ARM		0x0c100000	0x0c100000
 	MIPS		0x80200000	0x80200000
 	Blackfin	0x00001000	0x00001000
+	NDS32		0x00300000	0x00300000
 	Nios II		0x02000000	0x02000000
 
    For example, the "hello world" application may be loaded and
-- 
1.7.3.5

[U-Boot] [PATCH v17 1/9] nds32: add header files support for nds32

[Macpaul Lin]

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code cleanup and style formatting.
Changes for v5-v6:
  - This patch also updated the following changes against the
    change after master tree (v2010.12-rc1).
  - fix upper case definitions in cache.h
  - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
  - Add readsb, writesb functions into io.h.
Changes for v7:
  - clean up
  - volatile:
   - types.h
    - remove typedef volatile unsigned char  vuchar;
    - remove typedef volatile unsigned long  vulong;
    - remove typedef volatile unsigned short vushort;
   - u-boot.h: remove bd_info_ext bi_ext
   - bitops.h: add accessor function to bit operation with volatile var.
   - system.h: add system.h for local_irq operation with flag.
Changes for v8:
  - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
  - ptregs.h: removed
Changes for v9:
  - No change.
Changes for v10:
  - macro.h: add writel and setbf macros
  - u-boot-nds32.h:
   - Remove obsolete andesboot_* symbols for relocation.
   - Add _bss_*_offset symbols for relocation.
  - config.h: add manual relocation support as default.
Changes for v11:
  - unaligned.h: replace asm/unaligned.h with asm-generic/unaligned.h
Changes for v12:
  - remove no used memory.h
  - remove seldom used bi_env parameter
  - u-boot-nds32.h:
   - remove duplicate timer_init()
Changes for v13-v14:
  - No change.
Changes for v15:
  - u-boot.h: fix for new image.h according to Mike's contribution.
Changes for v16:
  - asm/io.h:
   - fix line over 80 characters.
   - remove volatiles for __arch_getb
  - asm/bitops.h: remove volatiles for inline __set_bit()
  - asm/global_data.h: fix line over 80 characters.
Changes for v17:
  - No Change.

 arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
 arch/nds32/include/asm/byteorder.h    |   36 +++
 arch/nds32/include/asm/cache.h        |   54 +++++
 arch/nds32/include/asm/config.h       |   28 +++
 arch/nds32/include/asm/global_data.h  |   89 +++++++
 arch/nds32/include/asm/io.h           |  412 +++++++++++++++++++++++++++++++++
 arch/nds32/include/asm/mach-types.h   |   29 +++
 arch/nds32/include/asm/macro.h        |   96 ++++++++
 arch/nds32/include/asm/posix_types.h  |   84 +++++++
 arch/nds32/include/asm/processor.h    |   25 ++
 arch/nds32/include/asm/ptrace.h       |   88 +++++++
 arch/nds32/include/asm/string.h       |   57 +++++
 arch/nds32/include/asm/system.h       |   88 +++++++
 arch/nds32/include/asm/types.h        |   63 +++++
 arch/nds32/include/asm/u-boot-nds32.h |   51 ++++
 arch/nds32/include/asm/u-boot.h       |   63 +++++
 arch/nds32/include/asm/unaligned.h    |    1 +
 17 files changed, 1450 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/bitops.h
 create mode 100644 arch/nds32/include/asm/byteorder.h
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/config.h
 create mode 100644 arch/nds32/include/asm/global_data.h
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/include/asm/mach-types.h
 create mode 100644 arch/nds32/include/asm/macro.h
 create mode 100644 arch/nds32/include/asm/posix_types.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/system.h
 create mode 100644 arch/nds32/include/asm/types.h
 create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
 create mode 100644 arch/nds32/include/asm/u-boot.h
 create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..f1aa9a3
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, void *addr);
+
+static inline void __set_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+extern void clear_bit(int nr, void *addr);
+
+static inline void __clear_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, void *addr);
+
+static inline void __change_bit(int nr, void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, void *addr);
+
+static inline int __test_and_set_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, void *addr);
+
+static inline int __test_and_clear_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, void *addr);
+
+static inline int __test_and_change_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ	6	/* I-cache line size */
+#define ICM_CFG_MSK_ISZ	(0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
+#define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..6f654d9
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_NEEDS_MANUAL_RELOC
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..de20a0a
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+
+	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t	ram_size;	/* RAM size */
+	unsigned long	mon_len;	/* monitor len */
+	unsigned long	irq_sp;		/* irq stack pointer */
+	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	unsigned long	tlb_addr;
+#endif
+
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT		0x00004	/* Silent mode			*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	*/
+#define GD_FLG_ENV_READY	0x00080	/* Envs imported into hash table */
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r10")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..2504c2b
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,412 @@
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(unsigned char *)(a))
+#define __arch_getw(a)			(*(unsigned short *)(a))
+#define __arch_getl(a)			(*(unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+#define writeb(v, a)			__arch_putb(v, a)
+#define writew(v, a)			__arch_putw(v, a)
+#define writel(v, a)			__arch_putl(v, a)
+
+#define readb(a)			__arch_getb(a)
+#define readw(a)			__arch_getw(a)
+#define readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache)				\
+({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
+	_ret;								\
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = \
+			__raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = \
+			le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = \
+			le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"), 0)
+#define readw(addr)			(__readwrite_bug("readw"), 0)
+#define readl(addr)			(__readwrite_bug("readl"), 0)
+#define writeb(v, addr)			__readwrite_bug("writeb")
+#define writew(v, addr)			__readwrite_bug("writew")
+#define writel(v, addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101             0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101()	(machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101()	(0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/macro.h b/arch/nds32/include/asm/macro.h
new file mode 100644
index 0000000..acda060
--- /dev/null
+++ b/arch/nds32/include/asm/macro.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-nds32/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NDS_MACRO_H
+#define __ASM_NDS_MACRO_H
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to an "immediate address (address used by periphal)" only.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any NDS32 architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	li	$r4, addr
+	li	$r5, data
+	swi	$r5, [$r4]
+.endm
+
+.macro	write16, addr, data
+	li	$r4, addr
+	li	$r5, data
+	shi	$r5, [$r4]
+.endm
+
+.macro	write8, addr, data
+	li	$r4, addr
+	li	$r5, data
+	sbi	$r5, [$r4]
+.endm
+
+/*
+ * This macro read a value from a register, then do OR operation
+ * (set bit fields) to the value, and then store it back to the register.
+ * Note: Instruction 'ori' supports immediate value up to 15 bits.
+ */
+.macro	setbf32, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	li	$r6, data
+	or	$r5, $r5, $r6
+	swi	$r5, [$r4]
+.endm
+
+.macro	setbf15, addr, data
+	li	$r4, addr
+	lwi	$r5, [$r4]
+	ori	$r5, $r5, data
+	swi	$r5, [$r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any NDS32 architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	li	$r4, time
+1:
+	nop
+	addi	$r4, $r4, -1
+	bnez    $r4, 1b
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..4336083
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+	NDS32_REG ir0;
+	NDS32_REG ipsw;
+	NDS32_REG ipc;
+	NDS32_REG sp;
+	NDS32_REG orig_r0;
+	NDS32_REG pipsw;
+	NDS32_REG pipc;
+	NDS32_REG pp0;
+	NDS32_REG pp1;
+	NDS32_REG d0hi;
+	NDS32_REG d0lo;
+	NDS32_REG d1hi;
+	NDS32_REG d1lo;
+	NDS32_REG r[26];	/* r0 - r25 */
+	NDS32_REG fp;		/* r28 */
+	NDS32_REG gp;		/* r29 */
+	NDS32_REG lp;		/* r30 */
+	NDS32_REG fucop_ctl;
+	NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+	(((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..ae1918d
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong __bss_start;	/* BSS start relative to _start */
+extern ulong __bss_end__;	/* BSS end relative to _start */
+extern ulong _end;		/* end of image relative to _start */
+extern ulong _start;		/* start of image relative to _start */
+extern ulong _TEXT_BASE;	/* code start */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..9a69750
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <environment.h>
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_NDS32
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
-- 
1.7.3.5

[U-Boot] [PATCH v17 1/9] nds32: add header files support for nds32

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1319092871-28135-1-git-send-email-macpaul@andestech.com> you wrote:
> Add generic header files support for nds32 architecture.
> Cache, ptregs, data type and other definitions are included.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v4:
>   - Code cleanup and style formatting.
> Changes for v5-v6:
>   - This patch also updated the following changes against the
>     change after master tree (v2010.12-rc1).
>   - fix upper case definitions in cache.h
>   - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
>   - Add readsb, writesb functions into io.h.
> Changes for v7:
>   - clean up
>   - volatile:
>    - types.h
>     - remove typedef volatile unsigned char  vuchar;
>     - remove typedef volatile unsigned long  vulong;
>     - remove typedef volatile unsigned short vushort;
>    - u-boot.h: remove bd_info_ext bi_ext
>    - bitops.h: add accessor function to bit operation with volatile var.
>    - system.h: add system.h for local_irq operation with flag.
> Changes for v8:
>   - ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
>   - ptregs.h: removed
> Changes for v9:
>   - No change.
> Changes for v10:
>   - macro.h: add writel and setbf macros
>   - u-boot-nds32.h:
>    - Remove obsolete andesboot_* symbols for relocation.
>    - Add _bss_*_offset symbols for relocation.
>   - config.h: add manual relocation support as default.
> Changes for v11:
>   - unaligned.h: replace asm/unaligned.h with asm-generic/unaligned.h
> Changes for v12:
>   - remove no used memory.h
>   - remove seldom used bi_env parameter
>   - u-boot-nds32.h:
>    - remove duplicate timer_init()
> Changes for v13-v14:
>   - No change.
> Changes for v15:
>   - u-boot.h: fix for new image.h according to Mike's contribution.
> Changes for v16:
>   - asm/io.h:
>    - fix line over 80 characters.
>    - remove volatiles for __arch_getb
>   - asm/bitops.h: remove volatiles for inline __set_bit()
>   - asm/global_data.h: fix line over 80 characters.
> Changes for v17:
>   - No Change.
> 
>  arch/nds32/include/asm/bitops.h       |  186 +++++++++++++++
>  arch/nds32/include/asm/byteorder.h    |   36 +++
>  arch/nds32/include/asm/cache.h        |   54 +++++
>  arch/nds32/include/asm/config.h       |   28 +++
>  arch/nds32/include/asm/global_data.h  |   89 +++++++
>  arch/nds32/include/asm/io.h           |  412 +++++++++++++++++++++++++++++++++
>  arch/nds32/include/asm/mach-types.h   |   29 +++
>  arch/nds32/include/asm/macro.h        |   96 ++++++++
>  arch/nds32/include/asm/posix_types.h  |   84 +++++++
>  arch/nds32/include/asm/processor.h    |   25 ++
>  arch/nds32/include/asm/ptrace.h       |   88 +++++++
>  arch/nds32/include/asm/string.h       |   57 +++++
>  arch/nds32/include/asm/system.h       |   88 +++++++
>  arch/nds32/include/asm/types.h        |   63 +++++
>  arch/nds32/include/asm/u-boot-nds32.h |   51 ++++
>  arch/nds32/include/asm/u-boot.h       |   63 +++++
>  arch/nds32/include/asm/unaligned.h    |    1 +
>  17 files changed, 1450 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/include/asm/bitops.h
>  create mode 100644 arch/nds32/include/asm/byteorder.h
>  create mode 100644 arch/nds32/include/asm/cache.h
>  create mode 100644 arch/nds32/include/asm/config.h
>  create mode 100644 arch/nds32/include/asm/global_data.h
>  create mode 100644 arch/nds32/include/asm/io.h
>  create mode 100644 arch/nds32/include/asm/mach-types.h
>  create mode 100644 arch/nds32/include/asm/macro.h
>  create mode 100644 arch/nds32/include/asm/posix_types.h
>  create mode 100644 arch/nds32/include/asm/processor.h
>  create mode 100644 arch/nds32/include/asm/ptrace.h
>  create mode 100644 arch/nds32/include/asm/string.h
>  create mode 100644 arch/nds32/include/asm/system.h
>  create mode 100644 arch/nds32/include/asm/types.h
>  create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
>  create mode 100644 arch/nds32/include/asm/u-boot.h
>  create mode 100644 arch/nds32/include/asm/unaligned.h

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Open the pod bay doors, HAL."                    - Dave Bowman, 2001

[U-Boot] [PATCH v17 1/9] nds32: add header files support for nds32

[馬克泡]

Hi Wolfgang,

2011/10/22 Wolfgang Denk <wd@denx.de>:
> Dear Macpaul Lin,
>
>> Changes for v17:
>
> Applied, thanks.
>
> Best regards,
>
> Wolfgang Denk

Great Thanks to Wolfgang, Mike, Po-Yu, Greentime, CM Chao and other
people contributed to u-boot.

-- 
Best regards,
Macpaul Lin

[U-Boot] [PATCH v17 2/9] nds32: add NDS32 support into common header file

[Macpaul Lin]

Add NDS32 support into common header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v7:
  - No change
Changes for v8:
  - Fix the patch according to dependency of x86's Fix
Changes for v9-v16:
  - No change
Changes for v17:
  - Fix for arch Sandbox has been committed.

 include/common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index 4c3e3a6..e3ef66d 100644
--- a/include/common.h
+++ b/include/common.h
@@ -314,6 +314,10 @@ int	setenv	     (const char *, const char *);
 #ifdef CONFIG_SANDBOX
 # include <asm/u-boot-sandbox.h>	/* TODO(sjg) what needs to be fixed? */
 #endif
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h>
+#endif /* CONFIG_NDS32 */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
-- 
1.7.3.5

[U-Boot] [PATCH v17 2/9] nds32: add NDS32 support into common header file

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1319092871-28135-2-git-send-email-macpaul@andestech.com> you wrote:
> Add NDS32 support into common header file.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v7:
>   - No change
> Changes for v8:
>   - Fix the patch according to dependency of x86's Fix
> Changes for v9-v16:
>   - No change
> Changes for v17:
>   - Fix for arch Sandbox has been committed.
> 
>  include/common.h |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Tactical? TACTICAL!?!? Hey, buddy, we went from kilotons to  megatons
several  minutes  ago.  We don't need no stinkin' tactical nukes. (By
the way, do you have change for 10 million people?)           - lwall

[U-Boot] [PATCH v17 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Macpaul Lin]

Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
Changes for v1 to v6:
  - Style clean up and reorganize code
Changes for v7-v9:
  - No Change.
Changes for v10:
  - start.S of N1213 CPU has been rewrote for relocation support.
  - u-boot.lds:
   - Add got and *(.got.plt) section for support GCC 4 toolchain
   - Modified for relocation implementation.
Changes for v11:
  - arch/nds32/cpu/n1213/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - u-boot.lds
   - Remove the 0x00000000 base address in linker script.
     The base address of the binary will be determined by CONFIG_SYS_TEXT_BASE
  - Remove the CPU features in commit log and add to README in later patches.
Changes for v13-v14:
  - No change.
Changes for v15:
  - start.S: fix exception vector aligment (add setivb in reset vector).
Changes for v16:
  - start.S: remove lines over 80 characters.
Changes for v17:
  - Fix a space ident warning which checkpatch doesn't found.

 arch/nds32/cpu/n1213/Makefile   |   50 ++++
 arch/nds32/cpu/n1213/start.S    |  529 +++++++++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/u-boot.lds |   70 +++++
 3 files changed, 649 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/Makefile
 create mode 100644 arch/nds32/cpu/n1213/start.S
 create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..da15574
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..1d1fcf7
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,529 @@
+/*
+ *	Andesboot - Startup Code for Whitiger core
+ *
+ *	Copyright (C) 2006	Andes Technology Corporation
+ *	Copyright (C) 2006	Shawn Lin <nobuhiro@andestech.com>
+ *	Copyright (C) 2011	Macpaul Lin <macpaul@andestech.com>
+ *				Greentime Hu <greentime@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <asm/macro.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC		2UL
+#define DIS_DCAC		~ENA_DCAC
+#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
+#define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
+#define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY	(0x07<<3)	! D cache ways
+#define DCAC_MEM_KBF_DSZ	(0x07<<6)	! D cache line size
+
+#define PSW			$ir0
+#define EIT_INTR_PSW		$ir1		! interruption $PSW
+#define EIT_PREV_IPSW		$ir2		! previous $IPSW
+#define EIT_IVB			$ir3		! intr vector base address
+#define EIT_EVA			$ir4		! MMU related Exception VA reg
+#define EIT_PREV_EVA		$ir5		! previous $eva
+#define EIT_ITYPE		$ir6		! interruption type
+#define EIT_PREV_ITYPE		$ir7		! prev intr type
+#define EIT_MACH_ERR		$ir8		! machine error log
+#define EIT_INTR_PC		$ir9		! Interruption PC
+#define EIT_PREV_IPC		$ir10		! previous $IPC
+#define EIT_OVL_INTR_PC		$ir11		! overflow interruption PC
+#define EIT_PREV_P0		$ir12		! prev $P0
+#define EIT_PREV_P1		$ir13		! prev $p1
+#define CR_ICAC_MEM		$cr1		! I-cache/memory config reg
+#define CR_DCAC_MEM		$cr2		! D-cache/memory config reg
+#define MR_CAC_CTL		$mr8
+
+.globl _start
+
+_start:	j	reset
+	j	tlb_fill
+	j	tlb_not_present
+	j	tlb_misc
+	j	tlb_vlpt_miss
+	j	cache_parity_error
+	j	debug
+	j	general_exception
+	j	internal_interrupt		! H0I
+	j	internal_interrupt		! H1I
+	j	internal_interrupt		! H2I
+	j	internal_interrupt		! H3I
+	j	internal_interrupt		! H4I
+	j	internal_interrupt		! H5I
+
+	.balign 16
+
+/*
+ * Andesboot Startup Code (reset vector)
+ *
+ *	1.	bootstrap
+ *		1.1 reset - start of u-boot
+ *		1.2 to superuser mode - as is when reset
+ *		1.4 Do lowlevel_init
+ *			- (this will jump out to lowlevel_init.S in SoC)
+ *			- (lowlevel_init)
+ *		1.3 Turn off watchdog timer
+ *			- (this will jump out to watchdog.S in SoC)
+ *			- (turnoff_watchdog)
+ *	2.	Do critical init when reboot (not from mem)
+ *	3.	Relocate andesboot to ram
+ *	4.	Setup stack
+ *	5.	Jump to second stage (board_init_r)
+ */
+
+/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word 0x0badc0de
+
+/*
+ * The bootstrap code of nds32 core
+ */
+
+reset:
+set_ivb:
+	li	$r0, 0x0
+
+	/* turn on BTB */
+	mtsr	$r0, $misc_ctl
+	/* set IVIC, vector size: 4 bytes, base: 0x0 */
+	mtsr	$r0, $ivb
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	jal	load_lowlevel_init
+	jral	$p0
+#endif
+
+/*
+ * Set the N1213 (Whitiger) core to superuser mode
+ * According to spec, it is already when reset
+ */
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+	jal	load_turnoff_watchdog
+	jral	$p0
+#endif
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+	bal	cpu_init_crit		! Do CPU critical regs init
+#endif
+
+/*
+ * Set stackpointer in internal RAM to call board_init_f
+ * $sp must be 8-byte alignment for ABI compliance.
+ */
+call_board_init_f:
+	li	$sp, CONFIG_SYS_INIT_SP_ADDR
+	li	$r0, 0x00000000
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__
+/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
+	la	$r15, board_init_f	! store function address into $r15
+#endif
+#endif
+	j	board_init_f		! jump to board_init_f() in lib/board.c
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl	relocate_code
+relocate_code:
+	move	$r4, $r0		/* save addr_sp */
+	move	$r5, $r1		/* save addr of gd */
+	move	$r6, $r2		/* save addr of destination */
+
+/* Set up the stack */
+stack_setup:
+	move	$sp, $r4
+
+	la	$r0, _start
+
+	beq	$r0, $r6, clear_bss	/* skip relocation */
+
+	move	$r1, $r6		/* r1 <- scratch for copy_loop */
+	la	$r3, __bss_start
+	sub	$r3, $r3, $r0		/* r3 <- __bss_start_ofs */
+	add	$r2, $r0, $r3		/* r2 <- source end address */
+
+copy_loop:
+	lwi.p	$r7, [$r0], #4
+	swi.p	$r7, [$r1], #4
+	blt	$r0, $r2, copy_loop
+
+/*
+ * fix relocations related issues
+ */
+fix_relocations:
+	l.w	$r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	$r9, $r6, $r0		/* r9 <- relocation offset */
+
+fix_got:
+/*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+	la	$r2, __got_start	/* r2 <- rel __got_start in FLASH */
+	add	$r2, $r2, $r9		/* r2 <- rel __got_start in RAM */
+	la	$r3, __got_end		/* r3 <- rel __got_end in FLASH */
+	add	$r3, $r3, $r9		/* r3 <- rel __got_end in RAM */
+	addi	$r2, $r2, #8		/* skipping first two entries */
+fix_got_loop:
+	lwi	$r0, [$r2]		/* r0 <- location in FLASH to fix up */
+	add	$r0, $r0, $r9		/* r0 <- location fix up to RAM */
+	swi.p	$r0, [$r2], #4		/* r0 <- store fix into .got in RAM */
+	blt	$r2, $r3, fix_got_loop
+
+clear_bss:
+	la	$r0, __bss_start	/* r0 <- rel __bss_start in FLASH */
+	add	$r0, $r0, $r9		/* r0 <- rel __bss_start in FLASH */
+	la	$r1, __bss_end__	/* r1 <- rel __bss_end in RAM */
+	add	$r1, $r1, $r9		/* r0 <- rel __bss_end in RAM */
+	li	$r2, 0x00000000		/* clear */
+
+clbss_l:
+	sw	$r2, [$r0]		/* clear loop... */
+	addi	$r0, $r0, #4
+	bne	$r0, $r1, clbss_l
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+	la	$r0, board_init_r
+	move	$lp, $r0		/* offset of board_init_r() */
+	add	$lp, $lp, $r9		/* real address of board_init_r() */
+	/* setup parameters for board_init_r */
+	move	$r0, $r5		/* gd_t */
+	move	$r1, $r6		/* dest_addr */
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__		/* NDS32 V0 ISA	*/
+	move	$r15, $lp		/* store function address into $r15 */
+#endif
+#endif
+
+	/* jump to it ... */
+	jr	$lp			/* jump to board_init_r() */
+
+/*
+ * Initialize CPU critical registers
+ *
+ *	1.	Setup control registers
+ *		1.1 Mask all IRQs
+ *		1.2 Flush cache and TLB
+ *		1.3 Disable MMU and cache
+ *	2.	Setup memory timing
+ */
+
+cpu_init_crit:
+
+	move	$r0, $lp		/* push	ra */
+
+	/* Disable Interrupts by clear GIE in $PSW reg */
+	setgie.d
+
+	/* Flush caches and TLB */
+	/* Invalidate caches */
+	bal	invalidate_icac
+	bal	invalidate_dcac
+
+	/* Flush TLB */
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+
+1:
+	! Disable MMU, Dcache
+	! Whitiger is MMU disabled when reset
+	! Disable the D$
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Set DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! write back the $CACHE_CTL reg
+	isb
+
+	move	$lp, $r0
+2:
+	ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+	la  $r6, lowlevel_init
+	la  $r7, load_lli + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+	la  $r6, turnoff_watchdog
+	la  $r7, turnoff_wtdog + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+/*
+ * Invalidate I$
+ */
+invalidate_icac:
+	! read $cr1(I CAC/MEM cfg. reg.) configuration
+	mfsr	$t0, CR_ICAC_MEM
+
+	! Get the ISZ field
+	andi	$p0, $t0, ICAC_MEM_KBF_ISZ
+
+	! if $p0=0, then no I CAC existed
+	beqz	$p0, end_flush_icache
+
+	! get $p0 the index of I$ block
+	srli	$p0, $p0, 6
+
+	! $t1= bit width of I cache line size(ISZ)
+	addi	$t1, $p0, 2
+
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, ICAC_MEM_KBF_ISET	! get the ISET field
+	addi	$t2, $p1, 6			! $t2= bit width of ISET
+	andi	$p1, $t0, ICAC_MEM_KBF_IWAY	! get bitfield of Iway
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is I way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+ICAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1I_IX_INVAL
+	bnez	$p1, ICAC_LOOP
+end_flush_icache:
+	ret
+
+/*
+ * Invalidate D$
+ */
+invalidate_dcac:
+	! read $cr2(D CAC/MEM cfg. reg.) configuration
+	mfsr	$t0, CR_DCAC_MEM
+
+	! Get the DSZ field
+	andi	$p0, $t0, DCAC_MEM_KBF_DSZ
+
+	! if $p0=0, then no D CAC existed
+	beqz	$p0, end_flush_dcache
+
+	! get $p0 the index of D$ block
+	srli	$p0, $p0, 6
+
+	! $t1= bit width of D cache line size(DSZ)
+	addi	$t1, $p0, 2
+
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, DCAC_MEM_KBF_DSET	! get the DSET field
+	addi	$t2, $p1, 6			! $t2= bit width of DSET
+	andi	$p1, $t0, DCAC_MEM_KBF_DWAY	! get bitfield of D way
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is D way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+DCAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1D_IX_INVAL
+	bnez	$p1, DCAC_LOOP
+end_flush_dcache:
+	ret
+
+/*
+ * Interrupt handling
+ */
+
+/*
+ * exception handlers
+ */
+	.align	5
+
+.macro	SAVE_ALL
+	! FIXME: Other way to get PC?
+	! FIXME: Update according to the newest spec!!
+1:
+	la	 $r28, 1
+	push $r28
+	mfsr $r28, PSW			! $PSW
+	push $r28
+	mfsr $r28, EIT_EVA		! $ir1 $EVA
+	push $r28
+	mfsr $r28, EIT_ITYPE		! $ir2 $ITYPE
+	push $r28
+	mfsr $r28, EIT_MACH_ERR		! $ir3 Mach Error
+	push $r28
+	mfsr $r28, EIT_INTR_PSW		! $ir5 $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_IPSW	! $ir6 prev $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_EVA		! $ir7 prev $EVA
+	push $r28
+	mfsr $r28, EIT_PREV_ITYPE	! $ir8 prev $ITYPE
+	push $r28
+	mfsr $r28, EIT_INTR_PC		! $ir9 Interruption PC
+	push $r28
+	mfsr $r28, EIT_PREV_IPC		! $ir10 prev INTR_PC
+	push $r28
+	mfsr $r28, EIT_OVL_INTR_PC	! $ir11 Overflowed INTR_PC
+	push $r28
+	mfusr $r28, $d1.lo
+	push $r28
+	mfusr $r28, $d1.hi
+	push $r28
+	mfusr $r28, $d0.lo
+	push $r28
+	mfusr $r28, $d0.hi
+	push $r28
+	pushm $r0, $r30		! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
+	addi	$sp, $sp, -4	! make room for implicit pt_regs parameters
+.endm
+
+	.align	5
+tlb_fill:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 1				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_not_present:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 2				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_misc:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 3				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_vlpt_miss:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 4				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+cache_parity_error:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 5				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+debug:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 6				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+general_exception:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 7				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+internal_interrupt:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 8				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+
+/*
+ * void reset_cpu(ulong addr);
+ * $r0: input address to jump to
+ */
+.globl reset_cpu
+reset_cpu:
+/* No need to disable MMU because we never enable it */
+
+	bal	invalidate_icac
+	bal	invalidate_dcac
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+1:
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Clear the DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! Write back the $CACHE_CTL reg
+	br	$r0				! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..45221ee
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		arch/nds32/cpu/n1213/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		 *(.got.plt) *(.got)
+		__got_end = .;
+	}
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+}
-- 
1.7.3.5

[U-Boot] [PATCH v17 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1319092871-28135-3-git-send-email-macpaul@andestech.com> you wrote:
> Add N1213 cpu core (N12 Core family) support for NDS32 arch.
> This patch includes start.S for the initialize procedure of N1213.
> 
> Start procedure:
>  start.S will start up the N1213 CPU core at first,
>  then jump to SoC dependent "lowlevel_init.S" and
>  "watchdog.S" to configure peripheral devices.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> Signed-off-by: Greentime Hu <greentime@andestech.com>
> ---
> Changes for v1 to v6:
>   - Style clean up and reorganize code
> Changes for v7-v9:
>   - No Change.
> Changes for v10:
>   - start.S of N1213 CPU has been rewrote for relocation support.
>   - u-boot.lds:
>    - Add got and *(.got.plt) section for support GCC 4 toolchain
>    - Modified for relocation implementation.
> Changes for v11:
>   - arch/nds32/cpu/n1213/Makefile
>    - replace $(AR) $(call cmd_link_o_target,...)
> Changes for v12:
>   - u-boot.lds
>    - Remove the 0x00000000 base address in linker script.
>      The base address of the binary will be determined by CONFIG_SYS_TEXT_BASE
>   - Remove the CPU features in commit log and add to README in later patches.
> Changes for v13-v14:
>   - No change.
> Changes for v15:
>   - start.S: fix exception vector aligment (add setivb in reset vector).
> Changes for v16:
>   - start.S: remove lines over 80 characters.
> Changes for v17:
>   - Fix a space ident warning which checkpatch doesn't found.
> 
>  arch/nds32/cpu/n1213/Makefile   |   50 ++++
>  arch/nds32/cpu/n1213/start.S    |  529 +++++++++++++++++++++++++++++++++++++++
>  arch/nds32/cpu/n1213/u-boot.lds |   70 +++++
>  3 files changed, 649 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/cpu/n1213/Makefile
>  create mode 100644 arch/nds32/cpu/n1213/start.S
>  create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
All he had was nothing, but that was something, and now it  had  been
taken away.                             - Terry Pratchett, _Sourcery_

[U-Boot] [PATCH v17 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Macpaul Lin]

SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
Add lowlevel_init.S and other periphal related code.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code clean up.
Changes for v5-v6:
  - Split watchdog.S from lowlevel_init.S.
  - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
   - reset_cpu was remove inside do_reset().
  - lowlevel_init.S
   - Change hard code value into MARCO definitions.
   - ftsmc010
     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
   - ftsdmc021
     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
     - Fix the default configuration value of FTSDMC and FTSMC controller.
   - Remove some ftpmu010 and flash probe code to C functions.
Changes for v7:
  - clean up.
Changes for v8-v9:
  - No change.
Changes for v10:
  - asm-offset.c: file added for ag101 use only.
  - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
  - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
  - cpu.c: remove unused cpu_init().
  - lowlevel_init.S
   - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
   - Replace routings by macros to made code much easier to understand.
   - Add debug LED support.
   - Add CONFIG_MEM_REMAP for those boards must do memort remapping.
Changes for v11:
  - arch/nds32/cpu/n1213/ag101/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - Simplify the commit log about the part of lowlevel_init.S.
Changes for v13:
  - arch/nds32/cpu/n1213/ag101/Makefile: remove unused gen-asm-offset.
  - Makefile: remove unused gen-asm-offset because merged asm-offsets.
Changes for v14:
  - lowlevel_init.S: fix include path of <generated/asm-offsets.h>
Changes for v15:
  - fix sleep delay.
Changes for v16:
  - arch/nds32/include/asm/arch-ag101/ag101.h: fix lines over 80 characters
  - arch/nds32/cpu/n1213/ag101/lowlevel_init.S: fix lines over 80 characters
  - arch/nds32/cpu/n1213/ag101/timer.c: fix line over 80 characters
Changes for v17:
  - No changes.

 arch/nds32/cpu/n1213/ag101/Makefile        |   58 +++++++
 arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
 arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/timer.c         |  205 ++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
 arch/nds32/include/asm/arch-ag101/ag101.h  |  103 ++++++++++++
 7 files changed, 895 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
 create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
 create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..8716c4e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
new file mode 100644
index 0000000..92ada8a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
@@ -0,0 +1,43 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..0ab666e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+	unsigned long i;
+#endif
+
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+	while (1)
+		;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr , addr + size);
+	icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..29c93fe
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#include <asm/macro.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+
+#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro	wait_sdram
+	li	$r0, CONFIG_FTSDMC021_BASE
+1:
+	lwi	$r1, [$r0+FTSDMC021_CR2]
+	bnez	$r1, 1b
+.endm
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+
+	led	0x0
+	jal	mem_init
+
+	led	0x10
+	jal	remap
+
+	led	0x20
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	led	0x01
+	write32	SMC_BANK0_CR_A, SMC_BANK0_CR_D			! 0x10000052
+	write32	SMC_BANK0_TPR_A, SMC_BANK0_TPR_D		! 0x00151151
+
+	/*
+	 * config AHB Controller
+	 */
+	led	0x02
+	write32	AHBC_BSR6_A, AHBC_BSR6_D
+
+	/*
+	 * config PMU controller
+	 */
+	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
+	led	0x03
+	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
+
+	/*
+	 * config SDRAM controller
+	 */
+	led	0x04
+	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
+	led	0x05
+	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
+	led	0x06
+	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
+
+	led	0x07
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
+	wait_sdram
+
+	led	0x08
+	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
+	wait_sdram
+
+	led	0x09
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
+	wait_sdram
+
+	led	0x0a
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+	/*
+	 * Remapping
+	 */
+	led	0x1a
+	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
+
+	/* clear empty BSR registers */
+	led	0x1b
+	li	$r4, CONFIG_FTSDMC021_BASE
+	li	$r5, 0x0
+	swi	$r5, [$r4 + FTSDMC021_BANK1_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
+
+#ifdef CONFIG_MEM_REMAP
+	/*
+	 * Copy ROM code to SDRAM base for memory remap layout.
+	 * This is not the real relocation, the real relocation is the function
+	 * relocate_code() is start.S which supports the systems is memory
+	 * remapped or not.
+	 */
+	/*
+	 * Doing memory remap is essential for preparing some non-OS or RTOS
+	 * applications.
+	 *
+	 * This is also a must on ADP-AG101 board.
+	 * The reason is because the ROM/FLASH circuit on PCB board.
+	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	 * ROM/FLASH is used to boot.
+	 *
+	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	 * and the FLASH is connected to BANK1.
+	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	 * and the FLASH is connected to BANK0.
+	 * It will occur problem when doing flash probing if the flash is at
+	 * BANK0 (0x00000000) while memory remapping was skipped.
+	 *
+	 * Other board like ADP-AG101P may not enable this since there is only
+	 * a FLASH connected to bank0.
+	 */
+	led	0x11
+	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
+	li	$r5, 0x0
+	la	$r1, relo_base				/* get $pc or $lp */
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(_end)
+	ori	$r6, $r6, lo12(_end)
+	add	$r6, $r6, $r2
+1:
+	lwi.p	$r7, [$r5], #4
+	swi.p	$r7, [$r4], #4
+	blt	$r5, $r6, 1b
+
+	/* set remap bit */
+	/*
+	 * MEM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
+	 */
+	led	0x1c
+	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..c099c33
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / \
+			(CONFIG_SYS_CLK_FREQ / 2 / 1024);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl	turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+#endif
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..141ba2a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+
+/* AHB Controller */
+#define CONFIG_FTAHBC020S_BASE		0x90100000
+/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSMC020_BASE		0x90200000
+/* FTSDMC021 SDRAM Controller */
+#define CONFIG_FTSDMC021_BASE		0x90300000
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000
+/* AHB-to-APB Bridge */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000
+/* LCD Controller */
+#define CONFIG_FTLCDC100_BASE		0x90600000
+/* Reserved */
+#define CONFIG_RESERVED_01_BASE		0x90700000
+/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000
+/* Ethernet */
+#define CONFIG_FTMAC100_BASE		0x90900000
+/* External USB host */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000
+/* USB Device */
+#define CONFIG_USB_DEV_BASE		0x90B00000
+/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000
+/* Reserved */
+#define CONFIG_RESERVED_03_BASE		0x90D00000
+/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000
+/* External AHB slave1 (LCD) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000
+/* External AHB slave2 (FUSBH200) */
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC
+
+/* APB Device definitions */
+
+/* Power Management Unit */
+#define CONFIG_FTPMU010_BASE		0x98100000
+/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTUART010_01_BASE	0x98300000
+/* Counter/Timers */
+#define CONFIG_FTTMR010_BASE		0x98400000
+/* Watchdog Timer */
+#define CONFIG_FTWDT010_BASE		0x98500000
+/* Real Time Clock */
+#define CONFIG_FTRTC010_BASE		0x98600000
+/* GPIO */
+#define CONFIG_FTGPIO010_BASE		0x98700000
+/* Interrupt Controller */
+#define CONFIG_FTINTC010_BASE		0x98800000
+/* I2C */
+#define CONFIG_FTIIC010_BASE		0x98A00000
+/* Reserved */
+#define CONFIG_RESERVED_04_BASE		0x98C00000
+/* Compat Flash Controller */
+#define CONFIG_FTCFC010_BASE		0x98D00000
+/* SD Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000
+
+/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTSSP010_02_BASE		0x99400000
+/* ST UART ? SSP 02 (UART 02 in Linux) */
+#define CONFIG_FTUART010_02_BASE	0x99600000
+
+/* The following address was not defined in Linux */
+
+/* FF UART 3 */
+#define CONFIG_FTUART010_03_BASE	0x98200000
+/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000
+/* IrDA */
+#define CONFIG_IRDA_BASE		0x98900000
+/* PWM - Pulse Width Modulator Controller */
+#define CONFIG_PMW_BASE			0x99100000
+
+#endif	/* __AG101_H */
-- 
1.7.3.5

[U-Boot] [PATCH v17 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1319092871-28135-4-git-send-email-macpaul@andestech.com> you wrote:
> SoC ag101 is the first chip using NDS32 N1213 cpu core.
> Add header file of device offset support for SoC ag101.
> Add main function of SoC ag101 based on NDS32 n1213 core.
> Add lowlevel_init.S and other periphal related code.
> 
> This version of lowlevel_init.S also replace hardcode value
> by MARCO defines from the GPL version andesboot for better
> code quality.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v4:
>   - Code clean up.
> Changes for v5-v6:
>   - Split watchdog.S from lowlevel_init.S.
>   - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
>    - reset_cpu was remove inside do_reset().
>   - lowlevel_init.S
>    - Change hard code value into MARCO definitions.
>    - ftsmc010
>      - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
>    - ftsdmc021
>      - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
>      - Fix the default configuration value of FTSDMC and FTSMC controller.
>    - Remove some ftpmu010 and flash probe code to C functions.
> Changes for v7:
>   - clean up.
> Changes for v8-v9:
>   - No change.
> Changes for v10:
>   - asm-offset.c: file added for ag101 use only.
>   - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
>   - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
>   - cpu.c: remove unused cpu_init().
>   - lowlevel_init.S
>    - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
>    - Replace routings by macros to made code much easier to understand.
>    - Add debug LED support.
>    - Add CONFIG_MEM_REMAP for those boards must do memort remapping.
> Changes for v11:
>   - arch/nds32/cpu/n1213/ag101/Makefile
>    - replace $(AR) $(call cmd_link_o_target,...)
> Changes for v12:
>   - Simplify the commit log about the part of lowlevel_init.S.
> Changes for v13:
>   - arch/nds32/cpu/n1213/ag101/Makefile: remove unused gen-asm-offset.
>   - Makefile: remove unused gen-asm-offset because merged asm-offsets.
> Changes for v14:
>   - lowlevel_init.S: fix include path of <generated/asm-offsets.h>
> Changes for v15:
>   - fix sleep delay.
> Changes for v16:
>   - arch/nds32/include/asm/arch-ag101/ag101.h: fix lines over 80 characters
>   - arch/nds32/cpu/n1213/ag101/lowlevel_init.S: fix lines over 80 characters
>   - arch/nds32/cpu/n1213/ag101/timer.c: fix line over 80 characters
> Changes for v17:
>   - No changes.
> 
>  arch/nds32/cpu/n1213/ag101/Makefile        |   58 +++++++
>  arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
>  arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
>  arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
>  arch/nds32/cpu/n1213/ag101/timer.c         |  205 ++++++++++++++++++++++++
>  arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
>  arch/nds32/include/asm/arch-ag101/ag101.h  |  103 ++++++++++++
>  7 files changed, 895 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
>  create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
>  create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
>  create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
>  create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
>  create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
>  create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"I didn't know it was impossible when I did it."

[U-Boot] [PATCH v17 5/9] nds32/lib: add generic funcs in NDS32 lib

[Macpaul Lin]

Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up and formatting style.
Changes for v5-v6:
  - board.c
   - Do some clean up and add code
   - Remove display banner which hasn't support.
   - Add ftpmu010 related power management unit code.
   - Remove useless LED related code.
   - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
   - Remove CONFIG_SOFT_I2C which hasn't been support.
   - Remove CONFIG_FSL_ESDHC which hasn't been support.
   - clean up.
Changes for v7:
  - clean up.
  - move single file patch arch/nds32/config.mk to this commit.
  - interrupts.c refine origin interrupt enable and disable.
Changes for v8:
  - interrups.c: fix up for new ptraces.h.
Changes for v9:
  - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
Changes for v10:
  - config.mk:
   - add -fpie flag.
   - replace -ffixed-8 to -ffixed-10.
   - add -mrelax and --gc-sections to LDFLAG
  - board.c:
   - fix lib/board.c for relocation.
   - fix dram init for relocation.
Changes for v11:
  - arch/nds32/lib/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - config.mk
   - remove $(SRCTREE)/$(CPUDIR)/u-boot.lds
  - board.c:
   - remove obsolelte version_string.
   - remove declaration "extern __bss_end" which is not need.
   - replace sizeof(gd_t) and sizeof(bd_t) to
     GENERATED_GBL_DATA_SIZE and GENERATED_BD_INFO_SIZE
   - add memset to board info (bd)
   - remove compiler optimization barrier which is not need.
Changes for v13:
  - board.c: remove unused CONFIG_IDENT_STRING.
  - arch/nds32/lib/Makefile: remove unused clean and distclean.
Changes for v14:
  - No change.
Changes for v15:
  - lib/board.c:
   - remove duplicate pci init
   - drop NET_MULTI
Changes for v16-v17:
  - No changes.

 arch/nds32/config.mk        |   35 ++++
 arch/nds32/lib/Makefile     |   46 +++++
 arch/nds32/lib/board.c      |  439 +++++++++++++++++++++++++++++++++++++++++++
 arch/nds32/lib/bootm.c      |  241 ++++++++++++++++++++++++
 arch/nds32/lib/interrupts.c |  129 +++++++++++++
 5 files changed, 890 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/config.mk
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/board.c
 create mode 100644 arch/nds32/lib/bootm.c
 create mode 100644 arch/nds32/lib/interrupts.c

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..c589829
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common -mrelax
+PLATFORM_RELFLAGS	+= -gdwarf-2
+PLATFORM_CPPFLAGS	+= -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-10 -fpie
+
+LDFLAGS_u-boot		= --gc-sections --relax
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..e5c31c3
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+OBJS	:= board.o bootm.o interrupts.o
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..1776a72
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,439 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong monitor_flash_len;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	char tmp[64];	/* long enough for environment variables */
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+			? (int) simple_strtoul(tmp, NULL, 10)
+			: CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+void __dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size =  gd->ram_size;
+}
+void dram_init_banksize(void)
+	__attribute__((weak, alias("__dram_init_banksize")));
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	pmu_init,
+#endif
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+	display_dram_config,
+	NULL,
+};
+
+void board_init_f(ulong bootflag)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	gd_t *id;
+	ulong addr, addr_sp;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
+
+	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+
+	gd->mon_len = (unsigned int)(&__bss_end__) - (unsigned int)(&_start);
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	debug("monitor len: %08lX\n", gd->mon_len);
+	/*
+	 * Ram is setup, size stored in gd !!
+	 */
+	debug("ramsize: %08lX\n", gd->ram_size);
+
+	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	/* reserve TLB table */
+	addr -= (4096 * 4);
+
+	/* round down to next 64 kB limit */
+	addr &= ~(0x10000 - 1);
+
+	gd->tlb_addr = addr;
+	debug("TLB table at: %08lx\n", addr);
+#endif
+
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+	gd->fb_base = CONFIG_FB_ADDR;
+#else
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
+	/*
+	 * reserve memory for U-Boot code, data & bss
+	 * round down to next 4 kB limit
+	 */
+	addr -= gd->mon_len;
+	addr &= ~(4096 - 1);
+
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+
+	/*
+	 * reserve memory for malloc() arena
+	 */
+	addr_sp = addr - TOTAL_MALLOC_LEN;
+	debug("Reserving %dk for malloc() at: %08lx\n",
+			TOTAL_MALLOC_LEN >> 10, addr_sp);
+	/*
+	 * (permanently) allocate a Board Info struct
+	 * and a permanent copy of the "global" data
+	 */
+	addr_sp -= GENERATED_BD_INFO_SIZE;
+	bd = (bd_t *) addr_sp;
+	gd->bd = bd;
+	memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+			GENERATED_BD_INFO_SIZE, addr_sp);
+
+	addr_sp -= GENERATED_GBL_DATA_SIZE;
+	id = (gd_t *) addr_sp;
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			GENERATED_GBL_DATA_SIZE, addr_sp);
+
+	/* setup stackpointer for exeptions */
+	gd->irq_sp = addr_sp;
+#ifdef CONFIG_USE_IRQ
+	addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
+#endif
+	/* leave 3 words for abort-stack    */
+	addr_sp -= 12;
+
+	/* 8-byte alignment for ABI compliance */
+	addr_sp &= ~0x07;
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
+
+	gd->bd->bi_baudrate = gd->baudrate;
+	/* Ram isn't board specific, so move it to board code ... */
+	dram_init_banksize();
+	display_dram_config();	/* and display it */
+
+	gd->relocaddr = addr;
+	gd->start_addr_sp = addr_sp;
+
+	gd->reloc_off = addr - _TEXT_BASE;
+
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	memcpy(id, (void *)gd, GENERATED_GBL_DATA_SIZE);
+
+	relocate_code(addr_sp, id, addr);
+
+	/* NOTREACHED - relocate_code() does not return */
+}
+
+/*
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	char *s;
+	bd_t *bd;
+	ulong malloc_start;
+
+	extern void malloc_bin_reloc(void);
+
+	gd = id;
+	bd = gd->bd;
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	monitor_flash_len = &_end - &_start;
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
+
+	board_init();	/* Setup chipselects */
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	/*
+	 * We have to relocate the command table manually
+	 */
+	fixup_cmdtable(&__u_boot_cmd_start,
+		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
+
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+	mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+	malloc_bin_reloc();
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init();
+#endif
+
+	/* IP Address */
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+#if defined(CONFIG_USE_IRQ)
+	/* set up exceptions */
+	interrupt_init();
+	/* enable exceptions */
+	enable_interrupts();
+#endif
+
+	/* Initialize from environment */
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#if defined(CONFIG_CMD_NET)
+	puts("Net:   ");
+
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	show_boot_progress(15);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..974d52a
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"lp : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}
-- 
1.7.3.5

[U-Boot] [PATCH v17 5/9] nds32/lib: add generic funcs in NDS32 lib

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1319092871-28135-5-git-send-email-macpaul@andestech.com> you wrote:
> Add Makefile, board.c, interrupts.c and bootm.c functions
> to nds32 architecture.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v4:
>   - code clean up and formatting style.
> Changes for v5-v6:
>   - board.c
>    - Do some clean up and add code
>    - Remove display banner which hasn't support.
>    - Add ftpmu010 related power management unit code.
>    - Remove useless LED related code.
>    - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
>    - Remove CONFIG_SOFT_I2C which hasn't been support.
>    - Remove CONFIG_FSL_ESDHC which hasn't been support.
>    - clean up.
> Changes for v7:
>   - clean up.
>   - move single file patch arch/nds32/config.mk to this commit.
>   - interrupts.c refine origin interrupt enable and disable.
> Changes for v8:
>   - interrups.c: fix up for new ptraces.h.
> Changes for v9:
>   - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
> Changes for v10:
>   - config.mk:
>    - add -fpie flag.
>    - replace -ffixed-8 to -ffixed-10.
>    - add -mrelax and --gc-sections to LDFLAG
>   - board.c:
>    - fix lib/board.c for relocation.
>    - fix dram init for relocation.
> Changes for v11:
>   - arch/nds32/lib/Makefile
>    - replace $(AR) $(call cmd_link_o_target,...)
> Changes for v12:
>   - config.mk
>    - remove $(SRCTREE)/$(CPUDIR)/u-boot.lds
>   - board.c:
>    - remove obsolelte version_string.
>    - remove declaration "extern __bss_end" which is not need.
>    - replace sizeof(gd_t) and sizeof(bd_t) to
>      GENERATED_GBL_DATA_SIZE and GENERATED_BD_INFO_SIZE
>    - add memset to board info (bd)
>    - remove compiler optimization barrier which is not need.
> Changes for v13:
>   - board.c: remove unused CONFIG_IDENT_STRING.
>   - arch/nds32/lib/Makefile: remove unused clean and distclean.
> Changes for v14:
>   - No change.
> Changes for v15:
>   - lib/board.c:
>    - remove duplicate pci init
>    - drop NET_MULTI
> Changes for v16-v17:
>   - No changes.
> 
>  arch/nds32/config.mk        |   35 ++++
>  arch/nds32/lib/Makefile     |   46 +++++
>  arch/nds32/lib/board.c      |  439 +++++++++++++++++++++++++++++++++++++++++++
>  arch/nds32/lib/bootm.c      |  241 ++++++++++++++++++++++++
>  arch/nds32/lib/interrupts.c |  129 +++++++++++++
>  5 files changed, 890 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/config.mk
>  create mode 100644 arch/nds32/lib/Makefile
>  create mode 100644 arch/nds32/lib/board.c
>  create mode 100644 arch/nds32/lib/bootm.c
>  create mode 100644 arch/nds32/lib/interrupts.c

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When all else fails, read the instructions.

[U-Boot] [PATCH v17 6/9] nds32: standalone support

[Macpaul Lin]

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - code clean up.
Changes for v7-v11:
  - No change.
Changes for v12:
  - clean up for linker script.
Changes for v13-v15:
  - No change.
Changes for v16:
  - x86-testapp.c: fix line over 80 characters.
Changes for v17:
  - No change.

 examples/standalone/nds32.lds     |   56 +++++++++++++++++++++++++++++++++++++
 examples/standalone/stubs.c       |   17 ++++++++++-
 examples/standalone/x86-testapp.c |   13 ++++++++
 3 files changed, 85 insertions(+), 1 deletions(-)
 create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..50b4c4b
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	_end = .;
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 507d38c..11c7565 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
 "	jmp %%g1\n"					\
 "	nop\n"						\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	lwi	$r16, [$gp + (%0)]\n"	\
+"	lwi	$r16, [$r16 + (%1)]\n"	\
+"	jr	$r16\n"			\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
 #else
+/*"	addi	$sp, $sp, -24\n"	\
+"	br	$r16\n"			\*/
+
 #error stubs definition missing for this architecture
 #endif
 
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..1e16ec7 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,17 @@ asm volatile (						\
 "	lw	$25, %1($25)\n"				\
 "	jr	$25\n"					\
 	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x)					\
+asm volatile (						\
+"	.globl mon_" #x "\n"				\
+"mon_" #x ":\n"						\
+"	lwi	$r16, [$gp + (%0)]\n"			\
+"	lwi	$r16, [$r16 + (%1)]\n"			\
+"	jr	$r16\n"					\
+: : "i"(offsetof(xxx_t, pfunc)),			\
+"i"(XF_ ## x * sizeof(void *)) : "$r16");
+
 #else
 #error [No stub code for this arch]
 #endif
@@ -72,6 +83,8 @@ int main(void)
 	register volatile xxx_t *pq asm("r8");
 #elif defined(__mips__)
 	register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+	register volatile xxx_t *pq asm("$r16");
 #endif
 	char buf[32];
 
-- 
1.7.3.5

[U-Boot] [PATCH v17 6/9] nds32: standalone support

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1319092871-28135-6-git-send-email-macpaul@andestech.com> you wrote:
> Add standalone program related support for nds32 architecture.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v6:
>   - code clean up.
> Changes for v7-v11:
>   - No change.
> Changes for v12:
>   - clean up for linker script.
> Changes for v13-v15:
>   - No change.
> Changes for v16:
>   - x86-testapp.c: fix line over 80 characters.
> Changes for v17:
>   - No change.
> 
>  examples/standalone/nds32.lds     |   56 +++++++++++++++++++++++++++++++++++++
>  examples/standalone/stubs.c       |   17 ++++++++++-
>  examples/standalone/x86-testapp.c |   13 ++++++++
>  3 files changed, 85 insertions(+), 1 deletions(-)
>  create mode 100644 examples/standalone/nds32.lds

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
He'd been wrong, there _was_ a light at the end of the tunnel, and it
was a flamethrower.                         - Terry Pratchett, _Mort_

[U-Boot] [PATCH v17 7/9] nds32: common bdinfo, bootm, image support

[Macpaul Lin]

Add support of NDS32 to common commands bdinfo, bootm, and image format.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - Code clean up
Changes for v7-v9:
  - No Change.
Changes for v10:
  - fix up according to the changes in master tree.
Changes for v11:
  - No Change.
Changes for v12:
  - remove seldom used bi_env parameter.
Changes for v13-v14:
  - No change.
Changes for v15:
  - cmd_bootm.c and image.h
    - Fix for new image.h according to Mike's Contribute.
Changes for v16:
  - No change.
Changes for v17:
  - Fix for Sandbox added in.

 common/cmd_bdinfo.c |   25 +++++++++++++++++++++++++
 common/image.c      |    1 +
 include/image.h     |    1 +
 3 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 9c1d7d0..122729d 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -439,6 +439,31 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num("arch_number",	bd->bi_arch_number);
+	print_num("boot_params",	(ulong)bd->bi_boot_params);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
diff --git a/common/image.c b/common/image.c
index 32ad4da..1538256 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	-1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index b7caaa6..2ec31bd 100644
--- a/include/image.h
+++ b/include/image.h
@@ -107,6 +107,7 @@
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
 #define IH_ARCH_SANDBOX		19	/* Sandbox architecture (test only) */
+#define IH_ARCH_NDS32	        19	/* ANDES Technology - NDS32  */
 
 /*
  * Image Types
-- 
1.7.3.5

[U-Boot] [PATCH v17 7/9] nds32: common bdinfo, bootm, image support

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1319092871-28135-7-git-send-email-macpaul@andestech.com> you wrote:
> Add support of NDS32 to common commands bdinfo, bootm, and image format.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v6:
>   - Code clean up
> Changes for v7-v9:
>   - No Change.
> Changes for v10:
>   - fix up according to the changes in master tree.
> Changes for v11:
>   - No Change.
> Changes for v12:
>   - remove seldom used bi_env parameter.
> Changes for v13-v14:
>   - No change.
> Changes for v15:
>   - cmd_bootm.c and image.h
>     - Fix for new image.h according to Mike's Contribute.
> Changes for v16:
>   - No change.
> Changes for v17:
>   - Fix for Sandbox added in.
> 
>  common/cmd_bdinfo.c |   25 +++++++++++++++++++++++++
>  common/image.c      |    1 +
>  include/image.h     |    1 +
>  3 files changed, 27 insertions(+), 0 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"There is nothing  so  deadly  as  not  to  hold  up  to  people  the
opportunity to do great and wonderful things, if we wish to stimulate
them in an active way."
- Dr. Harold Urey, Nobel Laureate in chemistry

[U-Boot] [PATCH v17 8/9] adp-ag101: add board adp-ag101 support

[Macpaul Lin]

Add evaluation board "adp-ag101" configuration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up
Changes for v5-v6:
  - Refine the definitions and parameters about CLK,
    AHB controller, SDRAM controller, Static memory controllers.
  - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
  - ftahbc010:
    - Update include path of ftahbc010.
  - ftsdmc021:
    - Update include path of ftsdmc021.
  - ftsmc020:
    - Update include path of ftsmc020.
  - ftwdt010:
    - Fix WDT define and update include path.
    - Fix ftwdt010 for hardware reset.
  - ftpmu010:
    - Remove duplicate PMU definitions.
    - Add related configurations.
  - Fix MAX malloc len and fix saveenv.
  - clean up.
Changes for v7:
  - clean up.
  - Move CONFIG_SYS_TEXT_BASE from board/config.mk.
  - Fix Makefile and remove config.mk
Changes for v8:
  - No change.
Changes for v9:
  - Fix because other boards has been added into boards.cfg and
    broken this patch.
Changes for v10:
  - adp-ag101.h
   - Fix lines over 80 characters.
   - Fix for introducing gen-asm-offset.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix flash init.
   - fix ftsmc010 configuraion for flash probing.
   - Add SP_INIT related configurations for supporting relocation.
   - Fix CONFIG_TEXT_BASE for relocation.
   - Add CONFIG_MEM_REMAP for some hardware boards and non-OS application.
  - adp-ag101.c
   - Clean up for braces according to Wolfgang's suggestion.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix dram init(), made this more simpler.
Changes for v11:
  - No change.
Changes for v12:
  - adp-ag101.h
   - fix address when enable CONFIG_SKIP_LOWLEVEL_INIT
Changes for v13:
  - board/AndesTech/adp-ag101/Makefile: remove unused clean and distclean.
Changes for v14:
  - No change.
Changes for v15:
  - adp-ag101.h: drop NET_MULTI
  - Makefile: clean up Makefile
Changes for v16:
  - No change.
Changes for v17:
  - Fix boards.cfg (update only).

 MAINTAINERS                           |   11 +
 MAKEALL                               |    6 +
 board/AndesTech/adp-ag101/Makefile    |   44 ++++
 board/AndesTech/adp-ag101/adp-ag101.c |   89 +++++++
 boards.cfg                            |    1 +
 include/configs/adp-ag101.h           |  406 +++++++++++++++++++++++++++++++++
 6 files changed, 557 insertions(+), 0 deletions(-)
 create mode 100644 board/AndesTech/adp-ag101/Makefile
 create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
 create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index bb95e6d..e648ccf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1124,5 +1124,16 @@ Chong Huang <chuang@ucrobotics.com>
 	bf525-ucr2	BF525
 
 #########################################################################
+# NDS32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+	ADP-AG101	N1213 (AG101 SoC)
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index f582f8b..7b3a75d 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -483,6 +483,12 @@ LIST_sh="$(boards_by_arch sh)"
 
 LIST_sparc="$(boards_by_arch sparc)"
 
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
 #-----------------------------------------------------------------------
 
 build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..d55a799
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= adp-ag101.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..82ce4c9
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	ftsdc010_mmc_init(0);
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 1e3bfdc..049fcb4 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -305,6 +305,7 @@ vct_platinumavc_onenand      mips        mips32      vct                 microna
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
 qi_lb60                      mips        xburst      qi_lb60             qi
 nios2-generic                nios2       nios2       nios2-generic       altera
+adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..8421c79
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,406 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x03200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_CMD_FAT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#else
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#endif
+
+/*
+ * There are 2 bank connected to FTSMC020 on ADP-AG101.
+ * You can use jumper and switch to force it booted from ROM or FLASH.
+ * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
+ * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
+ * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
+ *    Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
+ * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
+				 FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M	|	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_RBE	|	\
+				 FTSMC020_TPR_AST(1)	|	\
+				 FTSMC020_TPR_CTW(1)	|	\
+				 FTSMC020_TPR_ATI(1)	|	\
+				 FTSMC020_TPR_AT2(1)	|	\
+				 FTSMC020_TPR_WTC(1)	|	\
+				 FTSMC020_TPR_AHT(1)	|	\
+				 FTSMC020_TPR_TRNA(1))
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif	/* CONFIG_MEM_REMAP */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif	/* __CONFIG_H */
-- 
1.7.3.5

[U-Boot] [PATCH v17 8/9] adp-ag101: add board adp-ag101 support

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1319092871-28135-8-git-send-email-macpaul@andestech.com> you wrote:
> Add evaluation board "adp-ag101" configuration file adp-ag101.h.
> Add adp-ag101.c board config and related settings.
> Add board adp-ag101 into boards.cfg
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v4:
>   - code clean up
> Changes for v5-v6:
>   - Refine the definitions and parameters about CLK,
>     AHB controller, SDRAM controller, Static memory controllers.
>   - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
>   - ftahbc010:
>     - Update include path of ftahbc010.
>   - ftsdmc021:
>     - Update include path of ftsdmc021.
>   - ftsmc020:
>     - Update include path of ftsmc020.
>   - ftwdt010:
>     - Fix WDT define and update include path.
>     - Fix ftwdt010 for hardware reset.
>   - ftpmu010:
>     - Remove duplicate PMU definitions.
>     - Add related configurations.
>   - Fix MAX malloc len and fix saveenv.
>   - clean up.
> Changes for v7:
>   - clean up.
>   - Move CONFIG_SYS_TEXT_BASE from board/config.mk.
>   - Fix Makefile and remove config.mk
> Changes for v8:
>   - No change.
> Changes for v9:
>   - Fix because other boards has been added into boards.cfg and
>     broken this patch.
> Changes for v10:
>   - adp-ag101.h
>    - Fix lines over 80 characters.
>    - Fix for introducing gen-asm-offset.
>    - Add mmc support for FTSDC010 SD/MMC Controller.
>    - fix flash init.
>    - fix ftsmc010 configuraion for flash probing.
>    - Add SP_INIT related configurations for supporting relocation.
>    - Fix CONFIG_TEXT_BASE for relocation.
>    - Add CONFIG_MEM_REMAP for some hardware boards and non-OS application.
>   - adp-ag101.c
>    - Clean up for braces according to Wolfgang's suggestion.
>    - Add mmc support for FTSDC010 SD/MMC Controller.
>    - fix dram init(), made this more simpler.
> Changes for v11:
>   - No change.
> Changes for v12:
>   - adp-ag101.h
>    - fix address when enable CONFIG_SKIP_LOWLEVEL_INIT
> Changes for v13:
>   - board/AndesTech/adp-ag101/Makefile: remove unused clean and distclean.
> Changes for v14:
>   - No change.
> Changes for v15:
>   - adp-ag101.h: drop NET_MULTI
>   - Makefile: clean up Makefile
> Changes for v16:
>   - No change.
> Changes for v17:
>   - Fix boards.cfg (update only).
> 
>  MAINTAINERS                           |   11 +
>  MAKEALL                               |    6 +
>  board/AndesTech/adp-ag101/Makefile    |   44 ++++
>  board/AndesTech/adp-ag101/adp-ag101.c |   89 +++++++
>  boards.cfg                            |    1 +
>  include/configs/adp-ag101.h           |  406 +++++++++++++++++++++++++++++++++
>  6 files changed, 557 insertions(+), 0 deletions(-)
>  create mode 100644 board/AndesTech/adp-ag101/Makefile
>  create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
>  create mode 100644 include/configs/adp-ag101.h

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"'Tis true, 'tis pity, and pity 'tis 'tis true."
    - Poloniouius, in Willie the Shake's _Hamlet, Prince of Darkness_

[U-Boot] [PATCH v17 9/9] doc/README: documents and readme for NDS32 arch

[Macpaul Lin]

Documents and READMEs for NDS32 architecture.
It patch also provides usage of SoC AG101 and board ADP-AG101.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v10:
  - The patch of documentation was not included.
Changes for v11:
  - Add the documents of NDS32, ag101, N1213.
Changes for v12-v16:
  - No change.
Changes for v17:
  - Fix README (update only).

 README                |   24 ++++++++++++++--
 doc/README.N1213      |   55 ++++++++++++++++++++++++++++++++++++
 doc/README.NDS32      |   41 +++++++++++++++++++++++++++
 doc/README.ag101      |   74 +++++++++++++++++++++++++++++++++++++++++++++++++
 doc/README.standalone |    1 +
 5 files changed, 192 insertions(+), 3 deletions(-)
 create mode 100644 doc/README.N1213
 create mode 100644 doc/README.NDS32
 create mode 100644 doc/README.ag101

diff --git a/README b/README
index eb9ade9..c6b179c 100644
--- a/README
+++ b/README
@@ -183,6 +183,10 @@ Directory Hierarchy:
       /mips32		Files specific to MIPS32 CPUs
       /xburst		Files specific to Ingenic XBurst CPUs
     /lib		Architecture specific library files
+  /nds32		Files generic to NDS32 architecture
+    /cpu		CPU specific files
+      /n1213		Files specific to Andes Technology N1213 CPUs
+    /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
@@ -3156,7 +3160,7 @@ Low Level (hardware related) configuration options:
 		globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-		[ARM, MIPS only] If this variable is defined, then certain
+		[ARM, NDS32, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
@@ -3723,8 +3727,8 @@ details; basically, the header defines the following image properties:
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
-  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
+  IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -4417,6 +4421,20 @@ On Nios II, the ABI is documented here:
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 
+On NDS32, the following registers are used:
+
+	R0-R1:	argument/return
+	R2-R5:	argument
+	R15:	temporary register for assembler
+	R16:	trampoline register
+	R28:	frame pointer (FP)
+	R29:	global pointer (GP)
+	R30:	link register (LP)
+	R31:	stack pointer (SP)
+	PC:	program counter (PC)
+
+    ==> U-Boot will use R10 to hold a pointer to the global data
+
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 
diff --git a/doc/README.N1213 b/doc/README.N1213
new file mode 100644
index 0000000..e107166
--- /dev/null
+++ b/doc/README.N1213
@@ -0,0 +1,55 @@
+N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
+
+Features
+========
+
+CPU Core
+ - 16-/32-bit mixable instruction format.
+ - 32 general-purpose 32-bit registers.
+ - 8-stage pipeline.
+ - Dynamic branch prediction.
+ - 32/64/128/256 BTB.
+ - Return address stack (RAS).
+ - Vector interrupts for internal/external.
+   interrupt controller with 6 hardware interrupt signals.
+ - 3 HW-level nested interruptions.
+ - User and super-user mode support.
+ - Memory-mapped I/O.
+ - Address space up to 4GB.
+
+Memory Management Unit
+ - TLB
+   - 4/8-entry fully associative iTLB/dTLB.
+   - 32/64/128-entry 4-way set-associati.ve main TLB.
+   - TLB locking support
+ - Optional hardware page table walker.
+ - Two groups of page size support.
+  - 4KB & 1MB.
+  - 8KB & 1MB.
+
+Memory Subsystem
+ - I & D cache.
+   - Virtually indexed and physically tagged.
+   - Cache size: 8KB/16KB/32KB/64KB.
+   - Cache line size: 16B/32B.
+   - Set associativity: 2-way, 4-way or direct-mapped.
+   - Cache locking support.
+ - I & D local memory (LM).
+   - Size: 4KB to 1MB.
+   - Bank numbers: 1 or 2.
+   - Optional 1D/2D DMA engine.
+   - Internal or external to CPU core.
+
+Bus Interface
+ - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
+ - Synchronous High speed memory port.
+   (HSMP): 0, 1 or 2 ports.
+
+Debug
+ - JTAG debug interface.
+ - Embedded debug module (EDM).
+ - Optional embedded program tracer interface.
+
+Miscellaneous
+ - Programmable data endian control.
+ - Performance monitoring mechanism.
diff --git a/doc/README.NDS32 b/doc/README.NDS32
new file mode 100644
index 0000000..b2b58fc
--- /dev/null
+++ b/doc/README.NDS32
@@ -0,0 +1,41 @@
+NDS32 is a new high-performance 32-bit RISC microprocessor core.
+
+http://www.andestech.com/
+
+AndeStar ISA
+============
+AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
+achieve optimal system performance, code density, and power efficiency.
+
+It contains the following features:
+ - Intermixable 32-bit and 16-bit instruction sets without the need for
+   mode switch.
+ - 16-bit instructions as a frequently used subset of 32-bit instructions.
+ - RISC-style register-based instruction set.
+ - 32 32-bit General Purpose Registers (GPR).
+ - Upto 1024 User Special Registers (USR) for existing and extension
+   instructions.
+ - Rich load/store instructions for...
+   - Single memory access with base address update.
+   - Multiple aligned and unaligned memory accesses for memory copy and stack
+     operations.
+   - Data prefetch to improve data cache performance.
+   - Non-bus locking synchronization instructions.
+ - PC relative jump and PC read instructions for efficient position independent
+   code.
+ - Multiply-add and multiple-sub with 64-bit accumulator.
+ - Instruction for efficient power management.
+ - Bi-endian support.
+ - Three instruction extension space for application acceleration:
+   - Performance extension.
+   - Andes future extensions (for floating-point, multimedia, etc.)
+   - Customer extensions.
+
+AndesCore CPU
+=============
+Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
+
+For details about N12 CPU family, please check doc/README.N1213.
+
+The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
+other associated software are actively supported by Andes Technology Corporation.
diff --git a/doc/README.ag101 b/doc/README.ag101
new file mode 100644
index 0000000..46fc637
--- /dev/null
+++ b/doc/README.ag101
@@ -0,0 +1,74 @@
+Andes Technology SoC AG101
+==========================
+
+AG101 is the first SoC produced by Andes Technology using N1213 CPU core.
+AG101 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG101
+=========
+
+ADP-AG101 is the SoC with AG101 hardcore CPU.
+
+Please check http://www.andestech.com/p2-4.htm for detail of this SoC.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+	This is also a must on ADP-AG101 board.
+	(While other boards may not have this problem).
+
+	The reason is because the ROM/FLASH circuit on PCB board.
+	AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	ROM/FLASH is used to boot.
+
+	When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	and the FLASH is connected to BANK1.
+	When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	and the FLASH is connected to BANK0.
+	It will occur problem when doing flash probing if the flash is at
+	BANK0 (0x00000000) while memory remapping was skipped.
+
+	Other board like ADP-AG101P may not enable this since there is only
+	a FLASH connected to bank0.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from FLASH and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag101.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101` in u-boot root to build the image.
+
+burn u-boot to flash:
+1. Make sure the MA17 (J16) is Lo.
+2. Make sure the dip switch SW5 is set to "0101".
+3. Power On. Press button "S1", then press button "SW1", then you will found the
+   debug LED show 67 means the system successfully booted into e-bios.
+   Now you can control the e-bios boot loader from your console.
+4. Under "Command>>" prompt, enter "97" (CopyImageFromCard)
+5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c".
+6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you
+   just build. It is usually "u-boot.bin".
+7. Under "Enter Dest. Address =>" prompt, enter the memory address where you
+   want to put the binary from SD card to RAM.
+   Address "0x500000" is our suggestion.
+8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command
+   environment.
+9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the
+   binary from RAM to FLASH.
+10. Under "CLI>" prompt, enter "exit" to finish the burn process.
+
+boot u-boot from flash:
+1. Make sure the MA17 (J16) is Hi).
+2. Make sure the dip switch SW5 is set to "1010".
+3. Power On. Press button "S1", then you will see the debug LED count to 20.
+4. Now you can use u-boot on ADP-AG101 board.
diff --git a/doc/README.standalone b/doc/README.standalone
index 6e6b65f..2be5f27 100644
--- a/doc/README.standalone
+++ b/doc/README.standalone
@@ -56,6 +56,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
 	ARM		0x0c100000	0x0c100000
 	MIPS		0x80200000	0x80200000
 	Blackfin	0x00001000	0x00001000
+	NDS32		0x00300000	0x00300000
 	Nios II		0x02000000	0x02000000
 
    For example, the "hello world" application may be loaded and
-- 
1.7.3.5

[U-Boot] [PATCH v17 9/9] doc/README: documents and readme for NDS32 arch

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1319092871-28135-9-git-send-email-macpaul@andestech.com> you wrote:
> Documents and READMEs for NDS32 architecture.
> It patch also provides usage of SoC AG101 and board ADP-AG101.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v10:
>   - The patch of documentation was not included.
> Changes for v11:
>   - Add the documents of NDS32, ag101, N1213.
> Changes for v12-v16:
>   - No change.
> Changes for v17:
>   - Fix README (update only).
> 
>  README                |   24 ++++++++++++++--
>  doc/README.N1213      |   55 ++++++++++++++++++++++++++++++++++++
>  doc/README.NDS32      |   41 +++++++++++++++++++++++++++
>  doc/README.ag101      |   74 +++++++++++++++++++++++++++++++++++++++++++++++++
>  doc/README.standalone |    1 +
>  5 files changed, 192 insertions(+), 3 deletions(-)
>  create mode 100644 doc/README.N1213
>  create mode 100644 doc/README.NDS32
>  create mode 100644 doc/README.ag101

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is more rational to sacrifice one life than six.
	-- Spock, "The Galileo Seven", stardate 2822.3

[U-Boot] [PATCH v15 2/9] nds32: add NDS32 support into common header file

[Macpaul Lin]

Add NDS32 support into common header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v7:
  - No change
Changes for v8:
  - Fix the patch according to dependency of x86's Fix
Changes for v9-v15:
  - No change

 include/common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/common.h b/include/common.h
index bcc00e8..42b00a0 100644
--- a/include/common.h
+++ b/include/common.h
@@ -302,6 +302,10 @@ int	setenv	     (const char *, const char *);
 #ifdef CONFIG_X86		/* x86 version to be fixed! */
 # include <asm/u-boot-x86.h>
 #endif /* CONFIG_X86 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h>	/* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
-- 
1.7.3.5

[U-Boot] [PATCH v15 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Macpaul Lin]

Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
Changes v1 to v6:
  - Style clean up and reorganize code
Changes v7-v9:
  - No Change.
Changes v10:
  - start.S of N1213 CPU has been rewrote for relocation support.
  - u-boot.lds:
   - Add got and *(.got.plt) section for support GCC 4 toolchain
   - Modified for relocation implementation.
Changes v11:
  - arch/nds32/cpu/n1213/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes v12:
  - u-boot.lds
   - Remove the 0x00000000 base address in linker script.
     The base address of the binary will be determined by CONFIG_SYS_TEXT_BASE
  - Remove the CPU features in commit log and add to README in later patches.
Changes v13-v14:
  - No change.
Changes v15:
  - start.S: fix exception vector aligment (add setivb in reset vector).

 arch/nds32/cpu/n1213/Makefile   |   50 ++++
 arch/nds32/cpu/n1213/start.S    |  509 +++++++++++++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/u-boot.lds |   70 ++++++
 3 files changed, 629 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/Makefile
 create mode 100644 arch/nds32/cpu/n1213/start.S
 create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..da15574
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..14ccd41
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,509 @@
+/*
+ *	Andesboot - Startup Code for Whitiger core
+ *
+ *	Copyright (C) 2006	Andes Technology Corporation
+ *	Copyright (C) 2006	Shawn Lin <nobuhiro@andestech.com>
+ *	Copyright (C) 2011	Macpaul Lin <macpaul@andestech.com>
+ *				Greentime Hu <greentime@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <asm/macro.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC		2UL
+#define DIS_DCAC		~ENA_DCAC
+#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
+#define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
+#define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY	(0x07<<3)	! D cache ways
+#define DCAC_MEM_KBF_DSZ	(0x07<<6)	! D cache line size
+
+#define PSW			$ir0
+#define EIT_INTR_PSW		$ir1		! interruption $PSW
+#define EIT_PREV_IPSW		$ir2		! previous $IPSW
+#define EIT_IVB			$ir3		! intr vector base address
+#define EIT_EVA			$ir4		! MMU related Exception Virtual Address register
+#define EIT_PREV_EVA		$ir5		! previous $eva
+#define EIT_ITYPE		$ir6		! interruption type
+#define EIT_PREV_ITYPE		$ir7		! prev intr type
+#define EIT_MACH_ERR		$ir8		! machine error log
+#define EIT_INTR_PC		$ir9		! Interruption PC
+#define EIT_PREV_IPC		$ir10		! previous $IPC
+#define EIT_OVL_INTR_PC		$ir11		! overflow interruption PC
+#define EIT_PREV_P0		$ir12		! prev $P0
+#define EIT_PREV_P1		$ir13		! prev $p1
+#define CR_ICAC_MEM		$cr1		! I-cache/memory config reg
+#define CR_DCAC_MEM		$cr2		! D-cache/memory config reg
+#define MR_CAC_CTL		$mr8
+
+.globl _start
+
+_start:	j	reset
+	j	tlb_fill
+	j	tlb_not_present
+	j	tlb_misc
+	j	tlb_vlpt_miss
+	j	cache_parity_error
+	j	debug
+	j	general_exception
+	j	internal_interrupt		! H0I
+	j	internal_interrupt		! H1I
+	j	internal_interrupt		! H2I
+	j	internal_interrupt		! H3I
+	j	internal_interrupt		! H4I
+	j	internal_interrupt		! H5I
+
+	.balign 16
+
+/*
+ * Andesboot Startup Code (reset vector)
+ *
+ *	1.	bootstrap
+ *		1.1 reset - start of u-boot
+ *		1.2 to superuser mode - as is when reset
+ *		1.4 Do lowlevel_init
+ *			- (this will jump out to lowlevel_init.S in SoC)
+ *			- (lowlevel_init)
+ *		1.3 Turn off watchdog timer
+ *			- (this will jump out to watchdog.S in SoC)
+ *			- (turnoff_watchdog)
+ *	2.	Do critical init when reboot (not from mem)
+ *	3.	Relocate andesboot to ram
+ *	4.	Setup stack
+ *	5.	Jump to second stage (board_init_r)
+ */
+
+/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word 0x0badc0de
+
+/*
+ * The bootstrap code of nds32 core
+ */
+
+reset:
+set_ivb:
+	li	$r0, 0x0
+
+	/* turn on BTB */
+	mtsr	$r0, $misc_ctl
+	/* set IVIC, vector size: 4 bytes, base: 0x0 */
+	mtsr	$r0, $ivb
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	jal	load_lowlevel_init
+	jral	$p0
+#endif
+
+/*
+ * Set the N1213 (Whitiger) core to superuser mode
+ * According to spec, it is already when reset
+ */
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+	jal	load_turnoff_watchdog
+	jral	$p0
+#endif
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+	bal	cpu_init_crit		! Do CPU critical regs init
+#endif
+
+/*
+ * Set stackpointer in internal RAM to call board_init_f
+ * $sp must be 8-byte alignment for ABI compliance.
+ */
+call_board_init_f:
+	li	$sp, CONFIG_SYS_INIT_SP_ADDR
+	li	$r0, 0x00000000
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__
+/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
+	la	$r15, board_init_f	! store function address into $r15
+#endif
+#endif
+	j	board_init_f		! jump to board_init_f() in lib/board.c
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl	relocate_code
+relocate_code:
+	move	$r4, $r0		/* save addr_sp */
+	move	$r5, $r1		/* save addr of gd */
+	move	$r6, $r2		/* save addr of destination */
+
+/* Set up the stack */
+stack_setup:
+	move	$sp, $r4
+
+	la	$r0, _start
+
+	beq	$r0, $r6, clear_bss	/* skip relocation */
+
+	move	$r1, $r6		/* r1 <- scratch for copy_loop */
+	la	$r3, __bss_start
+	sub	$r3, $r3, $r0		/* r3 <- __bss_start_ofs */
+	add	$r2, $r0, $r3		/* r2 <- source end address */
+
+copy_loop:
+	lwi.p	$r7, [$r0], #4
+	swi.p	$r7, [$r1], #4
+	blt	$r0, $r2, copy_loop
+
+/*
+ * fix relocations related issues
+ */
+fix_relocations:
+	l.w	$r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	$r9, $r6, $r0		/* r9 <- relocation offset */
+
+fix_got:
+/*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+	la	$r2, __got_start	/* r2 <- rel __got_start in FLASH */
+	add	$r2, $r2, $r9		/* r2 <- rel __got_start in RAM */
+	la	$r3, __got_end		/* r3 <- rel __got_end in FLASH */
+	add	$r3, $r3, $r9		/* r3 <- rel __got_end in RAM */
+	addi	$r2, $r2, #8		/* skipping first two entries */
+fix_got_loop:
+	lwi	$r0, [$r2]		/* r0 <- location in FLASH to fix up */
+	add	$r0, $r0, $r9		/* r0 <- location fix up to RAM */
+	swi.p	$r0, [$r2], #4		/* r0 <- store fix into .got in RAM */
+	blt	$r2, $r3, fix_got_loop
+
+clear_bss:
+	la	$r0, __bss_start	/* r0 <- rel __bss_start in FLASH */
+	add	$r0, $r0, $r9		/* r0 <- rel __bss_start in FLASH */
+	la	$r1, __bss_end__	/* r1 <- rel __bss_end in RAM */
+	add	$r1, $r1, $r9		/* r0 <- rel __bss_end in RAM */
+	li	$r2, 0x00000000		/* clear */
+
+clbss_l:
+	sw	$r2, [$r0]		/* clear loop... */
+	addi	$r0, $r0, #4
+	bne	$r0, $r1, clbss_l
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+	la	$r0, board_init_r
+	move	$lp, $r0		/* offset of board_init_r() */
+	add	$lp, $lp, $r9		/* real address of board_init_r() */
+	/* setup parameters for board_init_r */
+	move	$r0, $r5		/* gd_t */
+	move	$r1, $r6		/* dest_addr */
+
+#ifdef __PIC__
+#ifdef __NDS32_N1213_43U1H__		/* NDS32 V0 ISA	*/
+	move	$r15, $lp		/* store function address into $r15 */
+#endif
+#endif
+
+	/* jump to it ... */
+	jr	$lp			/* jump to board_init_r() */
+
+/*
+ * Initialize CPU critical registers
+ *
+ *	1.	Setup control registers
+ *		1.1 Mask all IRQs
+ *		1.2 Flush cache and TLB
+ *		1.3 Disable MMU and cache
+ *	2.	Setup memory timing
+ */
+
+cpu_init_crit:
+
+	move	$r0, $lp		/* push	ra */
+
+	/* Disable Interrupts by clear GIE in $PSW reg */
+	setgie.d
+
+	/* Flush caches and TLB */
+	/* Invalidate caches */
+	bal	invalidate_icac
+	bal	invalidate_dcac
+
+	/* Flush TLB */
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+
+1:
+	! Disable MMU, Dcache
+	! Whitiger is MMU disabled when reset
+	! Disable the D$
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Set DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! write back the $CACHE_CTL reg
+	isb
+
+	move	$lp, $r0
+2:
+	ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+	la  $r6, lowlevel_init
+	la  $r7, load_lli + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+	la  $r6, turnoff_watchdog
+	la  $r7, turnoff_wtdog + 4
+	sub $p0, $r6, $r7
+	add $p0, $p0, $lp
+ret
+#endif
+
+/*
+ * Invalidate I$
+ */
+invalidate_icac:
+	mfsr	$t0, CR_ICAC_MEM		! read $cr1(I CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, ICAC_MEM_KBF_ISZ 	! Get the ISZ field
+	beqz	$p0, end_flush_icache		! if $p0=0, then no I CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of I$ block
+	addi	$t1, $p0, 2			! $t1= bit width of I cache line size(ISZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, ICAC_MEM_KBF_ISET	! get the ISET field
+	addi	$t2, $p1, 6			! $t2= bit width of ISET
+	andi	$p1, $t0, ICAC_MEM_KBF_IWAY	! get bitfield of Iway
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is I way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+ICAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1I_IX_INVAL
+	bnez	$p1, ICAC_LOOP
+end_flush_icache:
+	ret
+
+/*
+ * Invalidate D$
+ */
+invalidate_dcac:
+	mfsr	$t0, CR_DCAC_MEM		! read $cr2(D CAC/MEM cfg. reg.) configuration
+	andi	$p0, $t0, DCAC_MEM_KBF_DSZ	! Get the DSZ field
+	beqz	$p0, end_flush_dcache		! if $p0=0, then no D CAC existed
+	srli	$p0, $p0, 6			! get $p0 the index of D$ block
+	addi	$t1, $p0, 2			! $t1= bit width of D cache line size(DSZ)
+	li	$t4, 1
+	sll	$t5, $t4, $t1			! get $t5 cache line size
+	andi	$p1, $t0, DCAC_MEM_KBF_DSET	! get the DSET field
+	addi	$t2, $p1, 6			! $t2= bit width of DSET
+	andi	$p1, $t0, DCAC_MEM_KBF_DWAY	! get bitfield of D way
+	srli	$p1, $p1, 3
+	addi	$p1, $p1, 1			! then $p1 is D way number
+	add	$t3, $t2, $t1			! SHIFT
+	sll	$p1, $p1, $t3			! GET the total cache size
+DCAC_LOOP:
+	sub	$p1, $p1, $t5
+	cctl	$p1, L1D_IX_INVAL
+	bnez	$p1, DCAC_LOOP
+end_flush_dcache:
+	ret
+
+/*
+ * Interrupt handling
+ */
+
+/*
+ * exception handlers
+ */
+	.align	5
+
+.macro	SAVE_ALL
+	! FIXME: Other way to get PC?
+	! FIXME: Update according to the newest spec!!
+1:
+	la	 $r28, 1
+	push $r28
+	mfsr $r28, PSW			! $PSW
+	push $r28
+	mfsr $r28, EIT_EVA		! $ir1 $EVA
+	push $r28
+	mfsr $r28, EIT_ITYPE		! $ir2 $ITYPE
+	push $r28
+	mfsr $r28, EIT_MACH_ERR		! $ir3 Mach Error
+	push $r28
+	mfsr $r28, EIT_INTR_PSW		! $ir5 $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_IPSW	! $ir6 prev $IPSW
+	push $r28
+	mfsr $r28, EIT_PREV_EVA		! $ir7 prev $EVA
+	push $r28
+	mfsr $r28, EIT_PREV_ITYPE	! $ir8 prev $ITYPE
+	push $r28
+	mfsr $r28, EIT_INTR_PC		! $ir9 Interruption PC
+	push $r28
+	mfsr $r28, EIT_PREV_IPC		! $ir10 prev INTR_PC
+	push $r28
+	mfsr $r28, EIT_OVL_INTR_PC	! $ir11 Overflowed INTR_PC
+	push $r28
+	mfusr $r28, $d1.lo
+	push $r28
+	mfusr $r28, $d1.hi
+	push $r28
+	mfusr $r28, $d0.lo
+	push $r28
+	mfusr $r28, $d0.hi
+	push $r28
+	pushm $r0, $r30		! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
+	addi	$sp, $sp, -4	! make room for implicit pt_regs parameters
+.endm
+
+	.align	5
+tlb_fill:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 1				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_not_present:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 2				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_misc:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 3				! Determine interruption type
+	bal 	do_interruption
+
+	.align	5
+tlb_vlpt_miss:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 4				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+cache_parity_error:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 5				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+debug:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 6				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+general_exception:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 7				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+internal_interrupt:
+	SAVE_ALL
+	move	$r0, $sp			! To get the kernel stack
+	li	$r1, 8				! Determine interruption type
+	bal	do_interruption
+
+	.align	5
+
+/*
+ * void reset_cpu(ulong addr);
+ * $r0: input address to jump to
+ */
+.globl reset_cpu
+reset_cpu:
+/* No need to disable MMU because we never enable it */
+
+	bal	invalidate_icac
+	bal	invalidate_dcac
+	mfsr	$p0, $MMU_CFG
+	andi	$p0, $p0, 0x3			! MMPS
+	li	$p1, 0x2			! TLB MMU
+	bne	$p0, $p1, 1f
+	tlbop	flushall			! Flush TLB
+1:
+	mfsr	$p0, MR_CAC_CTL			! Get the $CACHE_CTL reg
+	li	$p1, DIS_DCAC
+	and	$p0, $p0, $p1			! Clear the DC_EN bit
+	mtsr	$p0, MR_CAC_CTL			! Write back the $CACHE_CTL reg
+	br	$r0				! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..45221ee
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		arch/nds32/cpu/n1213/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		 *(.got.plt) *(.got)
+		__got_end = .;
+	}
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+}
-- 
1.7.3.5

[U-Boot] [PATCH v15 3/9] nds32/core N1213: NDS32 N12 core family N1213

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1317896723-9284-3-git-send-email-macpaul@andestech.com> you wrote:
> Add N1213 cpu core (N12 Core family) support for NDS32 arch.
> This patch includes start.S for the initialize procedure of N1213.
> 
> Start procedure:
>  start.S will start up the N1213 CPU core at first,
>  then jump to SoC dependent "lowlevel_init.S" and
>  "watchdog.S" to configure peripheral devices.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> Signed-off-by: Greentime Hu <greentime@andestech.com>
> ---
> Changes v1 to v6:
>   - Style clean up and reorganize code
> Changes v7-v9:
>   - No Change.
> Changes v10:
>   - start.S of N1213 CPU has been rewrote for relocation support.
>   - u-boot.lds:
>    - Add got and *(.got.plt) section for support GCC 4 toolchain
>    - Modified for relocation implementation.
> Changes v11:
>   - arch/nds32/cpu/n1213/Makefile
>    - replace $(AR) $(call cmd_link_o_target,...)
> Changes v12:
>   - u-boot.lds
>    - Remove the 0x00000000 base address in linker script.
>      The base address of the binary will be determined by CONFIG_SYS_TEXT_BASE
>   - Remove the CPU features in commit log and add to README in later patches.
> Changes v13-v14:
>   - No change.
> Changes v15:
>   - start.S: fix exception vector aligment (add setivb in reset vector).
> 
>  arch/nds32/cpu/n1213/Makefile   |   50 ++++
>  arch/nds32/cpu/n1213/start.S    |  509 +++++++++++++++++++++++++++++++++++++++
>  arch/nds32/cpu/n1213/u-boot.lds |   70 ++++++
>  3 files changed, 629 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/cpu/n1213/Makefile
>  create mode 100644 arch/nds32/cpu/n1213/start.S
>  create mode 100644 arch/nds32/cpu/n1213/u-boot.lds

Checkpatch says:

total: 0 errors, 7 warnings, 629 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"I knew then (in 1970) that a 4-kbyte minicomputer would cost as much
as a house. So I reasoned  that  after  college,  I'd  have  to  live
cheaply in an apartment and put all my money into owning a computer."
      - Apple co-founder Steve Wozniak, EE Times, June 6, 1988, pg 45

[U-Boot] [PATCH v15 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Macpaul Lin]

SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
Add lowlevel_init.S and other periphal related code.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - Code clean up.
Changes for v5-v6:
  - Split watchdog.S from lowlevel_init.S.
  - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
   - reset_cpu was remove inside do_reset().
  - lowlevel_init.S
   - Change hard code value into MARCO definitions.
   - ftsmc010
     - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
   - ftsdmc021
     - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
     - Fix the default configuration value of FTSDMC and FTSMC controller.
   - Remove some ftpmu010 and flash probe code to C functions.
Changes for v7:
  - clean up.
Changes for v8-v9:
  - No change.
Changes for v10:
  - asm-offset.c: file added for ag101 use only.
  - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
  - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
  - cpu.c: remove unused cpu_init().
  - lowlevel_init.S
   - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
   - Replace routings by macros to made code much easier to understand.
   - Add debug LED support.
   - Add CONFIG_MEM_REMAP for those boards must do memort remapping.
Changes for v11:
  - arch/nds32/cpu/n1213/ag101/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - Simplify the commit log about the part of lowlevel_init.S.
Changes for v13:
  - arch/nds32/cpu/n1213/ag101/Makefile: remove unused gen-asm-offset.
  - Makefile: remove unused gen-asm-offset because merged asm-offsets.
Changes for v14:
  - lowlevel_init.S: fix include path of <generated/asm-offsets.h>
Changes for v15:
  - fix sleep delay.

 arch/nds32/cpu/n1213/ag101/Makefile        |   58 +++++++
 arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
 arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/timer.c         |  204 ++++++++++++++++++++++++
 arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
 arch/nds32/include/asm/arch-ag101/ag101.h  |   68 ++++++++
 7 files changed, 859 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
 create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
 create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
 create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..8716c4e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
new file mode 100644
index 0000000..92ada8a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
@@ -0,0 +1,43 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..0ab666e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+	unsigned long i;
+#endif
+
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+	while (1)
+		;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr , addr + size);
+	icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..e349118
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#include <asm/macro.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+
+#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro	wait_sdram
+	li	$r0, CONFIG_FTSDMC021_BASE
+1:
+	lwi	$r1, [$r0+FTSDMC021_CR2]
+	bnez	$r1, 1b
+.endm
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+
+	led	0x0
+	jal	mem_init
+
+	led	0x10
+	jal	remap
+
+	led	0x20
+	ret	$r10
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * mem_init:
+	 *	There are 2 bank connected to FTSMC020 on AG101
+	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+	 *	we need to set onboard SDRAM before remap and relocation.
+	 */
+	led	0x01
+	write32	SMC_BANK0_CR_A, SMC_BANK0_CR_D			! 0x10000052
+	write32	SMC_BANK0_TPR_A, SMC_BANK0_TPR_D		! 0x00151151
+
+	/*
+	 * config AHB Controller
+	 */
+	led	0x02
+	write32	AHBC_BSR6_A, AHBC_BSR6_D
+
+	/*
+	 * config PMU controller
+	 */
+	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
+	led	0x03
+	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
+
+	/*
+	 * config SDRAM controller
+	 */
+	led	0x04
+	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
+	led	0x05
+	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
+	led	0x06
+	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
+
+	led	0x07
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
+	wait_sdram
+
+	led	0x08
+	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
+	wait_sdram
+
+	led	0x09
+	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
+	wait_sdram
+
+	led	0x0a
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+	/*
+	 * Remapping
+	 */
+	led	0x1a
+	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
+
+	/* clear empty BSR registers */
+	led	0x1b
+	li	$r4, CONFIG_FTSDMC021_BASE
+	li	$r5, 0x0
+	swi	$r5, [$r4 + FTSDMC021_BANK1_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
+	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
+
+#ifdef CONFIG_MEM_REMAP
+	/*
+	 * Copy ROM code to SDRAM base for memory remap layout.
+	 * This is not the real relocation, the real relocation is the function
+	 * relocate_code() is start.S which supports the systems is memory
+	 * remapped or not.
+	 */
+	/*
+	 * Doing memory remap is essential for preparing some non-OS or RTOS
+	 * applications.
+	 *
+	 * This is also a must on ADP-AG101 board.
+	 * The reason is because the ROM/FLASH circuit on PCB board.
+	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	 * ROM/FLASH is used to boot.
+	 *
+	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	 * and the FLASH is connected to BANK1.
+	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	 * and the FLASH is connected to BANK0.
+	 * It will occur problem when doing flash probing if the flash is at
+	 * BANK0 (0x00000000) while memory remapping was skipped.
+	 *
+	 * Other board like ADP-AG101P may not enable this since there is only
+	 * a FLASH connected to bank0.
+	 */
+	led	0x11
+	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
+	li	$r5, 0x0
+	la	$r1, relo_base				/* get $pc or $lp */
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(_end)
+	ori	$r6, $r6, lo12(_end)
+	add	$r6, $r6, $r2
+1:
+	lwi.p	$r7, [$r5], #4
+	swi.p	$r7, [$r4], #4
+	blt	$r5, $r6, 1b
+
+	/* set remap bit */
+	/*
+	 * MEM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
+	 */
+	led	0x1c
+	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..85776dc
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2 / 1024);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl	turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+#endif
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE		0x90100000	/* AHB Controller */
+#define CONFIG_FTSMC020_BASE		0x90200000	/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE		0x90300000	/* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000	/* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000	/* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE		0x90600000	/* LCD Controller */
+#define CONFIG_RESERVED_01_BASE		0x90700000	/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000	/* Reserved */
+#define CONFIG_FTMAC100_BASE		0x90900000	/* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000	/* External USB host */
+#define CONFIG_USB_DEV_BASE		0x90B00000	/* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000	/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE		0x90D00000	/* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000	/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000	/* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000	/* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC	/* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE		0x98100000	/* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE	0x98300000	/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE		0x98400000	/* Counter/Timers */
+#define CONFIG_FTWDT010_BASE		0x98500000	/* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE		0x98600000	/* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE		0x98700000	/* GPIO */
+#define CONFIG_FTINTC010_BASE		0x98800000	/* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE		0x98A00000	/* I2C */
+#define CONFIG_RESERVED_04_BASE		0x98C00000	/* Reserved */
+#define CONFIG_FTCFC010_BASE		0x98D00000	/* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000	/* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE		0x99400000	/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE	0x99600000	/* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE	0x98200000	/* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000	/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE		0x98900000	/* IrDA */
+#define CONFIG_PMW_BASE			0x99100000	/* PWM - Pulse Width Modulator Controller */
+
+#endif	/* __AG101_H */
-- 
1.7.3.5

[U-Boot] [PATCH v15 4/9] nds32/ag101: cpu and init funcs of SoC ag101

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1317896723-9284-4-git-send-email-macpaul@andestech.com> you wrote:
> SoC ag101 is the first chip using NDS32 N1213 cpu core.
> Add header file of device offset support for SoC ag101.
> Add main function of SoC ag101 based on NDS32 n1213 core.
> Add lowlevel_init.S and other periphal related code.
> 
> This version of lowlevel_init.S also replace hardcode value
> by MARCO defines from the GPL version andesboot for better
> code quality.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v4:
>   - Code clean up.
> Changes for v5-v6:
>   - Split watchdog.S from lowlevel_init.S.
>   - Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
>    - reset_cpu was remove inside do_reset().
>   - lowlevel_init.S
>    - Change hard code value into MARCO definitions.
>    - ftsmc010
>      - Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
>    - ftsdmc021
>      - Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
>      - Fix the default configuration value of FTSDMC and FTSMC controller.
>    - Remove some ftpmu010 and flash probe code to C functions.
> Changes for v7:
>   - clean up.
> Changes for v8-v9:
>   - No change.
> Changes for v10:
>   - asm-offset.c: file added for ag101 use only.
>   - ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
>   - Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
>   - cpu.c: remove unused cpu_init().
>   - lowlevel_init.S
>    - Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
>    - Replace routings by macros to made code much easier to understand.
>    - Add debug LED support.
>    - Add CONFIG_MEM_REMAP for those boards must do memort remapping.
> Changes for v11:
>   - arch/nds32/cpu/n1213/ag101/Makefile
>    - replace $(AR) $(call cmd_link_o_target,...)
> Changes for v12:
>   - Simplify the commit log about the part of lowlevel_init.S.
> Changes for v13:
>   - arch/nds32/cpu/n1213/ag101/Makefile: remove unused gen-asm-offset.
>   - Makefile: remove unused gen-asm-offset because merged asm-offsets.
> Changes for v14:
>   - lowlevel_init.S: fix include path of <generated/asm-offsets.h>
> Changes for v15:
>   - fix sleep delay.
> 
>  arch/nds32/cpu/n1213/ag101/Makefile        |   58 +++++++
>  arch/nds32/cpu/n1213/ag101/asm-offsets.c   |   43 +++++
>  arch/nds32/cpu/n1213/ag101/cpu.c           |  200 +++++++++++++++++++++++
>  arch/nds32/cpu/n1213/ag101/lowlevel_init.S |  238 ++++++++++++++++++++++++++++
>  arch/nds32/cpu/n1213/ag101/timer.c         |  204 ++++++++++++++++++++++++
>  arch/nds32/cpu/n1213/ag101/watchdog.S      |   48 ++++++
>  arch/nds32/include/asm/arch-ag101/ag101.h  |   68 ++++++++
>  7 files changed, 859 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
>  create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
>  create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
>  create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
>  create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
>  create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
>  create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

Checkpatch says:

total: 0 errors, 16 warnings, 859 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
You don't have to worry about me. I might have been born yesterday...
but I stayed up all night.

[U-Boot] [PATCH v15 5/9] nds32/lib: add generic funcs in NDS32 lib

[Macpaul Lin]

Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up and formatting style.
Changes for v5-v6:
  - board.c
   - Do some clean up and add code
   - Remove display banner which hasn't support.
   - Add ftpmu010 related power management unit code.
   - Remove useless LED related code.
   - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
   - Remove CONFIG_SOFT_I2C which hasn't been support.
   - Remove CONFIG_FSL_ESDHC which hasn't been support.
   - clean up.
Changes for v7:
  - clean up.
  - move single file patch arch/nds32/config.mk to this commit.
  - interrupts.c refine origin interrupt enable and disable.
Changes for v8:
  - interrups.c: fix up for new ptraces.h.
Changes for v9:
  - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
Changes for v10:
  - config.mk:
   - add -fpie flag.
   - replace -ffixed-8 to -ffixed-10.
   - add -mrelax and --gc-sections to LDFLAG
  - board.c:
   - fix lib/board.c for relocation.
   - fix dram init for relocation.
Changes for v11:
  - arch/nds32/lib/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - config.mk
   - remove $(SRCTREE)/$(CPUDIR)/u-boot.lds
  - board.c:
   - remove obsolelte version_string.
   - remove declaration "extern __bss_end" which is not need.
   - replace sizeof(gd_t) and sizeof(bd_t) to
     GENERATED_GBL_DATA_SIZE and GENERATED_BD_INFO_SIZE
   - add memset to board info (bd)
   - remove compiler optimization barrier which is not need.
Changes for v13:
  - board.c: remove unused CONFIG_IDENT_STRING.
  - arch/nds32/lib/Makefile: remove unused clean and distclean.
Changes for v14:
  - No change.
Changes for v15:
  - lib/board.c:
   - remove duplicate pci init
   - drop NET_MULTI

 arch/nds32/config.mk        |   35 ++++
 arch/nds32/lib/Makefile     |   46 +++++
 arch/nds32/lib/board.c      |  439 +++++++++++++++++++++++++++++++++++++++++++
 arch/nds32/lib/bootm.c      |  241 ++++++++++++++++++++++++
 arch/nds32/lib/interrupts.c |  131 +++++++++++++
 5 files changed, 892 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/config.mk
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/board.c
 create mode 100644 arch/nds32/lib/bootm.c
 create mode 100644 arch/nds32/lib/interrupts.c

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..c589829
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common -mrelax
+PLATFORM_RELFLAGS	+= -gdwarf-2
+PLATFORM_CPPFLAGS	+= -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-10 -fpie
+
+LDFLAGS_u-boot		= --gc-sections --relax
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..e5c31c3
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+OBJS	:= board.o bootm.o interrupts.o
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..1776a72
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,439 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong monitor_flash_len;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	char tmp[64];	/* long enough for environment variables */
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+			? (int) simple_strtoul(tmp, NULL, 10)
+			: CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+void __dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size =  gd->ram_size;
+}
+void dram_init_banksize(void)
+	__attribute__((weak, alias("__dram_init_banksize")));
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	pmu_init,
+#endif
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+	display_dram_config,
+	NULL,
+};
+
+void board_init_f(ulong bootflag)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	gd_t *id;
+	ulong addr, addr_sp;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
+
+	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+
+	gd->mon_len = (unsigned int)(&__bss_end__) - (unsigned int)(&_start);
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	debug("monitor len: %08lX\n", gd->mon_len);
+	/*
+	 * Ram is setup, size stored in gd !!
+	 */
+	debug("ramsize: %08lX\n", gd->ram_size);
+
+	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	/* reserve TLB table */
+	addr -= (4096 * 4);
+
+	/* round down to next 64 kB limit */
+	addr &= ~(0x10000 - 1);
+
+	gd->tlb_addr = addr;
+	debug("TLB table at: %08lx\n", addr);
+#endif
+
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+	gd->fb_base = CONFIG_FB_ADDR;
+#else
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
+	/*
+	 * reserve memory for U-Boot code, data & bss
+	 * round down to next 4 kB limit
+	 */
+	addr -= gd->mon_len;
+	addr &= ~(4096 - 1);
+
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+
+	/*
+	 * reserve memory for malloc() arena
+	 */
+	addr_sp = addr - TOTAL_MALLOC_LEN;
+	debug("Reserving %dk for malloc() at: %08lx\n",
+			TOTAL_MALLOC_LEN >> 10, addr_sp);
+	/*
+	 * (permanently) allocate a Board Info struct
+	 * and a permanent copy of the "global" data
+	 */
+	addr_sp -= GENERATED_BD_INFO_SIZE;
+	bd = (bd_t *) addr_sp;
+	gd->bd = bd;
+	memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+			GENERATED_BD_INFO_SIZE, addr_sp);
+
+	addr_sp -= GENERATED_GBL_DATA_SIZE;
+	id = (gd_t *) addr_sp;
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			GENERATED_GBL_DATA_SIZE, addr_sp);
+
+	/* setup stackpointer for exeptions */
+	gd->irq_sp = addr_sp;
+#ifdef CONFIG_USE_IRQ
+	addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
+#endif
+	/* leave 3 words for abort-stack    */
+	addr_sp -= 12;
+
+	/* 8-byte alignment for ABI compliance */
+	addr_sp &= ~0x07;
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
+
+	gd->bd->bi_baudrate = gd->baudrate;
+	/* Ram isn't board specific, so move it to board code ... */
+	dram_init_banksize();
+	display_dram_config();	/* and display it */
+
+	gd->relocaddr = addr;
+	gd->start_addr_sp = addr_sp;
+
+	gd->reloc_off = addr - _TEXT_BASE;
+
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	memcpy(id, (void *)gd, GENERATED_GBL_DATA_SIZE);
+
+	relocate_code(addr_sp, id, addr);
+
+	/* NOTREACHED - relocate_code() does not return */
+}
+
+/*
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	char *s;
+	bd_t *bd;
+	ulong malloc_start;
+
+	extern void malloc_bin_reloc(void);
+
+	gd = id;
+	bd = gd->bd;
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	monitor_flash_len = &_end - &_start;
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
+
+	board_init();	/* Setup chipselects */
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	/*
+	 * We have to relocate the command table manually
+	 */
+	fixup_cmdtable(&__u_boot_cmd_start,
+		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
+
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+	mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+	malloc_bin_reloc();
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init();
+#endif
+
+	/* IP Address */
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+#if defined(CONFIG_USE_IRQ)
+	/* set up exceptions */
+	interrupt_init();
+	/* enable exceptions */
+	enable_interrupts();
+#endif
+
+	/* Initialize from environment */
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#if defined(CONFIG_CMD_NET)
+	puts("Net:   ");
+
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	show_boot_progress(15);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..c42ad2b
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+extern void reset_cpu(ulong addr);
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"lp : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}
-- 
1.7.3.5

[U-Boot] [PATCH v15 5/9] nds32/lib: add generic funcs in NDS32 lib

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1317896723-9284-5-git-send-email-macpaul@andestech.com> you wrote:
> Add Makefile, board.c, interrupts.c and bootm.c functions
> to nds32 architecture.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v4:
>   - code clean up and formatting style.
> Changes for v5-v6:
>   - board.c
>    - Do some clean up and add code
>    - Remove display banner which hasn't support.
>    - Add ftpmu010 related power management unit code.
>    - Remove useless LED related code.
>    - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
>    - Remove CONFIG_SOFT_I2C which hasn't been support.
>    - Remove CONFIG_FSL_ESDHC which hasn't been support.
>    - clean up.
> Changes for v7:
>   - clean up.
>   - move single file patch arch/nds32/config.mk to this commit.
>   - interrupts.c refine origin interrupt enable and disable.
> Changes for v8:
>   - interrups.c: fix up for new ptraces.h.
> Changes for v9:
>   - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
> Changes for v10:
>   - config.mk:
>    - add -fpie flag.
>    - replace -ffixed-8 to -ffixed-10.
>    - add -mrelax and --gc-sections to LDFLAG
>   - board.c:
>    - fix lib/board.c for relocation.
>    - fix dram init for relocation.
> Changes for v11:
>   - arch/nds32/lib/Makefile
>    - replace $(AR) $(call cmd_link_o_target,...)
> Changes for v12:
>   - config.mk
>    - remove $(SRCTREE)/$(CPUDIR)/u-boot.lds
>   - board.c:
>    - remove obsolelte version_string.
>    - remove declaration "extern __bss_end" which is not need.
>    - replace sizeof(gd_t) and sizeof(bd_t) to
>      GENERATED_GBL_DATA_SIZE and GENERATED_BD_INFO_SIZE
>    - add memset to board info (bd)
>    - remove compiler optimization barrier which is not need.
> Changes for v13:
>   - board.c: remove unused CONFIG_IDENT_STRING.
>   - arch/nds32/lib/Makefile: remove unused clean and distclean.
> Changes for v14:
>   - No change.
> Changes for v15:
>   - lib/board.c:
>    - remove duplicate pci init
>    - drop NET_MULTI
> 
>  arch/nds32/config.mk        |   35 ++++
>  arch/nds32/lib/Makefile     |   46 +++++
>  arch/nds32/lib/board.c      |  439 +++++++++++++++++++++++++++++++++++++++++++
>  arch/nds32/lib/bootm.c      |  241 ++++++++++++++++++++++++
>  arch/nds32/lib/interrupts.c |  131 +++++++++++++
>  5 files changed, 892 insertions(+), 0 deletions(-)
>  create mode 100644 arch/nds32/config.mk
>  create mode 100644 arch/nds32/lib/Makefile
>  create mode 100644 arch/nds32/lib/board.c
>  create mode 100644 arch/nds32/lib/bootm.c
>  create mode 100644 arch/nds32/lib/interrupts.c

Checkpatch says:

total: 0 errors, 8 warnings, 892 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Anyone who knows history, particularly the history of Europe, will, I
think, recognize that the domination of education or of government by
any one particular religious faith is never a happy  arrangement  for
the people.                                       - Eleanor Roosevelt

[U-Boot] [PATCH v15 6/9] nds32: standalone support

[Macpaul Lin]

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - code clean up.
Changes for v7-v11:
  - No change.
Changes for v12:
  - clean up for linker script.
Changes for v13-v15:
  - No change.

 examples/standalone/nds32.lds     |   56 +++++++++++++++++++++++++++++++++++++
 examples/standalone/stubs.c       |   17 ++++++++++-
 examples/standalone/x86-testapp.c |   12 ++++++++
 3 files changed, 84 insertions(+), 1 deletions(-)
 create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..50b4c4b
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	_end = .;
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 507d38c..11c7565 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
 "	jmp %%g1\n"					\
 "	nop\n"						\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	lwi	$r16, [$gp + (%0)]\n"	\
+"	lwi	$r16, [$r16 + (%1)]\n"	\
+"	jr	$r16\n"			\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
 #else
+/*"	addi	$sp, $sp, -24\n"	\
+"	br	$r16\n"			\*/
+
 #error stubs definition missing for this architecture
 #endif
 
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile (						\
 "	lw	$25, %1($25)\n"				\
 "	jr	$25\n"					\
 	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x)					\
+asm volatile (						\
+"	.globl mon_" #x "\n"				\
+"mon_" #x ":\n"						\
+"	lwi	$r16, [$gp + (%0)]\n"			\
+"	lwi	$r16, [$r16 + (%1)]\n"			\
+"	jr	$r16\n"					\
+	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
+
 #else
 #error [No stub code for this arch]
 #endif
@@ -72,6 +82,8 @@ int main(void)
 	register volatile xxx_t *pq asm("r8");
 #elif defined(__mips__)
 	register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+	register volatile xxx_t *pq asm("$r16");
 #endif
 	char buf[32];
 
-- 
1.7.3.5

[U-Boot] [PATCH v15 6/9] nds32: standalone support

[Wolfgang Denk]

Dear Macpaul Lin,

In message <1317896723-9284-6-git-send-email-macpaul@andestech.com> you wrote:
> Add standalone program related support for nds32 architecture.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v1-v6:
>   - code clean up.
> Changes for v7-v11:
>   - No change.
> Changes for v12:
>   - clean up for linker script.
> Changes for v13-v15:
>   - No change.
> 
>  examples/standalone/nds32.lds     |   56 +++++++++++++++++++++++++++++++++++++
>  examples/standalone/stubs.c       |   17 ++++++++++-
>  examples/standalone/x86-testapp.c |   12 ++++++++
>  3 files changed, 84 insertions(+), 1 deletions(-)
>  create mode 100644 examples/standalone/nds32.lds

Checkpatch says:

total: 0 errors, 2 warnings, 104 lines checked

Please fix and resubmit.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
ATTENTION: Despite Any Other Listing of Product Contents Found  Here-
on, the Consumer is Advised That, in Actuality, This Product Consists
Of 99.9999999999% Empty Space.

[U-Boot] [PATCH v15 7/9] nds32: common bdinfo, bootm, image support

[Macpaul Lin]

Add support of NDS32 to common commands bdinfo, bootm, and image format.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - Code clean up
Changes for v7-v9:
  - No Change.
Changes for v10:
  - fix up according to the changes in master tree.
Changes for v11:
  - No Change.
Changes for v12:
  - remove seldom used bi_env parameter.
Changes for v13-v14:
  - No change.
Changes for v15:
  - cmd_bootm.c and image.h
    - Fix for new image.h according to Mike's Contribute.

 common/cmd_bdinfo.c |   25 +++++++++++++++++++++++++
 common/image.c      |    1 +
 include/image.h     |    1 +
 3 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 6051120..b3e506f 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -413,6 +413,31 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num("arch_number",	bd->bi_arch_number);
+	print_num("boot_params",	(ulong)bd->bi_boot_params);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
diff --git a/common/image.c b/common/image.c
index d38ce4a..d620b85 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	-1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index cca1cc5..e4c7ab9 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_NDS32	        19	/* ANDES Technology - NDS32  */
 
 /*
  * Image Types
-- 
1.7.3.5

[U-Boot] [PATCH v15 8/9] adp-ag101: add board adp-ag101 support

[Macpaul Lin]

Add evaluation board "adp-ag101" configuration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up
Changes for v5-v6:
  - Refine the definitions and parameters about CLK,
    AHB controller, SDRAM controller, Static memory controllers.
  - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
  - ftahbc010:
    - Update include path of ftahbc010.
  - ftsdmc021:
    - Update include path of ftsdmc021.
  - ftsmc020:
    - Update include path of ftsmc020.
  - ftwdt010:
    - Fix WDT define and update include path.
    - Fix ftwdt010 for hardware reset.
  - ftpmu010:
    - Remove duplicate PMU definitions.
    - Add related configurations.
  - Fix MAX malloc len and fix saveenv.
  - clean up.
Changes for v7:
  - clean up.
  - Move CONFIG_SYS_TEXT_BASE from board/config.mk.
  - Fix Makefile and remove config.mk
Changes for v8:
  - No change.
Changes for v9:
  - Fix because other boards has been added into boards.cfg and
    broken this patch.
Changes for v10:
  - adp-ag101.h
   - Fix lines over 80 characters.
   - Fix for introducing gen-asm-offset.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix flash init.
   - fix ftsmc010 configuraion for flash probing.
   - Add SP_INIT related configurations for supporting relocation.
   - Fix CONFIG_TEXT_BASE for relocation.
   - Add CONFIG_MEM_REMAP for some hardware boards and non-OS application.
  - adp-ag101.c
   - Clean up for braces according to Wolfgang's suggestion.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix dram init(), made this more simpler.
Changes for v11:
  - No change.
Changes for v12:
  - adp-ag101.h
   - fix address when enable CONFIG_SKIP_LOWLEVEL_INIT
Changes for v13:
  - board/AndesTech/adp-ag101/Makefile: remove unused clean and distclean.
Changes for v14:
  - No change.
Changes for v15:
  - adp-ag101.h: drop NET_MULTI
  - Makefile: clean up Makefile

 MAINTAINERS                           |   11 +
 MAKEALL                               |    6 +
 board/AndesTech/adp-ag101/Makefile    |   44 ++++
 board/AndesTech/adp-ag101/adp-ag101.c |   89 +++++++
 boards.cfg                            |    1 +
 include/configs/adp-ag101.h           |  406 +++++++++++++++++++++++++++++++++
 6 files changed, 557 insertions(+), 0 deletions(-)
 create mode 100644 board/AndesTech/adp-ag101/Makefile
 create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
 create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 3ab38fa..7009e38 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1120,5 +1120,16 @@ Chong Huang <chuang@ucrobotics.com>
 	bf525-ucr2	BF525
 
 #########################################################################
+# NDS32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+	ADP-AG101	N1213 (AG101 SoC)
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 52bc355..755e9b7 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -481,6 +481,12 @@ LIST_sh="$(boards_by_arch sh)"
 
 LIST_sparc="$(boards_by_arch sparc)"
 
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
 #-----------------------------------------------------------------------
 
 build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..d55a799
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= adp-ag101.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..82ce4c9
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	ftsdc010_mmc_init(0);
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 65482ac..f3685c5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -303,6 +303,7 @@ vct_platinumavc_small        mips        mips32      vct                 microna
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
 nios2-generic                nios2       nios2       nios2-generic       altera
+adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..8421c79
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,406 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x03200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_CMD_FAT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#else
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#endif
+
+/*
+ * There are 2 bank connected to FTSMC020 on ADP-AG101.
+ * You can use jumper and switch to force it booted from ROM or FLASH.
+ * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
+ * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
+ * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
+ *    Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
+ * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
+				 FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M	|	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_RBE	|	\
+				 FTSMC020_TPR_AST(1)	|	\
+				 FTSMC020_TPR_CTW(1)	|	\
+				 FTSMC020_TPR_ATI(1)	|	\
+				 FTSMC020_TPR_AT2(1)	|	\
+				 FTSMC020_TPR_WTC(1)	|	\
+				 FTSMC020_TPR_AHT(1)	|	\
+				 FTSMC020_TPR_TRNA(1))
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif	/* CONFIG_MEM_REMAP */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif	/* __CONFIG_H */
-- 
1.7.3.5

[U-Boot] [PATCH v15 9/9] doc/README: documents and readme for NDS32 arch

[Macpaul Lin]

Documents and READMEs for NDS32 architecture.
It patch also provides usage of SoC AG101 and board ADP-AG101.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v10:
  - The patch of documentation was not included.
Changes for v11:
  - Add the documents of NDS32, ag101, N1213.
Changes for v12-v15:
  - No change.

 README                |   24 ++++++++++++++--
 doc/README.N1213      |   55 ++++++++++++++++++++++++++++++++++++
 doc/README.NDS32      |   41 +++++++++++++++++++++++++++
 doc/README.ag101      |   74 +++++++++++++++++++++++++++++++++++++++++++++++++
 doc/README.standalone |    1 +
 5 files changed, 192 insertions(+), 3 deletions(-)
 create mode 100644 doc/README.N1213
 create mode 100644 doc/README.NDS32
 create mode 100644 doc/README.ag101

diff --git a/README b/README
index 0868531..2fd7acc 100644
--- a/README
+++ b/README
@@ -182,6 +182,10 @@ Directory Hierarchy:
     /cpu		CPU specific files
       /mips32		Files specific to MIPS32 CPUs
     /lib		Architecture specific library files
+  /nds32		Files generic to NDS32 architecture
+    /cpu		CPU specific files
+      /n1213		Files specific to Andes Technology N1213 CPUs
+    /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
@@ -3154,7 +3158,7 @@ Low Level (hardware related) configuration options:
 		globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-		[ARM, MIPS only] If this variable is defined, then certain
+		[ARM, NDS32, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
@@ -3702,8 +3706,8 @@ details; basically, the header defines the following image properties:
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
-  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
+  IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -4396,6 +4400,20 @@ On Nios II, the ABI is documented here:
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 
+On NDS32, the following registers are used:
+
+	R0-R1:	argument/return
+	R2-R5:	argument
+	R15:	temporary register for assembler
+	R16:	trampoline register
+	R28:	frame pointer (FP)
+	R29:	global pointer (GP)
+	R30:	link register (LP)
+	R31:	stack pointer (SP)
+	PC:	program counter (PC)
+
+    ==> U-Boot will use R10 to hold a pointer to the global data
+
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 
diff --git a/doc/README.N1213 b/doc/README.N1213
new file mode 100644
index 0000000..e107166
--- /dev/null
+++ b/doc/README.N1213
@@ -0,0 +1,55 @@
+N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
+
+Features
+========
+
+CPU Core
+ - 16-/32-bit mixable instruction format.
+ - 32 general-purpose 32-bit registers.
+ - 8-stage pipeline.
+ - Dynamic branch prediction.
+ - 32/64/128/256 BTB.
+ - Return address stack (RAS).
+ - Vector interrupts for internal/external.
+   interrupt controller with 6 hardware interrupt signals.
+ - 3 HW-level nested interruptions.
+ - User and super-user mode support.
+ - Memory-mapped I/O.
+ - Address space up to 4GB.
+
+Memory Management Unit
+ - TLB
+   - 4/8-entry fully associative iTLB/dTLB.
+   - 32/64/128-entry 4-way set-associati.ve main TLB.
+   - TLB locking support
+ - Optional hardware page table walker.
+ - Two groups of page size support.
+  - 4KB & 1MB.
+  - 8KB & 1MB.
+
+Memory Subsystem
+ - I & D cache.
+   - Virtually indexed and physically tagged.
+   - Cache size: 8KB/16KB/32KB/64KB.
+   - Cache line size: 16B/32B.
+   - Set associativity: 2-way, 4-way or direct-mapped.
+   - Cache locking support.
+ - I & D local memory (LM).
+   - Size: 4KB to 1MB.
+   - Bank numbers: 1 or 2.
+   - Optional 1D/2D DMA engine.
+   - Internal or external to CPU core.
+
+Bus Interface
+ - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
+ - Synchronous High speed memory port.
+   (HSMP): 0, 1 or 2 ports.
+
+Debug
+ - JTAG debug interface.
+ - Embedded debug module (EDM).
+ - Optional embedded program tracer interface.
+
+Miscellaneous
+ - Programmable data endian control.
+ - Performance monitoring mechanism.
diff --git a/doc/README.NDS32 b/doc/README.NDS32
new file mode 100644
index 0000000..b2b58fc
--- /dev/null
+++ b/doc/README.NDS32
@@ -0,0 +1,41 @@
+NDS32 is a new high-performance 32-bit RISC microprocessor core.
+
+http://www.andestech.com/
+
+AndeStar ISA
+============
+AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
+achieve optimal system performance, code density, and power efficiency.
+
+It contains the following features:
+ - Intermixable 32-bit and 16-bit instruction sets without the need for
+   mode switch.
+ - 16-bit instructions as a frequently used subset of 32-bit instructions.
+ - RISC-style register-based instruction set.
+ - 32 32-bit General Purpose Registers (GPR).
+ - Upto 1024 User Special Registers (USR) for existing and extension
+   instructions.
+ - Rich load/store instructions for...
+   - Single memory access with base address update.
+   - Multiple aligned and unaligned memory accesses for memory copy and stack
+     operations.
+   - Data prefetch to improve data cache performance.
+   - Non-bus locking synchronization instructions.
+ - PC relative jump and PC read instructions for efficient position independent
+   code.
+ - Multiply-add and multiple-sub with 64-bit accumulator.
+ - Instruction for efficient power management.
+ - Bi-endian support.
+ - Three instruction extension space for application acceleration:
+   - Performance extension.
+   - Andes future extensions (for floating-point, multimedia, etc.)
+   - Customer extensions.
+
+AndesCore CPU
+=============
+Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
+
+For details about N12 CPU family, please check doc/README.N1213.
+
+The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
+other associated software are actively supported by Andes Technology Corporation.
diff --git a/doc/README.ag101 b/doc/README.ag101
new file mode 100644
index 0000000..46fc637
--- /dev/null
+++ b/doc/README.ag101
@@ -0,0 +1,74 @@
+Andes Technology SoC AG101
+==========================
+
+AG101 is the first SoC produced by Andes Technology using N1213 CPU core.
+AG101 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG101
+=========
+
+ADP-AG101 is the SoC with AG101 hardcore CPU.
+
+Please check http://www.andestech.com/p2-4.htm for detail of this SoC.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+	This is also a must on ADP-AG101 board.
+	(While other boards may not have this problem).
+
+	The reason is because the ROM/FLASH circuit on PCB board.
+	AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	ROM/FLASH is used to boot.
+
+	When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	and the FLASH is connected to BANK1.
+	When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	and the FLASH is connected to BANK0.
+	It will occur problem when doing flash probing if the flash is at
+	BANK0 (0x00000000) while memory remapping was skipped.
+
+	Other board like ADP-AG101P may not enable this since there is only
+	a FLASH connected to bank0.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from FLASH and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag101.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101` in u-boot root to build the image.
+
+burn u-boot to flash:
+1. Make sure the MA17 (J16) is Lo.
+2. Make sure the dip switch SW5 is set to "0101".
+3. Power On. Press button "S1", then press button "SW1", then you will found the
+   debug LED show 67 means the system successfully booted into e-bios.
+   Now you can control the e-bios boot loader from your console.
+4. Under "Command>>" prompt, enter "97" (CopyImageFromCard)
+5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c".
+6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you
+   just build. It is usually "u-boot.bin".
+7. Under "Enter Dest. Address =>" prompt, enter the memory address where you
+   want to put the binary from SD card to RAM.
+   Address "0x500000" is our suggestion.
+8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command
+   environment.
+9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the
+   binary from RAM to FLASH.
+10. Under "CLI>" prompt, enter "exit" to finish the burn process.
+
+boot u-boot from flash:
+1. Make sure the MA17 (J16) is Hi).
+2. Make sure the dip switch SW5 is set to "1010".
+3. Power On. Press button "S1", then you will see the debug LED count to 20.
+4. Now you can use u-boot on ADP-AG101 board.
diff --git a/doc/README.standalone b/doc/README.standalone
index 6e6b65f..2be5f27 100644
--- a/doc/README.standalone
+++ b/doc/README.standalone
@@ -56,6 +56,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
 	ARM		0x0c100000	0x0c100000
 	MIPS		0x80200000	0x80200000
 	Blackfin	0x00001000	0x00001000
+	NDS32		0x00300000	0x00300000
 	Nios II		0x02000000	0x02000000
 
    For example, the "hello world" application may be loaded and
-- 
1.7.3.5

[U-Boot] [PATCH v12 5/9] nds32/lib: add generic funcs in NDS32 lib

[Macpaul Lin]

Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up and formatting style.
Changes for v5-v6:
  - board.c
   - Do some clean up and add code
   - Remove display banner which hasn't support.
   - Add ftpmu010 related power management unit code.
   - Remove useless LED related code.
   - Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
   - Remove CONFIG_SOFT_I2C which hasn't been support.
   - Remove CONFIG_FSL_ESDHC which hasn't been support.
   - clean up.
Changes for v7:
  - clean up.
  - move single file patch arch/nds32/config.mk to this commit.
  - interrupts.c refine origin interrupt enable and disable.
Changes for v8:
  - interrups.c: fix up for new ptraces.h.
Changes for v9:
  - support CONFIG_STANDALONE_LOAD_ADDR in config.mk
Changes for v10:
  - config.mk:
   - add -fpie flag.
   - replace -ffixed-8 to -ffixed-10.
   - add -mrelax and --gc-sections to LDFLAG
  - board.c:
   - fix lib/board.c for relocation.
   - fix dram init for relocation.
Changes for v11:
  - arch/nds32/lib/Makefile
   - replace $(AR) $(call cmd_link_o_target,...)
Changes for v12:
  - config.mk
   - remove $(SRCTREE)/$(CPUDIR)/u-boot.lds
  - board.c:
   - remove obsolelte version_string.
   - remove declaration "extern __bss_end" which is not need.
   - replace sizeof(gd_t) and sizeof(bd_t) to
     GENERATED_GBL_DATA_SIZE and GENERATED_BD_INFO_SIZE
   - add memset to board info (bd)
   - remove compiler optimization barrier which is not need.

 arch/nds32/config.mk        |   35 ++++
 arch/nds32/lib/Makefile     |   52 +++++
 arch/nds32/lib/board.c      |  447 +++++++++++++++++++++++++++++++++++++++++++
 arch/nds32/lib/bootm.c      |  241 +++++++++++++++++++++++
 arch/nds32/lib/interrupts.c |  131 +++++++++++++
 5 files changed, 906 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/config.mk
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/board.c
 create mode 100644 arch/nds32/lib/bootm.c
 create mode 100644 arch/nds32/lib/interrupts.c

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..c589829
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common -mrelax
+PLATFORM_RELFLAGS	+= -gdwarf-2
+PLATFORM_CPPFLAGS	+= -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-10 -fpie
+
+LDFLAGS_u-boot		= --gc-sections --relax
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..0475c7f
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+OBJS	:= board.o bootm.o interrupts.o
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..14b3d76
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,447 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong monitor_flash_len;
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	char tmp[64];	/* long enough for environment variables */
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+			? (int) simple_strtoul(tmp, NULL, 10)
+			: CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+void __dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size =  gd->ram_size;
+}
+void dram_init_banksize(void)
+	__attribute__((weak, alias("__dram_init_banksize")));
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	pmu_init,
+#endif
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init,
+#endif
+	display_dram_config,
+	NULL,
+};
+
+void board_init_f(ulong bootflag)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	gd_t *id;
+	ulong addr, addr_sp;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
+
+	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+
+	gd->mon_len = (unsigned int)(&__bss_end__) - (unsigned int)(&_start);
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	debug("monitor len: %08lX\n", gd->mon_len);
+	/*
+	 * Ram is setup, size stored in gd !!
+	 */
+	debug("ramsize: %08lX\n", gd->ram_size);
+
+	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	/* reserve TLB table */
+	addr -= (4096 * 4);
+
+	/* round down to next 64 kB limit */
+	addr &= ~(0x10000 - 1);
+
+	gd->tlb_addr = addr;
+	debug("TLB table at: %08lx\n", addr);
+#endif
+
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+	gd->fb_base = CONFIG_FB_ADDR;
+#else
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
+	/*
+	 * reserve memory for U-Boot code, data & bss
+	 * round down to next 4 kB limit
+	 */
+	addr -= gd->mon_len;
+	addr &= ~(4096 - 1);
+
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+
+	/*
+	 * reserve memory for malloc() arena
+	 */
+	addr_sp = addr - TOTAL_MALLOC_LEN;
+	debug("Reserving %dk for malloc() at: %08lx\n",
+			TOTAL_MALLOC_LEN >> 10, addr_sp);
+	/*
+	 * (permanently) allocate a Board Info struct
+	 * and a permanent copy of the "global" data
+	 */
+	addr_sp -= GENERATED_BD_INFO_SIZE;
+	bd = (bd_t *) addr_sp;
+	gd->bd = bd;
+	memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+			GENERATED_BD_INFO_SIZE, addr_sp);
+
+	addr_sp -= GENERATED_GBL_DATA_SIZE;
+	id = (gd_t *) addr_sp;
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			GENERATED_GBL_DATA_SIZE, addr_sp);
+
+	/* setup stackpointer for exeptions */
+	gd->irq_sp = addr_sp;
+#ifdef CONFIG_USE_IRQ
+	addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
+#endif
+	/* leave 3 words for abort-stack    */
+	addr_sp -= 12;
+
+	/* 8-byte alignment for ABI compliance */
+	addr_sp &= ~0x07;
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
+
+	gd->bd->bi_baudrate = gd->baudrate;
+	/* Ram isn't board specific, so move it to board code ... */
+	dram_init_banksize();
+	display_dram_config();	/* and display it */
+
+	gd->relocaddr = addr;
+	gd->start_addr_sp = addr_sp;
+
+	gd->reloc_off = addr - _TEXT_BASE;
+
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	memcpy(id, (void *)gd, GENERATED_GBL_DATA_SIZE);
+
+	relocate_code(addr_sp, id, addr);
+
+	/* NOTREACHED - relocate_code() does not return */
+}
+
+/*
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	char *s;
+	bd_t *bd;
+	ulong malloc_start;
+
+	extern void malloc_bin_reloc(void);
+
+	gd = id;
+	bd = gd->bd;
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	monitor_flash_len = &_end - &_start;
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
+
+	board_init();	/* Setup chipselects */
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	/*
+	 * We have to relocate the command table manually
+	 */
+	fixup_cmdtable(&__u_boot_cmd_start,
+		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
+
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+	mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+	malloc_bin_reloc();
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	nds32_pci_init();
+#endif
+
+	/* IP Address */
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+#if defined(CONFIG_USE_IRQ)
+	/* set up exceptions */
+	interrupt_init();
+	/* enable exceptions */
+	enable_interrupts();
+#endif
+
+	/* Initialize from environment */
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+	puts("Net:   ");
+#endif
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	show_boot_progress(15);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..c42ad2b
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+extern void reset_cpu(ulong addr);
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"lp : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}
-- 
1.7.3.5

[U-Boot] [PATCH v12 5/9] nds32/lib: add generic funcs in NDS32 lib

[Mike Frysinger]

On Tuesday, September 06, 2011 22:27:16 Macpaul Lin wrote:
> --- /dev/null
> +++ b/arch/nds32/lib/Makefile
> 
> +clean:
> +	rm -f $(SOBJS) $(OBJS)
> +
> +distclean:	clean
> +	rm -f $(LIB) core *.bak .depend

pretty sure neither of these get used, so you should punt both targets

> --- /dev/null
> +++ b/arch/nds32/lib/board.c
> 
> +#ifndef CONFIG_IDENT_STRING
> +#define CONFIG_IDENT_STRING ""
> +#endif

you forgot to delete this too when removing the version_string :)
-mike
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[U-Boot] [PATCH v12 6/9] nds32: standalone support

[Macpaul Lin]

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - code clean up.
Changes for v7-v11:
  - No change.
Changes for v12:
  - clean up link script.

 examples/standalone/nds32.lds     |   56 +++++++++++++++++++++++++++++++++++++
 examples/standalone/stubs.c       |   17 ++++++++++-
 examples/standalone/x86-testapp.c |   12 ++++++++
 3 files changed, 84 insertions(+), 1 deletions(-)
 create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..50b4c4b
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	_end = .;
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 507d38c..11c7565 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
 "	jmp %%g1\n"					\
 "	nop\n"						\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	lwi	$r16, [$gp + (%0)]\n"	\
+"	lwi	$r16, [$r16 + (%1)]\n"	\
+"	jr	$r16\n"			\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
 #else
+/*"	addi	$sp, $sp, -24\n"	\
+"	br	$r16\n"			\*/
+
 #error stubs definition missing for this architecture
 #endif
 
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile (						\
 "	lw	$25, %1($25)\n"				\
 "	jr	$25\n"					\
 	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x)					\
+asm volatile (						\
+"	.globl mon_" #x "\n"				\
+"mon_" #x ":\n"						\
+"	lwi	$r16, [$gp + (%0)]\n"			\
+"	lwi	$r16, [$r16 + (%1)]\n"			\
+"	jr	$r16\n"					\
+	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
+
 #else
 #error [No stub code for this arch]
 #endif
@@ -72,6 +82,8 @@ int main(void)
 	register volatile xxx_t *pq asm("r8");
 #elif defined(__mips__)
 	register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+	register volatile xxx_t *pq asm("$r16");
 #endif
 	char buf[32];
 
-- 
1.7.3.5

[U-Boot] [PATCH v12 7/9] nds32: common bdinfo, bootm, image support

[Macpaul Lin]

Add support of NDS32 to common commands bdinfo, bootm, and image format.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - Code clean up
Changes for v7-v9:
  - No Change.
Changes for v10:
  - fix up according to the changes in master tree.
Changes for v11:
  - No Change.
Changes for v12:
  - remove seldom used bi_env parameter.

 common/cmd_bdinfo.c |   25 +++++++++++++++++++++++++
 common/cmd_bootm.c  |    2 ++
 common/image.c      |    1 +
 include/image.h     |    5 +++++
 4 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 6051120..b3e506f 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -413,6 +413,31 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num("arch_number",	bd->bi_arch_number);
+	print_num("boot_params",	(ulong)bd->bi_boot_params);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 8909ee7..844be80 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -187,6 +187,8 @@ void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
   #define IH_INITRD_ARCH IH_ARCH_SH
 #elif defined(__sparc__)
   #define IH_INITRD_ARCH IH_ARCH_SPARC
+#elif defined(__nds32__)
+  #define IH_INITRD_ARCH IH_ARCH_NDS32
 #else
 # error Unknown CPU type
 #endif
diff --git a/common/image.c b/common/image.c
index 5eea2a1..95e16b8 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	-1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index 352e4a0..dcbbc8b 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_NDS32	        19	/* ANDES Technology - NDS32  */
 
 /*
  * Image Types
@@ -506,6 +507,8 @@ static inline int image_check_target_arch (const image_header_t *hdr)
 	if (!image_check_arch (hdr, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!image_check_arch (hdr, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!image_check_arch(hdr, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
@@ -658,6 +661,8 @@ static inline int fit_image_check_target_arch (const void *fdt, int node)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!fit_image_check_arch(fdt, node, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
-- 
1.7.3.5

[U-Boot] [PATCH v12 8/9] adp-ag101: add board adp-ag101 support

[Macpaul Lin]

Add evaluation board "adp-ag101" configuration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up
Changes for v5-v6:
  - Refine the definitions and parameters about CLK,
    AHB controller, SDRAM controller, Static memory controllers.
  - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
  - ftahbc010:
    - Update include path of ftahbc010.
  - ftsdmc021:
    - Update include path of ftsdmc021.
  - ftsmc020:
    - Update include path of ftsmc020.
  - ftwdt010:
    - Fix WDT define and update include path.
    - Fix ftwdt010 for hardware reset.
  - ftpmu010:
    - Remove duplicate PMU definitions.
    - Add related configurations.
  - Fix MAX malloc len and fix saveenv.
  - clean up.
Changes for v7:
  - clean up.
  - Move CONFIG_SYS_TEXT_BASE from board/config.mk.
  - Fix Makefile and remove config.mk
Changes for v8:
  - No change.
Changes for v9:
  - Fix because other boards has been added into boards.cfg and
    broken this patch.
Changes for v10:
  - adp-ag101.h
   - Fix lines over 80 characters.
   - Fix for introducing gen-asm-offset.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix flash init.
   - fix ftsmc010 configuraion for flash probing.
   - Add SP_INIT related configurations for supporting relocation.
   - Fix CONFIG_TEXT_BASE for relocation.
   - Add CONFIG_MEM_REMAP for some hardware boards and non-OS application.
  - adp-ag101.c
   - Clean up for braces according to Wolfgang's suggestion.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix dram init(), made this more simpler.
Changes for v11:
  - No Change.
Changes for v12:
  - adp-ag101.h
   - fix address when enable CONFIG_SKIP_LOWLEVEL_INIT

 MAINTAINERS                           |   11 +
 MAKEALL                               |    6 +
 board/AndesTech/adp-ag101/Makefile    |   57 +++++
 board/AndesTech/adp-ag101/adp-ag101.c |   89 +++++++
 boards.cfg                            |    1 +
 include/configs/adp-ag101.h           |  407 +++++++++++++++++++++++++++++++++
 6 files changed, 571 insertions(+), 0 deletions(-)
 create mode 100644 board/AndesTech/adp-ag101/Makefile
 create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
 create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 3bfe3fb..fc84f1f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1148,5 +1148,16 @@ Chong Huang <chuang@ucrobotics.com>
 	bf525-ucr2	BF525
 
 #########################################################################
+# NDS32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+	ADP-AG101	N1213 (AG101 SoC)
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index e72a019..6a3580b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -537,6 +537,12 @@ LIST_sh="$(boards_by_arch sh)"
 
 LIST_sparc="$(boards_by_arch sparc)"
 
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
 #-----------------------------------------------------------------------
 
 build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..5a403b1
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,57 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= adp-ag101.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+ifdef CONFIG_SYS_LDSCRIPT
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else
+LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..82ce4c9
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	ftsdc010_mmc_init(0);
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 60723d5..f70fd00 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -309,6 +309,7 @@ vct_platinumavc_small        mips        mips32      vct                 microna
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
 nios2-generic                nios2       nios2       nios2-generic       altera
+adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..3544412
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,407 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x03200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_CMD_FAT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#else
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#endif
+
+/*
+ * There are 2 bank connected to FTSMC020 on ADP-AG101.
+ * You can use jumper and switch to force it booted from ROM or FLASH.
+ * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
+ * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
+ * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
+ *    Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
+ * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
+				 FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M	|	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_RBE	|	\
+				 FTSMC020_TPR_AST(1)	|	\
+				 FTSMC020_TPR_CTW(1)	|	\
+				 FTSMC020_TPR_ATI(1)	|	\
+				 FTSMC020_TPR_AT2(1)	|	\
+				 FTSMC020_TPR_WTC(1)	|	\
+				 FTSMC020_TPR_AHT(1)	|	\
+				 FTSMC020_TPR_TRNA(1))
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif	/* CONFIG_MEM_REMAP */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif	/* __CONFIG_H */
-- 
1.7.3.5

[U-Boot] [PATCH v12 8/9] adp-ag101: add board adp-ag101 support

[Mike Frysinger]

On Tuesday, September 06, 2011 22:27:19 Macpaul Lin wrote:
> --- /dev/null
> +++ b/board/AndesTech/adp-ag101/Makefile
> 
> +clean:
> +	rm -f $(SOBJS) $(OBJS)
> +
> +distclean:	clean
> +	rm -f $(LIB) core *.bak $(obj).depend

i think both of these are unused, so punt them

> +ifdef CONFIG_SYS_LDSCRIPT
> +LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
> +else
> +LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds
> +endif

i dont think defining LDSCRIPT in the board Makefile does anything (would only 
really matter if it was in config.mk).  so punt this.
-mike
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[U-Boot] [PATCH v12 9/9] doc/README: documents and readme for NDS32 arch

[Macpaul Lin]

Documents and READMEs for NDS32 architecture.
It patch also provides usage of SoC AG101 and board ADP-AG101.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v10:
  - The patch of documentation was not included.
Changes for v11:
  - Add the documents of NDS32, ag101, N1213.
Changes for v12:
  - No change.

 README                |   24 ++++++++++++++--
 doc/README.N1213      |   55 ++++++++++++++++++++++++++++++++++++
 doc/README.NDS32      |   41 +++++++++++++++++++++++++++
 doc/README.ag101      |   74 +++++++++++++++++++++++++++++++++++++++++++++++++
 doc/README.standalone |    1 +
 5 files changed, 192 insertions(+), 3 deletions(-)
 create mode 100644 doc/README.N1213
 create mode 100644 doc/README.NDS32
 create mode 100644 doc/README.ag101

diff --git a/README b/README
index 0886987..381e1e2 100644
--- a/README
+++ b/README
@@ -182,6 +182,10 @@ Directory Hierarchy:
     /cpu		CPU specific files
       /mips32		Files specific to MIPS32 CPUs
     /lib		Architecture specific library files
+  /nds32		Files generic to NDS32 architecture
+    /cpu		CPU specific files
+      /n1213		Files specific to Andes Technology N1213 CPUs
+    /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
@@ -3103,7 +3107,7 @@ Low Level (hardware related) configuration options:
 		globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-		[ARM, MIPS only] If this variable is defined, then certain
+		[ARM, NDS32, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
@@ -3653,8 +3657,8 @@ details; basically, the header defines the following image properties:
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
-  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
+  IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -4347,6 +4351,20 @@ On Nios II, the ABI is documented here:
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 
+On NDS32, the following registers are used:
+
+	R0-R1:	argument/return
+	R2-R5:	argument
+	R15:	temporary register for assembler
+	R16:	trampoline register
+	R28:	frame pointer (FP)
+	R29:	global pointer (GP)
+	R30:	link register (LP)
+	R31:	stack pointer (SP)
+	PC:	program counter (PC)
+
+    ==> U-Boot will use R10 to hold a pointer to the global data
+
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 
diff --git a/doc/README.N1213 b/doc/README.N1213
new file mode 100644
index 0000000..e107166
--- /dev/null
+++ b/doc/README.N1213
@@ -0,0 +1,55 @@
+N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
+
+Features
+========
+
+CPU Core
+ - 16-/32-bit mixable instruction format.
+ - 32 general-purpose 32-bit registers.
+ - 8-stage pipeline.
+ - Dynamic branch prediction.
+ - 32/64/128/256 BTB.
+ - Return address stack (RAS).
+ - Vector interrupts for internal/external.
+   interrupt controller with 6 hardware interrupt signals.
+ - 3 HW-level nested interruptions.
+ - User and super-user mode support.
+ - Memory-mapped I/O.
+ - Address space up to 4GB.
+
+Memory Management Unit
+ - TLB
+   - 4/8-entry fully associative iTLB/dTLB.
+   - 32/64/128-entry 4-way set-associati.ve main TLB.
+   - TLB locking support
+ - Optional hardware page table walker.
+ - Two groups of page size support.
+  - 4KB & 1MB.
+  - 8KB & 1MB.
+
+Memory Subsystem
+ - I & D cache.
+   - Virtually indexed and physically tagged.
+   - Cache size: 8KB/16KB/32KB/64KB.
+   - Cache line size: 16B/32B.
+   - Set associativity: 2-way, 4-way or direct-mapped.
+   - Cache locking support.
+ - I & D local memory (LM).
+   - Size: 4KB to 1MB.
+   - Bank numbers: 1 or 2.
+   - Optional 1D/2D DMA engine.
+   - Internal or external to CPU core.
+
+Bus Interface
+ - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
+ - Synchronous High speed memory port.
+   (HSMP): 0, 1 or 2 ports.
+
+Debug
+ - JTAG debug interface.
+ - Embedded debug module (EDM).
+ - Optional embedded program tracer interface.
+
+Miscellaneous
+ - Programmable data endian control.
+ - Performance monitoring mechanism.
diff --git a/doc/README.NDS32 b/doc/README.NDS32
new file mode 100644
index 0000000..b2b58fc
--- /dev/null
+++ b/doc/README.NDS32
@@ -0,0 +1,41 @@
+NDS32 is a new high-performance 32-bit RISC microprocessor core.
+
+http://www.andestech.com/
+
+AndeStar ISA
+============
+AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
+achieve optimal system performance, code density, and power efficiency.
+
+It contains the following features:
+ - Intermixable 32-bit and 16-bit instruction sets without the need for
+   mode switch.
+ - 16-bit instructions as a frequently used subset of 32-bit instructions.
+ - RISC-style register-based instruction set.
+ - 32 32-bit General Purpose Registers (GPR).
+ - Upto 1024 User Special Registers (USR) for existing and extension
+   instructions.
+ - Rich load/store instructions for...
+   - Single memory access with base address update.
+   - Multiple aligned and unaligned memory accesses for memory copy and stack
+     operations.
+   - Data prefetch to improve data cache performance.
+   - Non-bus locking synchronization instructions.
+ - PC relative jump and PC read instructions for efficient position independent
+   code.
+ - Multiply-add and multiple-sub with 64-bit accumulator.
+ - Instruction for efficient power management.
+ - Bi-endian support.
+ - Three instruction extension space for application acceleration:
+   - Performance extension.
+   - Andes future extensions (for floating-point, multimedia, etc.)
+   - Customer extensions.
+
+AndesCore CPU
+=============
+Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
+
+For details about N12 CPU family, please check doc/README.N1213.
+
+The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
+other associated software are actively supported by Andes Technology Corporation.
diff --git a/doc/README.ag101 b/doc/README.ag101
new file mode 100644
index 0000000..46fc637
--- /dev/null
+++ b/doc/README.ag101
@@ -0,0 +1,74 @@
+Andes Technology SoC AG101
+==========================
+
+AG101 is the first SoC produced by Andes Technology using N1213 CPU core.
+AG101 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG101
+=========
+
+ADP-AG101 is the SoC with AG101 hardcore CPU.
+
+Please check http://www.andestech.com/p2-4.htm for detail of this SoC.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+	This is also a must on ADP-AG101 board.
+	(While other boards may not have this problem).
+
+	The reason is because the ROM/FLASH circuit on PCB board.
+	AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	ROM/FLASH is used to boot.
+
+	When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	and the FLASH is connected to BANK1.
+	When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	and the FLASH is connected to BANK0.
+	It will occur problem when doing flash probing if the flash is at
+	BANK0 (0x00000000) while memory remapping was skipped.
+
+	Other board like ADP-AG101P may not enable this since there is only
+	a FLASH connected to bank0.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from FLASH and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag101.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101` in u-boot root to build the image.
+
+burn u-boot to flash:
+1. Make sure the MA17 (J16) is Lo.
+2. Make sure the dip switch SW5 is set to "0101".
+3. Power On. Press button "S1", then press button "SW1", then you will found the
+   debug LED show 67 means the system successfully booted into e-bios.
+   Now you can control the e-bios boot loader from your console.
+4. Under "Command>>" prompt, enter "97" (CopyImageFromCard)
+5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c".
+6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you
+   just build. It is usually "u-boot.bin".
+7. Under "Enter Dest. Address =>" prompt, enter the memory address where you
+   want to put the binary from SD card to RAM.
+   Address "0x500000" is our suggestion.
+8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command
+   environment.
+9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the
+   binary from RAM to FLASH.
+10. Under "CLI>" prompt, enter "exit" to finish the burn process.
+
+boot u-boot from flash:
+1. Make sure the MA17 (J16) is Hi).
+2. Make sure the dip switch SW5 is set to "1010".
+3. Power On. Press button "S1", then you will see the debug LED count to 20.
+4. Now you can use u-boot on ADP-AG101 board.
diff --git a/doc/README.standalone b/doc/README.standalone
index 6e6b65f..2be5f27 100644
--- a/doc/README.standalone
+++ b/doc/README.standalone
@@ -56,6 +56,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
 	ARM		0x0c100000	0x0c100000
 	MIPS		0x80200000	0x80200000
 	Blackfin	0x00001000	0x00001000
+	NDS32		0x00300000	0x00300000
 	Nios II		0x02000000	0x02000000
 
    For example, the "hello world" application may be loaded and
-- 
1.7.3.5

[U-Boot] [PATCH v11 6/9] nds32: standalone support

[Macpaul Lin]

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - code clean up.
Changes for v7-v11:
  - No change.

 examples/standalone/nds32.lds     |   64 +++++++++++++++++++++++++++++++++++++
 examples/standalone/stubs.c       |   17 +++++++++-
 examples/standalone/x86-testapp.c |   12 +++++++
 3 files changed, 92 insertions(+), 1 deletions(-)
 create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..c2ac107
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	. = ALIGN(4);
+	.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+	_end = .;
+
+	. = 0x02000000;
+	.u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 507d38c..11c7565 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
 "	jmp %%g1\n"					\
 "	nop\n"						\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	lwi	$r16, [$gp + (%0)]\n"	\
+"	lwi	$r16, [$r16 + (%1)]\n"	\
+"	jr	$r16\n"			\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
 #else
+/*"	addi	$sp, $sp, -24\n"	\
+"	br	$r16\n"			\*/
+
 #error stubs definition missing for this architecture
 #endif
 
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile (						\
 "	lw	$25, %1($25)\n"				\
 "	jr	$25\n"					\
 	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x)					\
+asm volatile (						\
+"	.globl mon_" #x "\n"				\
+"mon_" #x ":\n"						\
+"	lwi	$r16, [$gp + (%0)]\n"			\
+"	lwi	$r16, [$r16 + (%1)]\n"			\
+"	jr	$r16\n"					\
+	: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
+
 #else
 #error [No stub code for this arch]
 #endif
@@ -72,6 +82,8 @@ int main(void)
 	register volatile xxx_t *pq asm("r8");
 #elif defined(__mips__)
 	register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+	register volatile xxx_t *pq asm("$r16");
 #endif
 	char buf[32];
 
-- 
1.7.3.5

[U-Boot] [PATCH v11 7/9] nds32: common bdinfo, bootm, image support

[Macpaul Lin]

Add support of NDS32 to common commands bdinfo, bootm, and image format.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v6:
  - Code clean up
Changes for v7-v9:
  - No Change.
Changes for v10:
  - fix up according to the changes in master tree.
Changes for v11:
  - No Change.

 common/cmd_bdinfo.c |   26 ++++++++++++++++++++++++++
 common/cmd_bootm.c  |    2 ++
 common/image.c      |    1 +
 include/image.h     |    5 +++++
 4 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 6051120..52102db 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -413,6 +413,32 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num("arch_number",	bd->bi_arch_number);
+	print_num("env_t",		(ulong)bd->bi_env);
+	print_num("boot_params",	(ulong)bd->bi_boot_params);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 272d879..99ec547 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -187,6 +187,8 @@ void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
   #define IH_INITRD_ARCH IH_ARCH_SH
 #elif defined(__sparc__)
   #define IH_INITRD_ARCH IH_ARCH_SPARC
+#elif defined(__nds32__)
+  #define IH_INITRD_ARCH IH_ARCH_NDS32
 #else
 # error Unknown CPU type
 #endif
diff --git a/common/image.c b/common/image.c
index 5eea2a1..95e16b8 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	-1,			"",		"",		},
 };
 
diff --git a/include/image.h b/include/image.h
index 352e4a0..dcbbc8b 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_NDS32	        19	/* ANDES Technology - NDS32  */
 
 /*
  * Image Types
@@ -506,6 +507,8 @@ static inline int image_check_target_arch (const image_header_t *hdr)
 	if (!image_check_arch (hdr, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!image_check_arch (hdr, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!image_check_arch(hdr, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
@@ -658,6 +661,8 @@ static inline int fit_image_check_target_arch (const void *fdt, int node)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SH))
 #elif defined(__sparc__)
 	if (!fit_image_check_arch (fdt, node, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+	if (!fit_image_check_arch(fdt, node, IH_ARCH_NDS32))
 #else
 # error Unknown CPU type
 #endif
-- 
1.7.3.5

[U-Boot] [PATCH v11 8/9] adp-ag101: add board adp-ag101 support

[Macpaul Lin]

Add evaluation board "adp-ag101" configuration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
  - code clean up
Changes for v5-v6:
  - Refine the definitions and parameters about CLK,
    AHB controller, SDRAM controller, Static memory controllers.
  - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
  - ftahbc010:
    - Update include path of ftahbc010.
  - ftsdmc021:
    - Update include path of ftsdmc021.
  - ftsmc020:
    - Update include path of ftsmc020.
  - ftwdt010:
    - Fix WDT define and update include path.
    - Fix ftwdt010 for hardware reset.
  - ftpmu010:
    - Remove duplicate PMU definitions.
    - Add related configurations.
  - Fix MAX malloc len and fix saveenv.
  - clean up.
Changes for v7:
  - clean up.
  - Move CONFIG_SYS_TEXT_BASE from board/config.mk.
  - Fix Makefile and remove config.mk
Changes for v8:
  - No change.
Changes for v9:
  - Fix because other boards has been added into boards.cfg and
    broken this patch.
Changes for v10:
  - adp-ag101.h
   - Fix lines over 80 characters.
   - Fix for introducing gen-asm-offset.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix flash init.
   - fix ftsmc010 configuraion for flash probing.
   - Add SP_INIT related configurations for supporting relocation.
   - Fix CONFIG_TEXT_BASE for relocation.
   - Add CONFIG_MEM_REMAP for some hardware boards and non-OS application.
  - adp-ag101.c
   - Clean up for braces according to Wolfgang's suggestion.
   - Add mmc support for FTSDC010 SD/MMC Controller.
   - fix dram init(), made this more simpler.
Changes for v11:
  - No Change.

 MAINTAINERS                           |   11 +
 MAKEALL                               |    6 +
 board/AndesTech/adp-ag101/Makefile    |   57 +++++
 board/AndesTech/adp-ag101/adp-ag101.c |   89 +++++++
 boards.cfg                            |    1 +
 include/configs/adp-ag101.h           |  411 +++++++++++++++++++++++++++++++++
 6 files changed, 575 insertions(+), 0 deletions(-)
 create mode 100644 board/AndesTech/adp-ag101/Makefile
 create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
 create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 7982c36..6b7c664 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1162,5 +1162,16 @@ Chong Huang <chuang@ucrobotics.com>
 	bf525-ucr2	BF525
 
 #########################################################################
+# NDS32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+	ADP-AG101	N1213 (AG101 SoC)
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 3b98f03..232ed3b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -600,6 +600,12 @@ LIST_sh="$(boards_by_arch sh)"
 
 LIST_sparc="$(boards_by_arch sparc)"
 
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
 #-----------------------------------------------------------------------
 
 build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..5a403b1
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,57 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= adp-ag101.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+ifdef CONFIG_SYS_LDSCRIPT
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else
+LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..82ce4c9
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	ftsdc010_mmc_init(0);
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index c253f03..ce01cda 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -308,6 +308,7 @@ vct_platinumavc_small        mips        mips32      vct                 microna
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
 nios2-generic                nios2       nios2       nios2-generic       altera
+adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..0108033
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x80500000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_CMD_FAT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#else
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#endif
+
+#ifdef CONFIG_ADP_AG101
+/*
+ * There are 2 bank connected to FTSMC020 on ADP-AG101.
+ * You can use jumper and switch to force it booted from ROM or FLASH.
+ * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
+ * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
+ */
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0 (FLASH)
+ * PHYS_FLASH_1 should be 0x400000 (13 bits to store addr, 0x1000000)
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
+				 FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M	|	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_RBE	|	\
+				 FTSMC020_TPR_AST(1)	|	\
+				 FTSMC020_TPR_CTW(1)	|	\
+				 FTSMC020_TPR_ATI(1)	|	\
+				 FTSMC020_TPR_AT2(1)	|	\
+				 FTSMC020_TPR_WTC(1)	|	\
+				 FTSMC020_TPR_AHT(1)	|	\
+				 FTSMC020_TPR_TRNA(1))
+
+#endif /* CONFIG_ADP_AG101 */
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif	/* CONFIG_MEM_REMAP */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif	/* __CONFIG_H */
-- 
1.7.3.5

[U-Boot] [PATCH v11 9/9] doc/README: documents and readme for NDS32 arch

[Macpaul Lin]

Documents and READMEs for NDS32 architecture.
It patch also provides usage of SoC AG101 and board ADP-AG101.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v10:
  - The patch of documentation was not included.
Changes for v11:
  - Add the documents of NDS32, ag101, N1213.

 README                |   24 ++++++++++++++--
 doc/README.N1213      |   55 ++++++++++++++++++++++++++++++++++++
 doc/README.NDS32      |   41 +++++++++++++++++++++++++++
 doc/README.ag101      |   74 +++++++++++++++++++++++++++++++++++++++++++++++++
 doc/README.standalone |    1 +
 5 files changed, 192 insertions(+), 3 deletions(-)
 create mode 100644 doc/README.N1213
 create mode 100644 doc/README.NDS32
 create mode 100644 doc/README.ag101

diff --git a/README b/README
index 0886987..381e1e2 100644
--- a/README
+++ b/README
@@ -182,6 +182,10 @@ Directory Hierarchy:
     /cpu		CPU specific files
       /mips32		Files specific to MIPS32 CPUs
     /lib		Architecture specific library files
+  /nds32		Files generic to NDS32 architecture
+    /cpu		CPU specific files
+      /n1213		Files specific to Andes Technology N1213 CPUs
+    /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
@@ -3103,7 +3107,7 @@ Low Level (hardware related) configuration options:
 		globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-		[ARM, MIPS only] If this variable is defined, then certain
+		[ARM, NDS32, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
@@ -3653,8 +3657,8 @@ details; basically, the header defines the following image properties:
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
-  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
+  IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -4347,6 +4351,20 @@ On Nios II, the ABI is documented here:
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 
+On NDS32, the following registers are used:
+
+	R0-R1:	argument/return
+	R2-R5:	argument
+	R15:	temporary register for assembler
+	R16:	trampoline register
+	R28:	frame pointer (FP)
+	R29:	global pointer (GP)
+	R30:	link register (LP)
+	R31:	stack pointer (SP)
+	PC:	program counter (PC)
+
+    ==> U-Boot will use R10 to hold a pointer to the global data
+
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 
diff --git a/doc/README.N1213 b/doc/README.N1213
new file mode 100644
index 0000000..e107166
--- /dev/null
+++ b/doc/README.N1213
@@ -0,0 +1,55 @@
+N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
+
+Features
+========
+
+CPU Core
+ - 16-/32-bit mixable instruction format.
+ - 32 general-purpose 32-bit registers.
+ - 8-stage pipeline.
+ - Dynamic branch prediction.
+ - 32/64/128/256 BTB.
+ - Return address stack (RAS).
+ - Vector interrupts for internal/external.
+   interrupt controller with 6 hardware interrupt signals.
+ - 3 HW-level nested interruptions.
+ - User and super-user mode support.
+ - Memory-mapped I/O.
+ - Address space up to 4GB.
+
+Memory Management Unit
+ - TLB
+   - 4/8-entry fully associative iTLB/dTLB.
+   - 32/64/128-entry 4-way set-associati.ve main TLB.
+   - TLB locking support
+ - Optional hardware page table walker.
+ - Two groups of page size support.
+  - 4KB & 1MB.
+  - 8KB & 1MB.
+
+Memory Subsystem
+ - I & D cache.
+   - Virtually indexed and physically tagged.
+   - Cache size: 8KB/16KB/32KB/64KB.
+   - Cache line size: 16B/32B.
+   - Set associativity: 2-way, 4-way or direct-mapped.
+   - Cache locking support.
+ - I & D local memory (LM).
+   - Size: 4KB to 1MB.
+   - Bank numbers: 1 or 2.
+   - Optional 1D/2D DMA engine.
+   - Internal or external to CPU core.
+
+Bus Interface
+ - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
+ - Synchronous High speed memory port.
+   (HSMP): 0, 1 or 2 ports.
+
+Debug
+ - JTAG debug interface.
+ - Embedded debug module (EDM).
+ - Optional embedded program tracer interface.
+
+Miscellaneous
+ - Programmable data endian control.
+ - Performance monitoring mechanism.
diff --git a/doc/README.NDS32 b/doc/README.NDS32
new file mode 100644
index 0000000..b2b58fc
--- /dev/null
+++ b/doc/README.NDS32
@@ -0,0 +1,41 @@
+NDS32 is a new high-performance 32-bit RISC microprocessor core.
+
+http://www.andestech.com/
+
+AndeStar ISA
+============
+AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
+achieve optimal system performance, code density, and power efficiency.
+
+It contains the following features:
+ - Intermixable 32-bit and 16-bit instruction sets without the need for
+   mode switch.
+ - 16-bit instructions as a frequently used subset of 32-bit instructions.
+ - RISC-style register-based instruction set.
+ - 32 32-bit General Purpose Registers (GPR).
+ - Upto 1024 User Special Registers (USR) for existing and extension
+   instructions.
+ - Rich load/store instructions for...
+   - Single memory access with base address update.
+   - Multiple aligned and unaligned memory accesses for memory copy and stack
+     operations.
+   - Data prefetch to improve data cache performance.
+   - Non-bus locking synchronization instructions.
+ - PC relative jump and PC read instructions for efficient position independent
+   code.
+ - Multiply-add and multiple-sub with 64-bit accumulator.
+ - Instruction for efficient power management.
+ - Bi-endian support.
+ - Three instruction extension space for application acceleration:
+   - Performance extension.
+   - Andes future extensions (for floating-point, multimedia, etc.)
+   - Customer extensions.
+
+AndesCore CPU
+=============
+Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
+
+For details about N12 CPU family, please check doc/README.N1213.
+
+The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
+other associated software are actively supported by Andes Technology Corporation.
diff --git a/doc/README.ag101 b/doc/README.ag101
new file mode 100644
index 0000000..46fc637
--- /dev/null
+++ b/doc/README.ag101
@@ -0,0 +1,74 @@
+Andes Technology SoC AG101
+==========================
+
+AG101 is the first SoC produced by Andes Technology using N1213 CPU core.
+AG101 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG101
+=========
+
+ADP-AG101 is the SoC with AG101 hardcore CPU.
+
+Please check http://www.andestech.com/p2-4.htm for detail of this SoC.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+	This is also a must on ADP-AG101 board.
+	(While other boards may not have this problem).
+
+	The reason is because the ROM/FLASH circuit on PCB board.
+	AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	ROM/FLASH is used to boot.
+
+	When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	and the FLASH is connected to BANK1.
+	When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	and the FLASH is connected to BANK0.
+	It will occur problem when doing flash probing if the flash is at
+	BANK0 (0x00000000) while memory remapping was skipped.
+
+	Other board like ADP-AG101P may not enable this since there is only
+	a FLASH connected to bank0.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from FLASH and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag101.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101` in u-boot root to build the image.
+
+burn u-boot to flash:
+1. Make sure the MA17 (J16) is Lo.
+2. Make sure the dip switch SW5 is set to "0101".
+3. Power On. Press button "S1", then press button "SW1", then you will found the
+   debug LED show 67 means the system successfully booted into e-bios.
+   Now you can control the e-bios boot loader from your console.
+4. Under "Command>>" prompt, enter "97" (CopyImageFromCard)
+5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c".
+6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you
+   just build. It is usually "u-boot.bin".
+7. Under "Enter Dest. Address =>" prompt, enter the memory address where you
+   want to put the binary from SD card to RAM.
+   Address "0x500000" is our suggestion.
+8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command
+   environment.
+9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the
+   binary from RAM to FLASH.
+10. Under "CLI>" prompt, enter "exit" to finish the burn process.
+
+boot u-boot from flash:
+1. Make sure the MA17 (J16) is Hi).
+2. Make sure the dip switch SW5 is set to "1010".
+3. Power On. Press button "S1", then you will see the debug LED count to 20.
+4. Now you can use u-boot on ADP-AG101 board.
diff --git a/doc/README.standalone b/doc/README.standalone
index 6e6b65f..2be5f27 100644
--- a/doc/README.standalone
+++ b/doc/README.standalone
@@ -56,6 +56,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
 	ARM		0x0c100000	0x0c100000
 	MIPS		0x80200000	0x80200000
 	Blackfin	0x00001000	0x00001000
+	NDS32		0x00300000	0x00300000
 	Nios II		0x02000000	0x02000000
 
    For example, the "hello world" application may be loaded and
-- 
1.7.3.5