* [Qemu-devel] [PATCH v4 01/14] Introduce TCGOpcode for memory barrier
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 02/14] tcg/i386: Add support for fence Pranith Kumar
` (15 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Richard Henderson, open list:All patches CC here
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell
This commit introduces the TCGOpcode for memory barrier instruction.
This opcode takes an argument which is the type of memory barrier
which should be generated.
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
tcg/README | 17 +++++++++++++++++
tcg/tcg-op.c | 17 +++++++++++++++++
tcg/tcg-op.h | 2 ++
tcg/tcg-opc.h | 2 ++
tcg/tcg.h | 19 +++++++++++++++++++
5 files changed, 57 insertions(+)
diff --git a/tcg/README b/tcg/README
index ce8beba..1d48aa9 100644
--- a/tcg/README
+++ b/tcg/README
@@ -402,6 +402,23 @@ double-word product T0. The later is returned in two single-word outputs.
Similar to mulu2, except the two inputs T1 and T2 are signed.
+********* Memory Barrier support
+
+* mb <$arg>
+
+Generate a target memory barrier instruction to ensure memory ordering as being
+enforced by a corresponding guest memory barrier instruction. The ordering
+enforced by the backend may be stricter than the ordering required by the guest.
+It cannot be weaker. This opcode takes a constant argument which is required to
+generate the appropriate barrier instruction. The backend should take care to
+emit the target barrier instruction only when necessary i.e., for SMP guests and
+when MTTCG is enabled.
+
+The guest translators should generate this opcode for all guest instructions
+which have ordering side effects.
+
+Please see docs/atomics.txt for more information on memory barriers.
+
********* 64-bit guest on 32-bit host support
The following opcodes are internal to TCG. Thus they are to be implemented by
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 293b854..149f4a9 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -148,6 +148,23 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
tcg_emit_op(ctx, opc, pi);
}
+void tcg_gen_mb(TCGArg mb_type)
+{
+ bool emit_barriers = true;
+
+#ifndef CONFIG_USER_ONLY
+ /* TODO: When MTTCG is available for system mode, we will check
+ * the following condition and enable emit_barriers
+ * (qemu_tcg_mttcg_enabled() && smp_cpus > 1)
+ */
+ emit_barriers = false;
+#endif
+
+ if (emit_barriers) {
+ tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type);
+ }
+}
+
/* 32 bit ops */
void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index f217e80..41890cc 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -261,6 +261,8 @@ static inline void tcg_gen_br(TCGLabel *l)
tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l));
}
+void tcg_gen_mb(TCGArg a);
+
/* Helper calls. */
/* 32 bit ops */
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 6d0410c..45528d2 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END)
# define IMPL64 TCG_OPF_64BIT
#endif
+DEF(mb, 0, 0, 1, 0)
+
DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
DEF(setcond_i32, 1, 2, 1, 0)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 66ae0c7..639e30c 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -478,6 +478,25 @@ static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
#define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1)
#define TCG_CALL_DUMMY_ARG ((TCGArg)(-1))
+/* used to indicate the type of accesses on which ordering is to be
+ ensured. Modeled after SPARC barriers */
+typedef enum {
+ TCG_MO_LD_LD = 1,
+ TCG_MO_ST_LD = 2,
+ TCG_MO_LD_ST = 4,
+ TCG_MO_ST_ST = 8,
+ TCG_MO_ALL = 0xF, /* OR of all above */
+} TCGOrder;
+
+/* used to indicate the kind of ordering which is to be ensured by the
+ instruction. These types are derived from x86/aarch64 instructions.
+ It should be noted that these are different from C11 semantics */
+typedef enum {
+ TCG_BAR_LDAQ = 0x10, /* generated for aarch64 load-acquire inst. */
+ TCG_BAR_STRL = 0x20, /* generated for aarch64 store-rel inst. */
+ TCG_BAR_SC = 0x40, /* generated for all other ordering inst. */
+} TCGBar;
+
/* Conditions. Note that these are laid out for easy manipulation by
the functions below:
bit 0 is used for inverting;
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH v4 02/14] tcg/i386: Add support for fence
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 01/14] Introduce TCGOpcode for memory barrier Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] " Pranith Kumar
` (14 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Richard Henderson, open list:i386 target
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell
Generate a 'lock orl $0,0(%esp)' instruction for ordering instead of
mfence which has similar ordering semantics.
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
tcg/i386/tcg-target.inc.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 6f8cdca..a516ec9 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -686,6 +686,18 @@ static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)
}
}
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ /* lock orl $0,0(%esp) is used instead of mfence,
+ * sfence/lfence are not generated
+ */
+ if (a0 & TCG_MO_ST_LD) {
+ tcg_out8(s, 0xf0);
+ tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0);
+ tcg_out8(s, 0);
+ }
+}
+
static inline void tcg_out_push(TCGContext *s, int reg)
{
tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0);
@@ -2130,6 +2142,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_mb:
+ tcg_debug_assert(args[0] != 0);
+ tcg_out_mb(s, args[0]);
+ break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -2195,6 +2211,8 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
+ { INDEX_op_mb, { } },
+
#if TCG_TARGET_REG_BITS == 32
{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
{ INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v4 03/14] tcg/aarch64: Add support for fence
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 02/14] tcg/i386: Add support for fence Pranith Kumar
` (15 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Claudio Fontana, Richard Henderson, open list:AArch64 target,
open list:All patches CC here
Cc: qemu-devel, alex.bennee, serge.fdrv, pbonzini, peter.maydell,
Claudio Fontana
Cc: Claudio Fontana <claudio.fontana@gmail.com>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
tcg/aarch64/tcg-target.inc.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 08b2d03..1d220b7 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -372,6 +372,11 @@ typedef enum {
I3510_EOR = 0x4a000000,
I3510_EON = 0x4a200000,
I3510_ANDS = 0x6a000000,
+
+ /* System instructions. */
+ DMB_ISH = 0xd50338bf,
+ DMB_LD = 0x00000100,
+ DMB_ST = 0x00000200,
} AArch64Insn;
static inline uint32_t tcg_in32(TCGContext *s)
@@ -981,6 +986,22 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
tcg_out_mov(s, ext, orig_rl, rl);
}
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ uint32_t dmb_type = DMB_ISH;
+ if (a0 & (TCG_MO_LD_ST | TCG_MO_ST_LD)) {
+ tcg_out32(s, dmb_type | DMB_LD | DMB_ST);
+ return;
+ }
+ if (a0 & TCG_MO_LD_LD) {
+ dmb_type |= DMB_LD;
+ }
+ if (a0 & TCG_MO_ST_ST) {
+ dmb_type |= DMB_ST;
+ }
+ tcg_out32(s, dmb_type);
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* TCGMemOpIdx oi, uintptr_t ra)
@@ -1648,6 +1669,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -1772,6 +1797,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_muluh_i64, { "r", "r", "r" } },
{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH v4 03/14] tcg/aarch64: Add support for fence
@ 2016-07-14 20:20 ` Pranith Kumar
0 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Claudio Fontana, Richard Henderson, open list:AArch64 target,
open list:All patches CC here
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell, Claudio Fontana
Cc: Claudio Fontana <claudio.fontana@gmail.com>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
tcg/aarch64/tcg-target.inc.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 08b2d03..1d220b7 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -372,6 +372,11 @@ typedef enum {
I3510_EOR = 0x4a000000,
I3510_EON = 0x4a200000,
I3510_ANDS = 0x6a000000,
+
+ /* System instructions. */
+ DMB_ISH = 0xd50338bf,
+ DMB_LD = 0x00000100,
+ DMB_ST = 0x00000200,
} AArch64Insn;
static inline uint32_t tcg_in32(TCGContext *s)
@@ -981,6 +986,22 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
tcg_out_mov(s, ext, orig_rl, rl);
}
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ uint32_t dmb_type = DMB_ISH;
+ if (a0 & (TCG_MO_LD_ST | TCG_MO_ST_LD)) {
+ tcg_out32(s, dmb_type | DMB_LD | DMB_ST);
+ return;
+ }
+ if (a0 & TCG_MO_LD_LD) {
+ dmb_type |= DMB_LD;
+ }
+ if (a0 & TCG_MO_ST_ST) {
+ dmb_type |= DMB_ST;
+ }
+ tcg_out32(s, dmb_type);
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* TCGMemOpIdx oi, uintptr_t ra)
@@ -1648,6 +1669,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -1772,6 +1797,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_muluh_i64, { "r", "r", "r" } },
{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v4 04/14] tcg/arm: Add support for fence
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 02/14] tcg/i386: Add support for fence Pranith Kumar
` (15 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Andrzej Zaborowski, Richard Henderson, open list:ARM target,
open list:All patches CC here
Cc: qemu-devel, alex.bennee, serge.fdrv, pbonzini, peter.maydell
Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 172feba..4e66bcd 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -313,6 +313,10 @@ typedef enum {
INSN_LDRD_REG = 0x000000d0,
INSN_STRD_IMM = 0x004000f0,
INSN_STRD_REG = 0x000000f0,
+
+ INSN_DMB_ISH = 0x5bf07ff5,
+ INSN_DMB_MCR = 0xba0f07ee,
+
} ARMInsn;
#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
@@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
}
}
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ if (use_armv7_instructions) {
+ tcg_out32(s, INSN_DMB_ISH);
+ } else if (use_armv6_instructions) {
+ tcg_out32(s, INSN_DMB_MCR);
+ }
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
@@ -1923,6 +1936,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_call: /* Always emitted via tcg_out_call. */
@@ -1997,6 +2014,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_div_i32, { "r", "r", "r" } },
{ INDEX_op_divu_i32, { "r", "r", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH v4 04/14] tcg/arm: Add support for fence
@ 2016-07-14 20:20 ` Pranith Kumar
0 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Andrzej Zaborowski, Richard Henderson, open list:ARM target,
open list:All patches CC here
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell
Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 172feba..4e66bcd 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -313,6 +313,10 @@ typedef enum {
INSN_LDRD_REG = 0x000000d0,
INSN_STRD_IMM = 0x004000f0,
INSN_STRD_REG = 0x000000f0,
+
+ INSN_DMB_ISH = 0x5bf07ff5,
+ INSN_DMB_MCR = 0xba0f07ee,
+
} ARMInsn;
#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
@@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
}
}
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ if (use_armv7_instructions) {
+ tcg_out32(s, INSN_DMB_ISH);
+ } else if (use_armv6_instructions) {
+ tcg_out32(s, INSN_DMB_MCR);
+ }
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
@@ -1923,6 +1936,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_call: /* Always emitted via tcg_out_call. */
@@ -1997,6 +2014,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_div_i32, { "r", "r", "r" } },
{ INDEX_op_divu_i32, { "r", "r", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v4 05/14] tcg/ia64: Add support for fence
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (3 preceding siblings ...)
2016-07-14 20:20 ` [Qemu-devel] " Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 06/14] tcg/mips: " Pranith Kumar
` (11 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Aurelien Jarno, Richard Henderson, open list:All patches CC here
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
tcg/ia64/tcg-target.inc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/tcg/ia64/tcg-target.inc.c b/tcg/ia64/tcg-target.inc.c
index c91f392..26812ee 100644
--- a/tcg/ia64/tcg-target.inc.c
+++ b/tcg/ia64/tcg-target.inc.c
@@ -247,6 +247,7 @@ enum {
OPC_LD4_M3 = 0x0a080000000ull,
OPC_LD8_M1 = 0x080c0000000ull,
OPC_LD8_M3 = 0x0a0c0000000ull,
+ OPC_MF_M24 = 0x00110000000ull,
OPC_MUX1_I3 = 0x0eca0000000ull,
OPC_NOP_B9 = 0x04008000000ull,
OPC_NOP_F16 = 0x00008000000ull,
@@ -2223,6 +2224,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_qemu_st(s, args);
break;
+ case INDEX_op_mb:
+ tcg_out_bundle(s, mmI, OPC_MF_M24, INSN_NOP_M, INSN_NOP_I);
+ break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -2336,6 +2340,7 @@ static const TCGTargetOpDef ia64_op_defs[] = {
{ INDEX_op_qemu_st_i32, { "SZ", "r" } },
{ INDEX_op_qemu_st_i64, { "SZ", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH v4 06/14] tcg/mips: Add support for fence
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (4 preceding siblings ...)
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 05/14] tcg/ia64: " Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 07/14] tcg/ppc: " Pranith Kumar
` (10 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Aurelien Jarno, Richard Henderson, open list:All patches CC here
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
tcg/mips/tcg-target.inc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 2f9be48..1f5adbe 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -292,6 +292,7 @@ typedef enum {
OPC_JALR = OPC_SPECIAL | 0x09,
OPC_MOVZ = OPC_SPECIAL | 0x0A,
OPC_MOVN = OPC_SPECIAL | 0x0B,
+ OPC_SYNC = OPC_SPECIAL | 0x0F,
OPC_MFHI = OPC_SPECIAL | 0x10,
OPC_MFLO = OPC_SPECIAL | 0x12,
OPC_MULT = OPC_SPECIAL | 0x18,
@@ -1646,6 +1647,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
const_args[4], const_args[5], true);
break;
+ case INDEX_op_mb:
+ tcg_out32(s, OPC_SYNC);
+ break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_call: /* Always emitted via tcg_out_call. */
@@ -1726,6 +1730,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_qemu_ld_i64, { "L", "L", "lZ", "lZ" } },
{ INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } },
#endif
+
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH v4 07/14] tcg/ppc: Add support for fence
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (5 preceding siblings ...)
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 06/14] tcg/mips: " Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 08/14] tcg/s390: " Pranith Kumar
` (9 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Vassili Karpov (malc), Richard Henderson,
open list:All patches CC here
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/ppc/tcg-target.inc.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index eaf1bd9..1547d8f 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -469,6 +469,10 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define STHX XO31(407)
#define STWX XO31(151)
+#define EIEIO XO31(854)
+#define HWSYNC XO31(598)
+#define LWSYNC (HWSYNC | (1u << 21))
+
#define SPR(a, b) ((((a)<<5)|(b))<<11)
#define LR SPR(8, 0)
#define CTR SPR(9, 0)
@@ -1243,6 +1247,19 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
}
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ if (a0 & TCG_MO_LD_LD) {
+ tcg_out32(s, LWSYNC);
+ return;
+ }
+ if (a0 & TCG_MO_ST_ST) {
+ tcg_out32(s, EIEIO);
+ return;
+ }
+ tcg_out32(s, HWSYNC);
+}
+
#ifdef __powerpc64__
void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
{
@@ -2449,6 +2466,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -2596,6 +2617,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
#endif
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH v4 08/14] tcg/s390: Add support for fence
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (6 preceding siblings ...)
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 07/14] tcg/ppc: " Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-10-16 8:47 ` Stefan Hajnoczi
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 09/14] tcg/sparc: " Pranith Kumar
` (8 subsequent siblings)
16 siblings, 1 reply; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Alexander Graf, Richard Henderson, open list:All patches CC here
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/s390/tcg-target.inc.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 5a7495b..01aae35 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -343,6 +343,7 @@ static tcg_insn_unit *tb_ret_addr;
#define FACILITY_EXT_IMM (1ULL << (63 - 21))
#define FACILITY_GEN_INST_EXT (1ULL << (63 - 34))
#define FACILITY_LOAD_ON_COND (1ULL << (63 - 45))
+#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
static uint64_t facilities;
@@ -2172,6 +2173,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tgen_deposit(s, args[0], args[2], args[3], args[4]);
break;
+ case INDEX_op_mb:
+ /* The host memory model is quite strong, we simply need to
+ serialize the instruction stream. */
+ if (args[0] == TCG_MO_ALL || args[0] == TCG_MO_ST_LD) {
+ tcg_out_insn(s, RR, BCR,
+ facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
+ }
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -2293,6 +2303,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } },
{ INDEX_op_deposit_i64, { "r", "0", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [Qemu-devel] [PATCH v4 08/14] tcg/s390: Add support for fence
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 08/14] tcg/s390: " Pranith Kumar
@ 2016-10-16 8:47 ` Stefan Hajnoczi
2016-10-16 16:17 ` Pranith Kumar
0 siblings, 1 reply; 26+ messages in thread
From: Stefan Hajnoczi @ 2016-10-16 8:47 UTC (permalink / raw)
To: Pranith Kumar
Cc: Alexander Graf, Richard Henderson, open list:All patches CC here,
peter.maydell, serge.fdrv, alex.bennee, pbonzini
[-- Attachment #1: Type: text/plain, Size: 1633 bytes --]
On Thu, Jul 14, 2016 at 04:20:20PM -0400, Pranith Kumar wrote:
> Cc: Alexander Graf <agraf@suse.de>
> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/s390/tcg-target.inc.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
> index 5a7495b..01aae35 100644
> --- a/tcg/s390/tcg-target.inc.c
> +++ b/tcg/s390/tcg-target.inc.c
> @@ -343,6 +343,7 @@ static tcg_insn_unit *tb_ret_addr;
> #define FACILITY_EXT_IMM (1ULL << (63 - 21))
> #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34))
> #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45))
> +#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
>
> static uint64_t facilities;
>
> @@ -2172,6 +2173,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
> tgen_deposit(s, args[0], args[2], args[3], args[4]);
> break;
>
> + case INDEX_op_mb:
> + /* The host memory model is quite strong, we simply need to
> + serialize the instruction stream. */
> + if (args[0] == TCG_MO_ALL || args[0] == TCG_MO_ST_LD) {
> + tcg_out_insn(s, RR, BCR,
> + facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
> + }
args[0] == TCG_MO_ALL is always false since frontends bitwise-OR
TCG_BAR_SC.
Did you mean:
switch (args[0] & TCG_MO_ALL) {
case TCG_MO_ALL: /* fall-through */
case TCG_MO_ST_LD:
tcg_out_insn(s, RR, BCR,
facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
break;
}
?
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 455 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [Qemu-devel] [PATCH v4 08/14] tcg/s390: Add support for fence
2016-10-16 8:47 ` Stefan Hajnoczi
@ 2016-10-16 16:17 ` Pranith Kumar
0 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-10-16 16:17 UTC (permalink / raw)
To: Stefan Hajnoczi
Cc: Alexander Graf, Richard Henderson, open list:All patches CC here,
Peter Maydell, Sergey Fedorov, Alex Bennée, Paolo Bonzini
On Sun, Oct 16, 2016 at 4:47 AM, Stefan Hajnoczi <stefanha@gmail.com> wrote:
> On Thu, Jul 14, 2016 at 04:20:20PM -0400, Pranith Kumar wrote:
>> Cc: Alexander Graf <agraf@suse.de>
>> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>> ---
>> tcg/s390/tcg-target.inc.c | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
>> index 5a7495b..01aae35 100644
>> --- a/tcg/s390/tcg-target.inc.c
>> +++ b/tcg/s390/tcg-target.inc.c
>> @@ -343,6 +343,7 @@ static tcg_insn_unit *tb_ret_addr;
>> #define FACILITY_EXT_IMM (1ULL << (63 - 21))
>> #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34))
>> #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45))
>> +#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
>>
>> static uint64_t facilities;
>>
>> @@ -2172,6 +2173,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
>> tgen_deposit(s, args[0], args[2], args[3], args[4]);
>> break;
>>
>> + case INDEX_op_mb:
>> + /* The host memory model is quite strong, we simply need to
>> + serialize the instruction stream. */
>> + if (args[0] == TCG_MO_ALL || args[0] == TCG_MO_ST_LD) {
>> + tcg_out_insn(s, RR, BCR,
>> + facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
>> + }
>
> args[0] == TCG_MO_ALL is always false since frontends bitwise-OR
> TCG_BAR_SC.
>
> Did you mean:
>
> switch (args[0] & TCG_MO_ALL) {
> case TCG_MO_ALL: /* fall-through */
> case TCG_MO_ST_LD:
> tcg_out_insn(s, RR, BCR,
> facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
> break;
> }
Yup, that is what is intended. It looks like this patch was fixed by
rth when he merged it to do the correct thing. phew :)
--
Pranith
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v4 09/14] tcg/sparc: Add support for fence
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (7 preceding siblings ...)
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 08/14] tcg/s390: " Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 10/14] tcg/tci: " Pranith Kumar
` (7 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Richard Henderson, open list:All patches CC here
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell, Blue Swirl
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/sparc/tcg-target.inc.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 8e98172..04a6404 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -249,6 +249,8 @@ static const int tcg_target_call_oarg_regs[] = {
#define STWA (INSN_OP(3) | INSN_OP3(0x14))
#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
+#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
+
#ifndef ASI_PRIMARY_LITTLE
#define ASI_PRIMARY_LITTLE 0x88
#endif
@@ -835,6 +837,24 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
tcg_out_nop(s);
}
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ uint8_t bar_opcode = MEMBAR;
+ if (a0 & TCG_MO_LD_LD) {
+ /* #LoadLoad */
+ bar_opcode |= 0x5;
+ }
+ if (a0 & TCG_MO_ST_ST) {
+ /* #StoreStore */
+ bar_opcode |= 0xa;
+ }
+ if (a0 & (TCG_MO_LD_ST | TCG_MO_ST_LD)) {
+ /* #StoreLoad | #LoadStore */
+ bar_opcode |= 0xf;
+ }
+ tcg_out32(s, bar_opcode);
+}
+
#ifdef CONFIG_SOFTMMU
static tcg_insn_unit *qemu_ld_trampoline[16];
static tcg_insn_unit *qemu_st_trampoline[16];
@@ -1460,6 +1480,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -1561,6 +1585,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_qemu_st_i32, { "sZ", "A" } },
{ INDEX_op_qemu_st_i64, { "SZ", "A" } },
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH v4 10/14] tcg/tci: Add support for fence
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (8 preceding siblings ...)
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 09/14] tcg/sparc: " Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] " Pranith Kumar
` (6 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Stefan Weil, Richard Henderson, open list:All patches CC here
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell
Cc: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tci/tcg-target.inc.c | 3 +++
tci.c | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c
index 3c47ea7..9dbf4d5 100644
--- a/tcg/tci/tcg-target.inc.c
+++ b/tcg/tci/tcg-target.inc.c
@@ -255,6 +255,7 @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
{ INDEX_op_bswap32_i32, { R, R } },
#endif
+ { INDEX_op_mb, { } },
{ -1 },
};
@@ -800,6 +801,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
}
tcg_out_i(s, *args++);
break;
+ case INDEX_op_mb:
+ break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
diff --git a/tci.c b/tci.c
index b488c0d..4bdc645 100644
--- a/tci.c
+++ b/tci.c
@@ -1236,6 +1236,10 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
tcg_abort();
}
break;
+ case INDEX_op_mb:
+ /* Ensure ordering for all kinds */
+ smp_mb();
+ break;
default:
TODO();
break;
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v4 11/14] target-arm: Generate fences in ARMv7 frontend
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 02/14] tcg/i386: Add support for fence Pranith Kumar
` (15 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Peter Maydell, open list:ARM, open list:All patches CC here
Cc: qemu-devel, alex.bennee, serge.fdrv, rth, pbonzini
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
target-arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index bd5d5cb..693d4bc 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8083,7 +8083,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
case 4: /* dsb */
case 5: /* dmb */
ARCH(7);
- /* We don't emulate caches so these are a no-op. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
return;
case 6: /* isb */
/* We need to break the TB after this insn to execute
@@ -10432,7 +10432,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
break;
case 4: /* dsb */
case 5: /* dmb */
- /* These execute as NOPs. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
break;
case 6: /* isb */
/* We need to break the TB after this insn
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH v4 11/14] target-arm: Generate fences in ARMv7 frontend
@ 2016-07-14 20:20 ` Pranith Kumar
0 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Peter Maydell, open list:ARM, open list:All patches CC here
Cc: alex.bennee, serge.fdrv, rth, pbonzini
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
target-arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index bd5d5cb..693d4bc 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8083,7 +8083,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
case 4: /* dsb */
case 5: /* dmb */
ARCH(7);
- /* We don't emulate caches so these are a no-op. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
return;
case 6: /* isb */
/* We need to break the TB after this insn to execute
@@ -10432,7 +10432,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
break;
case 4: /* dsb */
case 5: /* dmb */
- /* These execute as NOPs. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
break;
case 6: /* isb */
/* We need to break the TB after this insn
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v4 12/14] target-alpha: Generate fence op
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (10 preceding siblings ...)
2016-07-14 20:20 ` [Qemu-devel] " Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] " Pranith Kumar
` (4 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Richard Henderson, open list:All patches CC here
Cc: alex.bennee, serge.fdrv, pbonzini, peter.maydell
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-alpha/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 0ea0e6e..c27c7b9 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2338,11 +2338,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x4000:
/* MB */
- /* No-op */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
break;
case 0x4400:
/* WMB */
- /* No-op */
+ tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC);
break;
case 0x8000:
/* FETCH */
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v4 13/14] target-aarch64: Generate fences for aarch64
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 02/14] tcg/i386: Add support for fence Pranith Kumar
` (15 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Peter Maydell, open list:ARM, open list:All patches CC here
Cc: qemu-devel, alex.bennee, serge.fdrv, rth, pbonzini
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
target-arm/translate-a64.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index f5e29d2..09877bc 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1305,7 +1305,7 @@ static void handle_sync(DisasContext *s, uint32_t insn,
return;
case 4: /* DSB */
case 5: /* DMB */
- /* We don't emulate caches so barriers are no-ops */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
return;
case 6: /* ISB */
/* We need to break the TB after this insn to execute
@@ -1934,7 +1934,13 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (!is_store) {
s->is_ldex = true;
gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
} else {
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
}
} else {
@@ -1943,11 +1949,17 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
/* Generate ISS for non-exclusive accesses including LASR. */
if (is_store) {
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
do_gpr_st(s, tcg_rt, tcg_addr, size,
true, rt, iss_sf, is_lasr);
} else {
do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false,
true, rt, iss_sf, is_lasr);
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
}
}
}
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH v4 13/14] target-aarch64: Generate fences for aarch64
@ 2016-07-14 20:20 ` Pranith Kumar
0 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Peter Maydell, open list:ARM, open list:All patches CC here
Cc: alex.bennee, serge.fdrv, rth, pbonzini
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
target-arm/translate-a64.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index f5e29d2..09877bc 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1305,7 +1305,7 @@ static void handle_sync(DisasContext *s, uint32_t insn,
return;
case 4: /* DSB */
case 5: /* DMB */
- /* We don't emulate caches so barriers are no-ops */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
return;
case 6: /* ISB */
/* We need to break the TB after this insn to execute
@@ -1934,7 +1934,13 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (!is_store) {
s->is_ldex = true;
gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
} else {
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
}
} else {
@@ -1943,11 +1949,17 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
/* Generate ISS for non-exclusive accesses including LASR. */
if (is_store) {
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
do_gpr_st(s, tcg_rt, tcg_addr, size,
true, rt, iss_sf, is_lasr);
} else {
do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false,
true, rt, iss_sf, is_lasr);
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
}
}
}
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v4 14/14] target-i386: Generate fences for x86
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (12 preceding siblings ...)
2016-07-14 20:20 ` [Qemu-devel] " Pranith Kumar
@ 2016-07-14 20:20 ` Pranith Kumar
2016-07-23 16:08 ` [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (2 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-14 20:20 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost,
open list:All patches CC here
Cc: alex.bennee, serge.fdrv, peter.maydell
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
target-i386/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7dea18b..ebeb6f0 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8012,13 +8012,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
+ tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC);
break;
case 0xe8 ... 0xef: /* lfence */
+ if (!(s->cpuid_features & CPUID_SSE)
+ || (prefixes & PREFIX_LOCK)) {
+ goto illegal_op;
+ }
+ tcg_gen_mb(TCG_MO_LD_LD | TCG_BAR_SC);
+ break;
case 0xf0 ... 0xf7: /* mfence */
if (!(s->cpuid_features & CPUID_SSE2)
|| (prefixes & PREFIX_LOCK)) {
goto illegal_op;
}
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
break;
default:
--
2.9.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (13 preceding siblings ...)
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 14/14] target-i386: Generate fences for x86 Pranith Kumar
@ 2016-07-23 16:08 ` Pranith Kumar
2016-07-23 17:34 ` Paolo Bonzini
2016-08-08 14:05 ` Pranith Kumar
2016-09-07 17:33 ` Richard Henderson
16 siblings, 1 reply; 26+ messages in thread
From: Pranith Kumar @ 2016-07-23 16:08 UTC (permalink / raw)
To: Pranith Kumar
Cc: qemu-devel, Alex Bennée, Sergey Fedorov, Richard Henderson,
Paolo Bonzini, Peter Maydell
Ping for review!
On Thu, Jul 14, 2016 at 4:20 PM, Pranith Kumar <bobby.prani@gmail.com> wrote:
> Hello,
>
> The following series adds fence instruction generation support to
> TCG. Based on feedback to the last series, I added the four
> combinations of orderings modeled after Sparc membar.
>
> This has been tested and confirmed to fix ordering issues on
> x86/armv7/aarch64 hosts with MTTCG enabled for an ARMv7 guest using
> KVM unit tests. It has also been tested with litmus tests provided by
> Alex Bennée.
>
> TODO:
>
> * The acquire/release order is not utilized yet. Currently we generate
> SC barriers even for acquire/release barriers. The idea is to write
> a pass which combines acquire/release barrier with its corresponding
> load/store operation to generate the load acquire/store release
> instruction on hosts which have such instruction(aarch64 for
> now).
>
> v4:
>
> - Update with comments from v3
> - Use 'lock orl' instead of mfence on x86. Remove sse2 checks.
> - Rebase on qemu/master instead of MTTCG
> - Rename acquire barrier to load-acquire and release to store-release
> to avoid confusion with prevailing terminology
>
> v3:
>
> - Create different types of barriers. The barrier tcg opcode now takes
> an argument to generate the appropriate barrier instruction.
> - Also add acquire/release/sc ordering flag to argument.
>
> v2:
>
> - Rebase on Richard's patches generating fences for other
> architectures.
>
> v1:
>
> - Initial version: Introduce memory barrier tcg opcode.
>
> Pranith Kumar (14):
> Introduce TCGOpcode for memory barrier
> tcg/i386: Add support for fence
> tcg/aarch64: Add support for fence
> tcg/arm: Add support for fence
> tcg/ia64: Add support for fence
> tcg/mips: Add support for fence
> tcg/ppc: Add support for fence
> tcg/s390: Add support for fence
> tcg/sparc: Add support for fence
> tcg/tci: Add support for fence
> target-arm: Generate fences in ARMv7 frontend
> target-alpha: Generate fence op
> target-aarch64: Generate fences for aarch64
> target-i386: Generate fences for x86
>
> target-alpha/translate.c | 4 ++--
> target-arm/translate-a64.c | 14 +++++++++++++-
> target-arm/translate.c | 4 ++--
> target-i386/translate.c | 8 ++++++++
> tcg/README | 17 +++++++++++++++++
> tcg/aarch64/tcg-target.inc.c | 26 ++++++++++++++++++++++++++
> tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
> tcg/i386/tcg-target.inc.c | 18 ++++++++++++++++++
> tcg/ia64/tcg-target.inc.c | 5 +++++
> tcg/mips/tcg-target.inc.c | 6 ++++++
> tcg/ppc/tcg-target.inc.c | 22 ++++++++++++++++++++++
> tcg/s390/tcg-target.inc.c | 11 +++++++++++
> tcg/sparc/tcg-target.inc.c | 25 +++++++++++++++++++++++++
> tcg/tcg-op.c | 17 +++++++++++++++++
> tcg/tcg-op.h | 2 ++
> tcg/tcg-opc.h | 2 ++
> tcg/tcg.h | 19 +++++++++++++++++++
> tcg/tci/tcg-target.inc.c | 3 +++
> tci.c | 4 ++++
> 19 files changed, 220 insertions(+), 5 deletions(-)
>
> --
> 2.9.0
>
--
Pranith
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation
2016-07-23 16:08 ` [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
@ 2016-07-23 17:34 ` Paolo Bonzini
2016-07-23 18:00 ` Pranith Kumar
0 siblings, 1 reply; 26+ messages in thread
From: Paolo Bonzini @ 2016-07-23 17:34 UTC (permalink / raw)
To: Pranith Kumar
Cc: qemu-devel, Alex Bennée, Sergey Fedorov, Richard Henderson,
Peter Maydell
> Ping for review!
Hi,
we're on hard freeze so it's normal that maintainers focus on bugfixes
at this time.
Paolo
> On Thu, Jul 14, 2016 at 4:20 PM, Pranith Kumar <bobby.prani@gmail.com> wrote:
> > Hello,
> >
> > The following series adds fence instruction generation support to
> > TCG. Based on feedback to the last series, I added the four
> > combinations of orderings modeled after Sparc membar.
> >
> > This has been tested and confirmed to fix ordering issues on
> > x86/armv7/aarch64 hosts with MTTCG enabled for an ARMv7 guest using
> > KVM unit tests. It has also been tested with litmus tests provided by
> > Alex Bennée.
> >
> > TODO:
> >
> > * The acquire/release order is not utilized yet. Currently we generate
> > SC barriers even for acquire/release barriers. The idea is to write
> > a pass which combines acquire/release barrier with its corresponding
> > load/store operation to generate the load acquire/store release
> > instruction on hosts which have such instruction(aarch64 for
> > now).
> >
> > v4:
> >
> > - Update with comments from v3
> > - Use 'lock orl' instead of mfence on x86. Remove sse2 checks.
> > - Rebase on qemu/master instead of MTTCG
> > - Rename acquire barrier to load-acquire and release to store-release
> > to avoid confusion with prevailing terminology
> >
> > v3:
> >
> > - Create different types of barriers. The barrier tcg opcode now takes
> > an argument to generate the appropriate barrier instruction.
> > - Also add acquire/release/sc ordering flag to argument.
> >
> > v2:
> >
> > - Rebase on Richard's patches generating fences for other
> > architectures.
> >
> > v1:
> >
> > - Initial version: Introduce memory barrier tcg opcode.
> >
> > Pranith Kumar (14):
> > Introduce TCGOpcode for memory barrier
> > tcg/i386: Add support for fence
> > tcg/aarch64: Add support for fence
> > tcg/arm: Add support for fence
> > tcg/ia64: Add support for fence
> > tcg/mips: Add support for fence
> > tcg/ppc: Add support for fence
> > tcg/s390: Add support for fence
> > tcg/sparc: Add support for fence
> > tcg/tci: Add support for fence
> > target-arm: Generate fences in ARMv7 frontend
> > target-alpha: Generate fence op
> > target-aarch64: Generate fences for aarch64
> > target-i386: Generate fences for x86
> >
> > target-alpha/translate.c | 4 ++--
> > target-arm/translate-a64.c | 14 +++++++++++++-
> > target-arm/translate.c | 4 ++--
> > target-i386/translate.c | 8 ++++++++
> > tcg/README | 17 +++++++++++++++++
> > tcg/aarch64/tcg-target.inc.c | 26 ++++++++++++++++++++++++++
> > tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
> > tcg/i386/tcg-target.inc.c | 18 ++++++++++++++++++
> > tcg/ia64/tcg-target.inc.c | 5 +++++
> > tcg/mips/tcg-target.inc.c | 6 ++++++
> > tcg/ppc/tcg-target.inc.c | 22 ++++++++++++++++++++++
> > tcg/s390/tcg-target.inc.c | 11 +++++++++++
> > tcg/sparc/tcg-target.inc.c | 25 +++++++++++++++++++++++++
> > tcg/tcg-op.c | 17 +++++++++++++++++
> > tcg/tcg-op.h | 2 ++
> > tcg/tcg-opc.h | 2 ++
> > tcg/tcg.h | 19 +++++++++++++++++++
> > tcg/tci/tcg-target.inc.c | 3 +++
> > tci.c | 4 ++++
> > 19 files changed, 220 insertions(+), 5 deletions(-)
> >
> > --
> > 2.9.0
> >
>
>
>
> --
> Pranith
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation
2016-07-23 17:34 ` Paolo Bonzini
@ 2016-07-23 18:00 ` Pranith Kumar
0 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-07-23 18:00 UTC (permalink / raw)
To: Paolo Bonzini
Cc: qemu-devel, Alex Bennée, Sergey Fedorov, Richard Henderson,
Peter Maydell
On Sat, Jul 23, 2016 at 1:34 PM, Paolo Bonzini <pbonzini@redhat.com> wrote:
>> Ping for review!
>
> Hi,
>
> we're on hard freeze so it's normal that maintainers focus on bugfixes
> at this time.
>
OK. I will wait for 2 weeks and then ping to remind.
Thanks!
--
Pranith
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (14 preceding siblings ...)
2016-07-23 16:08 ` [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
@ 2016-08-08 14:05 ` Pranith Kumar
2016-09-07 17:33 ` Richard Henderson
16 siblings, 0 replies; 26+ messages in thread
From: Pranith Kumar @ 2016-08-08 14:05 UTC (permalink / raw)
To: Pranith Kumar
Cc: qemu-devel, Alex Bennée, Sergey Fedorov, Richard Henderson,
Paolo Bonzini, Peter Maydell
ping for review!
On Thu, Jul 14, 2016 at 4:20 PM, Pranith Kumar <bobby.prani@gmail.com> wrote:
> Hello,
>
> The following series adds fence instruction generation support to
> TCG. Based on feedback to the last series, I added the four
> combinations of orderings modeled after Sparc membar.
>
> This has been tested and confirmed to fix ordering issues on
> x86/armv7/aarch64 hosts with MTTCG enabled for an ARMv7 guest using
> KVM unit tests. It has also been tested with litmus tests provided by
> Alex Bennée.
>
> TODO:
>
> * The acquire/release order is not utilized yet. Currently we generate
> SC barriers even for acquire/release barriers. The idea is to write
> a pass which combines acquire/release barrier with its corresponding
> load/store operation to generate the load acquire/store release
> instruction on hosts which have such instruction(aarch64 for
> now).
>
> v4:
>
> - Update with comments from v3
> - Use 'lock orl' instead of mfence on x86. Remove sse2 checks.
> - Rebase on qemu/master instead of MTTCG
> - Rename acquire barrier to load-acquire and release to store-release
> to avoid confusion with prevailing terminology
>
> v3:
>
> - Create different types of barriers. The barrier tcg opcode now takes
> an argument to generate the appropriate barrier instruction.
> - Also add acquire/release/sc ordering flag to argument.
>
> v2:
>
> - Rebase on Richard's patches generating fences for other
> architectures.
>
> v1:
>
> - Initial version: Introduce memory barrier tcg opcode.
>
> Pranith Kumar (14):
> Introduce TCGOpcode for memory barrier
> tcg/i386: Add support for fence
> tcg/aarch64: Add support for fence
> tcg/arm: Add support for fence
> tcg/ia64: Add support for fence
> tcg/mips: Add support for fence
> tcg/ppc: Add support for fence
> tcg/s390: Add support for fence
> tcg/sparc: Add support for fence
> tcg/tci: Add support for fence
> target-arm: Generate fences in ARMv7 frontend
> target-alpha: Generate fence op
> target-aarch64: Generate fences for aarch64
> target-i386: Generate fences for x86
>
> target-alpha/translate.c | 4 ++--
> target-arm/translate-a64.c | 14 +++++++++++++-
> target-arm/translate.c | 4 ++--
> target-i386/translate.c | 8 ++++++++
> tcg/README | 17 +++++++++++++++++
> tcg/aarch64/tcg-target.inc.c | 26 ++++++++++++++++++++++++++
> tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
> tcg/i386/tcg-target.inc.c | 18 ++++++++++++++++++
> tcg/ia64/tcg-target.inc.c | 5 +++++
> tcg/mips/tcg-target.inc.c | 6 ++++++
> tcg/ppc/tcg-target.inc.c | 22 ++++++++++++++++++++++
> tcg/s390/tcg-target.inc.c | 11 +++++++++++
> tcg/sparc/tcg-target.inc.c | 25 +++++++++++++++++++++++++
> tcg/tcg-op.c | 17 +++++++++++++++++
> tcg/tcg-op.h | 2 ++
> tcg/tcg-opc.h | 2 ++
> tcg/tcg.h | 19 +++++++++++++++++++
> tcg/tci/tcg-target.inc.c | 3 +++
> tci.c | 4 ++++
> 19 files changed, 220 insertions(+), 5 deletions(-)
>
> --
> 2.9.0
>
--
Pranith
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
` (15 preceding siblings ...)
2016-08-08 14:05 ` Pranith Kumar
@ 2016-09-07 17:33 ` Richard Henderson
16 siblings, 0 replies; 26+ messages in thread
From: Richard Henderson @ 2016-09-07 17:33 UTC (permalink / raw)
To: Pranith Kumar
Cc: peter.maydell, qemu-devel, pbonzini, serge.fdrv, alex.bennee
On 07/14/2016 01:20 PM, Pranith Kumar wrote:
> Pranith Kumar (14):
> Introduce TCGOpcode for memory barrier
> tcg/i386: Add support for fence
> tcg/aarch64: Add support for fence
> tcg/arm: Add support for fence
> tcg/ia64: Add support for fence
> tcg/mips: Add support for fence
> tcg/ppc: Add support for fence
> tcg/s390: Add support for fence
> tcg/sparc: Add support for fence
> tcg/tci: Add support for fence
> target-arm: Generate fences in ARMv7 frontend
> target-alpha: Generate fence op
> target-aarch64: Generate fences for aarch64
> target-i386: Generate fences for x86
>
> target-alpha/translate.c | 4 ++--
> target-arm/translate-a64.c | 14 +++++++++++++-
> target-arm/translate.c | 4 ++--
> target-i386/translate.c | 8 ++++++++
> tcg/README | 17 +++++++++++++++++
> tcg/aarch64/tcg-target.inc.c | 26 ++++++++++++++++++++++++++
> tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
> tcg/i386/tcg-target.inc.c | 18 ++++++++++++++++++
> tcg/ia64/tcg-target.inc.c | 5 +++++
> tcg/mips/tcg-target.inc.c | 6 ++++++
> tcg/ppc/tcg-target.inc.c | 22 ++++++++++++++++++++++
> tcg/s390/tcg-target.inc.c | 11 +++++++++++
> tcg/sparc/tcg-target.inc.c | 25 +++++++++++++++++++++++++
> tcg/tcg-op.c | 17 +++++++++++++++++
> tcg/tcg-op.h | 2 ++
> tcg/tcg-opc.h | 2 ++
> tcg/tcg.h | 19 +++++++++++++++++++
> tcg/tci/tcg-target.inc.c | 3 +++
> tci.c | 4 ++++
> 19 files changed, 220 insertions(+), 5 deletions(-)
Queued.
r~
^ permalink raw reply [flat|nested] 26+ messages in thread