* [PATCH 00/12] tests/tcg: Multiarch tests for riscv64
@ 2026-08-27 5:09 Joel Stanley
2026-08-27 5:09 ` [PATCH 01/12] tests/tcg/riscv64: Include stdint.h in semicall.h Joel Stanley
` (12 more replies)
0 siblings, 13 replies; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
When testing Richard's TCG RVV changes I went down the rabbit hole that
is tests/tcg/multiarch. Out the other side is this series, which enables
the multiarch and record/replay tests for riscv64, and fixes the
memory-sve aarch64 test while adding a memory-rvv test for riscv64.
The first half of the series performs some housekeeping on the semihost
tests and the softmmu makefile in tests/tcg/riscv64. The second half
enables the multiarch tests, and looks at the vectorised memory.c test.
The final patch adds a very coarse check for vectorisation by grepping
objdump for vector loads and stores. Although it's not the neatest, it
would have caught the regression in memory-sve, so it is worthwhile
having in the tree.
Joel Stanley (12):
tests/tcg/riscv64: Include stdint.h in semicall.h
tests/tcg/riscv64: Clean up semicall.h inline asm
tests/tcg/riscv64: Boot semihost tests with -bios none -kernel
tests/tcg/riscv64: Update semihosting linker script
tests/tcg/riscv64: Rework rules for semihost tests
tests/tcg/riscv64: Enable multiarch system tests
tests/tcg/riscv64: Enable memory record and replay test
tests/tcg/aarch64: Don't leak memory-sve CFLAGS
tests/tcg/multiarch: Fix vectorisation of memory test
tests/tcg/riscv64: Enable vectorised memory test
configure: Provide OBJDUMP to the tcg tests
tests/tcg: Check vector memory tests contain vector ops
configure | 11 ++
tests/tcg/riscv64/semicall.h | 12 +-
tests/tcg/multiarch/system/memory.c | 113 ++++++++----------
tests/tcg/riscv64/system.c | 30 +++++
tests/tcg/Makefile.target | 10 +-
tests/tcg/aarch64/Makefile.softmmu-target | 3 +-
tests/tcg/riscv64/Makefile.softmmu-target | 134 +++++++++++++---------
tests/tcg/riscv64/boot.S | 23 ++++
tests/tcg/riscv64/semihost.ld | 47 ++++++--
9 files changed, 251 insertions(+), 132 deletions(-)
create mode 100644 tests/tcg/riscv64/system.c
create mode 100644 tests/tcg/riscv64/boot.S
--
2.47.3
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/12] tests/tcg/riscv64: Include stdint.h in semicall.h
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:07 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 02/12] tests/tcg/riscv64: Clean up semicall.h inline asm Joel Stanley
` (11 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
semicall.h uses uintptr_t.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/riscv64/semicall.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/tcg/riscv64/semicall.h b/tests/tcg/riscv64/semicall.h
index 11d0650cb06c..2fdd322af91f 100644
--- a/tests/tcg/riscv64/semicall.h
+++ b/tests/tcg/riscv64/semicall.h
@@ -6,6 +6,7 @@
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
+#include <stdint.h>
uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
{
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 02/12] tests/tcg/riscv64: Clean up semicall.h inline asm
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
2026-08-27 5:09 ` [PATCH 01/12] tests/tcg/riscv64: Include stdint.h in semicall.h Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:09 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 03/12] tests/tcg/riscv64: Boot semihost tests with -bios none -kernel Joel Stanley
` (10 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Make __semi_call static inline so semicall.h can be included more
than once in a program.
Use .option push/pop rather than leaving norvc set for the rest of
the file.
Set the constraints for the asm block.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/riscv64/semicall.h | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/tests/tcg/riscv64/semicall.h b/tests/tcg/riscv64/semicall.h
index 2fdd322af91f..34e87332de44 100644
--- a/tests/tcg/riscv64/semicall.h
+++ b/tests/tcg/riscv64/semicall.h
@@ -8,16 +8,19 @@
*/
#include <stdint.h>
-uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
+static inline uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
{
register uintptr_t t asm("a0") = type;
register uintptr_t a0 asm("a1") = arg0;
- asm(".option norvc\n\t"
+ asm(".option push\n\t"
+ ".option norvc\n\t"
".balign 16\n\t"
"slli zero, zero, 0x1f\n\t"
"ebreak\n\t"
"srai zero, zero, 0x7\n\t"
- : "=r" (t)
- : "r" (t), "r" (a0));
+ ".option pop\n\t"
+ : "+r" (t) /* Output: read as input, written as return value */
+ : "r" (a0) /* Input: arg0 */
+ : "memory"); /* Clobber: may modify memory, depending on type */
return t;
}
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 03/12] tests/tcg/riscv64: Boot semihost tests with -bios none -kernel
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
2026-08-27 5:09 ` [PATCH 01/12] tests/tcg/riscv64: Include stdint.h in semicall.h Joel Stanley
2026-08-27 5:09 ` [PATCH 02/12] tests/tcg/riscv64: Clean up semicall.h inline asm Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:10 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 04/12] tests/tcg/riscv64: Update semihosting linker script Joel Stanley
` (9 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Loading tests should conflict with the opensbi ROM, however the generic
loader writes through the CPU address space which bypasses the ROM
overlap check.
Instead of depending on this happy accident, set -bios none to skip
loading opensbi. This frees up the address space to load the test with
-kernel, required by a future change that uses the same rules to run the
multiarch tests for riscv64.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/riscv64/Makefile.softmmu-target | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
index 6a219c306c43..562ac9b0e0fb 100644
--- a/tests/tcg/riscv64/Makefile.softmmu-target
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
@@ -14,36 +14,36 @@ CFLAGS += -g -Og
%: %.o $(LINK_SCRIPT)
$(LD) $(LDFLAGS) $< -o $@
-QEMU_OPTS += -M virt -display none -semihosting -device loader,file=
+QEMU_OPTS += -M virt -display none -bios none -semihosting -kernel
EXTRA_RUNS += run-issue1060
run-issue1060: issue1060
- $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
EXTRA_RUNS += run-test-mepc-masking
run-test-mepc-masking: test-mepc-masking
- $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
EXTRA_RUNS += run-test-minstret-ecall
run-test-minstret-ecall: test-minstret-ecall
- $(call run-test, $<, $(QEMU) -icount shift=1 $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) -icount shift=1 $(QEMU_OPTS) $<)
EXTRA_RUNS += run-plugin-doubletrap
run-plugin-doubletrap: doubletrap
$(call run-test, $<, \
$(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
- $(QEMU_OPTS)$<)
+ $(QEMU_OPTS) $<)
EXTRA_RUNS += run-plugin-interruptedmemory
run-plugin-interruptedmemory: interruptedmemory
$(call run-test, $<, \
$(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
- $(QEMU_OPTS)$<)
+ $(QEMU_OPTS) $<)
EXTRA_RUNS += run-test-crc32
comma:= ,
run-test-crc32: test-crc32
- $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true $(QEMU_OPTS) $<)
# Zicclsm: misaligned load/store support. Assemble one source twice: the
# default build expects every misaligned access to succeed (zicclsm=true),
@@ -61,11 +61,11 @@ test-zicclsm-off: test-zicclsm.S $(LINK_SCRIPT)
EXTRA_RUNS += run-test-zicclsm
run-test-zicclsm: test-zicclsm
- $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=true $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=true $(QEMU_OPTS) $<)
EXTRA_RUNS += run-test-zicclsm-off
run-test-zicclsm-off: test-zicclsm-off
- $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=false $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=false $(QEMU_OPTS) $<)
EXTRA_RUNS += run-test-misa-w
run-test-misa-w: test-misa-w
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 04/12] tests/tcg/riscv64: Update semihosting linker script
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
` (2 preceding siblings ...)
2026-08-27 5:09 ` [PATCH 03/12] tests/tcg/riscv64: Boot semihost tests with -bios none -kernel Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:14 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 05/12] tests/tcg/riscv64: Rework rules for semihost tests Joel Stanley
` (8 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Keep the tests at the start of RAM but bound them with a MEMORY region,
and use this to define __stack_top, which the multiarch system test boot
code will use.
Add more sections generated by the test binaries so they are placed
explicitly.
Split text and data into separate rx/rw regions, instead of one rwx
region to avoid binutils warnings.
A -kernel boot jumps to the lowest loaded address rather than the ELF
entry point, so _start must be first in .text. Use a .text._start input
section to make that explicit.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/riscv64/semihost.ld | 47 +++++++++++++++++++++++++++--------
1 file changed, 36 insertions(+), 11 deletions(-)
diff --git a/tests/tcg/riscv64/semihost.ld b/tests/tcg/riscv64/semihost.ld
index a59cc56b289a..eff3701e4a19 100644
--- a/tests/tcg/riscv64/semihost.ld
+++ b/tests/tcg/riscv64/semihost.ld
@@ -1,21 +1,46 @@
+/*
+ * Linker script for the RISC-V system tests
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
ENTRY(_start)
+MEMORY
+{
+ /*
+ * Virt machine, RAM starts at 2GB
+ *
+ * Separate sections for executable and writable data to avoid linker
+ * warnings.
+ */
+ TXT (rx) : ORIGIN = 0x80000000, LENGTH = 2M
+ DAT (rw) : ORIGIN = 0x80000000 + 2M, LENGTH = 2M
+}
+
SECTIONS
{
- /* virt machine, RAM starts at 2gb */
- . = 0x80000000;
.text : {
+ *(.text._start)
*(.text)
- }
+ } > TXT
+
.rodata : {
- *(.rodata)
- }
- /* align r/w section to next 2mb */
- . = ALIGN(1 << 21);
+ *(.rodata .rodata.*)
+ *(.eh_frame)
+ } > TXT
+
+ .got : {
+ *(.got .got.plt)
+ } > DAT
+
.data : {
- *(.data)
- }
+ *(.data .data.* .sdata .sdata.*)
+ } > DAT
+
.bss : {
- *(.bss)
- }
+ *(.bss .bss.* .sbss .sbss.*)
+ } > DAT
+
+ /* Stack grows down from the end of the data region */
+ __stack_top = ORIGIN(DAT) + LENGTH(DAT);
}
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 05/12] tests/tcg/riscv64: Rework rules for semihost tests
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
` (3 preceding siblings ...)
2026-08-27 5:09 ` [PATCH 04/12] tests/tcg/riscv64: Update semihosting linker script Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:17 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 06/12] tests/tcg/riscv64: Enable multiarch system tests Joel Stanley
` (7 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Rework the makefile so the semihost tests can share run rules, with
individual tests overwriting QEMU_CPU or providing more options via
QEMU_EXTRA.
The program output now comes from the test framework's output chardev
instead of stdout, but there is no functional change as none of the
tests use semihosting putc.
Add quiet-command to the compile and link rules so builds print
CC/LD lines like the run rules.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/riscv64/Makefile.softmmu-target | 94 +++++++++++------------
1 file changed, 47 insertions(+), 47 deletions(-)
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
index 562ac9b0e0fb..f2850a194084 100644
--- a/tests/tcg/riscv64/Makefile.softmmu-target
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
@@ -9,67 +9,67 @@ LINK_SCRIPT = $(TEST_SRC)/semihost.ld
LDFLAGS = -T $(LINK_SCRIPT)
CFLAGS += -g -Og
+# Used by riscv64 tcg tests and shared 'multiarch' tests
+QEMU_CPU = rv64
+QEMU_BASE_MACHINE = -M virt -cpu $(QEMU_CPU) -display none -bios none
+QEMU_BASE_ARGS = -semihosting-config enable=on,chardev=output
+QEMU_OPTS += $(QEMU_BASE_MACHINE) $(QEMU_EXTRA) $(QEMU_BASE_ARGS) -kernel
+
+# These tests provide _start and use semihosting directly.
+# -kernel entry point is the lowest loaded address, not the ELF entry
+# point, so _start must remain first in .text.
+RISCV64_TESTS = issue1060 test-mepc-masking test-minstret-ecall \
+ doubletrap interruptedmemory test-crc32 \
+ test-zicclsm test-zicclsm-off test-misa-w
+
+# -Wl,--noexecstack to avoid linker warnings for .S files
%.o: %.S
- $(CC) $(CFLAGS) $< -Wa,--noexecstack -c -o $@
-%: %.o $(LINK_SCRIPT)
- $(LD) $(LDFLAGS) $< -o $@
+ $(call quiet-command, \
+ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -Wa$(COMMA)--noexecstack -c -o $@, CC, $@)
-QEMU_OPTS += -M virt -display none -bios none -semihosting -kernel
+%.o: %.c
+ $(call quiet-command, \
+ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -c -o $@, CC, $@)
-EXTRA_RUNS += run-issue1060
-run-issue1060: issue1060
- $(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
+$(RISCV64_TESTS): %: %.o $(LINK_SCRIPT)
+ $(call quiet-command, $(LD) -T $(LINK_SCRIPT) $< -o $@, LD, $@)
-EXTRA_RUNS += run-test-mepc-masking
-run-test-mepc-masking: test-mepc-masking
- $(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
+TESTS += issue1060 test-mepc-masking test-minstret-ecall test-crc32 \
+ test-misa-w test-zicclsm test-zicclsm-off
-EXTRA_RUNS += run-test-minstret-ecall
-run-test-minstret-ecall: test-minstret-ecall
- $(call run-test, $<, $(QEMU) -icount shift=1 $(QEMU_OPTS) $<)
+# Tests can provide a custom kernel command line here
+run-test-minstret-ecall: QEMU_EXTRA = -icount shift=1
+run-test-crc32: QEMU_CPU = rv64,xlrbr=true
+run-test-misa-w: QEMU_CPU = rv64,x-misa-w=true,c=true,v=true
+run-test-zicclsm: QEMU_CPU = rv64,v=true,zfh=true,zicclsm=true
+run-test-zicclsm-off: QEMU_CPU = rv64,v=true,zfh=true,zicclsm=false
+
+# Zicclsm: misaligned load/store support. Assemble one source twice: the
+# default build expects every misaligned access to succeed (zicclsm=true),
+# the -DZICCLSM_DISABLED build expects every one to trap (zicclsm=false).
+test-zicclsm.o test-zicclsm-off.o: CFLAGS += -march=rv64gcv_zfh
+test-zicclsm-off.o: CFLAGS += -DZICCLSM_DISABLED
+test-zicclsm-off.o: test-zicclsm.S
+ $(call quiet-command, \
+ $(CC) $(CFLAGS) $< -Wa$(COMMA)--noexecstack -c -o $@, CC, $@)
EXTRA_RUNS += run-plugin-doubletrap
run-plugin-doubletrap: doubletrap
$(call run-test, $<, \
- $(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
- $(QEMU_OPTS) $<)
+ $(QEMU) -monitor none -display none \
+ -chardev file$(COMMA)path=$<.out$(COMMA)id=output \
+ -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
+ $(QEMU_OPTS) $<)
EXTRA_RUNS += run-plugin-interruptedmemory
run-plugin-interruptedmemory: interruptedmemory
$(call run-test, $<, \
- $(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
- $(QEMU_OPTS) $<)
-
-EXTRA_RUNS += run-test-crc32
-comma:= ,
-run-test-crc32: test-crc32
- $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true $(QEMU_OPTS) $<)
-
-# Zicclsm: misaligned load/store support. Assemble one source twice: the
-# default build expects every misaligned access to succeed (zicclsm=true),
-# the -DZICCLSM_DISABLED build expects every one to trap (zicclsm=false).
-ZICCLSM_MARCH = -march=rv64gcv_zfh
-CLEANFILES += test-zicclsm test-zicclsm-off
-
-test-zicclsm: test-zicclsm.S $(LINK_SCRIPT)
- $(CC) $(CFLAGS) $(ZICCLSM_MARCH) $< -Wa,--noexecstack -c -o test-zicclsm.o
- $(LD) $(LDFLAGS) test-zicclsm.o -o $@
-
-test-zicclsm-off: test-zicclsm.S $(LINK_SCRIPT)
- $(CC) $(CFLAGS) $(ZICCLSM_MARCH) -DZICCLSM_DISABLED $< -Wa,--noexecstack -c -o test-zicclsm-off.o
- $(LD) $(LDFLAGS) test-zicclsm-off.o -o $@
-
-EXTRA_RUNS += run-test-zicclsm
-run-test-zicclsm: test-zicclsm
- $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=true $(QEMU_OPTS) $<)
-
-EXTRA_RUNS += run-test-zicclsm-off
-run-test-zicclsm-off: test-zicclsm-off
- $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=false $(QEMU_OPTS) $<)
+ $(QEMU) -monitor none -display none \
+ -chardev file$(COMMA)path=$<.out$(COMMA)id=output \
+ -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
+ $(QEMU_OPTS) $<)
-EXTRA_RUNS += run-test-misa-w
-run-test-misa-w: test-misa-w
- $(call run-test, $<, $(QEMU) -cpu rv64$(comma)x-misa-w=true$(comma)c=true$(comma)v=true $(QEMU_OPTS)$<)
+CLEANFILES += interruptedmemory doubletrap
# We don't currently support the multiarch system tests
undefine MULTIARCH_TESTS
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 06/12] tests/tcg/riscv64: Enable multiarch system tests
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
` (4 preceding siblings ...)
2026-08-27 5:09 ` [PATCH 05/12] tests/tcg/riscv64: Rework rules for semihost tests Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:20 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 07/12] tests/tcg/riscv64: Enable memory record and replay test Joel Stanley
` (6 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Add the boot code and semihosting helpers needed to run the multiarch
system tests on riscv64, and add riscv64 to MULTIARCH_SOFTMMU_TARGETS.
The aarch64 makefile was used as a guide for the make rules.
boot.S does not clear bss as the libmem plugin test would count the
stores and fail with a mismatch. Instead the BSS is described as
PT_LOAD, so the QEMU ELF loader fills the region with zero, the same as
aarch64 and loongarch64.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/riscv64/system.c | 30 +++++++++++++++++
tests/tcg/Makefile.target | 2 +-
tests/tcg/riscv64/Makefile.softmmu-target | 40 ++++++++++++-----------
tests/tcg/riscv64/boot.S | 23 +++++++++++++
4 files changed, 75 insertions(+), 20 deletions(-)
create mode 100644 tests/tcg/riscv64/system.c
create mode 100644 tests/tcg/riscv64/boot.S
diff --git a/tests/tcg/riscv64/system.c b/tests/tcg/riscv64/system.c
new file mode 100644
index 000000000000..08196a540f96
--- /dev/null
+++ b/tests/tcg/riscv64/system.c
@@ -0,0 +1,30 @@
+/*
+ * RISC-V semihosting support for multiarch test suite
+ *
+ * Copyright 2026 Tenstorrent USA Inc
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "semicall.h"
+
+#define SYS_WRITEC 0x3
+#define SYS_EXIT 0x18
+
+#define ADP_Stopped_ApplicationExit 0x20026
+
+void __sys_outc(char c)
+{
+ __semi_call(SYS_WRITEC, (uintptr_t)&c);
+}
+
+void _exit(int code)
+{
+ const uintptr_t args[2] = { ADP_Stopped_ApplicationExit, (uintptr_t)code };
+
+ __semi_call(SYS_EXIT, (uintptr_t)args);
+
+ /* Hang if QEMU fails to exit */
+ while (1) {
+ asm volatile("wfi");
+ }
+}
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index 1b83824ff4e7..d4dd0fec650d 100644
--- a/tests/tcg/Makefile.target
+++ b/tests/tcg/Makefile.target
@@ -129,7 +129,7 @@ else
EXTRA_CFLAGS += -ffreestanding -fno-stack-protector
# We skip the multiarch tests if the target hasn't provided a boot.S
-MULTIARCH_SOFTMMU_TARGETS = i386 alpha aarch64 arm loongarch64 s390x x86_64
+MULTIARCH_SOFTMMU_TARGETS = i386 alpha aarch64 arm loongarch64 s390x x86_64 riscv64
ifneq ($(filter $(TARGET_NAME),$(MULTIARCH_SOFTMMU_TARGETS)),)
-include $(SRC_PATH)/tests/tcg/minilib/Makefile.target
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
index f2850a194084..82e8fe2664b0 100644
--- a/tests/tcg/riscv64/Makefile.softmmu-target
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
@@ -5,9 +5,11 @@
TEST_SRC = $(SRC_PATH)/tests/tcg/riscv64
VPATH += $(TEST_SRC)
+CRT_OBJS = boot.o system.o
+
LINK_SCRIPT = $(TEST_SRC)/semihost.ld
-LDFLAGS = -T $(LINK_SCRIPT)
-CFLAGS += -g -Og
+LDFLAGS = -Wl,-T$(LINK_SCRIPT) -static -nostdlib $(MINILIB_OBJS) -lgcc
+CFLAGS += -g -Og $(MINILIB_INC)
# Used by riscv64 tcg tests and shared 'multiarch' tests
QEMU_CPU = rv64
@@ -53,23 +55,23 @@ test-zicclsm-off.o: test-zicclsm.S
$(call quiet-command, \
$(CC) $(CFLAGS) $< -Wa$(COMMA)--noexecstack -c -o $@, CC, $@)
-EXTRA_RUNS += run-plugin-doubletrap
-run-plugin-doubletrap: doubletrap
- $(call run-test, $<, \
- $(QEMU) -monitor none -display none \
- -chardev file$(COMMA)path=$<.out$(COMMA)id=output \
- -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
- $(QEMU_OPTS) $<)
-
-EXTRA_RUNS += run-plugin-interruptedmemory
-run-plugin-interruptedmemory: interruptedmemory
- $(call run-test, $<, \
- $(QEMU) -monitor none -display none \
- -chardev file$(COMMA)path=$<.out$(COMMA)id=output \
- -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
- $(QEMU_OPTS) $<)
+ifeq ($(CONFIG_PLUGIN),y)
+EXTRA_RUNS_WITH_PLUGIN += run-plugin-doubletrap-with-libdiscons.so \
+ run-plugin-interruptedmemory-with-libdiscons.so
+endif
CLEANFILES += interruptedmemory doubletrap
-# We don't currently support the multiarch system tests
-undefine MULTIARCH_TESTS
+# Multiarch tests
+TESTS += $(MULTIARCH_TESTS)
+EXTRA_RUNS += $(MULTIARCH_RUNS)
+
+.PRECIOUS: $(CRT_OBJS)
+
+# Build and link the multiarch tests
+%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
+ $(call quiet-command, \
+ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(CRT_OBJS), CC, $@)
+
+# Default is zicclsm=true, so misaligned accesses must work
+memory: private CFLAGS += -DCHECK_UNALIGNED=1
diff --git a/tests/tcg/riscv64/boot.S b/tests/tcg/riscv64/boot.S
new file mode 100644
index 000000000000..b403549345a1
--- /dev/null
+++ b/tests/tcg/riscv64/boot.S
@@ -0,0 +1,23 @@
+/*
+ * RISC-V boot code for multiarch test suite
+ *
+ * Copyright 2026 Tenstorrent USA Inc
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#define MSTATUS_VS 0x00000600
+#define MSTATUS_FS 0x00006000
+
+.section .text._start
+ .global _start
+ .type _start, @function
+_start:
+ /* Enable FPU and vector unit */
+ li t0, (MSTATUS_FS | MSTATUS_VS)
+ csrs mstatus, t0
+ la sp, __stack_top
+ call main
+
+exit:
+ /* exit with main()'s return code */
+ call _exit
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 07/12] tests/tcg/riscv64: Enable memory record and replay test
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
` (5 preceding siblings ...)
2026-08-27 5:09 ` [PATCH 06/12] tests/tcg/riscv64: Enable multiarch system tests Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:21 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS Joel Stanley
` (5 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Run the memory test under icount record and replay, copied from aarch64.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/riscv64/Makefile.softmmu-target | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
index 82e8fe2664b0..3f2a8ed16142 100644
--- a/tests/tcg/riscv64/Makefile.softmmu-target
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
@@ -75,3 +75,22 @@ EXTRA_RUNS += $(MULTIARCH_RUNS)
# Default is zicclsm=true, so misaligned accesses must work
memory: private CFLAGS += -DCHECK_UNALIGNED=1
+
+# Simple Record/Replay Test
+.PHONY: memory-record
+run-memory-record: memory-record memory
+ $(call run-test, $<, \
+ $(QEMU) -monitor none \
+ -chardev file$(COMMA)path=$<.out$(COMMA)id=output \
+ -icount shift=5$(COMMA)rr=record$(COMMA)rrfile=record.bin \
+ $(QEMU_OPTS) memory)
+
+.PHONY: memory-replay
+run-memory-replay: memory-replay run-memory-record
+ $(call run-test, $<, \
+ $(QEMU) -monitor none \
+ -chardev file$(COMMA)path=$<.out$(COMMA)id=output \
+ -icount shift=5$(COMMA)rr=replay$(COMMA)rrfile=record.bin \
+ $(QEMU_OPTS) memory)
+
+EXTRA_RUNS += run-memory-replay
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
` (6 preceding siblings ...)
2026-08-27 5:09 ` [PATCH 07/12] tests/tcg/riscv64: Enable memory record and replay test Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-09-22 5:39 ` Alistair Francis
2026-09-22 7:17 ` Alex Bennée
2026-08-27 5:09 ` [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test Joel Stanley
` (4 subsequent siblings)
12 siblings, 2 replies; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
The CFLAGS are added to prerequisites, so if memory-sve causes a build
of printf.o and boot.o, they will be compiled with -march=armv8.1-a+sve
-O3, and the executables that link printf.o and boot.o after that will
also get SVE instructions.
https://www.gnu.org/software/make/manual/html_node/Suppressing-Inheritance.html
By marking the rule 'private' printf.o and boot.o won't be built with
SVE, which avoids SVE for other binaries, and is okay for the memory-sve
case.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/aarch64/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target
index 3f30be6c5d63..196a2afa50ee 100644
--- a/tests/tcg/aarch64/Makefile.softmmu-target
+++ b/tests/tcg/aarch64/Makefile.softmmu-target
@@ -51,7 +51,7 @@ memory: CFLAGS+=-DCHECK_UNALIGNED=1
memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o
-memory-sve: CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve -O3
+memory-sve: private CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve -O3
gpc-test: gpc-test.c $(LINK_SCRIPT) vector_log_boot.o $(MINILIB_OBJS)
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) vector_log_boot.o
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
` (7 preceding siblings ...)
2026-08-27 5:09 ` [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:24 ` Alistair Francis
2026-09-01 10:06 ` Alex Bennée
2026-08-27 5:09 ` [PATCH 10/12] tests/tcg/riscv64: Enable vectorised " Joel Stanley
` (3 subsequent siblings)
12 siblings, 2 replies; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Compilers are not able to vectorise the load and store loops. Building
with -fopt-info-vec-missed with gcc 16.1:
missed: statement clobbers memory: ml_printf (".");
This can be fixed by doing the printf after the loops.
Also, autovectorisation doesn't like more than one if statement in the
loop:
missed: not vectorized: unsupported control flow in loop.
By combining them into ternary statements and one if, the loops are able
to be vectorised with both loads and stores.
The trade off is the dots are gone, and the tests no longer report fine
grained miscompares. A failure does report the number of bad elements in
a failing test loop.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/multiarch/system/memory.c | 113 ++++++++++++----------------
1 file changed, 50 insertions(+), 63 deletions(-)
diff --git a/tests/tcg/multiarch/system/memory.c b/tests/tcg/multiarch/system/memory.c
index 7508f6b916d0..6eeb738343ab 100644
--- a/tests/tcg/multiarch/system/memory.c
+++ b/tests/tcg/multiarch/system/memory.c
@@ -42,9 +42,6 @@ static void pdot(int count, bool write)
} else {
test_read_count++;
}
- if (count % 128 == 0) {
- ml_printf(".");
- }
}
/*
@@ -77,7 +74,6 @@ static void init_test_data_u8(int unused_offset)
*ptr++ = BYTE_NEXT(count);
pdot(i, true);
}
-
ml_printf("done %d @ %p\n", i, ptr);
}
@@ -127,7 +123,6 @@ static void reset_start_data(int offset)
*ptr++ = 0;
pdot(i, true);
}
-
ml_printf("done %d @ %p\n", i, ptr);
}
@@ -203,7 +198,7 @@ static void init_test_data_u64(int offset)
static bool read_test_data_u16(int offset)
{
uint16_t word, *ptr = (uint16_t *)&test_data[offset];
- int i;
+ int i, bad = 0;
const int max = (TEST_SIZE - offset) / sizeof(word);
ml_printf("Reading u16 from %#lx (offset %d):", ptr, offset);
@@ -214,12 +209,13 @@ static bool read_test_data_u16(int offset)
high = (word >> 8) & 0xff;
low = word & 0xff;
if (high < low && high != 0) {
- ml_printf("Error %d < %d\n", high, low);
- return false;
- } else {
- pdot(i, false);
+ bad++;
}
-
+ }
+ test_read_count += max;
+ if (bad) {
+ ml_printf("Error: %d bad u16 words\n", bad);
+ return false;
}
ml_printf("done %d @ %p\n", i, ptr);
return true;
@@ -228,7 +224,7 @@ static bool read_test_data_u16(int offset)
static bool read_test_data_u32(int offset)
{
uint32_t word, *ptr = (uint32_t *)&test_data[offset];
- int i;
+ int i, bad = 0;
const int max = (TEST_SIZE - offset) / sizeof(word);
ml_printf("Reading u32 from %#lx (offset %d):", ptr, offset);
@@ -247,21 +243,18 @@ static bool read_test_data_u32(int offset)
zeros += (b2 == 0 ? 1 : 0);
zeros += (b3 == 0 ? 1 : 0);
zeros += (b4 == 0 ? 1 : 0);
- if (zeros > 1) {
- ml_printf("Error @ %p, more zeros than expected: %d, %d, %d, %d",
- ptr - 1, b1, b2, b3, b4);
- return false;
- }
-
- if ((b1 < b2 && b1 != 0) ||
+ if (zeros > 1 ||
+ (b1 < b2 && b1 != 0) ||
(b2 < b3 && b2 != 0) ||
(b3 < b4 && b3 != 0)) {
- ml_printf("Error %d, %d, %d, %d", b1, b2, b3, b4);
- return false;
- } else {
- pdot(i, false);
+ bad++;
}
}
+ test_read_count += max;
+ if (bad) {
+ ml_printf("Error: %d bad u32 words\n", bad);
+ return false;
+ }
ml_printf("done %d @ %p\n", i, ptr);
return true;
}
@@ -270,7 +263,7 @@ static bool read_test_data_u32(int offset)
static bool read_test_data_u64(int offset)
{
uint64_t word, *ptr = (uint64_t *)&test_data[offset];
- int i;
+ int i, bad = 0;
const int max = (TEST_SIZE - offset) / sizeof(word);
ml_printf("Reading u64 from %#lx (offset %d):", ptr, offset);
@@ -297,26 +290,22 @@ static bool read_test_data_u64(int offset)
zeros += (b6 == 0 ? 1 : 0);
zeros += (b7 == 0 ? 1 : 0);
zeros += (b8 == 0 ? 1 : 0);
- if (zeros > 1) {
- ml_printf("Error @ %p, more zeros than expected: %d, %d, %d, %d, %d, %d, %d, %d",
- ptr - 1, b1, b2, b3, b4, b5, b6, b7, b8);
- return false;
- }
-
- if ((b1 < b2 && b1 != 0) ||
+ if (zeros > 1 ||
+ (b1 < b2 && b1 != 0) ||
(b2 < b3 && b2 != 0) ||
(b3 < b4 && b3 != 0) ||
(b4 < b5 && b4 != 0) ||
(b5 < b6 && b5 != 0) ||
(b6 < b7 && b6 != 0) ||
(b7 < b8 && b7 != 0)) {
- ml_printf("Error %d, %d, %d, %d, %d, %d, %d, %d",
- b1, b2, b3, b4, b5, b6, b7, b8);
- return false;
- } else {
- pdot(i, false);
+ bad++;
}
}
+ test_read_count += max;
+ if (bad) {
+ ml_printf("Error: %d bad u64 words\n", bad);
+ return false;
+ }
ml_printf("done %d @ %p\n", i, ptr);
return true;
}
@@ -374,28 +363,26 @@ static bool do_unsigned_test(init_ufn fn)
static bool read_test_data_s8(int offset, bool neg_first)
{
int8_t *ptr = (int8_t *)&test_data[offset];
- int i;
+ int i, bad = 0;
const int max = (TEST_SIZE - offset) / 2;
ml_printf("Reading s8 pairs from %#lx (offset %d):", ptr, offset);
for (i = 0; i < max; i++) {
int16_t first, second;
- bool ok;
first = *ptr++;
second = *ptr++;
- if (neg_first && first < 0 && second > 0) {
- pdot(i, false);
- pdot(i, false);
- } else if (!neg_first && first > 0 && second < 0) {
- pdot(i, false);
- pdot(i, false);
- } else {
- ml_printf("Error %d %c %d\n", first, neg_first ? '<' : '>', second);
- return false;
+ if (!(neg_first ? (first < 0 && second > 0)
+ : (first > 0 && second < 0))) {
+ bad++;
}
}
+ test_read_count += max * 2;
+ if (bad) {
+ ml_printf("Error: %d bad s8 pairs\n", bad);
+ return false;
+ }
ml_printf("done %d @ %p\n", i * 2, ptr);
return true;
}
@@ -403,7 +390,7 @@ static bool read_test_data_s8(int offset, bool neg_first)
static bool read_test_data_s16(int offset, bool neg_first)
{
int16_t *ptr = (int16_t *)&test_data[offset];
- int i;
+ int i, bad = 0;
const int max = (TEST_SIZE - offset) / (sizeof(*ptr));
ml_printf("Reading s16 from %#lx (offset %d, %s):", ptr,
@@ -420,15 +407,15 @@ static bool read_test_data_s16(int offset, bool neg_first)
for (i = 0; i < max; i++) {
int32_t data = *ptr++;
- if (neg_first && data < 0) {
- pdot(i, false);
- } else if (!neg_first && data > 0) {
- pdot(i, false);
- } else {
- ml_printf("Error %d %c 0\n", data, neg_first ? '<' : '>');
- return false;
+ if (!(neg_first ? data < 0 : data > 0)) {
+ bad++;
}
}
+ test_read_count += max;
+ if (bad) {
+ ml_printf("Error: %d bad s16 words\n", bad);
+ return false;
+ }
ml_printf("done %d @ %p\n", i, ptr);
return true;
}
@@ -436,7 +423,7 @@ static bool read_test_data_s16(int offset, bool neg_first)
static bool read_test_data_s32(int offset, bool neg_first)
{
int32_t *ptr = (int32_t *)&test_data[offset];
- int i;
+ int i, bad = 0;
const int max = (TEST_SIZE - offset) / (sizeof(int32_t));
ml_printf("Reading s32 from %#lx (offset %d, %s):",
@@ -453,15 +440,15 @@ static bool read_test_data_s32(int offset, bool neg_first)
for (i = 0; i < max; i++) {
int64_t data = *ptr++;
- if (neg_first && data < 0) {
- pdot(i, false);
- } else if (!neg_first && data > 0) {
- pdot(i, false);
- } else {
- ml_printf("Error %d %c 0\n", data, neg_first ? '<' : '>');
- return false;
+ if (!(neg_first ? data < 0 : data > 0)) {
+ bad++;
}
}
+ test_read_count += max;
+ if (bad) {
+ ml_printf("Error: %d bad s32 words\n", bad);
+ return false;
+ }
ml_printf("done %d @ %p\n", i, ptr);
return true;
}
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 10/12] tests/tcg/riscv64: Enable vectorised memory test
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
` (8 preceding siblings ...)
2026-08-27 5:09 ` [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:25 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 11/12] configure: Provide OBJDUMP to the tcg tests Joel Stanley
` (2 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Build memory.c a second time with -march=rv64gcv -O3, similar to
aarch64's memory-sve, so the memory test checks RVV loads and
stores, including across page boundaries.
Run it under -cpu rv64,v=true.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/riscv64/Makefile.softmmu-target | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
index 3f2a8ed16142..301a6e6e5700 100644
--- a/tests/tcg/riscv64/Makefile.softmmu-target
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
@@ -76,6 +76,14 @@ EXTRA_RUNS += $(MULTIARCH_RUNS)
# Default is zicclsm=true, so misaligned accesses must work
memory: private CFLAGS += -DCHECK_UNALIGNED=1
+memory-rvv: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
+ $(call quiet-command, \
+ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(CRT_OBJS), CC, $@)
+memory-rvv: private CFLAGS += -DCHECK_UNALIGNED=1 -march=rv64gcv -O3
+run-memory-rvv: QEMU_CPU = rv64,v=true
+
+TESTS += memory-rvv
+
# Simple Record/Replay Test
.PHONY: memory-record
run-memory-record: memory-record memory
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 11/12] configure: Provide OBJDUMP to the tcg tests
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
` (9 preceding siblings ...)
2026-08-27 5:09 ` [PATCH 10/12] tests/tcg/riscv64: Enable vectorised " Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:25 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 12/12] tests/tcg: Check vector memory tests contain vector ops Joel Stanley
2026-09-22 9:50 ` [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Alistair Francis
12 siblings, 1 reply; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Probe for a cross objdump alongside the other binutils and add
OBJDUMP to tests/tcg config-target.mak so test makefiles can
inspect the binaries they build.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
configure | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/configure b/configure
index 56158cd95f7b..b82a43018563 100755
--- a/configure
+++ b/configure
@@ -318,6 +318,7 @@ as="${AS-${cross_prefix}as}"
ccas="${CCAS-$cc}"
dlltool="${DLLTOOL-${cross_prefix}dlltool}"
objcopy="${OBJCOPY-${cross_prefix}objcopy}"
+objdump="${OBJDUMP-${cross_prefix}objdump}"
ld="${LD-${cross_prefix}ld}"
ranlib="${RANLIB-${cross_prefix}ranlib}"
nm="${NM-${cross_prefix}nm}"
@@ -1384,6 +1385,7 @@ probe_target_compiler() {
container_cross_ld=
container_cross_nm=
container_cross_objcopy=
+ container_cross_objdump=
container_cross_ranlib=
container_cross_strip=
@@ -1489,6 +1491,7 @@ probe_target_compiler() {
: ${container_cross_ld:=${container_cross_prefix}ld}
: ${container_cross_nm:=${container_cross_prefix}nm}
: ${container_cross_objcopy:=${container_cross_prefix}objcopy}
+ : ${container_cross_objdump:=${container_cross_prefix}objdump}
: ${container_cross_ranlib:=${container_cross_prefix}ranlib}
: ${container_cross_strip:=${container_cross_prefix}strip}
done
@@ -1517,6 +1520,7 @@ probe_target_compiler() {
target_ld=$ld
target_nm=$nm
target_objcopy=$objcopy
+ target_objdump=$objdump
target_ranlib=$ranlib
target_strip=$strip
;;
@@ -1535,6 +1539,7 @@ probe_target_compiler() {
compute_target_variable $target_arch target_ld ld
compute_target_variable $target_arch target_nm nm
compute_target_variable $target_arch target_objcopy objcopy
+ compute_target_variable $target_arch target_objdump objdump
compute_target_variable $target_arch target_ranlib ranlib
compute_target_variable $target_arch target_strip strip
;;
@@ -1596,6 +1601,7 @@ probe_target_compiler() {
target_ld=
target_nm=
target_objcopy=
+ target_objdump=
target_ranlib=
target_strip=
fi
@@ -1617,6 +1623,7 @@ write_target_makefile() {
echo "LD=$docker_py cc --cc $container_cross_ld -i qemu/$container_image -s $source_path --"
echo "NM=$docker_py cc --cc $container_cross_nm -i qemu/$container_image -s $source_path --"
echo "OBJCOPY=$docker_py cc --cc $container_cross_objcopy -i qemu/$container_image -s $source_path --"
+ echo "OBJDUMP=$docker_py cc --cc $container_cross_objdump -i qemu/$container_image -s $source_path --"
echo "RANLIB=$docker_py cc --cc $container_cross_ranlib -i qemu/$container_image -s $source_path --"
echo "STRIP=$docker_py cc --cc $container_cross_strip -i qemu/$container_image -s $source_path --"
else
@@ -1639,6 +1646,9 @@ write_target_makefile() {
if test -n "$target_objcopy"; then
echo "OBJCOPY=$target_objcopy"
fi
+ if test -n "$target_objdump"; then
+ echo "OBJDUMP=$target_objdump"
+ fi
if test -n "$target_ranlib"; then
echo "RANLIB=$target_ranlib"
fi
@@ -1998,6 +2008,7 @@ preserve_env LD_LIBRARY_PATH
preserve_env NM
preserve_env OBJCFLAGS
preserve_env OBJCOPY
+preserve_env OBJDUMP
preserve_env PATH
preserve_env PKG_CONFIG
preserve_env PKG_CONFIG_LIBDIR
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 12/12] tests/tcg: Check vector memory tests contain vector ops
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
` (10 preceding siblings ...)
2026-08-27 5:09 ` [PATCH 11/12] configure: Provide OBJDUMP to the tcg tests Joel Stanley
@ 2026-08-27 5:09 ` Joel Stanley
2026-08-31 1:26 ` Alistair Francis
2026-09-22 9:50 ` [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Alistair Francis
12 siblings, 1 reply; 28+ messages in thread
From: Joel Stanley @ 2026-08-27 5:09 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza, Alex Bennée,
Paolo Bonzini
Cc: Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Disassemble the tests and count the SVE or RVV memory access. Delete the
binary when the check fails otherwise a subsequent run will not run the
check and silently succeed.
CHECK memory-rvv contains 7 vector loads and 7 stores
CHECK memory-sve contains 20 vector loads and 17 stores
This is a coarse check and could be improved by checking specific
functions, and using something more precise than an opcode grep.
However, it would have caught the bug fixed in "tests/tcg/multiarch: Fix
vectorisation of memory test", which makes it worthwhile.
Skipped when no cross objdump was found.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/Makefile.target | 8 ++++++++
tests/tcg/aarch64/Makefile.softmmu-target | 1 +
tests/tcg/riscv64/Makefile.softmmu-target | 1 +
3 files changed, 10 insertions(+)
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index d4dd0fec650d..a5b694d2f21c 100644
--- a/tests/tcg/Makefile.target
+++ b/tests/tcg/Makefile.target
@@ -79,6 +79,14 @@ conditional-diff-out = \
$(call diff-out,$1,$2), \
$(call skip-test,"$1 check","no reference"))
+# Check an ELF for vector load ($1) and store ($2) patterns.
+# Deleted on failure so the check runs again on the next make.
+check-vectorised = $(if $(OBJDUMP), \
+ $(call quiet-command, \
+ ld=$$($(OBJDUMP) -d $@ | grep -cE '[[:space:]]$1'); \
+ st=$$($(OBJDUMP) -d $@ | grep -cE '[[:space:]]$2'); \
+ printf " %-7s %s\n" CHECK "$@ contains $$ld vector loads and $$st stores"; \
+ test "$$ld" -gt 0 && test "$$st" -gt 0 || { rm -f $@; exit 1; }))
# Tests we are building
TESTS=
diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target
index 196a2afa50ee..99ad1a2799d7 100644
--- a/tests/tcg/aarch64/Makefile.softmmu-target
+++ b/tests/tcg/aarch64/Makefile.softmmu-target
@@ -50,6 +50,7 @@ memory: CFLAGS+=-DCHECK_UNALIGNED=1
memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o
+ $(call check-vectorised,ld1[bhwds],st1[bhwd])
memory-sve: private CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve -O3
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
index 301a6e6e5700..5262007e39a5 100644
--- a/tests/tcg/riscv64/Makefile.softmmu-target
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
@@ -79,6 +79,7 @@ memory: private CFLAGS += -DCHECK_UNALIGNED=1
memory-rvv: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
$(call quiet-command, \
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(CRT_OBJS), CC, $@)
+ $(call check-vectorised,vle,vse[0-9])
memory-rvv: private CFLAGS += -DCHECK_UNALIGNED=1 -march=rv64gcv -O3
run-memory-rvv: QEMU_CPU = rv64,v=true
--
2.47.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 01/12] tests/tcg/riscv64: Include stdint.h in semicall.h
2026-08-27 5:09 ` [PATCH 01/12] tests/tcg/riscv64: Include stdint.h in semicall.h Joel Stanley
@ 2026-08-31 1:07 ` Alistair Francis
0 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:07 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> semicall.h uses uintptr_t.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/riscv64/semicall.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/tcg/riscv64/semicall.h
> b/tests/tcg/riscv64/semicall.h
> index 11d0650cb06c..2fdd322af91f 100644
> --- a/tests/tcg/riscv64/semicall.h
> +++ b/tests/tcg/riscv64/semicall.h
> @@ -6,6 +6,7 @@
> *
> * SPDX-License-Identifier: GPL-2.0-or-later
> */
> +#include <stdint.h>
>
> uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
> {
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 02/12] tests/tcg/riscv64: Clean up semicall.h inline asm
2026-08-27 5:09 ` [PATCH 02/12] tests/tcg/riscv64: Clean up semicall.h inline asm Joel Stanley
@ 2026-08-31 1:09 ` Alistair Francis
0 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:09 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> Make __semi_call static inline so semicall.h can be included more
> than once in a program.
>
> Use .option push/pop rather than leaving norvc set for the rest of
> the file.
>
> Set the constraints for the asm block.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/riscv64/semicall.h | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/tests/tcg/riscv64/semicall.h
> b/tests/tcg/riscv64/semicall.h
> index 2fdd322af91f..34e87332de44 100644
> --- a/tests/tcg/riscv64/semicall.h
> +++ b/tests/tcg/riscv64/semicall.h
> @@ -8,16 +8,19 @@
> */
> #include <stdint.h>
>
> -uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
> +static inline uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
> {
> register uintptr_t t asm("a0") = type;
> register uintptr_t a0 asm("a1") = arg0;
> - asm(".option norvc\n\t"
> + asm(".option push\n\t"
> + ".option norvc\n\t"
> ".balign 16\n\t"
> "slli zero, zero, 0x1f\n\t"
> "ebreak\n\t"
> "srai zero, zero, 0x7\n\t"
> - : "=r" (t)
> - : "r" (t), "r" (a0));
> + ".option pop\n\t"
> + : "+r" (t) /* Output: read as input, written as
> return value */
> + : "r" (a0) /* Input: arg0 */
> + : "memory"); /* Clobber: may modify memory, depending
> on type */
> return t;
> }
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 03/12] tests/tcg/riscv64: Boot semihost tests with -bios none -kernel
2026-08-27 5:09 ` [PATCH 03/12] tests/tcg/riscv64: Boot semihost tests with -bios none -kernel Joel Stanley
@ 2026-08-31 1:10 ` Alistair Francis
0 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:10 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> Loading tests should conflict with the opensbi ROM, however the
> generic
> loader writes through the CPU address space which bypasses the ROM
> overlap check.
>
> Instead of depending on this happy accident, set -bios none to skip
> loading opensbi. This frees up the address space to load the test
> with
> -kernel, required by a future change that uses the same rules to run
> the
> multiarch tests for riscv64.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/riscv64/Makefile.softmmu-target | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/tests/tcg/riscv64/Makefile.softmmu-target
> b/tests/tcg/riscv64/Makefile.softmmu-target
> index 6a219c306c43..562ac9b0e0fb 100644
> --- a/tests/tcg/riscv64/Makefile.softmmu-target
> +++ b/tests/tcg/riscv64/Makefile.softmmu-target
> @@ -14,36 +14,36 @@ CFLAGS += -g -Og
> %: %.o $(LINK_SCRIPT)
> $(LD) $(LDFLAGS) $< -o $@
>
> -QEMU_OPTS += -M virt -display none -semihosting -device loader,file=
> +QEMU_OPTS += -M virt -display none -bios none -semihosting -kernel
>
> EXTRA_RUNS += run-issue1060
> run-issue1060: issue1060
> - $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
> + $(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
>
> EXTRA_RUNS += run-test-mepc-masking
> run-test-mepc-masking: test-mepc-masking
> - $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
> + $(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
>
> EXTRA_RUNS += run-test-minstret-ecall
> run-test-minstret-ecall: test-minstret-ecall
> - $(call run-test, $<, $(QEMU) -icount shift=1 $(QEMU_OPTS)$<)
> + $(call run-test, $<, $(QEMU) -icount shift=1 $(QEMU_OPTS)
> $<)
>
> EXTRA_RUNS += run-plugin-doubletrap
> run-plugin-doubletrap: doubletrap
> $(call run-test, $<, \
> $(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D
> $<.pout \
> - $(QEMU_OPTS)$<)
> + $(QEMU_OPTS) $<)
>
> EXTRA_RUNS += run-plugin-interruptedmemory
> run-plugin-interruptedmemory: interruptedmemory
> $(call run-test, $<, \
> $(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D
> $<.pout \
> - $(QEMU_OPTS)$<)
> + $(QEMU_OPTS) $<)
>
> EXTRA_RUNS += run-test-crc32
> comma:= ,
> run-test-crc32: test-crc32
> - $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true
> $(QEMU_OPTS)$<)
> + $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true
> $(QEMU_OPTS) $<)
>
> # Zicclsm: misaligned load/store support. Assemble one source twice:
> the
> # default build expects every misaligned access to succeed
> (zicclsm=true),
> @@ -61,11 +61,11 @@ test-zicclsm-off: test-zicclsm.S $(LINK_SCRIPT)
>
> EXTRA_RUNS += run-test-zicclsm
> run-test-zicclsm: test-zicclsm
> - $(call run-test, $<, $(QEMU) -cpu
> rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=true
> $(QEMU_OPTS)$<)
> + $(call run-test, $<, $(QEMU) -cpu
> rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=true $(QEMU_OPTS)
> $<)
>
> EXTRA_RUNS += run-test-zicclsm-off
> run-test-zicclsm-off: test-zicclsm-off
> - $(call run-test, $<, $(QEMU) -cpu
> rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=false
> $(QEMU_OPTS)$<)
> + $(call run-test, $<, $(QEMU) -cpu
> rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=false $(QEMU_OPTS)
> $<)
>
> EXTRA_RUNS += run-test-misa-w
> run-test-misa-w: test-misa-w
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/12] tests/tcg/riscv64: Update semihosting linker script
2026-08-27 5:09 ` [PATCH 04/12] tests/tcg/riscv64: Update semihosting linker script Joel Stanley
@ 2026-08-31 1:14 ` Alistair Francis
0 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:14 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> Keep the tests at the start of RAM but bound them with a MEMORY
> region,
> and use this to define __stack_top, which the multiarch system test
> boot
> code will use.
>
> Add more sections generated by the test binaries so they are placed
> explicitly.
>
> Split text and data into separate rx/rw regions, instead of one rwx
> region to avoid binutils warnings.
>
> A -kernel boot jumps to the lowest loaded address rather than the ELF
> entry point, so _start must be first in .text. Use a .text._start
> input
> section to make that explicit.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/riscv64/semihost.ld | 47 +++++++++++++++++++++++++++------
> --
> 1 file changed, 36 insertions(+), 11 deletions(-)
>
> diff --git a/tests/tcg/riscv64/semihost.ld
> b/tests/tcg/riscv64/semihost.ld
> index a59cc56b289a..eff3701e4a19 100644
> --- a/tests/tcg/riscv64/semihost.ld
> +++ b/tests/tcg/riscv64/semihost.ld
> @@ -1,21 +1,46 @@
> +/*
> + * Linker script for the RISC-V system tests
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> ENTRY(_start)
>
> +MEMORY
> +{
> + /*
> + * Virt machine, RAM starts at 2GB
> + *
> + * Separate sections for executable and writable data to avoid
> linker
> + * warnings.
> + */
> + TXT (rx) : ORIGIN = 0x80000000, LENGTH = 2M
> + DAT (rw) : ORIGIN = 0x80000000 + 2M, LENGTH = 2M
> +}
> +
> SECTIONS
> {
> - /* virt machine, RAM starts at 2gb */
> - . = 0x80000000;
> .text : {
> + *(.text._start)
> *(.text)
> - }
> + } > TXT
> +
> .rodata : {
> - *(.rodata)
> - }
> - /* align r/w section to next 2mb */
> - . = ALIGN(1 << 21);
> + *(.rodata .rodata.*)
> + *(.eh_frame)
> + } > TXT
> +
> + .got : {
> + *(.got .got.plt)
> + } > DAT
> +
> .data : {
> - *(.data)
> - }
> + *(.data .data.* .sdata .sdata.*)
> + } > DAT
> +
> .bss : {
> - *(.bss)
> - }
> + *(.bss .bss.* .sbss .sbss.*)
> + } > DAT
> +
> + /* Stack grows down from the end of the data region */
> + __stack_top = ORIGIN(DAT) + LENGTH(DAT);
> }
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 05/12] tests/tcg/riscv64: Rework rules for semihost tests
2026-08-27 5:09 ` [PATCH 05/12] tests/tcg/riscv64: Rework rules for semihost tests Joel Stanley
@ 2026-08-31 1:17 ` Alistair Francis
0 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:17 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> Rework the makefile so the semihost tests can share run rules, with
> individual tests overwriting QEMU_CPU or providing more options via
> QEMU_EXTRA.
>
> The program output now comes from the test framework's output chardev
> instead of stdout, but there is no functional change as none of the
> tests use semihosting putc.
>
> Add quiet-command to the compile and link rules so builds print
> CC/LD lines like the run rules.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/riscv64/Makefile.softmmu-target | 94 +++++++++++----------
> --
> 1 file changed, 47 insertions(+), 47 deletions(-)
>
> diff --git a/tests/tcg/riscv64/Makefile.softmmu-target
> b/tests/tcg/riscv64/Makefile.softmmu-target
> index 562ac9b0e0fb..f2850a194084 100644
> --- a/tests/tcg/riscv64/Makefile.softmmu-target
> +++ b/tests/tcg/riscv64/Makefile.softmmu-target
> @@ -9,67 +9,67 @@ LINK_SCRIPT = $(TEST_SRC)/semihost.ld
> LDFLAGS = -T $(LINK_SCRIPT)
> CFLAGS += -g -Og
>
> +# Used by riscv64 tcg tests and shared 'multiarch' tests
> +QEMU_CPU = rv64
> +QEMU_BASE_MACHINE = -M virt -cpu $(QEMU_CPU) -display none -bios
> none
> +QEMU_BASE_ARGS = -semihosting-config enable=on,chardev=output
> +QEMU_OPTS += $(QEMU_BASE_MACHINE) $(QEMU_EXTRA) $(QEMU_BASE_ARGS) -
> kernel
> +
> +# These tests provide _start and use semihosting directly.
> +# -kernel entry point is the lowest loaded address, not the ELF
> entry
> +# point, so _start must remain first in .text.
> +RISCV64_TESTS = issue1060 test-mepc-masking test-minstret-ecall \
> + doubletrap interruptedmemory test-crc32 \
> + test-zicclsm test-zicclsm-off test-misa-w
> +
> +# -Wl,--noexecstack to avoid linker warnings for .S files
> %.o: %.S
> - $(CC) $(CFLAGS) $< -Wa,--noexecstack -c -o $@
> -%: %.o $(LINK_SCRIPT)
> - $(LD) $(LDFLAGS) $< -o $@
> + $(call quiet-command, \
> + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -Wa$(COMMA)--
> noexecstack -c -o $@, CC, $@)
>
> -QEMU_OPTS += -M virt -display none -bios none -semihosting -kernel
> +%.o: %.c
> + $(call quiet-command, \
> + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -c -o $@, CC, $@)
>
> -EXTRA_RUNS += run-issue1060
> -run-issue1060: issue1060
> - $(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
> +$(RISCV64_TESTS): %: %.o $(LINK_SCRIPT)
> + $(call quiet-command, $(LD) -T $(LINK_SCRIPT) $< -o $@, LD,
> $@)
>
> -EXTRA_RUNS += run-test-mepc-masking
> -run-test-mepc-masking: test-mepc-masking
> - $(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
> +TESTS += issue1060 test-mepc-masking test-minstret-ecall test-crc32
> \
> + test-misa-w test-zicclsm test-zicclsm-off
>
> -EXTRA_RUNS += run-test-minstret-ecall
> -run-test-minstret-ecall: test-minstret-ecall
> - $(call run-test, $<, $(QEMU) -icount shift=1 $(QEMU_OPTS)
> $<)
> +# Tests can provide a custom kernel command line here
> +run-test-minstret-ecall: QEMU_EXTRA = -icount shift=1
> +run-test-crc32: QEMU_CPU = rv64,xlrbr=true
> +run-test-misa-w: QEMU_CPU = rv64,x-misa-w=true,c=true,v=true
> +run-test-zicclsm: QEMU_CPU = rv64,v=true,zfh=true,zicclsm=true
> +run-test-zicclsm-off: QEMU_CPU = rv64,v=true,zfh=true,zicclsm=false
> +
> +# Zicclsm: misaligned load/store support. Assemble one source twice:
> the
> +# default build expects every misaligned access to succeed
> (zicclsm=true),
> +# the -DZICCLSM_DISABLED build expects every one to trap
> (zicclsm=false).
> +test-zicclsm.o test-zicclsm-off.o: CFLAGS += -march=rv64gcv_zfh
> +test-zicclsm-off.o: CFLAGS += -DZICCLSM_DISABLED
> +test-zicclsm-off.o: test-zicclsm.S
> + $(call quiet-command, \
> + $(CC) $(CFLAGS) $< -Wa$(COMMA)--noexecstack -c -o $@, CC,
> $@)
>
> EXTRA_RUNS += run-plugin-doubletrap
> run-plugin-doubletrap: doubletrap
> $(call run-test, $<, \
> - $(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D
> $<.pout \
> - $(QEMU_OPTS) $<)
> + $(QEMU) -monitor none -display none \
> + -chardev file$(COMMA)path=$<.out$(COMMA)id=output
> \
> + -plugin ../plugins/libdiscons.so -d plugin -D
> $<.pout \
> + $(QEMU_OPTS) $<)
>
> EXTRA_RUNS += run-plugin-interruptedmemory
> run-plugin-interruptedmemory: interruptedmemory
> $(call run-test, $<, \
> - $(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D
> $<.pout \
> - $(QEMU_OPTS) $<)
> -
> -EXTRA_RUNS += run-test-crc32
> -comma:= ,
> -run-test-crc32: test-crc32
> - $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true
> $(QEMU_OPTS) $<)
> -
> -# Zicclsm: misaligned load/store support. Assemble one source twice:
> the
> -# default build expects every misaligned access to succeed
> (zicclsm=true),
> -# the -DZICCLSM_DISABLED build expects every one to trap
> (zicclsm=false).
> -ZICCLSM_MARCH = -march=rv64gcv_zfh
> -CLEANFILES += test-zicclsm test-zicclsm-off
> -
> -test-zicclsm: test-zicclsm.S $(LINK_SCRIPT)
> - $(CC) $(CFLAGS) $(ZICCLSM_MARCH) $< -Wa,--noexecstack -c -o
> test-zicclsm.o
> - $(LD) $(LDFLAGS) test-zicclsm.o -o $@
> -
> -test-zicclsm-off: test-zicclsm.S $(LINK_SCRIPT)
> - $(CC) $(CFLAGS) $(ZICCLSM_MARCH) -DZICCLSM_DISABLED $< -Wa,-
> -noexecstack -c -o test-zicclsm-off.o
> - $(LD) $(LDFLAGS) test-zicclsm-off.o -o $@
> -
> -EXTRA_RUNS += run-test-zicclsm
> -run-test-zicclsm: test-zicclsm
> - $(call run-test, $<, $(QEMU) -cpu
> rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=true $(QEMU_OPTS)
> $<)
> -
> -EXTRA_RUNS += run-test-zicclsm-off
> -run-test-zicclsm-off: test-zicclsm-off
> - $(call run-test, $<, $(QEMU) -cpu
> rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=false $(QEMU_OPTS)
> $<)
> + $(QEMU) -monitor none -display none \
> + -chardev file$(COMMA)path=$<.out$(COMMA)id=output
> \
> + -plugin ../plugins/libdiscons.so -d plugin -D
> $<.pout \
> + $(QEMU_OPTS) $<)
>
> -EXTRA_RUNS += run-test-misa-w
> -run-test-misa-w: test-misa-w
> - $(call run-test, $<, $(QEMU) -cpu rv64$(comma)x-misa-
> w=true$(comma)c=true$(comma)v=true $(QEMU_OPTS)$<)
> +CLEANFILES += interruptedmemory doubletrap
>
> # We don't currently support the multiarch system tests
> undefine MULTIARCH_TESTS
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 06/12] tests/tcg/riscv64: Enable multiarch system tests
2026-08-27 5:09 ` [PATCH 06/12] tests/tcg/riscv64: Enable multiarch system tests Joel Stanley
@ 2026-08-31 1:20 ` Alistair Francis
0 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:20 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> Add the boot code and semihosting helpers needed to run the multiarch
> system tests on riscv64, and add riscv64 to
> MULTIARCH_SOFTMMU_TARGETS.
> The aarch64 makefile was used as a guide for the make rules.
>
> boot.S does not clear bss as the libmem plugin test would count the
> stores and fail with a mismatch. Instead the BSS is described as
> PT_LOAD, so the QEMU ELF loader fills the region with zero, the same
> as
> aarch64 and loongarch64.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/riscv64/system.c | 30 +++++++++++++++++
> tests/tcg/Makefile.target | 2 +-
> tests/tcg/riscv64/Makefile.softmmu-target | 40 ++++++++++++---------
> --
> tests/tcg/riscv64/boot.S | 23 +++++++++++++
> 4 files changed, 75 insertions(+), 20 deletions(-)
> create mode 100644 tests/tcg/riscv64/system.c
> create mode 100644 tests/tcg/riscv64/boot.S
>
> diff --git a/tests/tcg/riscv64/system.c b/tests/tcg/riscv64/system.c
> new file mode 100644
> index 000000000000..08196a540f96
> --- /dev/null
> +++ b/tests/tcg/riscv64/system.c
> @@ -0,0 +1,30 @@
> +/*
> + * RISC-V semihosting support for multiarch test suite
> + *
> + * Copyright 2026 Tenstorrent USA Inc
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "semicall.h"
> +
> +#define SYS_WRITEC 0x3
> +#define SYS_EXIT 0x18
> +
> +#define ADP_Stopped_ApplicationExit 0x20026
> +
> +void __sys_outc(char c)
> +{
> + __semi_call(SYS_WRITEC, (uintptr_t)&c);
> +}
> +
> +void _exit(int code)
> +{
> + const uintptr_t args[2] = { ADP_Stopped_ApplicationExit,
> (uintptr_t)code };
> +
> + __semi_call(SYS_EXIT, (uintptr_t)args);
> +
> + /* Hang if QEMU fails to exit */
> + while (1) {
> + asm volatile("wfi");
> + }
> +}
> diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
> index 1b83824ff4e7..d4dd0fec650d 100644
> --- a/tests/tcg/Makefile.target
> +++ b/tests/tcg/Makefile.target
> @@ -129,7 +129,7 @@ else
> EXTRA_CFLAGS += -ffreestanding -fno-stack-protector
>
> # We skip the multiarch tests if the target hasn't provided a boot.S
> -MULTIARCH_SOFTMMU_TARGETS = i386 alpha aarch64 arm loongarch64 s390x
> x86_64
> +MULTIARCH_SOFTMMU_TARGETS = i386 alpha aarch64 arm loongarch64 s390x
> x86_64 riscv64
>
> ifneq ($(filter $(TARGET_NAME),$(MULTIARCH_SOFTMMU_TARGETS)),)
> -include $(SRC_PATH)/tests/tcg/minilib/Makefile.target
> diff --git a/tests/tcg/riscv64/Makefile.softmmu-target
> b/tests/tcg/riscv64/Makefile.softmmu-target
> index f2850a194084..82e8fe2664b0 100644
> --- a/tests/tcg/riscv64/Makefile.softmmu-target
> +++ b/tests/tcg/riscv64/Makefile.softmmu-target
> @@ -5,9 +5,11 @@
> TEST_SRC = $(SRC_PATH)/tests/tcg/riscv64
> VPATH += $(TEST_SRC)
>
> +CRT_OBJS = boot.o system.o
> +
> LINK_SCRIPT = $(TEST_SRC)/semihost.ld
> -LDFLAGS = -T $(LINK_SCRIPT)
> -CFLAGS += -g -Og
> +LDFLAGS = -Wl,-T$(LINK_SCRIPT) -static -nostdlib $(MINILIB_OBJS) -
> lgcc
> +CFLAGS += -g -Og $(MINILIB_INC)
>
> # Used by riscv64 tcg tests and shared 'multiarch' tests
> QEMU_CPU = rv64
> @@ -53,23 +55,23 @@ test-zicclsm-off.o: test-zicclsm.S
> $(call quiet-command, \
> $(CC) $(CFLAGS) $< -Wa$(COMMA)--noexecstack -c -o $@, CC,
> $@)
>
> -EXTRA_RUNS += run-plugin-doubletrap
> -run-plugin-doubletrap: doubletrap
> - $(call run-test, $<, \
> - $(QEMU) -monitor none -display none \
> - -chardev file$(COMMA)path=$<.out$(COMMA)id=output
> \
> - -plugin ../plugins/libdiscons.so -d plugin -D
> $<.pout \
> - $(QEMU_OPTS) $<)
> -
> -EXTRA_RUNS += run-plugin-interruptedmemory
> -run-plugin-interruptedmemory: interruptedmemory
> - $(call run-test, $<, \
> - $(QEMU) -monitor none -display none \
> - -chardev file$(COMMA)path=$<.out$(COMMA)id=output
> \
> - -plugin ../plugins/libdiscons.so -d plugin -D
> $<.pout \
> - $(QEMU_OPTS) $<)
> +ifeq ($(CONFIG_PLUGIN),y)
> +EXTRA_RUNS_WITH_PLUGIN += run-plugin-doubletrap-with-libdiscons.so \
> + run-plugin-interruptedmemory-with-libdiscons.so
> +endif
>
> CLEANFILES += interruptedmemory doubletrap
>
> -# We don't currently support the multiarch system tests
> -undefine MULTIARCH_TESTS
> +# Multiarch tests
> +TESTS += $(MULTIARCH_TESTS)
> +EXTRA_RUNS += $(MULTIARCH_RUNS)
> +
> +.PRECIOUS: $(CRT_OBJS)
> +
> +# Build and link the multiarch tests
> +%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
> + $(call quiet-command, \
> + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
> $(CRT_OBJS), CC, $@)
> +
> +# Default is zicclsm=true, so misaligned accesses must work
> +memory: private CFLAGS += -DCHECK_UNALIGNED=1
> diff --git a/tests/tcg/riscv64/boot.S b/tests/tcg/riscv64/boot.S
> new file mode 100644
> index 000000000000..b403549345a1
> --- /dev/null
> +++ b/tests/tcg/riscv64/boot.S
> @@ -0,0 +1,23 @@
> +/*
> + * RISC-V boot code for multiarch test suite
> + *
> + * Copyright 2026 Tenstorrent USA Inc
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#define MSTATUS_VS 0x00000600
> +#define MSTATUS_FS 0x00006000
> +
> +.section .text._start
> + .global _start
> + .type _start, @function
> +_start:
> + /* Enable FPU and vector unit */
> + li t0, (MSTATUS_FS | MSTATUS_VS)
> + csrs mstatus, t0
> + la sp, __stack_top
> + call main
> +
> +exit:
> + /* exit with main()'s return code */
> + call _exit
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 07/12] tests/tcg/riscv64: Enable memory record and replay test
2026-08-27 5:09 ` [PATCH 07/12] tests/tcg/riscv64: Enable memory record and replay test Joel Stanley
@ 2026-08-31 1:21 ` Alistair Francis
0 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:21 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> Run the memory test under icount record and replay, copied from
> aarch64.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/riscv64/Makefile.softmmu-target | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/tests/tcg/riscv64/Makefile.softmmu-target
> b/tests/tcg/riscv64/Makefile.softmmu-target
> index 82e8fe2664b0..3f2a8ed16142 100644
> --- a/tests/tcg/riscv64/Makefile.softmmu-target
> +++ b/tests/tcg/riscv64/Makefile.softmmu-target
> @@ -75,3 +75,22 @@ EXTRA_RUNS += $(MULTIARCH_RUNS)
>
> # Default is zicclsm=true, so misaligned accesses must work
> memory: private CFLAGS += -DCHECK_UNALIGNED=1
> +
> +# Simple Record/Replay Test
> +.PHONY: memory-record
> +run-memory-record: memory-record memory
> + $(call run-test, $<, \
> + $(QEMU) -monitor none \
> + -chardev file$(COMMA)path=$<.out$(COMMA)id=output
> \
> + -icount
> shift=5$(COMMA)rr=record$(COMMA)rrfile=record.bin \
> + $(QEMU_OPTS) memory)
> +
> +.PHONY: memory-replay
> +run-memory-replay: memory-replay run-memory-record
> + $(call run-test, $<, \
> + $(QEMU) -monitor none \
> + -chardev file$(COMMA)path=$<.out$(COMMA)id=output
> \
> + -icount
> shift=5$(COMMA)rr=replay$(COMMA)rrfile=record.bin \
> + $(QEMU_OPTS) memory)
> +
> +EXTRA_RUNS += run-memory-replay
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test
2026-08-27 5:09 ` [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test Joel Stanley
@ 2026-08-31 1:24 ` Alistair Francis
2026-09-01 10:06 ` Alex Bennée
1 sibling, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:24 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> Compilers are not able to vectorise the load and store loops.
> Building
> with -fopt-info-vec-missed with gcc 16.1:
>
> missed: statement clobbers memory: ml_printf (".");
>
> This can be fixed by doing the printf after the loops.
>
> Also, autovectorisation doesn't like more than one if statement in
> the
> loop:
>
> missed: not vectorized: unsupported control flow in loop.
>
> By combining them into ternary statements and one if, the loops are
> able
> to be vectorised with both loads and stores.
>
> The trade off is the dots are gone, and the tests no longer report
> fine
> grained miscompares. A failure does report the number of bad elements
> in
> a failing test loop.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/multiarch/system/memory.c | 113 ++++++++++++--------------
> --
> 1 file changed, 50 insertions(+), 63 deletions(-)
>
> diff --git a/tests/tcg/multiarch/system/memory.c
> b/tests/tcg/multiarch/system/memory.c
> index 7508f6b916d0..6eeb738343ab 100644
> --- a/tests/tcg/multiarch/system/memory.c
> +++ b/tests/tcg/multiarch/system/memory.c
> @@ -42,9 +42,6 @@ static void pdot(int count, bool write)
> } else {
> test_read_count++;
> }
> - if (count % 128 == 0) {
> - ml_printf(".");
> - }
> }
>
> /*
> @@ -77,7 +74,6 @@ static void init_test_data_u8(int unused_offset)
> *ptr++ = BYTE_NEXT(count);
> pdot(i, true);
> }
> -
> ml_printf("done %d @ %p\n", i, ptr);
> }
>
> @@ -127,7 +123,6 @@ static void reset_start_data(int offset)
> *ptr++ = 0;
> pdot(i, true);
> }
> -
> ml_printf("done %d @ %p\n", i, ptr);
> }
>
> @@ -203,7 +198,7 @@ static void init_test_data_u64(int offset)
> static bool read_test_data_u16(int offset)
> {
> uint16_t word, *ptr = (uint16_t *)&test_data[offset];
> - int i;
> + int i, bad = 0;
> const int max = (TEST_SIZE - offset) / sizeof(word);
>
> ml_printf("Reading u16 from %#lx (offset %d):", ptr, offset);
> @@ -214,12 +209,13 @@ static bool read_test_data_u16(int offset)
> high = (word >> 8) & 0xff;
> low = word & 0xff;
> if (high < low && high != 0) {
> - ml_printf("Error %d < %d\n", high, low);
> - return false;
> - } else {
> - pdot(i, false);
> + bad++;
> }
> -
> + }
> + test_read_count += max;
> + if (bad) {
> + ml_printf("Error: %d bad u16 words\n", bad);
> + return false;
> }
> ml_printf("done %d @ %p\n", i, ptr);
> return true;
> @@ -228,7 +224,7 @@ static bool read_test_data_u16(int offset)
> static bool read_test_data_u32(int offset)
> {
> uint32_t word, *ptr = (uint32_t *)&test_data[offset];
> - int i;
> + int i, bad = 0;
> const int max = (TEST_SIZE - offset) / sizeof(word);
>
> ml_printf("Reading u32 from %#lx (offset %d):", ptr, offset);
> @@ -247,21 +243,18 @@ static bool read_test_data_u32(int offset)
> zeros += (b2 == 0 ? 1 : 0);
> zeros += (b3 == 0 ? 1 : 0);
> zeros += (b4 == 0 ? 1 : 0);
> - if (zeros > 1) {
> - ml_printf("Error @ %p, more zeros than expected: %d, %d,
> %d, %d",
> - ptr - 1, b1, b2, b3, b4);
> - return false;
> - }
> -
> - if ((b1 < b2 && b1 != 0) ||
> + if (zeros > 1 ||
> + (b1 < b2 && b1 != 0) ||
> (b2 < b3 && b2 != 0) ||
> (b3 < b4 && b3 != 0)) {
> - ml_printf("Error %d, %d, %d, %d", b1, b2, b3, b4);
> - return false;
> - } else {
> - pdot(i, false);
> + bad++;
> }
> }
> + test_read_count += max;
> + if (bad) {
> + ml_printf("Error: %d bad u32 words\n", bad);
> + return false;
> + }
> ml_printf("done %d @ %p\n", i, ptr);
> return true;
> }
> @@ -270,7 +263,7 @@ static bool read_test_data_u32(int offset)
> static bool read_test_data_u64(int offset)
> {
> uint64_t word, *ptr = (uint64_t *)&test_data[offset];
> - int i;
> + int i, bad = 0;
> const int max = (TEST_SIZE - offset) / sizeof(word);
>
> ml_printf("Reading u64 from %#lx (offset %d):", ptr, offset);
> @@ -297,26 +290,22 @@ static bool read_test_data_u64(int offset)
> zeros += (b6 == 0 ? 1 : 0);
> zeros += (b7 == 0 ? 1 : 0);
> zeros += (b8 == 0 ? 1 : 0);
> - if (zeros > 1) {
> - ml_printf("Error @ %p, more zeros than expected: %d, %d,
> %d, %d, %d, %d, %d, %d",
> - ptr - 1, b1, b2, b3, b4, b5, b6, b7, b8);
> - return false;
> - }
> -
> - if ((b1 < b2 && b1 != 0) ||
> + if (zeros > 1 ||
> + (b1 < b2 && b1 != 0) ||
> (b2 < b3 && b2 != 0) ||
> (b3 < b4 && b3 != 0) ||
> (b4 < b5 && b4 != 0) ||
> (b5 < b6 && b5 != 0) ||
> (b6 < b7 && b6 != 0) ||
> (b7 < b8 && b7 != 0)) {
> - ml_printf("Error %d, %d, %d, %d, %d, %d, %d, %d",
> - b1, b2, b3, b4, b5, b6, b7, b8);
> - return false;
> - } else {
> - pdot(i, false);
> + bad++;
> }
> }
> + test_read_count += max;
> + if (bad) {
> + ml_printf("Error: %d bad u64 words\n", bad);
> + return false;
> + }
> ml_printf("done %d @ %p\n", i, ptr);
> return true;
> }
> @@ -374,28 +363,26 @@ static bool do_unsigned_test(init_ufn fn)
> static bool read_test_data_s8(int offset, bool neg_first)
> {
> int8_t *ptr = (int8_t *)&test_data[offset];
> - int i;
> + int i, bad = 0;
> const int max = (TEST_SIZE - offset) / 2;
>
> ml_printf("Reading s8 pairs from %#lx (offset %d):", ptr,
> offset);
>
> for (i = 0; i < max; i++) {
> int16_t first, second;
> - bool ok;
> first = *ptr++;
> second = *ptr++;
>
> - if (neg_first && first < 0 && second > 0) {
> - pdot(i, false);
> - pdot(i, false);
> - } else if (!neg_first && first > 0 && second < 0) {
> - pdot(i, false);
> - pdot(i, false);
> - } else {
> - ml_printf("Error %d %c %d\n", first, neg_first ? '<' :
> '>', second);
> - return false;
> + if (!(neg_first ? (first < 0 && second > 0)
> + : (first > 0 && second < 0))) {
> + bad++;
> }
> }
> + test_read_count += max * 2;
> + if (bad) {
> + ml_printf("Error: %d bad s8 pairs\n", bad);
> + return false;
> + }
> ml_printf("done %d @ %p\n", i * 2, ptr);
> return true;
> }
> @@ -403,7 +390,7 @@ static bool read_test_data_s8(int offset, bool
> neg_first)
> static bool read_test_data_s16(int offset, bool neg_first)
> {
> int16_t *ptr = (int16_t *)&test_data[offset];
> - int i;
> + int i, bad = 0;
> const int max = (TEST_SIZE - offset) / (sizeof(*ptr));
>
> ml_printf("Reading s16 from %#lx (offset %d, %s):", ptr,
> @@ -420,15 +407,15 @@ static bool read_test_data_s16(int offset, bool
> neg_first)
> for (i = 0; i < max; i++) {
> int32_t data = *ptr++;
>
> - if (neg_first && data < 0) {
> - pdot(i, false);
> - } else if (!neg_first && data > 0) {
> - pdot(i, false);
> - } else {
> - ml_printf("Error %d %c 0\n", data, neg_first ? '<' :
> '>');
> - return false;
> + if (!(neg_first ? data < 0 : data > 0)) {
> + bad++;
> }
> }
> + test_read_count += max;
> + if (bad) {
> + ml_printf("Error: %d bad s16 words\n", bad);
> + return false;
> + }
> ml_printf("done %d @ %p\n", i, ptr);
> return true;
> }
> @@ -436,7 +423,7 @@ static bool read_test_data_s16(int offset, bool
> neg_first)
> static bool read_test_data_s32(int offset, bool neg_first)
> {
> int32_t *ptr = (int32_t *)&test_data[offset];
> - int i;
> + int i, bad = 0;
> const int max = (TEST_SIZE - offset) / (sizeof(int32_t));
>
> ml_printf("Reading s32 from %#lx (offset %d, %s):",
> @@ -453,15 +440,15 @@ static bool read_test_data_s32(int offset, bool
> neg_first)
> for (i = 0; i < max; i++) {
> int64_t data = *ptr++;
>
> - if (neg_first && data < 0) {
> - pdot(i, false);
> - } else if (!neg_first && data > 0) {
> - pdot(i, false);
> - } else {
> - ml_printf("Error %d %c 0\n", data, neg_first ? '<' :
> '>');
> - return false;
> + if (!(neg_first ? data < 0 : data > 0)) {
> + bad++;
> }
> }
> + test_read_count += max;
> + if (bad) {
> + ml_printf("Error: %d bad s32 words\n", bad);
> + return false;
> + }
> ml_printf("done %d @ %p\n", i, ptr);
> return true;
> }
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 10/12] tests/tcg/riscv64: Enable vectorised memory test
2026-08-27 5:09 ` [PATCH 10/12] tests/tcg/riscv64: Enable vectorised " Joel Stanley
@ 2026-08-31 1:25 ` Alistair Francis
0 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:25 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> Build memory.c a second time with -march=rv64gcv -O3, similar to
> aarch64's memory-sve, so the memory test checks RVV loads and
> stores, including across page boundaries.
>
> Run it under -cpu rv64,v=true.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/riscv64/Makefile.softmmu-target | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/tests/tcg/riscv64/Makefile.softmmu-target
> b/tests/tcg/riscv64/Makefile.softmmu-target
> index 3f2a8ed16142..301a6e6e5700 100644
> --- a/tests/tcg/riscv64/Makefile.softmmu-target
> +++ b/tests/tcg/riscv64/Makefile.softmmu-target
> @@ -76,6 +76,14 @@ EXTRA_RUNS += $(MULTIARCH_RUNS)
> # Default is zicclsm=true, so misaligned accesses must work
> memory: private CFLAGS += -DCHECK_UNALIGNED=1
>
> +memory-rvv: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
> + $(call quiet-command, \
> + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
> $(CRT_OBJS), CC, $@)
> +memory-rvv: private CFLAGS += -DCHECK_UNALIGNED=1 -march=rv64gcv -O3
> +run-memory-rvv: QEMU_CPU = rv64,v=true
> +
> +TESTS += memory-rvv
> +
> # Simple Record/Replay Test
> .PHONY: memory-record
> run-memory-record: memory-record memory
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 11/12] configure: Provide OBJDUMP to the tcg tests
2026-08-27 5:09 ` [PATCH 11/12] configure: Provide OBJDUMP to the tcg tests Joel Stanley
@ 2026-08-31 1:25 ` Alistair Francis
0 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:25 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> Probe for a cross objdump alongside the other binutils and add
> OBJDUMP to tests/tcg config-target.mak so test makefiles can
> inspect the binaries they build.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> configure | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/configure b/configure
> index 56158cd95f7b..b82a43018563 100755
> --- a/configure
> +++ b/configure
> @@ -318,6 +318,7 @@ as="${AS-${cross_prefix}as}"
> ccas="${CCAS-$cc}"
> dlltool="${DLLTOOL-${cross_prefix}dlltool}"
> objcopy="${OBJCOPY-${cross_prefix}objcopy}"
> +objdump="${OBJDUMP-${cross_prefix}objdump}"
> ld="${LD-${cross_prefix}ld}"
> ranlib="${RANLIB-${cross_prefix}ranlib}"
> nm="${NM-${cross_prefix}nm}"
> @@ -1384,6 +1385,7 @@ probe_target_compiler() {
> container_cross_ld=
> container_cross_nm=
> container_cross_objcopy=
> + container_cross_objdump=
> container_cross_ranlib=
> container_cross_strip=
>
> @@ -1489,6 +1491,7 @@ probe_target_compiler() {
> : ${container_cross_ld:=${container_cross_prefix}ld}
> : ${container_cross_nm:=${container_cross_prefix}nm}
> : ${container_cross_objcopy:=${container_cross_prefix}objcopy}
> + : ${container_cross_objdump:=${container_cross_prefix}objdump}
> : ${container_cross_ranlib:=${container_cross_prefix}ranlib}
> : ${container_cross_strip:=${container_cross_prefix}strip}
> done
> @@ -1517,6 +1520,7 @@ probe_target_compiler() {
> target_ld=$ld
> target_nm=$nm
> target_objcopy=$objcopy
> + target_objdump=$objdump
> target_ranlib=$ranlib
> target_strip=$strip
> ;;
> @@ -1535,6 +1539,7 @@ probe_target_compiler() {
> compute_target_variable $target_arch target_ld ld
> compute_target_variable $target_arch target_nm nm
> compute_target_variable $target_arch target_objcopy objcopy
> + compute_target_variable $target_arch target_objdump objdump
> compute_target_variable $target_arch target_ranlib ranlib
> compute_target_variable $target_arch target_strip strip
> ;;
> @@ -1596,6 +1601,7 @@ probe_target_compiler() {
> target_ld=
> target_nm=
> target_objcopy=
> + target_objdump=
> target_ranlib=
> target_strip=
> fi
> @@ -1617,6 +1623,7 @@ write_target_makefile() {
> echo "LD=$docker_py cc --cc $container_cross_ld -i
> qemu/$container_image -s $source_path --"
> echo "NM=$docker_py cc --cc $container_cross_nm -i
> qemu/$container_image -s $source_path --"
> echo "OBJCOPY=$docker_py cc --cc $container_cross_objcopy -i
> qemu/$container_image -s $source_path --"
> + echo "OBJDUMP=$docker_py cc --cc $container_cross_objdump -i
> qemu/$container_image -s $source_path --"
> echo "RANLIB=$docker_py cc --cc $container_cross_ranlib -i
> qemu/$container_image -s $source_path --"
> echo "STRIP=$docker_py cc --cc $container_cross_strip -i
> qemu/$container_image -s $source_path --"
> else
> @@ -1639,6 +1646,9 @@ write_target_makefile() {
> if test -n "$target_objcopy"; then
> echo "OBJCOPY=$target_objcopy"
> fi
> + if test -n "$target_objdump"; then
> + echo "OBJDUMP=$target_objdump"
> + fi
> if test -n "$target_ranlib"; then
> echo "RANLIB=$target_ranlib"
> fi
> @@ -1998,6 +2008,7 @@ preserve_env LD_LIBRARY_PATH
> preserve_env NM
> preserve_env OBJCFLAGS
> preserve_env OBJCOPY
> +preserve_env OBJDUMP
> preserve_env PATH
> preserve_env PKG_CONFIG
> preserve_env PKG_CONFIG_LIBDIR
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 12/12] tests/tcg: Check vector memory tests contain vector ops
2026-08-27 5:09 ` [PATCH 12/12] tests/tcg: Check vector memory tests contain vector ops Joel Stanley
@ 2026-08-31 1:26 ` Alistair Francis
0 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-08-31 1:26 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> Disassemble the tests and count the SVE or RVV memory access. Delete
> the
> binary when the check fails otherwise a subsequent run will not run
> the
> check and silently succeed.
>
> CHECK memory-rvv contains 7 vector loads and 7 stores
>
> CHECK memory-sve contains 20 vector loads and 17 stores
>
> This is a coarse check and could be improved by checking specific
> functions, and using something more precise than an opcode grep.
> However, it would have caught the bug fixed in "tests/tcg/multiarch:
> Fix
> vectorisation of memory test", which makes it worthwhile.
>
> Skipped when no cross objdump was found.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/Makefile.target | 8 ++++++++
> tests/tcg/aarch64/Makefile.softmmu-target | 1 +
> tests/tcg/riscv64/Makefile.softmmu-target | 1 +
> 3 files changed, 10 insertions(+)
>
> diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
> index d4dd0fec650d..a5b694d2f21c 100644
> --- a/tests/tcg/Makefile.target
> +++ b/tests/tcg/Makefile.target
> @@ -79,6 +79,14 @@ conditional-diff-out
> = \
> $(call diff-
> out,$1,$2), \
> $(call skip-test,"$1 check","no reference"))
>
> +# Check an ELF for vector load ($1) and store ($2) patterns.
> +# Deleted on failure so the check runs again on the next make.
> +check-vectorised = $(if $(OBJDUMP), \
> + $(call quiet-command, \
> + ld=$$($(OBJDUMP) -d $@ | grep -cE '[[:space:]]$1'); \
> + st=$$($(OBJDUMP) -d $@ | grep -cE '[[:space:]]$2'); \
> + printf " %-7s %s\n" CHECK "$@ contains $$ld vector
> loads and $$st stores"; \
> + test "$$ld" -gt 0 && test "$$st" -gt 0 || { rm -f $@;
> exit 1; }))
>
> # Tests we are building
> TESTS=
> diff --git a/tests/tcg/aarch64/Makefile.softmmu-target
> b/tests/tcg/aarch64/Makefile.softmmu-target
> index 196a2afa50ee..99ad1a2799d7 100644
> --- a/tests/tcg/aarch64/Makefile.softmmu-target
> +++ b/tests/tcg/aarch64/Makefile.softmmu-target
> @@ -50,6 +50,7 @@ memory: CFLAGS+=-DCHECK_UNALIGNED=1
>
> memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
> $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o
> + $(call check-vectorised,ld1[bhwds],st1[bhwd])
>
> memory-sve: private CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve
> -O3
>
> diff --git a/tests/tcg/riscv64/Makefile.softmmu-target
> b/tests/tcg/riscv64/Makefile.softmmu-target
> index 301a6e6e5700..5262007e39a5 100644
> --- a/tests/tcg/riscv64/Makefile.softmmu-target
> +++ b/tests/tcg/riscv64/Makefile.softmmu-target
> @@ -79,6 +79,7 @@ memory: private CFLAGS += -DCHECK_UNALIGNED=1
> memory-rvv: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
> $(call quiet-command, \
> $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
> $(CRT_OBJS), CC, $@)
> + $(call check-vectorised,vle,vse[0-9])
> memory-rvv: private CFLAGS += -DCHECK_UNALIGNED=1 -march=rv64gcv -O3
> run-memory-rvv: QEMU_CPU = rv64,v=true
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test
2026-08-27 5:09 ` [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test Joel Stanley
2026-08-31 1:24 ` Alistair Francis
@ 2026-09-01 10:06 ` Alex Bennée
1 sibling, 0 replies; 28+ messages in thread
From: Alex Bennée @ 2026-09-01 10:06 UTC (permalink / raw)
To: Joel Stanley
Cc: Alistair Francis, Daniel Henrique Barboza, Paolo Bonzini,
Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Joel Stanley <joel@jms.id.au> writes:
> Compilers are not able to vectorise the load and store loops. Building
> with -fopt-info-vec-missed with gcc 16.1:
>
> missed: statement clobbers memory: ml_printf (".");
>
> This can be fixed by doing the printf after the loops.
>
> Also, autovectorisation doesn't like more than one if statement in the
> loop:
>
> missed: not vectorized: unsupported control flow in loop.
>
> By combining them into ternary statements and one if, the loops are able
> to be vectorised with both loads and stores.
>
> The trade off is the dots are gone, and the tests no longer report fine
> grained miscompares. A failure does report the number of bad elements in
> a failing test loop.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS
2026-08-27 5:09 ` [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS Joel Stanley
@ 2026-09-22 5:39 ` Alistair Francis
2026-09-22 7:17 ` Alex Bennée
1 sibling, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-09-22 5:39 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> The CFLAGS are added to prerequisites, so if memory-sve causes a
> build
> of printf.o and boot.o, they will be compiled with -march=armv8.1-
> a+sve
> -O3, and the executables that link printf.o and boot.o after that
> will
> also get SVE instructions.
>
> https://www.gnu.org/software/make/manual/html_node/Suppressing-Inheritance.html
>
> By marking the rule 'private' printf.o and boot.o won't be built with
> SVE, which avoids SVE for other binaries, and is okay for the memory-
> sve
> case.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/tcg/aarch64/Makefile.softmmu-target | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/tcg/aarch64/Makefile.softmmu-target
> b/tests/tcg/aarch64/Makefile.softmmu-target
> index 3f30be6c5d63..196a2afa50ee 100644
> --- a/tests/tcg/aarch64/Makefile.softmmu-target
> +++ b/tests/tcg/aarch64/Makefile.softmmu-target
> @@ -51,7 +51,7 @@ memory: CFLAGS+=-DCHECK_UNALIGNED=1
> memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
> $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o
>
> -memory-sve: CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve -O3
> +memory-sve: private CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve
> -O3
>
> gpc-test: gpc-test.c $(LINK_SCRIPT) vector_log_boot.o
> $(MINILIB_OBJS)
> $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
> vector_log_boot.o
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS
2026-08-27 5:09 ` [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS Joel Stanley
2026-09-22 5:39 ` Alistair Francis
@ 2026-09-22 7:17 ` Alex Bennée
1 sibling, 0 replies; 28+ messages in thread
From: Alex Bennée @ 2026-09-22 7:17 UTC (permalink / raw)
To: Joel Stanley
Cc: Alistair Francis, Daniel Henrique Barboza, Paolo Bonzini,
Peter Maydell, Weiwei Li, Liu Zhiwei, Chao Liu, Nicholas Piggin,
Anirudh Srinivasan, Michael Ellerman, Portia Stephens, qemu-riscv,
qemu-devel, qemu-arm
Joel Stanley <joel@jms.id.au> writes:
> The CFLAGS are added to prerequisites, so if memory-sve causes a build
> of printf.o and boot.o, they will be compiled with -march=armv8.1-a+sve
> -O3, and the executables that link printf.o and boot.o after that will
> also get SVE instructions.
>
> https://www.gnu.org/software/make/manual/html_node/Suppressing-Inheritance.html
>
> By marking the rule 'private' printf.o and boot.o won't be built with
> SVE, which avoids SVE for other binaries, and is okay for the memory-sve
> case.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> tests/tcg/aarch64/Makefile.softmmu-target | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target
> index 3f30be6c5d63..196a2afa50ee 100644
> --- a/tests/tcg/aarch64/Makefile.softmmu-target
> +++ b/tests/tcg/aarch64/Makefile.softmmu-target
> @@ -51,7 +51,7 @@ memory: CFLAGS+=-DCHECK_UNALIGNED=1
> memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
> $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o
>
> -memory-sve: CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve -O3
> +memory-sve: private CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve
> -O3
Good catch. You will need to port this to meson now it is merged though.
>
> gpc-test: gpc-test.c $(LINK_SCRIPT) vector_log_boot.o $(MINILIB_OBJS)
> $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) vector_log_boot.o
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/12] tests/tcg: Multiarch tests for riscv64
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
` (11 preceding siblings ...)
2026-08-27 5:09 ` [PATCH 12/12] tests/tcg: Check vector memory tests contain vector ops Joel Stanley
@ 2026-09-22 9:50 ` Alistair Francis
12 siblings, 0 replies; 28+ messages in thread
From: Alistair Francis @ 2026-09-22 9:50 UTC (permalink / raw)
To: alex.bennee@linaro.org, daniel.barboza@oss.qualcomm.com,
pbonzini@redhat.com, joel@jms.id.au
Cc: npiggin@gmail.com, mpe@kernel.org, portias@oss.tenstorrent.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, chao.liu@processmission.com,
asrinivasan@oss.tenstorrent.com, qemu-riscv@nongnu.org,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com
On Thu, 2026-08-27 at 14:39 +0930, Joel Stanley wrote:
> When testing Richard's TCG RVV changes I went down the rabbit hole
> that
> is tests/tcg/multiarch. Out the other side is this series, which
> enables
> the multiarch and record/replay tests for riscv64, and fixes the
> memory-sve aarch64 test while adding a memory-rvv test for riscv64.
>
> The first half of the series performs some housekeeping on the
> semihost
> tests and the softmmu makefile in tests/tcg/riscv64. The second half
> enables the multiarch tests, and looks at the vectorised memory.c
> test.
>
> The final patch adds a very coarse check for vectorisation by
> grepping
> objdump for vector loads and stores. Although it's not the neatest,
> it
> would have caught the regression in memory-sve, so it is worthwhile
> having in the tree.
>
> Joel Stanley (12):
> tests/tcg/riscv64: Include stdint.h in semicall.h
> tests/tcg/riscv64: Clean up semicall.h inline asm
> tests/tcg/riscv64: Boot semihost tests with -bios none -kernel
> tests/tcg/riscv64: Update semihosting linker script
> tests/tcg/riscv64: Rework rules for semihost tests
> tests/tcg/riscv64: Enable multiarch system tests
> tests/tcg/riscv64: Enable memory record and replay test
> tests/tcg/aarch64: Don't leak memory-sve CFLAGS
> tests/tcg/multiarch: Fix vectorisation of memory test
> tests/tcg/riscv64: Enable vectorised memory test
> configure: Provide OBJDUMP to the tcg tests
> tests/tcg: Check vector memory tests contain vector ops
Urgh! This is all reviewed/acked, but conflicts with the meson test
changes. Do you mind rebasing?
Sorry :(
Alistair
>
> configure | 11 ++
> tests/tcg/riscv64/semicall.h | 12 +-
> tests/tcg/multiarch/system/memory.c | 113 ++++++++----------
> tests/tcg/riscv64/system.c | 30 +++++
> tests/tcg/Makefile.target | 10 +-
> tests/tcg/aarch64/Makefile.softmmu-target | 3 +-
> tests/tcg/riscv64/Makefile.softmmu-target | 134 +++++++++++++-------
> --
> tests/tcg/riscv64/boot.S | 23 ++++
> tests/tcg/riscv64/semihost.ld | 47 ++++++--
> 9 files changed, 251 insertions(+), 132 deletions(-)
> create mode 100644 tests/tcg/riscv64/system.c
> create mode 100644 tests/tcg/riscv64/boot.S
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2026-09-22 9:52 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
2026-08-27 5:09 ` [PATCH 01/12] tests/tcg/riscv64: Include stdint.h in semicall.h Joel Stanley
2026-08-31 1:07 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 02/12] tests/tcg/riscv64: Clean up semicall.h inline asm Joel Stanley
2026-08-31 1:09 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 03/12] tests/tcg/riscv64: Boot semihost tests with -bios none -kernel Joel Stanley
2026-08-31 1:10 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 04/12] tests/tcg/riscv64: Update semihosting linker script Joel Stanley
2026-08-31 1:14 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 05/12] tests/tcg/riscv64: Rework rules for semihost tests Joel Stanley
2026-08-31 1:17 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 06/12] tests/tcg/riscv64: Enable multiarch system tests Joel Stanley
2026-08-31 1:20 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 07/12] tests/tcg/riscv64: Enable memory record and replay test Joel Stanley
2026-08-31 1:21 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS Joel Stanley
2026-09-22 5:39 ` Alistair Francis
2026-09-22 7:17 ` Alex Bennée
2026-08-27 5:09 ` [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test Joel Stanley
2026-08-31 1:24 ` Alistair Francis
2026-09-01 10:06 ` Alex Bennée
2026-08-27 5:09 ` [PATCH 10/12] tests/tcg/riscv64: Enable vectorised " Joel Stanley
2026-08-31 1:25 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 11/12] configure: Provide OBJDUMP to the tcg tests Joel Stanley
2026-08-31 1:25 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 12/12] tests/tcg: Check vector memory tests contain vector ops Joel Stanley
2026-08-31 1:26 ` Alistair Francis
2026-09-22 9:50 ` [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Alistair Francis
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