[PATCH i-g-t CI run 00/14] CI run only

[PATCH i-g-t CI run 00/14] CI run only

[Umesh Nerlige Ramappa]

CI, not for review

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh Nerlige Ramappa (14):
  tests/intel/xe_oa: Use static for global variables
  tests/intel/xe_oa: Drop unused macro
  tests/intel/xe_oa: Rename oa_exp_1_millisec to oa_exponent_default
  tests/intel/xe_oa: Use default exponent for some tests
  tests/intel/xe_oa: Use same render copy width and height across tests
  tests/intel/xe_oa: Rewrite the polling small buf test
  tests/intel/xe_oa: Simplify the buffer-fill test
  tests/intel/xe_oa: Use default buffer size for non-zero reason
  tests/intel/xe_oa: Test oa buffer sizes
  tests/intel/xe_oa: Rewrite enable-disable test
  tests/intel/xe_oa: Enable unprivileged-single-ctx-counters and fix it
  tests/intel/xe_oa: Fix mmio_trigger_reports testing
  tests/intel/xe_oa: Set boundaries for OA exponent test
  tests/intel/xe_oa: Try largest buffer size and Xe1

 tests/intel/xe_oa.c | 574 ++++++++++++++++----------------------------
 1 file changed, 205 insertions(+), 369 deletions(-)

-- 
2.34.1

[PATCH i-g-t CI run 01/14] tests/intel/xe_oa: Use static for global variables

[Umesh Nerlige Ramappa]

Use static for mmio_data and hwe.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 0242fd594..3274d472d 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -296,12 +296,12 @@ static int pm_fd = -1;
 static int stream_fd = -1;
 static uint32_t devid;
 
-struct drm_xe_engine_class_instance default_hwe;
+static struct drm_xe_engine_class_instance default_hwe;
 
 static struct intel_xe_perf *intel_xe_perf;
 static uint64_t oa_exp_1_millisec;
 static size_t default_oa_buffer_size;
-struct intel_mmio_data mmio_data;
+static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
 
 static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
-- 
2.34.1

[PATCH i-g-t CI run 02/14] tests/intel/xe_oa: Drop unused macro

[Umesh Nerlige Ramappa]

Drop unused for helper

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 3274d472d..9c74315df 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -4788,13 +4788,6 @@ static const char *xe_engine_class_name(uint32_t engine_class)
 		igt_dynamic_f("%s-%d-%s", xe_engine_class_name(hwe->engine_class), \
 			      hwe->engine_instance, str)
 
-#define __for_one_render_engine_0(hwe) \
-	xe_for_each_engine(drm_fd, hwe) \
-		if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER) \
-			break; \
-	for_each_if(hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER) \
-		igt_dynamic_f("rcs-%d", hwe->engine_instance)
-
 #define __for_one_render_engine(hwe)	      \
 	for (int m = 0, done = 0; !done; m++) \
 		for_each_if(m < xe_number_engines(drm_fd) && \
-- 
2.34.1

[PATCH i-g-t CI run 03/14] tests/intel/xe_oa: Rename oa_exp_1_millisec to oa_exponent_default

[Umesh Nerlige Ramappa]

Rename the global exponent to default so it can be used in different
modes.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 9c74315df..e7d6ac5af 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -299,7 +299,7 @@ static uint32_t devid;
 static struct drm_xe_engine_class_instance default_hwe;
 
 static struct intel_xe_perf *intel_xe_perf;
-static uint64_t oa_exp_1_millisec;
+static uint64_t oa_exponent_default;
 static size_t default_oa_buffer_size;
 static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
@@ -514,7 +514,7 @@ static size_t get_default_oa_buffer_size(int fd)
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -1089,7 +1089,7 @@ init_sys_info(void)
 
 	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
 
-	oa_exp_1_millisec = max_oa_exponent_for_period_lte(1000000);
+	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
 
 	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
 	igt_debug("default_oa_buffer_size: %zu\n", default_oa_buffer_size);
@@ -1114,7 +1114,7 @@ static void test_system_wide_paranoid(void)
 			/* OA unit configuration */
 			DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		};
 		struct intel_xe_oa_open_prop param = {
 			.num_properties = ARRAY_SIZE(properties) / 2,
@@ -1140,7 +1140,7 @@ static void test_system_wide_paranoid(void)
 			/* OA unit configuration */
 			DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		};
 		struct intel_xe_oa_open_prop param = {
 			.num_properties = ARRAY_SIZE(properties) / 2,
@@ -1174,7 +1174,7 @@ static void test_invalid_oa_metric_set_id(void)
 
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, UINT64_MAX,
 	};
 	struct intel_xe_oa_open_prop param = {
@@ -1211,7 +1211,7 @@ static void test_invalid_oa_format_id(void)
 
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, UINT64_MAX, /* No __ff() here */
 	};
 	struct intel_xe_oa_open_prop param = {
@@ -1246,7 +1246,7 @@ static void test_missing_sample_flags(void)
 
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
 	};
 	struct intel_xe_oa_open_prop param = {
@@ -1536,7 +1536,7 @@ static void test_oa_formats(const struct drm_xe_engine_class_instance *hwe)
 		igt_debug("Checking OA format %s\n", format.name);
 
 		open_and_read_2_oa_reports(i,
-					   oa_exp_1_millisec,
+					   oa_exponent_default,
 					   oa_report0,
 					   oa_report1,
 					   false, /* timer reports only */
@@ -3420,7 +3420,7 @@ test_rc6_disable(void)
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -3648,7 +3648,7 @@ test_create_destroy_userspace_config(void)
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET
 	};
@@ -3948,7 +3948,7 @@ static void test_oa_regs_whitelist(const struct drm_xe_engine_class_instance *hw
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = sizeof(properties) / 16,
@@ -4154,7 +4154,7 @@ test_oa_unit_exclusive_stream(bool exponent)
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(0),
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, 0,
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -4216,7 +4216,7 @@ test_oa_unit_exclusive_stream(bool exponent)
 		properties[7] = __ff(test_set->perf_oa_format);
 		properties[9] = hwe->engine_instance;
 		properties[10] = DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT;
-		properties[11] = oa_exp_1_millisec;
+		properties[11] = oa_exponent_default;
 		intel_xe_perf_ioctl_err(drm_fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, &param, EBUSY);
 
 		/* case 2: concurrent access to non-OAG unit should fail */
@@ -4374,7 +4374,7 @@ static void map_oa_buffer_forked_access(const struct drm_xe_engine_class_instanc
 static void mmap_wait_for_periodic_reports(void *oa_vaddr, uint32_t n,
 					   const struct drm_xe_engine_class_instance *hwe)
 {
-	uint32_t period_us = oa_exponent_to_ns(oa_exp_1_millisec) / 1000;
+	uint32_t period_us = oa_exponent_to_ns(oa_exponent_default) / 1000;
 	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
 	uint64_t fmt = test_set->perf_oa_format;
 	uint32_t num_periodic_reports = 0;
@@ -4440,7 +4440,7 @@ static void closed_fd_and_unmapped_access(const struct drm_xe_engine_class_insta
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -4487,7 +4487,7 @@ static void test_mapped_oa_buffer(map_oa_buffer_test_t test_with_fd_open,
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
 	};
 	struct intel_xe_oa_open_prop param = {
-- 
2.34.1

Re: [PATCH i-g-t CI run 03/14] tests/intel/xe_oa: Rename oa_exp_1_millisec to oa_exponent_default

[Dixit, Ashutosh]

On Tue, 18 Feb 2025 12:28:01 -0800, Umesh Nerlige Ramappa wrote:
>
> Rename the global exponent to default so it can be used in different
> modes.
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 34 +++++++++++++++++-----------------
>  1 file changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index 9c74315df..e7d6ac5af 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -299,7 +299,7 @@ static uint32_t devid;
>  static struct drm_xe_engine_class_instance default_hwe;
>
>  static struct intel_xe_perf *intel_xe_perf;
> -static uint64_t oa_exp_1_millisec;
> +static uint64_t oa_exponent_default;
>  static size_t default_oa_buffer_size;
>  static struct intel_mmio_data mmio_data;
>  static igt_render_copyfunc_t render_copy;
> @@ -514,7 +514,7 @@ static size_t get_default_oa_buffer_size(int fd)
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,

My suggestion here would be to (a) either rename this to
oa_exponent_default_1ms, or alternatively, (b) to rename the period
argument of max_oa_exponent_for_period_lte() to period_ns. So it's clear
from the code, without having to guess, what the value of the default
exponent is.

>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
> @@ -1089,7 +1089,7 @@ init_sys_info(void)
>
>	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
>
> -	oa_exp_1_millisec = max_oa_exponent_for_period_lte(1000000);
> +	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);

Re: [PATCH i-g-t CI run 03/14] tests/intel/xe_oa: Rename oa_exp_1_millisec to oa_exponent_default

[Umesh Nerlige Ramappa]

On Fri, Feb 21, 2025 at 04:24:30PM -0800, Dixit, Ashutosh wrote:
>On Tue, 18 Feb 2025 12:28:01 -0800, Umesh Nerlige Ramappa wrote:
>>
>> Rename the global exponent to default so it can be used in different
>> modes.
>>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> ---
>>  tests/intel/xe_oa.c | 34 +++++++++++++++++-----------------
>>  1 file changed, 17 insertions(+), 17 deletions(-)
>>
>> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>> index 9c74315df..e7d6ac5af 100644
>> --- a/tests/intel/xe_oa.c
>> +++ b/tests/intel/xe_oa.c
>> @@ -299,7 +299,7 @@ static uint32_t devid;
>>  static struct drm_xe_engine_class_instance default_hwe;
>>
>>  static struct intel_xe_perf *intel_xe_perf;
>> -static uint64_t oa_exp_1_millisec;
>> +static uint64_t oa_exponent_default;
>>  static size_t default_oa_buffer_size;
>>  static struct intel_mmio_data mmio_data;
>>  static igt_render_copyfunc_t render_copy;
>> @@ -514,7 +514,7 @@ static size_t get_default_oa_buffer_size(int fd)
>>		/* OA unit configuration */
>>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
>> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
>> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>
>My suggestion here would be to (a) either rename this to
>oa_exponent_default_1ms, or alternatively, (b) to rename the period
>argument of max_oa_exponent_for_period_lte() to period_ns. So it's clear
>from the code, without having to guess, what the value of the default
>exponent is.

So, the idea is to set this default to a smaller value like 1000 ns for 
simulation, so that it gets applied to all the tests, hence not using 
any specific values in the name. Thoughts?

Thanks,
Umesh

>
>>	};
>>	struct intel_xe_oa_open_prop param = {
>>		.num_properties = ARRAY_SIZE(properties) / 2,
>> @@ -1089,7 +1089,7 @@ init_sys_info(void)
>>
>>	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
>>
>> -	oa_exp_1_millisec = max_oa_exponent_for_period_lte(1000000);
>> +	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);

Re: [PATCH i-g-t CI run 03/14] tests/intel/xe_oa: Rename oa_exp_1_millisec to oa_exponent_default

[Dixit, Ashutosh]

On Fri, 21 Feb 2025 16:29:03 -0800, Umesh Nerlige Ramappa wrote:
>
> On Fri, Feb 21, 2025 at 04:24:30PM -0800, Dixit, Ashutosh wrote:
> > On Tue, 18 Feb 2025 12:28:01 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >> Rename the global exponent to default so it can be used in different
> >> modes.
> >>
> >> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> >> ---
> >>  tests/intel/xe_oa.c | 34 +++++++++++++++++-----------------
> >>  1 file changed, 17 insertions(+), 17 deletions(-)
> >>
> >> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> >> index 9c74315df..e7d6ac5af 100644
> >> --- a/tests/intel/xe_oa.c
> >> +++ b/tests/intel/xe_oa.c
> >> @@ -299,7 +299,7 @@ static uint32_t devid;
> >>  static struct drm_xe_engine_class_instance default_hwe;
> >>
> >>  static struct intel_xe_perf *intel_xe_perf;
> >> -static uint64_t oa_exp_1_millisec;
> >> +static uint64_t oa_exponent_default;
> >>  static size_t default_oa_buffer_size;
> >>  static struct intel_mmio_data mmio_data;
> >>  static igt_render_copyfunc_t render_copy;
> >> @@ -514,7 +514,7 @@ static size_t get_default_oa_buffer_size(int fd)
> >>		/* OA unit configuration */
> >>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> >>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> >> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> >> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >
> > My suggestion here would be to (a) either rename this to
> > oa_exponent_default_1ms, or alternatively, (b) to rename the period
> > argument of max_oa_exponent_for_period_lte() to period_ns. So it's clear
> > from the code, without having to guess, what the value of the default
> > exponent is.
>
> So, the idea is to set this default to a smaller value like 1000 ns for
> simulation, so that it gets applied to all the tests, hence not using any
> specific values in the name. Thoughts?

Then let's do (b).

[PATCH i-g-t CI run 04/14] tests/intel/xe_oa: Use default exponent for some tests

[Umesh Nerlige Ramappa]

Use the default exponent for below tests:

oa-tlb-validate
short-reads
stress-open-close
mmio-triggered-reports

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index e7d6ac5af..7e40e9257 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2316,7 +2316,6 @@ num_valid_reports_captured(struct intel_xe_oa_open_prop *param,
 static void
 test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
 {
-	int oa_exponent = max_oa_exponent_for_period_lte(30000000);
 	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
@@ -2324,7 +2323,7 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
 
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
 	};
@@ -2342,14 +2341,14 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
 	 */
 	duration = 5LL * NSEC_PER_SEC;
 	num_reports1 = num_valid_reports_captured(&param, &duration, test_set->perf_oa_format);
-	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent);
+	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent_default);
 	igt_debug("expected num reports = %d\n", num_expected_reports);
 	igt_debug("actual num reports = %d\n", num_reports1);
 	igt_assert(num_reports1 > 0.95 * num_expected_reports);
 
 	duration = 5LL * NSEC_PER_SEC;
 	num_reports2 = num_valid_reports_captured(&param, &duration, test_set->perf_oa_format);
-	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent);
+	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent_default);
 	igt_debug("expected num reports = %d\n", num_expected_reports);
 	igt_debug("actual num reports = %d\n", num_reports2);
 	igt_assert(num_reports2 > 0.95 * num_expected_reports);
@@ -2738,7 +2737,6 @@ test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
 static void
 test_short_reads(void)
 {
-	int oa_exponent = max_oa_exponent_for_period_lte(5000);
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
 
@@ -2748,7 +2746,7 @@ test_short_reads(void)
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -3464,7 +3462,6 @@ test_stress_open_close(const struct drm_xe_engine_class_instance *hwe)
 	load_helper_run(HIGH);
 
 	igt_until_timeout(2) {
-		int oa_exponent = 5; /* 5 micro seconds */
 		uint64_t properties[] = {
 			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
 
@@ -3476,7 +3473,7 @@ test_stress_open_close(const struct drm_xe_engine_class_instance *hwe)
 			/* OA unit configuration */
 			DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
 			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
-			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 			DRM_XE_OA_PROPERTY_OA_DISABLED, true,
 			DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
 		};
@@ -3990,12 +3987,11 @@ static void
 __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
 {
 	struct intel_xe_perf_metric_set *test_set = default_test_set;
-	int oa_exponent = max_oa_exponent_for_period_lte(2 * NSEC_PER_SEC);
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
 	};
 	struct intel_xe_oa_open_prop param = {
-- 
2.34.1

Re: [PATCH i-g-t CI run 04/14] tests/intel/xe_oa: Use default exponent for some tests

[Dixit, Ashutosh]

On Tue, 18 Feb 2025 12:28:02 -0800, Umesh Nerlige Ramappa wrote:
>
> Use the default exponent for below tests:
>
> oa-tlb-validate
> short-reads
> stress-open-close
> mmio-triggered-reports

Why? Let's add a reason in the commit message, for all the patches, even
if, in this case, it might be "because it doesn't matter what exponent is
used".

Because these tests were ported from i915 I myself don't quite understand
why some of these tests do what the do. So it will help if we could
document why we are making the changes we are making, and, when needed,
what the effect of the changes is going to be.

Thanks.
--
Ashutosh

Re: [PATCH i-g-t CI run 04/14] tests/intel/xe_oa: Use default exponent for some tests

[Umesh Nerlige Ramappa]

On Fri, Feb 21, 2025 at 04:29:00PM -0800, Dixit, Ashutosh wrote:
>On Tue, 18 Feb 2025 12:28:02 -0800, Umesh Nerlige Ramappa wrote:
>>
>> Use the default exponent for below tests:
>>
>> oa-tlb-validate
>> short-reads
>> stress-open-close
>> mmio-triggered-reports
>
>Why? Let's add a reason in the commit message, for all the patches, even
>if, in this case, it might be "because it doesn't matter what exponent is
>used".

That's open for discussion in this review. My reasoning:

Other than the stress-open-close, none of the other tests actually 
depend on the oa exponent, so we might as well use one value everywhere.

>
>Because these tests were ported from i915 I myself don't quite understand
>why some of these tests do what the do. So it will help if we could
>document why we are making the changes we are making, and, when needed,
>what the effect of the changes is going to be.

There is one patch on top of this series which should adjust the 
exponent value for all tests so that they run quickly on simulation.  
Maybe I should post the v2 with that patch so the context is clear, 
otherwise, I agree that the reason for these changes is unclear.

Thanks,
Umesh

>
>Thanks.
>--
>Ashutosh

Re: [PATCH i-g-t CI run 04/14] tests/intel/xe_oa: Use default exponent for some tests

[Dixit, Ashutosh]

On Fri, 21 Feb 2025 16:37:53 -0800, Umesh Nerlige Ramappa wrote:
>
> On Fri, Feb 21, 2025 at 04:29:00PM -0800, Dixit, Ashutosh wrote:
> > On Tue, 18 Feb 2025 12:28:02 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >> Use the default exponent for below tests:
> >>
> >> oa-tlb-validate
> >> short-reads
> >> stress-open-close
> >> mmio-triggered-reports
> >
> > Why? Let's add a reason in the commit message, for all the patches, even
> > if, in this case, it might be "because it doesn't matter what exponent is
> > used".
>
> That's open for discussion in this review. My reasoning:
>
> Other than the stress-open-close, none of the other tests actually depend
> on the oa exponent, so we might as well use one value everywhere.

Yeah that's what I thought.

>
> >
> > Because these tests were ported from i915 I myself don't quite understand
> > why some of these tests do what the do. So it will help if we could
> > document why we are making the changes we are making, and, when needed,
> > what the effect of the changes is going to be.
>
> There is one patch on top of this series which should adjust the exponent
> value for all tests so that they run quickly on simulation.  Maybe I should
> post the v2 with that patch so the context is clear, otherwise, I agree
> that the reason for these changes is unclear.

Either way, or just state on the patch something like: "this would allow
these tests to run in a reasonable time on slower platforms".

Oops, should have commented on the original series, but ended up commenting
on the CI series :/

Thanks.
--
Ashutosh

Re: [PATCH i-g-t CI run 04/14] tests/intel/xe_oa: Use default exponent for some tests

[Umesh Nerlige Ramappa]

On Fri, Feb 21, 2025 at 04:43:46PM -0800, Dixit, Ashutosh wrote:
>On Fri, 21 Feb 2025 16:37:53 -0800, Umesh Nerlige Ramappa wrote:
>>
>> On Fri, Feb 21, 2025 at 04:29:00PM -0800, Dixit, Ashutosh wrote:
>> > On Tue, 18 Feb 2025 12:28:02 -0800, Umesh Nerlige Ramappa wrote:
>> >>
>> >> Use the default exponent for below tests:
>> >>
>> >> oa-tlb-validate
>> >> short-reads
>> >> stress-open-close
>> >> mmio-triggered-reports
>> >
>> > Why? Let's add a reason in the commit message, for all the patches, even
>> > if, in this case, it might be "because it doesn't matter what exponent is
>> > used".
>>
>> That's open for discussion in this review. My reasoning:
>>
>> Other than the stress-open-close, none of the other tests actually depend
>> on the oa exponent, so we might as well use one value everywhere.
>
>Yeah that's what I thought.
>
>>
>> >
>> > Because these tests were ported from i915 I myself don't quite understand
>> > why some of these tests do what the do. So it will help if we could
>> > document why we are making the changes we are making, and, when needed,
>> > what the effect of the changes is going to be.
>>
>> There is one patch on top of this series which should adjust the exponent
>> value for all tests so that they run quickly on simulation.  Maybe I should
>> post the v2 with that patch so the context is clear, otherwise, I agree
>> that the reason for these changes is unclear.
>
>Either way, or just state on the patch something like: "this would allow
>these tests to run in a reasonable time on slower platforms".

will do
>
>Oops, should have commented on the original series, but ended up commenting
>on the CI series :/

Either should be fine. Both series are identical except that the CI one 
forces 128MB buffer-size test and also runs on DG2.

Thanks,
Umesh

>
>Thanks.
>--
>Ashutosh

Re: [PATCH i-g-t CI run 04/14] tests/intel/xe_oa: Use default exponent for some tests

[Dixit, Ashutosh]

On Fri, 21 Feb 2025 16:46:54 -0800, Umesh Nerlige Ramappa wrote:
>
> On Fri, Feb 21, 2025 at 04:43:46PM -0800, Dixit, Ashutosh wrote:
> > On Fri, 21 Feb 2025 16:37:53 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >> On Fri, Feb 21, 2025 at 04:29:00PM -0800, Dixit, Ashutosh wrote:
> >> > On Tue, 18 Feb 2025 12:28:02 -0800, Umesh Nerlige Ramappa wrote:
> >> >>
> >> >> Use the default exponent for below tests:
> >> >>
> >> >> oa-tlb-validate
> >> >> short-reads
> >> >> stress-open-close
> >> >> mmio-triggered-reports
> >> >
> >> > Why? Let's add a reason in the commit message, for all the patches, even
> >> > if, in this case, it might be "because it doesn't matter what exponent is
> >> > used".
> >>
> >> That's open for discussion in this review. My reasoning:
> >>
> >> Other than the stress-open-close, none of the other tests actually depend
> >> on the oa exponent, so we might as well use one value everywhere.
> >
> > Yeah that's what I thought.
> >
> >>
> >> >
> >> > Because these tests were ported from i915 I myself don't quite understand
> >> > why some of these tests do what the do. So it will help if we could
> >> > document why we are making the changes we are making, and, when needed,
> >> > what the effect of the changes is going to be.
> >>
> >> There is one patch on top of this series which should adjust the exponent
> >> value for all tests so that they run quickly on simulation.  Maybe I should
> >> post the v2 with that patch so the context is clear, otherwise, I agree
> >> that the reason for these changes is unclear.
> >
> > Either way, or just state on the patch something like: "this would allow
> > these tests to run in a reasonable time on slower platforms".
>
> will do
> >
> > Oops, should have commented on the original series, but ended up commenting
> > on the CI series :/
>
> Either should be fine. Both series are identical except that the CI one
> forces 128MB buffer-size test and also runs on DG2.

I went ahead and copied this discussion into the original series and also
added the R-b there so that they can be picked up from a single place.

Thanks.
--
Ashutosh

[PATCH i-g-t CI run 05/14] tests/intel/xe_oa: Use same render copy width and height across tests

[Umesh Nerlige Ramappa]

Use the same width and height for render copy frame across tests.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 39 +++++++++++++++++++--------------------
 1 file changed, 19 insertions(+), 20 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 7e40e9257..aaf92308a 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -303,6 +303,7 @@ static uint64_t oa_exponent_default;
 static size_t default_oa_buffer_size;
 static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
+static uint32_t rc_width, rc_height;
 
 static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
 {
@@ -1089,6 +1090,8 @@ init_sys_info(void)
 
 	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
 
+	rc_width = 1920;
+	rc_height = 1080;
 	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
 
 	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
@@ -1608,7 +1611,7 @@ static void load_helper_run(enum load load)
 
 		while (!lh.exit) {
 			render_copy(lh.ibb,
-				    &lh.src, 0, 0, 1920, 1080,
+				    &lh.src, 0, 0, rc_width, rc_height,
 				    &lh.dst, 0, 0);
 
 			intel_bb_sync(lh.ibb);
@@ -1645,8 +1648,8 @@ static void load_helper_init(void)
 
 	lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, lh.vm, NULL, BATCH_SZ);
 
-	scratch_buf_init(lh.bops, &lh.dst, 1920, 1080, 0);
-	scratch_buf_init(lh.bops, &lh.src, 1920, 1080, 0);
+	scratch_buf_init(lh.bops, &lh.dst, rc_width, rc_height, 0);
+	scratch_buf_init(lh.bops, &lh.src, rc_width, rc_height, 0);
 }
 
 static void load_helper_fini(void)
@@ -3112,8 +3115,6 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	uint64_t delta_ts64, delta_oa32;
 	uint64_t delta_ts64_ns, delta_oa32_ns;
 	uint64_t delta_delta;
-	int width = 800;
-	int height = 600;
 #define INVALID_CTX_ID 0xffffffff
 	uint32_t ctx0_id = INVALID_CTX_ID;
 	uint32_t ctx1_id = INVALID_CTX_ID;
@@ -3125,8 +3126,8 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	bops = buf_ops_create(drm_fd);
 
 	for (int i = 0; i < ARRAY_SIZE(src); i++) {
-		scratch_buf_init(bops, &src[i], width, height, 0xff0000ff);
-		scratch_buf_init(bops, &dst[i], width, height, 0x00ff00ff);
+		scratch_buf_init(bops, &src[i], rc_width, rc_height, 0xff0000ff);
+		scratch_buf_init(bops, &dst[i], rc_width, rc_height, 0x00ff00ff);
 	}
 
 	vm = xe_vm_create(drm_fd, 0, 0);
@@ -3139,7 +3140,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 
 	/* Submit some early, unmeasured, work to the context we want */
 	render_copy(ibb0,
-		    &src[0], 0, 0, width, height,
+		    &src[0], 0, 0, rc_width, rc_height,
 		    &dst[0], 0, 0);
 
 	/* Initialize the context parameter to the perf open ioctl here */
@@ -3175,7 +3176,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 
 	/* This is the work/context that is measured for counter increments */
 	render_copy(ibb0,
-		    &src[0], 0, 0, width, height,
+		    &src[0], 0, 0, rc_width, rc_height,
 		    &dst[0], 0, 0);
 	intel_bb_flush_render(ibb0);
 
@@ -3200,11 +3201,11 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	 * context1
 	 */
 	render_copy(ibb1,
-		    &src[1], 0, 0, width, height,
+		    &src[1], 0, 0, rc_width, rc_height,
 		    &dst[1], 0, 0);
 
 	render_copy(ibb1,
-		    &src[2], 0, 0, width, height,
+		    &src[2], 0, 0, rc_width, rc_height,
 		    &dst[2], 0, 0);
 	intel_bb_flush_render(ibb1);
 
@@ -3325,7 +3326,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	igt_debug("n samples written = %"PRIu64"/%"PRIu64" (%ix%i)\n",
 		  accumulator.deltas[2 + 21],
 		  accumulator.deltas[2 + 26],
-		  width, height);
+		  rc_width, rc_height);
 	accumulator_print(&accumulator, "filtered");
 
 	/* Verify that the work actually happened by comparing the src
@@ -3334,7 +3335,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	buf_map(drm_fd, &src[0], false);
 	buf_map(drm_fd, &dst[0], false);
 
-	ret = memcmp(src[0].ptr, dst[0].ptr, 4 * width * height);
+	ret = memcmp(src[0].ptr, dst[0].ptr, 4 * rc_width * rc_height);
 	intel_buf_unmap(&src[0]);
 	intel_buf_unmap(&dst[0]);
 
@@ -3350,9 +3351,9 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	/* Check that this test passed. The test measures the number of 2x2
 	 * samples written to the render target using the counter A26. For
 	 * OAR, this counter will only have increments relevant to this specific
-	 * context. The value equals the width * height of the rendered work.
+	 * context. The value equals the rc_width * rc_height of the rendered work.
 	 */
-	igt_assert_eq(accumulator.deltas[2 + 26], width * height);
+	igt_assert_eq(accumulator.deltas[2 + 26], rc_width * rc_height);
 
  skip_check:
 	/* Clean up */
@@ -4006,8 +4007,6 @@ __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
 	struct buf_ops *bops;
 	struct intel_bb *ibb;
 	uint32_t context, vm;
-	int height = 600;
-	int width = 800;
 	uint8_t *buf;
 
 	bops = buf_ops_create(drm_fd);
@@ -4019,8 +4018,8 @@ __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
 	memset(dst_buf->ptr, 0, 4096);
 	intel_buf_unmap(dst_buf);
 
-	scratch_buf_init(bops, &src, width, height, 0xff0000ff);
-	scratch_buf_init(bops, &dst, width, height, 0x00ff00ff);
+	scratch_buf_init(bops, &src, rc_width, rc_height, 0xff0000ff);
+	scratch_buf_init(bops, &dst, rc_width, rc_height, 0x00ff00ff);
 
 	vm = xe_vm_create(drm_fd, 0, 0);
 	context = xe_exec_queue_create(drm_fd, vm, hwe, 0);
@@ -4039,7 +4038,7 @@ __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
 
 	if (render_copy)
 		render_copy(ibb,
-			    &src, 0, 0, width, height,
+			    &src, 0, 0, rc_width, rc_height,
 			    &dst, 0, 0);
 
 	emit_mmio_triggered_report(ibb, 0xc0ffee22);
-- 
2.34.1

[PATCH i-g-t CI run 06/14] tests/intel/xe_oa: Rewrite the polling small buf test

[Umesh Nerlige Ramappa]

Use mmio reads as a side-channel to determine if reports are available
and ensure that poll will return with POLLIN set. Then provide a small
buffer to force ENOSPC error. Then poll with a timeout of 0 to check if
POLLIN is still set.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 64 +++++++++++++++++++++++++--------------------
 1 file changed, 35 insertions(+), 29 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index aaf92308a..5792ffec2 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2216,7 +2216,6 @@ static void test_polling(uint64_t requested_oa_period,
  */
 static void test_polling_small_buf(void)
 {
-	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
 
@@ -2226,50 +2225,57 @@ static void test_polling_small_buf(void)
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
 		.properties_ptr = to_user_pointer(properties),
 	};
-	uint32_t test_duration = 80 * 1000 * 1000;
-	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
-	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
-	int n_expect_read_bytes = n_expected_reports * sample_size;
-	struct timespec ts = {};
-	int n_bytes_read = 0;
-	uint32_t n_polls = 0;
+	int report_size = get_oa_format(default_test_set->perf_oa_format).size;
+	u32 oa_tail, prev_tail;
+	struct pollfd pollfd;
+	uint8_t buf[10];
+	int ret, i = 0;
+
+	intel_register_access_init(&mmio_data,
+				   igt_device_get_pci_device(drm_fd), 0);
 
 	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
 	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
-	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
-
-	while (igt_nsec_elapsed(&ts) < test_duration) {
-		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
 
-		ppoll(&pollfd, 1, NULL, NULL);
-		if (pollfd.revents & POLLIN) {
-			uint8_t buf[1024];
-			int ret;
+#define OAG_OATAILPTR	(0xdb04)
+	/* Save the current tail */
+	prev_tail = oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
 
-			ret = read(stream_fd, buf, sizeof(buf));
-			if (ret >= 0)
-				n_bytes_read += ret;
-		}
+	/* Kickstart the capture */
+	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
 
-		n_polls++;
+	/* Wait for 5 reports */
+	while ((oa_tail - prev_tail) < (5 * report_size)) {
+		usleep(1000);
+		oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
+		if (i++ > 10)
+			break;
 	}
 
-	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
-		 n_bytes_read, n_expect_read_bytes,
-		 n_bytes_read * 100.0f / n_expect_read_bytes,
-		 n_polls);
+	intel_register_access_fini(&mmio_data);
 
-	__perf_close(stream_fd);
+	/* Just read one report and expect ENOSPC */
+	pollfd.fd = stream_fd;
+	pollfd.events = POLLIN;
+	poll(&pollfd, 1, 1000);
+	igt_assert(pollfd.revents & POLLIN);
+	errno = 0;
+	ret = read(stream_fd, buf, sizeof(buf));
+	igt_assert_eq(ret, -1);
+	igt_assert_eq(errno, ENOSPC);
 
-	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
-		   0.20 * n_expect_read_bytes);
+	/* Poll with 0 timeout and expect POLLIN flag to be set */
+	poll(&pollfd, 1, 0);
+	igt_assert(pollfd.revents & POLLIN);
+
+	__perf_close(stream_fd);
 }
 
 static int
-- 
2.34.1

Re: [PATCH i-g-t CI run 06/14] tests/intel/xe_oa: Rewrite the polling small buf test

[Dixit, Ashutosh]

On Tue, 18 Feb 2025 12:28:04 -0800, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> Use mmio reads as a side-channel to determine if reports are available
> and ensure that poll will return with POLLIN set. Then provide a small
> buffer to force ENOSPC error. Then poll with a timeout of 0 to check if
> POLLIN is still set.

Will need a reason for doing this here. But see below.

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 64 +++++++++++++++++++++++++--------------------
>  1 file changed, 35 insertions(+), 29 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index aaf92308a..5792ffec2 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -2216,7 +2216,6 @@ static void test_polling(uint64_t requested_oa_period,
>   */
>  static void test_polling_small_buf(void)
>  {
> -	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
>	uint64_t properties[] = {
>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>
> @@ -2226,50 +2225,57 @@ static void test_polling_small_buf(void)
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
>		.properties_ptr = to_user_pointer(properties),
>	};
> -	uint32_t test_duration = 80 * 1000 * 1000;
> -	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
> -	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
> -	int n_expect_read_bytes = n_expected_reports * sample_size;
> -	struct timespec ts = {};
> -	int n_bytes_read = 0;
> -	uint32_t n_polls = 0;
> +	int report_size = get_oa_format(default_test_set->perf_oa_format).size;
> +	u32 oa_tail, prev_tail;
> +	struct pollfd pollfd;
> +	uint8_t buf[10];
> +	int ret, i = 0;
> +
> +	intel_register_access_init(&mmio_data,
> +				   igt_device_get_pci_device(drm_fd), 0);
>
>	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
>	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
> -	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> -
> -	while (igt_nsec_elapsed(&ts) < test_duration) {
> -		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
>
> -		ppoll(&pollfd, 1, NULL, NULL);
> -		if (pollfd.revents & POLLIN) {
> -			uint8_t buf[1024];
> -			int ret;
> +#define OAG_OATAILPTR	(0xdb04)
> +	/* Save the current tail */
> +	prev_tail = oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
>
> -			ret = read(stream_fd, buf, sizeof(buf));
> -			if (ret >= 0)
> -				n_bytes_read += ret;
> -		}
> +	/* Kickstart the capture */
> +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>
> -		n_polls++;
> +	/* Wait for 5 reports */

Wait for 5 reports or 10 ms ?


> +	while ((oa_tail - prev_tail) < (5 * report_size)) {
> +		usleep(1000);
> +		oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
> +		if (i++ > 10)

So on slow platforms we might not get any reports in 10 ms? The idea here
should be to not have any timing dependence? So if we want to wait for 5
reports, just wait for 5 reports?

We tried doing this for the mmap OA buffer: see
mmap_wait_for_periodic_reports(), the function waits indefinitely.

So if this is done I am not sure if the intel_register_read() approach is
needed (but I didn't think of doing that :). But I guess we can use it to
see when there are N reports available.

Longer term it would be nice to have a centralized function
wait_for_n_reports(int n) or something like that which different tests can
use.

> +			break;
>	}
>
> -	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
> -		 n_bytes_read, n_expect_read_bytes,
> -		 n_bytes_read * 100.0f / n_expect_read_bytes,
> -		 n_polls);
> +	intel_register_access_fini(&mmio_data);
>
> -	__perf_close(stream_fd);
> +	/* Just read one report and expect ENOSPC */
> +	pollfd.fd = stream_fd;
> +	pollfd.events = POLLIN;
> +	poll(&pollfd, 1, 1000);
> +	igt_assert(pollfd.revents & POLLIN);

Is the assumption here that the kernel timer is firing every 5 ms (so if
we've waited for 10 ms POLLIN must be set since the timer is firing every 5
ms)? I am not sure if that 5 ms is uapi. Or is it? Actually I was thinking
of changing that 5 ms time or changing the timer to a delayed work.

> +	errno = 0;
> +	ret = read(stream_fd, buf, sizeof(buf));
> +	igt_assert_eq(ret, -1);
> +	igt_assert_eq(errno, ENOSPC);

This part looks ok, it's uapi.

>
> -	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
> -		   0.20 * n_expect_read_bytes);
> +	/* Poll with 0 timeout and expect POLLIN flag to be set */
> +	poll(&pollfd, 1, 0);
> +	igt_assert(pollfd.revents & POLLIN);
> +
> +	__perf_close(stream_fd);

How about just reading N reports using a small buffer for this test,
however long it takes? N can 5 or 10.

Thanks.
--
Ashutosh

PS: how about separating out the patches which currently have R-b into a
separate series and merging them first?

Re: [PATCH i-g-t CI run 06/14] tests/intel/xe_oa: Rewrite the polling small buf test

[Umesh Nerlige Ramappa]

On Mon, Feb 24, 2025 at 12:11:37PM -0800, Dixit, Ashutosh wrote:
>On Tue, 18 Feb 2025 12:28:04 -0800, Umesh Nerlige Ramappa wrote:
>>
>
>Hi Umesh,
>
>> Use mmio reads as a side-channel to determine if reports are available
>> and ensure that poll will return with POLLIN set. Then provide a small
>> buffer to force ENOSPC error. Then poll with a timeout of 0 to check if
>> POLLIN is still set.
>
>Will need a reason for doing this here. But see below.
>
>>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> ---
>>  tests/intel/xe_oa.c | 64 +++++++++++++++++++++++++--------------------
>>  1 file changed, 35 insertions(+), 29 deletions(-)
>>
>> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>> index aaf92308a..5792ffec2 100644
>> --- a/tests/intel/xe_oa.c
>> +++ b/tests/intel/xe_oa.c
>> @@ -2216,7 +2216,6 @@ static void test_polling(uint64_t requested_oa_period,
>>   */
>>  static void test_polling_small_buf(void)
>>  {
>> -	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
>>	uint64_t properties[] = {
>>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>>
>> @@ -2226,50 +2225,57 @@ static void test_polling_small_buf(void)
>>		/* OA unit configuration */
>>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
>> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
>> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>>		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
>>	};
>>	struct intel_xe_oa_open_prop param = {
>>		.num_properties = ARRAY_SIZE(properties) / 2,
>>		.properties_ptr = to_user_pointer(properties),
>>	};
>> -	uint32_t test_duration = 80 * 1000 * 1000;
>> -	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
>> -	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
>> -	int n_expect_read_bytes = n_expected_reports * sample_size;
>> -	struct timespec ts = {};
>> -	int n_bytes_read = 0;
>> -	uint32_t n_polls = 0;
>> +	int report_size = get_oa_format(default_test_set->perf_oa_format).size;
>> +	u32 oa_tail, prev_tail;
>> +	struct pollfd pollfd;
>> +	uint8_t buf[10];
>> +	int ret, i = 0;
>> +
>> +	intel_register_access_init(&mmio_data,
>> +				   igt_device_get_pci_device(drm_fd), 0);
>>
>>	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
>>	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
>> -	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>> -
>> -	while (igt_nsec_elapsed(&ts) < test_duration) {
>> -		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
>>
>> -		ppoll(&pollfd, 1, NULL, NULL);
>> -		if (pollfd.revents & POLLIN) {
>> -			uint8_t buf[1024];
>> -			int ret;
>> +#define OAG_OATAILPTR	(0xdb04)
>> +	/* Save the current tail */
>> +	prev_tail = oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
>>
>> -			ret = read(stream_fd, buf, sizeof(buf));
>> -			if (ret >= 0)
>> -				n_bytes_read += ret;
>> -		}
>> +	/* Kickstart the capture */
>> +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>>
>> -		n_polls++;
>> +	/* Wait for 5 reports */
>
>Wait for 5 reports or 10 ms ?
>
>
>> +	while ((oa_tail - prev_tail) < (5 * report_size)) {
>> +		usleep(1000);
>> +		oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
>> +		if (i++ > 10)
>
>So on slow platforms we might not get any reports in 10 ms? The idea here
>should be to not have any timing dependence? So if we want to wait for 5
>reports, just wait for 5 reports?

Oh, I think the loop was stuck while debugging something, so had added a 
counter to bail out in 10 iterations. I will remove that. We only need 
to wait for 5 reports.

>
>We tried doing this for the mmap OA buffer: see
>mmap_wait_for_periodic_reports(), the function waits indefinitely.

You mean this:

while (num_periodic_reports < n) {
	usleep(4 * n * period_us);
	num_periodic_reports = 0;
	for (reports = (uint32_t *)oa_vaddr;
	     reports[0] && oa_timestamp(reports, fmt) && oa_report_is_periodic(reports);
	     reports += get_oa_format(fmt).size) {
		num_periodic_reports++;
	}
}

Well.. if your reports start coming in fast enough, then you would just 
spin in the inner for loop. Maybe break the inner for loop when 
num_periodic_reports >= n;

>
>So if this is done I am not sure if the intel_register_read() approach is
>needed (but I didn't think of doing that :). But I guess we can use it to
>see when there are N reports available.
>
>Longer term it would be nice to have a centralized function
>wait_for_n_reports(int n) or something like that which different tests can
>use.

Agree, except that some tests will read the actual reports, while others 
just want to take a peek at how many reports are available without 
reading them. Since mmap is also a feature under test, I took the easier 
approach. We can always refine it if we find something better.

>
>> +			break;
>>	}
>>
>> -	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
>> -		 n_bytes_read, n_expect_read_bytes,
>> -		 n_bytes_read * 100.0f / n_expect_read_bytes,
>> -		 n_polls);
>> +	intel_register_access_fini(&mmio_data);
>>
>> -	__perf_close(stream_fd);
>> +	/* Just read one report and expect ENOSPC */
>> +	pollfd.fd = stream_fd;
>> +	pollfd.events = POLLIN;
>> +	poll(&pollfd, 1, 1000);
>> +	igt_assert(pollfd.revents & POLLIN);
>
>Is the assumption here that the kernel timer is firing every 5 ms (so if
>we've waited for 10 ms POLLIN must be set since the timer is firing every 5
>ms)? I am not sure if that 5 ms is uapi. Or is it? Actually I was thinking
>of changing that 5 ms time or changing the timer to a delayed work.

But here I am waiting 1000ms in the poll above. That should be 
sufficient for POLLIN  to be set. If not, we could set the timeout to a 
large value (a few seconds).

>
>> +	errno = 0;
>> +	ret = read(stream_fd, buf, sizeof(buf));
>> +	igt_assert_eq(ret, -1);
>> +	igt_assert_eq(errno, ENOSPC);
>
>This part looks ok, it's uapi.
>

Note:
ENOSPC is returned only if the buffer is small enough that not even one 
report will fit in. Initially I had a 600 byte buffer, but I did not get 
ENOSPC. Instead I got 576 in ret which I think is the correct behavior.

>>
>> -	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
>> -		   0.20 * n_expect_read_bytes);
>> +	/* Poll with 0 timeout and expect POLLIN flag to be set */
>> +	poll(&pollfd, 1, 0);
>> +	igt_assert(pollfd.revents & POLLIN);
>> +
>> +	__perf_close(stream_fd);
>
>How about just reading N reports using a small buffer for this test,
>however long it takes? N can 5 or 10.

Not sure I understand. You mean at this stage of the test, read 5/10 
reports? OR just alter the entire test somehow to do something 
different?

I thought the test was specifically testing that POLLIN is still set 
after an ENOSPC error, so I have written it for that case alone. The 0 
timeout will bypass the wait in the poll so that we only get the state 
of POLLIN.

Thanks,
Umesh


>
>Thanks.
>--
>Ashutosh
>
>PS: how about separating out the patches which currently have R-b into a
>separate series and merging them first?

Re: [PATCH i-g-t CI run 06/14] tests/intel/xe_oa: Rewrite the polling small buf test

[Umesh Nerlige Ramappa]

On Mon, Feb 24, 2025 at 02:56:05PM -0800, Umesh Nerlige Ramappa wrote:
>On Mon, Feb 24, 2025 at 12:11:37PM -0800, Dixit, Ashutosh wrote:
>>On Tue, 18 Feb 2025 12:28:04 -0800, Umesh Nerlige Ramappa wrote:
>>>
>>
>>Hi Umesh,
>>
>>>Use mmio reads as a side-channel to determine if reports are available
>>>and ensure that poll will return with POLLIN set. Then provide a small
>>>buffer to force ENOSPC error. Then poll with a timeout of 0 to check if
>>>POLLIN is still set.
>>
>>Will need a reason for doing this here. But see below.
>>
>>>
>>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>>---
>>> tests/intel/xe_oa.c | 64 +++++++++++++++++++++++++--------------------
>>> 1 file changed, 35 insertions(+), 29 deletions(-)
>>>
>>>diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>>>index aaf92308a..5792ffec2 100644
>>>--- a/tests/intel/xe_oa.c
>>>+++ b/tests/intel/xe_oa.c
>>>@@ -2216,7 +2216,6 @@ static void test_polling(uint64_t requested_oa_period,
>>>  */
>>> static void test_polling_small_buf(void)
>>> {
>>>-	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
>>>	uint64_t properties[] = {
>>>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>>>
>>>@@ -2226,50 +2225,57 @@ static void test_polling_small_buf(void)
>>>		/* OA unit configuration */
>>>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>>>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
>>>-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
>>>+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>>>		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
>>>	};
>>>	struct intel_xe_oa_open_prop param = {
>>>		.num_properties = ARRAY_SIZE(properties) / 2,
>>>		.properties_ptr = to_user_pointer(properties),
>>>	};
>>>-	uint32_t test_duration = 80 * 1000 * 1000;
>>>-	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
>>>-	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
>>>-	int n_expect_read_bytes = n_expected_reports * sample_size;
>>>-	struct timespec ts = {};
>>>-	int n_bytes_read = 0;
>>>-	uint32_t n_polls = 0;
>>>+	int report_size = get_oa_format(default_test_set->perf_oa_format).size;
>>>+	u32 oa_tail, prev_tail;
>>>+	struct pollfd pollfd;
>>>+	uint8_t buf[10];
>>>+	int ret, i = 0;
>>>+
>>>+	intel_register_access_init(&mmio_data,
>>>+				   igt_device_get_pci_device(drm_fd), 0);
>>>
>>>	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
>>>	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
>>>-	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>>>-
>>>-	while (igt_nsec_elapsed(&ts) < test_duration) {
>>>-		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
>>>
>>>-		ppoll(&pollfd, 1, NULL, NULL);
>>>-		if (pollfd.revents & POLLIN) {
>>>-			uint8_t buf[1024];
>>>-			int ret;
>>>+#define OAG_OATAILPTR	(0xdb04)
>>>+	/* Save the current tail */
>>>+	prev_tail = oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
>>>
>>>-			ret = read(stream_fd, buf, sizeof(buf));
>>>-			if (ret >= 0)
>>>-				n_bytes_read += ret;
>>>-		}
>>>+	/* Kickstart the capture */
>>>+	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>>>
>>>-		n_polls++;
>>>+	/* Wait for 5 reports */
>>
>>Wait for 5 reports or 10 ms ?
>>
>>
>>>+	while ((oa_tail - prev_tail) < (5 * report_size)) {
>>>+		usleep(1000);
>>>+		oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
>>>+		if (i++ > 10)
>>
>>So on slow platforms we might not get any reports in 10 ms? The idea here
>>should be to not have any timing dependence? So if we want to wait for 5
>>reports, just wait for 5 reports?

Oh, I think the loop was stuck while debugging something, so had added a 
counter to bail out in 10 iterations. I will remove that. We only need to 
wait for 5 reports.

>>
>>We tried doing this for the mmap OA buffer: see
>>mmap_wait_for_periodic_reports(), the function waits indefinitely.

You mean this:

while (num_periodic_reports < n) {
	usleep(4 * n * period_us);
	num_periodic_reports = 0;
	for (reports = (uint32_t *)oa_vaddr;
	     reports[0] && oa_timestamp(reports, fmt) && oa_report_is_periodic(reports);
	     reports += get_oa_format(fmt).size) {
		num_periodic_reports++;
	}
}

Well.. if your reports start coming in fast enough, then you would just spin 
in the inner for loop. Maybe break the inner for loop when 
num_periodic_reports >= n;

>>
>>So if this is done I am not sure if the intel_register_read() approach is
>>needed (but I didn't think of doing that :). But I guess we can use it to
>>see when there are N reports available.
>>
>>Longer term it would be nice to have a centralized function
>>wait_for_n_reports(int n) or something like that which different tests can
>>use.

Agree, except that some tests will read the actual reports, while others ust 
want to take a peek at how many reports are available without reading them. 
Since mmap is also a feature under test, I took the easier approach. We can 
always refine it if we find something better.
>
>>
>>>+			break;
>>>	}
>>>
>>>-	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
>>>-		 n_bytes_read, n_expect_read_bytes,
>>>-		 n_bytes_read * 100.0f / n_expect_read_bytes,
>>>-		 n_polls);
>>>+	intel_register_access_fini(&mmio_data);
>>>
>>>-	__perf_close(stream_fd);
>>>+	/* Just read one report and expect ENOSPC */
>>>+	pollfd.fd = stream_fd;
>>>+	pollfd.events = POLLIN;
>>>+	poll(&pollfd, 1, 1000);
>>>+	igt_assert(pollfd.revents & POLLIN);
>>
>>Is the assumption here that the kernel timer is firing every 5 ms (so if
>>we've waited for 10 ms POLLIN must be set since the timer is firing every 5
>>ms)? I am not sure if that 5 ms is uapi. Or is it? Actually I was thinking

But here I am waiting 1000ms in the poll above. That should be sufficient 
for POLLIN  to be set. If not, we could set the timeout to a large value (a 
few seconds).

>>
>>>+	errno = 0;
>>>+	ret = read(stream_fd, buf, sizeof(buf));
>>>+	igt_assert_eq(ret, -1);
>>>+	igt_assert_eq(errno, ENOSPC);
>>
>>This part looks ok, it's uapi.
>>

Note:
ENOSPC is returned only if the buffer is small enough that not even one 
report will fit in. Initially I had a 600 byte buffer, but I did not get 
ENOSPC. Instead I got 576 in ret which I think is the correct behavior.

>>>
>>>-	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
>>>-		   0.20 * n_expect_read_bytes);
>>>+	/* Poll with 0 timeout and expect POLLIN flag to be set */
>>>+	poll(&pollfd, 1, 0);
>>>+	igt_assert(pollfd.revents & POLLIN);
>>>+
>>>+	__perf_close(stream_fd);
>>
>>How about just reading N reports using a small buffer for this test,
>>however long it takes? N can 5 or 10.

Not sure I understand. You mean at this stage of the test, read 5/10 
reports? OR just alter the entire test somehow to do something 
different?

I thought the test was specifically testing that POLLIN is still set 
after an ENOSPC error, so I have written it for that case alone. The 0 
timeout will bypass the wait in the poll so that we only get the state 
of POLLIN.

Thanks,
Umesh


>>
>>Thanks.
>>--
>>Ashutosh
>>
>>PS: how about separating out the patches which currently have R-b into a
>>separate series and merging them first?

Re: [PATCH i-g-t CI run 06/14] tests/intel/xe_oa: Rewrite the polling small buf test

[Dixit, Ashutosh]

On Mon, 24 Feb 2025 16:02:05 -0800, Umesh Nerlige Ramappa wrote:
> 


Hi Umesh,

You seem to have responded twice on the CI series. I have responded on this
on the original series. Let's keep to the original series if possible. I am
monitoring the R-b's etc. there.

Thanks.
--
Ashutosh


> On Mon, Feb 24, 2025 at 02:56:05PM -0800, Umesh Nerlige Ramappa wrote:
> > On Mon, Feb 24, 2025 at 12:11:37PM -0800, Dixit, Ashutosh wrote:
> >> On Tue, 18 Feb 2025 12:28:04 -0800, Umesh Nerlige Ramappa wrote:
> >>> 
> >> 
> >> Hi Umesh,
> >> 
> >>> Use mmio reads as a side-channel to determine if reports are available
> >>> and ensure that poll will return with POLLIN set. Then provide a small
> >>> buffer to force ENOSPC error. Then poll with a timeout of 0 to check if
> >>> POLLIN is still set.
> >> 
> >> Will need a reason for doing this here. But see below.
> >> 
> >>> 
> >>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> >>> ---
> >>> tests/intel/xe_oa.c | 64 +++++++++++++++++++++++++--------------------
> >>> 1 file changed, 35 insertions(+), 29 deletions(-)
> >>> 
> >>> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> >>> index aaf92308a..5792ffec2 100644
> >>> --- a/tests/intel/xe_oa.c
> >>> +++ b/tests/intel/xe_oa.c
> >>> @@ -2216,7 +2216,6 @@ static void test_polling(uint64_t requested_oa_period,
> >>>  */
> >>> static void test_polling_small_buf(void)
> >>> {
> >>> -	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
> >>> 	uint64_t properties[] = {
> >>> 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
> >>> 
> >>> @@ -2226,50 +2225,57 @@ static void test_polling_small_buf(void)
> >>> 		/* OA unit configuration */
> >>> 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> >>> 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> >>> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> >>> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >>> 		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
> >>> 	};
> >>> 	struct intel_xe_oa_open_prop param = {
> >>> 		.num_properties = ARRAY_SIZE(properties) / 2,
> >>> 		.properties_ptr = to_user_pointer(properties),
> >>> 	};
> >>> -	uint32_t test_duration = 80 * 1000 * 1000;
> >>> -	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
> >>> -	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
> >>> -	int n_expect_read_bytes = n_expected_reports * sample_size;
> >>> -	struct timespec ts = {};
> >>> -	int n_bytes_read = 0;
> >>> -	uint32_t n_polls = 0;
> >>> +	int report_size = get_oa_format(default_test_set->perf_oa_format).size;
> >>> +	u32 oa_tail, prev_tail;
> >>> +	struct pollfd pollfd;
> >>> +	uint8_t buf[10];
> >>> +	int ret, i = 0;
> >>> +
> >>> +	intel_register_access_init(&mmio_data,
> >>> +				   igt_device_get_pci_device(drm_fd), 0);
> >>> 
> >>> 	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
> >>> 	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
> >>> -	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> >>> -
> >>> -	while (igt_nsec_elapsed(&ts) < test_duration) {
> >>> -		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
> >>> 
> >>> -		ppoll(&pollfd, 1, NULL, NULL);
> >>> -		if (pollfd.revents & POLLIN) {
> >>> -			uint8_t buf[1024];
> >>> -			int ret;
> >>> +#define OAG_OATAILPTR	(0xdb04)
> >>> +	/* Save the current tail */
> >>> +	prev_tail = oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
> >>> 
> >>> -			ret = read(stream_fd, buf, sizeof(buf));
> >>> -			if (ret >= 0)
> >>> -				n_bytes_read += ret;
> >>> -		}
> >>> +	/* Kickstart the capture */
> >>> +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> >>> 
> >>> -		n_polls++;
> >>> +	/* Wait for 5 reports */
> >> 
> >> Wait for 5 reports or 10 ms ?
> >> 
> >> 
> >>> +	while ((oa_tail - prev_tail) < (5 * report_size)) {
> >>> +		usleep(1000);
> >>> +		oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
> >>> +		if (i++ > 10)
> >> 
> >> So on slow platforms we might not get any reports in 10 ms? The idea here
> >> should be to not have any timing dependence? So if we want to wait for 5
> >> reports, just wait for 5 reports?
> 
> Oh, I think the loop was stuck while debugging something, so had added a
> counter to bail out in 10 iterations. I will remove that. We only need to
> wait for 5 reports.
> 
> >> 
> >> We tried doing this for the mmap OA buffer: see
> >> mmap_wait_for_periodic_reports(), the function waits indefinitely.
> 
> You mean this:
> 
> while (num_periodic_reports < n) {
> 	usleep(4 * n * period_us);
> 	num_periodic_reports = 0;
> 	for (reports = (uint32_t *)oa_vaddr;
> 	     reports[0] && oa_timestamp(reports, fmt) && oa_report_is_periodic(reports);
> 	     reports += get_oa_format(fmt).size) {
> 		num_periodic_reports++;
> 	}
> }
> 
> Well.. if your reports start coming in fast enough, then you would just
> spin in the inner for loop. Maybe break the inner for loop when
> num_periodic_reports >= n;
> 
> >> 
> >> So if this is done I am not sure if the intel_register_read() approach is
> >> needed (but I didn't think of doing that :). But I guess we can use it to
> >> see when there are N reports available.
> >> 
> >> Longer term it would be nice to have a centralized function
> >> wait_for_n_reports(int n) or something like that which different tests can
> >> use.
> 
> Agree, except that some tests will read the actual reports, while others
> ust want to take a peek at how many reports are available without reading
> them. Since mmap is also a feature under test, I took the easier
> approach. We can always refine it if we find something better.
> > 
> >> 
> >>> +			break;
> >>> 	}
> >>> 
> >>> -	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
> >>> -		 n_bytes_read, n_expect_read_bytes,
> >>> -		 n_bytes_read * 100.0f / n_expect_read_bytes,
> >>> -		 n_polls);
> >>> +	intel_register_access_fini(&mmio_data);
> >>> 
> >>> -	__perf_close(stream_fd);
> >>> +	/* Just read one report and expect ENOSPC */
> >>> +	pollfd.fd = stream_fd;
> >>> +	pollfd.events = POLLIN;
> >>> +	poll(&pollfd, 1, 1000);
> >>> +	igt_assert(pollfd.revents & POLLIN);
> >> 
> >> Is the assumption here that the kernel timer is firing every 5 ms (so if
> >> we've waited for 10 ms POLLIN must be set since the timer is firing every 5
> >> ms)? I am not sure if that 5 ms is uapi. Or is it? Actually I was thinking
> 
> But here I am waiting 1000ms in the poll above. That should be sufficient
> for POLLIN  to be set. If not, we could set the timeout to a large value (a
> few seconds).
> 
> >> 
> >>> +	errno = 0;
> >>> +	ret = read(stream_fd, buf, sizeof(buf));
> >>> +	igt_assert_eq(ret, -1);
> >>> +	igt_assert_eq(errno, ENOSPC);
> >> 
> >> This part looks ok, it's uapi.
> >> 
> 
> Note:
> ENOSPC is returned only if the buffer is small enough that not even one
> report will fit in. Initially I had a 600 byte buffer, but I did not get
> ENOSPC. Instead I got 576 in ret which I think is the correct behavior.
> 
> >>> 
> >>> -	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
> >>> -		   0.20 * n_expect_read_bytes);
> >>> +	/* Poll with 0 timeout and expect POLLIN flag to be set */
> >>> +	poll(&pollfd, 1, 0);
> >>> +	igt_assert(pollfd.revents & POLLIN);
> >>> +
> >>> +	__perf_close(stream_fd);
> >> 
> >> How about just reading N reports using a small buffer for this test,
> >> however long it takes? N can 5 or 10.
> 
> Not sure I understand. You mean at this stage of the test, read 5/10
> reports? OR just alter the entire test somehow to do something different?
> 
> I thought the test was specifically testing that POLLIN is still set after
> an ENOSPC error, so I have written it for that case alone. The 0 timeout
> will bypass the wait in the poll so that we only get the state of POLLIN.
> 
> Thanks,
> Umesh
> 
> 
> >> 
> >> Thanks.
> >> --
> >> Ashutosh
> >> 
> >> PS: how about separating out the patches which currently have R-b into a
> >> separate series and merging them first?

[PATCH i-g-t CI run 07/14] tests/intel/xe_oa: Simplify the buffer-fill test

[Umesh Nerlige Ramappa]

We only want to test that the BUFFER OVERFLOW status is set when we do
not read the OA stream data in time. To do so, keeping reading zero
bytes of data until you hit a buffer overflow.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 135 +++++++++-----------------------------------
 1 file changed, 26 insertions(+), 109 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 5792ffec2..fc03b74af 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -304,6 +304,7 @@ static size_t default_oa_buffer_size;
 static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
 static uint32_t rc_width, rc_height;
+static uint32_t buffer_fill_size;
 
 static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
 {
@@ -1092,6 +1093,7 @@ init_sys_info(void)
 
 	rc_width = 1920;
 	rc_height = 1080;
+	buffer_fill_size = SZ_16M;
 	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
 
 	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
@@ -2370,11 +2372,7 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
 static void
 test_buffer_fill(const struct drm_xe_engine_class_instance *hwe)
 {
-	/* ~5 micro second period */
-	int oa_exponent = max_oa_exponent_for_period_lte(5000);
-	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
 	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
-	uint64_t fmt = test_set->perf_oa_format;
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
 
@@ -2383,126 +2381,45 @@ test_buffer_fill(const struct drm_xe_engine_class_instance *hwe)
 
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
-		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
+		DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, buffer_fill_size,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
 		.properties_ptr = to_user_pointer(properties),
 	};
-	size_t report_size = get_oa_format(fmt).size;
-	int buf_size = 65536 * report_size;
-	uint8_t *buf = malloc(buf_size);
-	int len;
-	int n_full_oa_reports = default_oa_buffer_size / report_size;
-	uint64_t fill_duration = n_full_oa_reports * oa_period;
-	uint32_t *last_periodic_report = malloc(report_size);
+	uint64_t oa_period = oa_exponent_to_ns(oa_exponent_default);
+	char *buf = malloc(1024);
+	bool overflow_seen;
 	u32 oa_status;
+	int len;
 
-	igt_assert(fill_duration < 1000000000);
-
+	igt_debug("oa_period %s\n", pretty_print_oa_period(oa_period));
 	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
         set_fd_flags(stream_fd, O_CLOEXEC);
 
-	for (int i = 0; i < 5; i++) {
-		bool overflow_seen;
-		uint32_t n_periodic_reports;
-		uint32_t first_timestamp = 0, last_timestamp = 0;
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
-
-		nanosleep(&(struct timespec){ .tv_sec = 0,
-					      .tv_nsec = fill_duration * 1.25 },
-			  NULL);
-again:
-		oa_status = 0;
-		while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
-			;
-
-		if (errno == EIO) {
-			oa_status = get_stream_status(stream_fd);
-			igt_debug("oa_status %#x\n", oa_status);
-			overflow_seen = oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW;
-			igt_assert_eq(overflow_seen, true);
-			goto again;
-		}
-		igt_assert_neq(len, -1);
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
-
-		igt_debug("fill_duration = %"PRIu64"ns, oa_exponent = %u\n",
-			  fill_duration, oa_exponent);
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
-
-		nanosleep(&(struct timespec){ .tv_sec = 0,
-					.tv_nsec = fill_duration / 2 },
-			NULL);
-
-		n_periodic_reports = 0;
-
-		/* Because of the race condition between notification of new
-		 * reports and reports landing in memory, we need to rely on
-		 * timestamps to figure whether we've read enough of them.
-		 */
-		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
-
-			igt_debug("dts=%u elapsed=%"PRIu64" duration=%"PRIu64"\n",
-				  last_timestamp - first_timestamp,
-				  (last_timestamp - first_timestamp) * oa_period,
-				  fill_duration / 2);
-again_1:
-			oa_status = 0;
-			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
-				;
-			if (errno == EIO) {
-				oa_status = get_stream_status(stream_fd);
-				igt_debug("oa_status %#x\n", oa_status);
-				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
-				goto again_1;
-			}
-			igt_assert_neq(len, -1);
-
-			for (int offset = 0; offset < len; offset += report_size) {
-				uint32_t *report = (void *) (buf + offset);
-
-				igt_debug(" > report ts=%"PRIu64""
-					  " ts_delta_last_periodic=%"PRIu64" is_timer=%i ctx_id=%8x nb_periodic=%u\n",
-					  oa_timestamp(report, fmt),
-					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
-					  oa_report_is_periodic(report),
-					  oa_report_get_ctx_id(report),
-					  n_periodic_reports);
-
-				if (first_timestamp == 0)
-					first_timestamp = oa_timestamp(report, fmt);
-				last_timestamp = oa_timestamp(report, fmt);
-
-				if (oa_report_is_periodic(report)) {
-					memcpy(last_periodic_report, report, report_size);
-					n_periodic_reports++;
-				}
-			}
-		}
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
-
-		igt_debug("first ts = %u, last ts = %u\n", first_timestamp, last_timestamp);
+	/* OA buffer is disable, we do not expect any error status */
+	oa_status = get_stream_status(stream_fd);
+	overflow_seen = !!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW);
+	igt_assert_eq(overflow_seen, 0);
 
-		igt_debug("%f < %zu < %f\n",
-			  report_size * n_full_oa_reports * 0.45,
-			  n_periodic_reports * report_size,
-			  report_size * n_full_oa_reports * 0.55);
+	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
 
-		igt_assert(n_periodic_reports * report_size >
-			   report_size * n_full_oa_reports * 0.45);
-		igt_assert(n_periodic_reports * report_size <
-			   report_size * n_full_oa_reports * 0.55);
+	errno = 0;
+	/* Read 0 bytes repeatedly until you see an EIO */
+	while ((len = read(stream_fd, buf, 0)) == -1 && (errno == EINTR || errno == ENOSPC)) {
+		usleep(100);
 	}
+	igt_assert_eq(len, -1);
+	igt_assert_eq(errno, EIO);
 
-	free(last_periodic_report);
-	free(buf);
+	/* Ensure buffer overflowed */
+	oa_status = get_stream_status(stream_fd);
+	overflow_seen = !!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW);
+	igt_assert(overflow_seen);
 
 	__perf_close(stream_fd);
 }
-- 
2.34.1

Re: [PATCH i-g-t CI run 07/14] tests/intel/xe_oa: Simplify the buffer-fill test

[Dixit, Ashutosh]

On Tue, 18 Feb 2025 12:28:05 -0800, Umesh Nerlige Ramappa wrote:
>
> We only want to test that the BUFFER OVERFLOW status is set when we do
> not read the OA stream data in time. To do so, keeping reading zero
> bytes of data until you hit a buffer overflow.

The approach in this patch is great!

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 135 +++++++++-----------------------------------
>  1 file changed, 26 insertions(+), 109 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index 5792ffec2..fc03b74af 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -304,6 +304,7 @@ static size_t default_oa_buffer_size;
>  static struct intel_mmio_data mmio_data;
>  static igt_render_copyfunc_t render_copy;
>  static uint32_t rc_width, rc_height;
> +static uint32_t buffer_fill_size;

I am assuming these globals will be changed for slow platforms?

>
>  static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
>  {
> @@ -1092,6 +1093,7 @@ init_sys_info(void)
>
>	rc_width = 1920;
>	rc_height = 1080;
> +	buffer_fill_size = SZ_16M;
>	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
>
>	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
> @@ -2370,11 +2372,7 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
>  static void
>  test_buffer_fill(const struct drm_xe_engine_class_instance *hwe)

There is this comment above this line:

Description: Test filling, wraparound and overflow of OA buffer

I think we should drop "wraparound", since this test never tested the
wraparound of the OA buffer, it just tested overflow.

To test wraparound I was using non-zero-reason.

>  {
> -	/* ~5 micro second period */
> -	int oa_exponent = max_oa_exponent_for_period_lte(5000);
> -	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
>	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
> -	uint64_t fmt = test_set->perf_oa_format;
>	uint64_t properties[] = {
>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>
> @@ -2383,126 +2381,45 @@ test_buffer_fill(const struct drm_xe_engine_class_instance *hwe)
>
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
> -		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> +		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
> +		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
> +		DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, buffer_fill_size,
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
>		.properties_ptr = to_user_pointer(properties),
>	};
> -	size_t report_size = get_oa_format(fmt).size;
> -	int buf_size = 65536 * report_size;
> -	uint8_t *buf = malloc(buf_size);
> -	int len;
> -	int n_full_oa_reports = default_oa_buffer_size / report_size;
> -	uint64_t fill_duration = n_full_oa_reports * oa_period;
> -	uint32_t *last_periodic_report = malloc(report_size);
> +	uint64_t oa_period = oa_exponent_to_ns(oa_exponent_default);
> +	char *buf = malloc(1024);
> +	bool overflow_seen;
>	u32 oa_status;
> +	int len;
>
> -	igt_assert(fill_duration < 1000000000);
> -
> +	igt_debug("oa_period %s\n", pretty_print_oa_period(oa_period));
>	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
>          set_fd_flags(stream_fd, O_CLOEXEC);
>
> -	for (int i = 0; i < 5; i++) {
> -		bool overflow_seen;
> -		uint32_t n_periodic_reports;
> -		uint32_t first_timestamp = 0, last_timestamp = 0;
> -
> -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> -
> -		nanosleep(&(struct timespec){ .tv_sec = 0,
> -					      .tv_nsec = fill_duration * 1.25 },
> -			  NULL);
> -again:
> -		oa_status = 0;
> -		while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
> -			;
> -
> -		if (errno == EIO) {
> -			oa_status = get_stream_status(stream_fd);
> -			igt_debug("oa_status %#x\n", oa_status);
> -			overflow_seen = oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW;
> -			igt_assert_eq(overflow_seen, true);
> -			goto again;
> -		}
> -		igt_assert_neq(len, -1);
> -
> -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
> -
> -		igt_debug("fill_duration = %"PRIu64"ns, oa_exponent = %u\n",
> -			  fill_duration, oa_exponent);
> -
> -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> -
> -		nanosleep(&(struct timespec){ .tv_sec = 0,
> -					.tv_nsec = fill_duration / 2 },
> -			NULL);
> -
> -		n_periodic_reports = 0;
> -
> -		/* Because of the race condition between notification of new
> -		 * reports and reports landing in memory, we need to rely on
> -		 * timestamps to figure whether we've read enough of them.
> -		 */
> -		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
> -
> -			igt_debug("dts=%u elapsed=%"PRIu64" duration=%"PRIu64"\n",
> -				  last_timestamp - first_timestamp,
> -				  (last_timestamp - first_timestamp) * oa_period,
> -				  fill_duration / 2);
> -again_1:
> -			oa_status = 0;
> -			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
> -				;
> -			if (errno == EIO) {
> -				oa_status = get_stream_status(stream_fd);
> -				igt_debug("oa_status %#x\n", oa_status);
> -				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
> -				goto again_1;
> -			}
> -			igt_assert_neq(len, -1);
> -
> -			for (int offset = 0; offset < len; offset += report_size) {
> -				uint32_t *report = (void *) (buf + offset);
> -
> -				igt_debug(" > report ts=%"PRIu64""
> -					  " ts_delta_last_periodic=%"PRIu64" is_timer=%i ctx_id=%8x nb_periodic=%u\n",
> -					  oa_timestamp(report, fmt),
> -					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
> -					  oa_report_is_periodic(report),
> -					  oa_report_get_ctx_id(report),
> -					  n_periodic_reports);
> -
> -				if (first_timestamp == 0)
> -					first_timestamp = oa_timestamp(report, fmt);
> -				last_timestamp = oa_timestamp(report, fmt);
> -
> -				if (oa_report_is_periodic(report)) {
> -					memcpy(last_periodic_report, report, report_size);
> -					n_periodic_reports++;
> -				}
> -			}
> -		}
> -
> -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
> -
> -		igt_debug("first ts = %u, last ts = %u\n", first_timestamp, last_timestamp);
> +	/* OA buffer is disable, we do not expect any error status */

disabled

> +	oa_status = get_stream_status(stream_fd);
> +	overflow_seen = !!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW);

Don't need !!

> +	igt_assert_eq(overflow_seen, 0);
>
> -		igt_debug("%f < %zu < %f\n",
> -			  report_size * n_full_oa_reports * 0.45,
> -			  n_periodic_reports * report_size,
> -			  report_size * n_full_oa_reports * 0.55);
> +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>
> -		igt_assert(n_periodic_reports * report_size >
> -			   report_size * n_full_oa_reports * 0.45);
> -		igt_assert(n_periodic_reports * report_size <
> -			   report_size * n_full_oa_reports * 0.55);
> +	errno = 0;
> +	/* Read 0 bytes repeatedly until you see an EIO */
> +	while ((len = read(stream_fd, buf, 0)) == -1 && (errno == EINTR || errno == ENOSPC)) {
> +		usleep(100);
>	}
> +	igt_assert_eq(len, -1);
> +	igt_assert_eq(errno, EIO);
>
> -	free(last_periodic_report);
> -	free(buf);
> +	/* Ensure buffer overflowed */
> +	oa_status = get_stream_status(stream_fd);
> +	overflow_seen = !!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW);

Don't need !!

> +	igt_assert(overflow_seen);

Also I am wondering if we disabled the stream now using
DRM_XE_OBSERVATION_IOCTL_DISABLE, would it clear the overflow status? But
anyway the test is good as is.

>
>	__perf_close(stream_fd);
>  }

Apart from the above nits, this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

[PATCH i-g-t CI run 08/14] tests/intel/xe_oa: Use default buffer size for non-zero reason

[Umesh Nerlige Ramappa]

Use a default buffer size for non-zero-reason for and strip
out testing buffer size in the same test.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index fc03b74af..03d223df4 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2447,7 +2447,7 @@ test_non_zero_reason(const struct drm_xe_engine_class_instance *hwe, size_t oa_b
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
 		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
-		DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, oa_buffer_size,
+		DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, oa_buffer_size ?: buffer_fill_size
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -4805,15 +4805,9 @@ igt_main
 		__for_one_hwe_in_oag(hwe)
 			test_buffer_fill(hwe);
 
-	igt_subtest_with_dynamic("non-zero-reason") {
-		if (oau->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE) {
-			__for_one_hwe_in_oag_w_arg(hwe, "16M")
-				test_non_zero_reason(hwe, SZ_16M);
-		} else {
-			__for_one_hwe_in_oag_w_arg(hwe, "default")
-				test_non_zero_reason(hwe, 0);
-		}
-	}
+	igt_subtest_with_dynamic("non-zero-reason")
+		__for_one_hwe_in_oag(hwe)
+			test_non_zero_reason(hwe, 0);
 
 	igt_subtest("disabled-read-error")
 		test_disabled_read_error();
-- 
2.34.1

[PATCH i-g-t CI run 09/14] tests/intel/xe_oa: Test oa buffer sizes

[Umesh Nerlige Ramappa]

Introduce oa buffer size test separately. Pick a random valid buffer
size for the test.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 03d223df4..ee87b7338 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -93,6 +93,23 @@ struct accumulator {
 	uint64_t deltas[MAX_RAW_OA_COUNTERS];
 };
 
+struct oa_buf_size {
+	char name[12];
+	uint32_t size;
+} buf_sizes[] = {
+	{ "128K", SZ_128K },
+	{ "256K", SZ_256K },
+	{ "512K", SZ_512K },
+	{ "1M", SZ_1M },
+	{ "2M", SZ_2M },
+	{ "4M", SZ_4M },
+	{ "8M", SZ_8M },
+	{ "16M", SZ_16M },
+	{ "32M", SZ_32M },
+	{ "64M", SZ_64M },
+	{ "128M", SZ_128M },
+};
+
 /* OA unit types */
 enum {
 	OAG,
@@ -305,6 +322,7 @@ static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
 static uint32_t rc_width, rc_height;
 static uint32_t buffer_fill_size;
+static uint32_t num_buf_sizes;
 
 static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
 {
@@ -1094,6 +1112,7 @@ init_sys_info(void)
 	rc_width = 1920;
 	rc_height = 1080;
 	buffer_fill_size = SZ_16M;
+	num_buf_sizes = ARRAY_SIZE(buf_sizes);
 	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
 
 	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
@@ -4805,6 +4824,17 @@ igt_main
 		__for_one_hwe_in_oag(hwe)
 			test_buffer_fill(hwe);
 
+	/**
+	 * SUBTEST: buffer-size
+	 * Description: Test various OA buffer sizes
+	 */
+	igt_subtest_with_dynamic("buffer-size") {
+		long k = random() % num_buf_sizes;
+
+		__for_one_hwe_in_oag_w_arg(hwe, buf_sizes[k].name)
+			test_non_zero_reason(hwe, buf_sizes[k].size);
+	}
+
 	igt_subtest_with_dynamic("non-zero-reason")
 		__for_one_hwe_in_oag(hwe)
 			test_non_zero_reason(hwe, 0);
-- 
2.34.1

[PATCH i-g-t CI run 10/14] tests/intel/xe_oa: Rewrite enable-disable test

[Umesh Nerlige Ramappa]

Keep it simple and just check if enable/disable is working correctly
using mmio.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 129 +++++---------------------------------------
 1 file changed, 13 insertions(+), 116 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index ee87b7338..c6c1c2358 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2534,21 +2534,13 @@ test_non_zero_reason(const struct drm_xe_engine_class_instance *hwe, size_t oa_b
 static void
 test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
 {
-	/* ~5 micro second period */
-	int oa_exponent = max_oa_exponent_for_period_lte(5000);
-	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
 	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
-	uint64_t fmt = test_set->perf_oa_format;
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
-
-		/* Include OA reports in samples */
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
-
-		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
-		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
 	};
@@ -2556,123 +2548,28 @@ test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
 		.num_properties = ARRAY_SIZE(properties) / 2,
 		.properties_ptr = to_user_pointer(properties),
 	};
-	size_t report_size = get_oa_format(fmt).size;
-	int buf_size = 65536 * report_size;
-	uint8_t *buf = malloc(buf_size);
-	int n_full_oa_reports = default_oa_buffer_size / report_size;
-	uint64_t fill_duration = n_full_oa_reports * oa_period;
-	uint32_t *last_periodic_report = malloc(report_size);
-
-	load_helper_init();
-	load_helper_run(HIGH);
+	u32 oacontrol;
 
 	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
         set_fd_flags(stream_fd, O_CLOEXEC);
 
-	for (int i = 0; i < 5; i++) {
-		int len;
-		uint32_t n_periodic_reports;
-		uint64_t first_timestamp = 0, last_timestamp = 0;
-		u32 oa_status;
-
-		/* Giving enough time for an overflow might help catch whether
-		 * the OA unit has been enabled even if the driver might at
-		 * least avoid copying reports while disabled.
-		 */
-		nanosleep(&(struct timespec){ .tv_sec = 0,
-					      .tv_nsec = fill_duration * 1.25 },
-			  NULL);
-
-		while ((len = read(stream_fd, buf, buf_size)) == -1 &&
-		       (errno == EINTR || errno == EIO))
-			;
-
-		igt_assert_eq(len, -1);
-		igt_assert_eq(errno, EINVAL);
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
+#define OAG_OACONTROL	(0xdaf4)
+#define  OAG_OACONTROL_OA_COUNTER_ENABLE	(1 << 0)
 
-		nanosleep(&(struct timespec){ .tv_sec = 0,
-					      .tv_nsec = fill_duration / 2 },
-			NULL);
-
-		n_periodic_reports = 0;
-
-		/* Because of the race condition between notification of new
-		 * reports and reports landing in memory, we need to rely on
-		 * timestamps to figure whether we've read enough of them.
-		 */
-		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
-
-			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
-				;
-			if (errno == EIO) {
-				oa_status = get_stream_status(stream_fd);
-				igt_debug("oa_status %#x\n", oa_status);
-				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
-				continue;
-			}
-			igt_assert_neq(len, -1);
-
-			for (int offset = 0; offset < len; offset += report_size) {
-				uint32_t *report = (void *) (buf + offset);
-
-				if (first_timestamp == 0)
-					first_timestamp = oa_timestamp(report, fmt);
-				last_timestamp = oa_timestamp(report, fmt);
-
-				igt_debug(" > report ts=%"PRIx64""
-					  " ts_delta_last_periodic=%s%"PRIu64""
-					  " is_timer=%i ctx_id=0x%8x\n",
-					  oa_timestamp(report, fmt),
-					  oa_report_is_periodic(report) ? " " : "*",
-					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
-					  oa_report_is_periodic(report),
-					  oa_report_get_ctx_id(report));
-
-				if (oa_report_is_periodic(report)) {
-					memcpy(last_periodic_report, report, report_size);
-
-					/* We want to measure only the periodic reports,
-					 * ctx-switch might inflate the content of the
-					 * buffer and skew or measurement.
-					 */
-					n_periodic_reports++;
-				}
-			}
-		}
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
-
-		igt_debug("first ts = %"PRIu64", last ts = %"PRIu64"\n", first_timestamp, last_timestamp);
-
-		igt_debug("%f < %zu < %f\n",
-			  report_size * n_full_oa_reports * 0.45,
-			  n_periodic_reports * report_size,
-			  report_size * n_full_oa_reports * 0.55);
-
-		igt_assert((n_periodic_reports * report_size) >
-			   (report_size * n_full_oa_reports * 0.45));
-		igt_assert((n_periodic_reports * report_size) <
-			   report_size * n_full_oa_reports * 0.55);
+	intel_register_access_init(&mmio_data,
+				   igt_device_get_pci_device(drm_fd), 0);
 
+	oacontrol = intel_register_read(&mmio_data, OAG_OACONTROL);
+	igt_assert_eq(oacontrol & OAG_OACONTROL_OA_COUNTER_ENABLE, 0);
 
-		/* It's considered an error to read a stream while it's disabled
-		 * since it would block indefinitely...
-		 */
-		len = read(stream_fd, buf, buf_size);
+	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
 
-		igt_assert_eq(len, -1);
-		igt_assert_eq(errno, EINVAL);
-	}
+	oacontrol = intel_register_read(&mmio_data, OAG_OACONTROL);
 
-	free(last_periodic_report);
-	free(buf);
+	igt_assert_eq(oacontrol & OAG_OACONTROL_OA_COUNTER_ENABLE, 1);
 
+	intel_register_access_fini(&mmio_data);
 	__perf_close(stream_fd);
-
-	load_helper_stop();
-	load_helper_fini();
 }
 
 /**
-- 
2.34.1

[PATCH i-g-t CI run 11/14] tests/intel/xe_oa: Enable unprivileged-single-ctx-counters and fix it

[Umesh Nerlige Ramappa]

unprivileged-single-ctx-counters was hardcoded for a format size of 256
bytes. Fix it up for generic format size.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 93 +++++++++++++++++++++++----------------------
 1 file changed, 48 insertions(+), 45 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index c6c1c2358..ff1b873d5 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2961,6 +2961,16 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	struct accumulator accumulator = {
 		.format = fmt
 	};
+	uint32_t ctx_id_offset, counter_offset, dst_buf_size;
+	struct oa_format format = get_oa_format(fmt);
+
+	if (format.report_hdr_64bit) {
+		ctx_id_offset = 4;
+		counter_offset = 8;
+	} else {
+		ctx_id_offset = 2;
+		counter_offset = 4;
+	}
 
 	bops = buf_ops_create(drm_fd);
 
@@ -2989,25 +2999,29 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	stream_fd = __perf_open(drm_fd, &param, false);
         set_fd_flags(stream_fd, O_CLOEXEC);
 
-	dst_buf = intel_buf_create(bops, 4096, 1, 8, 64,
+#define FOUR_REPORTS (4 * format.size)
+#define BO_REPORT_OFFSET(_r) (_r * format.size)
+
+#define FOUR_TIMESTAMPS (4 * 8)
+#define BO_TIMESTAMP_OFFSET(_r) (FOUR_REPORTS + (_r * 8))
+
+	dst_buf_size = FOUR_REPORTS + FOUR_TIMESTAMPS;
+	dst_buf = intel_buf_create(bops, dst_buf_size, 1, 8, 64,
 				   I915_TILING_NONE,
 				   I915_COMPRESSION_NONE);
 
 	/* Set write domain to cpu briefly to fill the buffer with 80s */
 	buf_map(drm_fd, dst_buf, true /* write enable */);
-	memset(dst_buf->ptr, 0x80, 2048);
-	memset((uint8_t *) dst_buf->ptr + 2048, 0, 2048);
+	memset(dst_buf->ptr, 0, dst_buf_size);
+	memset(dst_buf->ptr, 0x80, FOUR_REPORTS);
 	intel_buf_unmap(dst_buf);
 
 	/* Submit an mi-rpc to context0 before measurable work */
-#define BO_TIMESTAMP_OFFSET0 1024
-#define BO_REPORT_OFFSET0 0
-#define BO_REPORT_ID0 0xdeadbeef
 	emit_stall_timestamp_and_rpc(ibb0,
 				     dst_buf,
-				     BO_TIMESTAMP_OFFSET0,
-				     BO_REPORT_OFFSET0,
-				     BO_REPORT_ID0);
+				     BO_TIMESTAMP_OFFSET(0),
+				     BO_REPORT_OFFSET(0),
+				     0xdeadbeef);
 	intel_bb_flush_render(ibb0);
 
 	/* Remove intel_buf from ibb0 added implicitly in rendercopy */
@@ -3025,14 +3039,11 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	 * all zeroes, since the counters will only increment for the
 	 * context passed to perf open ioctl
 	 */
-#define BO_TIMESTAMP_OFFSET2 1040
-#define BO_REPORT_OFFSET2 512
-#define BO_REPORT_ID2 0x00c0ffee
 	emit_stall_timestamp_and_rpc(ibb1,
 				     dst_buf,
-				     BO_TIMESTAMP_OFFSET2,
-				     BO_REPORT_OFFSET2,
-				     BO_REPORT_ID2);
+				     BO_TIMESTAMP_OFFSET(2),
+				     BO_REPORT_OFFSET(2),
+				     0x00c0ffee);
 	intel_bb_flush_render(ibb1);
 
 	/* Submit two copies on the other context to avoid a false
@@ -3049,28 +3060,22 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	intel_bb_flush_render(ibb1);
 
 	/* Submit an mi-rpc to context1 after all work */
-#define BO_TIMESTAMP_OFFSET3 1048
-#define BO_REPORT_OFFSET3 768
-#define BO_REPORT_ID3 0x01c0ffee
 	emit_stall_timestamp_and_rpc(ibb1,
 				     dst_buf,
-				     BO_TIMESTAMP_OFFSET3,
-				     BO_REPORT_OFFSET3,
-				     BO_REPORT_ID3);
+				     BO_TIMESTAMP_OFFSET(3),
+				     BO_REPORT_OFFSET(3),
+				     0x01c0ffee);
 	intel_bb_flush_render(ibb1);
 
 	/* Remove intel_buf from ibb1 added implicitly in rendercopy */
 	intel_bb_remove_intel_buf(ibb1, dst_buf);
 
 	/* Submit an mi-rpc to context0 after all measurable work */
-#define BO_TIMESTAMP_OFFSET1 1032
-#define BO_REPORT_OFFSET1 256
-#define BO_REPORT_ID1 0xbeefbeef
 	emit_stall_timestamp_and_rpc(ibb0,
 				     dst_buf,
-				     BO_TIMESTAMP_OFFSET1,
-				     BO_REPORT_OFFSET1,
-				     BO_REPORT_ID1);
+				     BO_TIMESTAMP_OFFSET(1),
+				     BO_REPORT_OFFSET(1),
+				     0xbeefbeef);
 	intel_bb_flush_render(ibb0);
 	intel_bb_sync(ibb0);
 	intel_bb_sync(ibb1);
@@ -3090,33 +3095,32 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	report0_32 = dst_buf->ptr;
 	igt_assert_eq(report0_32[0], 0xdeadbeef);
 	igt_assert(oa_timestamp(report0_32, fmt));
-	ctx0_id = report0_32[2];
+	ctx0_id = report0_32[ctx_id_offset];
 	igt_debug("MI_RPC(start) CTX ID: %u\n", ctx0_id);
-	dump_report(report0_32, 64, "report0_32");
+	dump_report(report0_32, format.size / 4, "report0_32");
 
-	report1_32 = report0_32 + 64;
+	report1_32 = report0_32 + format.size / 4;
 	igt_assert_eq(report1_32[0], 0xbeefbeef);
 	igt_assert(oa_timestamp(report1_32, fmt));
-	ctx1_id = report1_32[2];
+	ctx1_id = report1_32[ctx_id_offset];
 	igt_debug("CTX ID1: %u\n", ctx1_id);
-	dump_report(report1_32, 64, "report1_32");
+	dump_report(report1_32, format.size / 4, "report1_32");
 
 	/* Verify that counters in context1 are all zeroes */
-	report2_32 = report0_32 + 128;
+	report2_32 = report1_32 + format.size / 4;
 	igt_assert_eq(report2_32[0], 0x00c0ffee);
 	igt_assert(oa_timestamp(report2_32, fmt));
-	dump_report(report2_32, 64, "report2_32");
-	igt_assert_eq(0, memcmp(&report2_32[4],
-				(uint8_t *) dst_buf->ptr + 2048,
-				240));
+	dump_report(report2_32, format.size / 4, "report2_32");
 
-	report3_32 = report0_32 + 192;
+	report3_32 = report2_32 + format.size / 4;
 	igt_assert_eq(report3_32[0], 0x01c0ffee);
 	igt_assert(oa_timestamp(report3_32, fmt));
-	dump_report(report3_32, 64, "report3_32");
-	igt_assert_eq(0, memcmp(&report3_32[4],
-				(uint8_t *) dst_buf->ptr + 2048,
-				240));
+	dump_report(report3_32, format.size / 4, "report3_32");
+
+	for (int k = counter_offset; k < format.size / 4; k++) {
+		igt_assert_f(report2_32[k] == 0, "Failed counter %d check\n", k);
+		igt_assert_f(report3_32[k] == 0, "Failed counter %d check\n", k);
+	}
 
 	/* Accumulate deltas for counters - A0, A21 and A26 */
 	memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
@@ -3135,8 +3139,8 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	 * the OA report timestamps should be almost identical but
 	 * allow a 500 nanoseconds margin.
 	 */
-	timestamp0_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET0);
-	timestamp1_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET1);
+	timestamp0_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET(0));
+	timestamp1_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET(1));
 
 	igt_debug("ts_timestamp64 0 = %"PRIu64"\n", timestamp0_64);
 	igt_debug("ts_timestamp64 1 = %"PRIu64"\n", timestamp1_64);
@@ -4781,7 +4785,6 @@ igt_main
 
 		igt_subtest_with_dynamic("unprivileged-single-ctx-counters") {
 			igt_require_f(render_copy, "no render-copy function\n");
-			igt_require(intel_graphics_ver(devid) < IP_VER(20, 0));
 			__for_one_render_engine(hwe)
 				test_single_ctx_render_target_writes_a_counter(hwe);
 		}
-- 
2.34.1

[PATCH i-g-t CI run 12/14] tests/intel/xe_oa: Fix mmio_trigger_reports testing

[Umesh Nerlige Ramappa]

The MI_STORE command needs modification to set the right amount of dwords. While
at it, set the default exponent and add a render_copy check.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index ff1b873d5..d44832a8a 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -3688,7 +3688,7 @@ emit_oa_reg_read(struct intel_bb *ibb, struct intel_buf *dst, uint32_t offset,
 {
 	intel_bb_add_intel_buf(ibb, dst, true);
 
-	intel_bb_out(ibb, MI_STORE_REGISTER_MEM | 2);
+	intel_bb_out(ibb, MI_STORE_REGISTER_MEM_GEN8);
 	intel_bb_out(ibb, reg);
 	intel_bb_emit_reloc(ibb, dst->handle,
 			    I915_GEM_DOMAIN_INSTRUCTION,
-- 
2.34.1

[PATCH i-g-t CI run 13/14] tests/intel/xe_oa: Set boundaries for OA exponent test

[Umesh Nerlige Ramappa]

Define min and max oa exponents for the oa exponent test

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index d44832a8a..22ff3f20d 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -321,6 +321,8 @@ static size_t default_oa_buffer_size;
 static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
 static uint32_t rc_width, rc_height;
+static uint32_t max_oa_exponent;
+static uint32_t min_oa_exponent;
 static uint32_t buffer_fill_size;
 static uint32_t num_buf_sizes;
 
@@ -1109,6 +1111,8 @@ init_sys_info(void)
 
 	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
 
+	min_oa_exponent = 5;
+	max_oa_exponent = 20;
 	rc_width = 1920;
 	rc_height = 1080;
 	buffer_fill_size = SZ_16M;
@@ -1710,7 +1714,7 @@ static void test_oa_exponents(const struct drm_xe_engine_class_instance *hwe)
 	 * test can fail due to buffer overflows if it wasn't possible to
 	 * keep up, so we don't start from an exponent of zero...
 	 */
-	for (int exponent = 5; exponent < 20; exponent++) {
+	for (int exponent = min_oa_exponent; exponent < max_oa_exponent; exponent++) {
 		uint64_t properties[] = {
 			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
 
-- 
2.34.1

[PATCH i-g-t CI run 14/14] tests/intel/xe_oa: Try largest buffer size and Xe1

[Umesh Nerlige Ramappa]

Patch just for CI and not for merging

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 22ff3f20d..148918181 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -4692,9 +4692,6 @@ igt_main
 		devid = intel_get_drm_devid(drm_fd);
 		sysfs = igt_sysfs_open(drm_fd);
 
-		/* Currently only run on Xe2+ */
-		igt_require(intel_graphics_ver(devid) >= IP_VER(20, 0));
-
 		igt_require(init_sys_info());
 
 		write_u64_file("/proc/sys/dev/xe/observation_paranoid", 1);
@@ -4734,7 +4731,7 @@ igt_main
 	 * Description: Test various OA buffer sizes
 	 */
 	igt_subtest_with_dynamic("buffer-size") {
-		long k = random() % num_buf_sizes;
+		long k = num_buf_sizes - 1;
 
 		__for_one_hwe_in_oag_w_arg(hwe, buf_sizes[k].name)
 			test_non_zero_reason(hwe, buf_sizes[k].size);
-- 
2.34.1

✓ Xe.CI.BAT: success for CI run only

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3369 bytes --]

== Series Details ==

Series: CI run only
URL   : https://patchwork.freedesktop.org/series/145042/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8236_BAT -> XEIGTPW_12628_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_12628_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - bat-adlp-vf:        NOTRUN -> [SKIP][1] ([Intel XE#2229] / [Intel XE#455]) +1 other test skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/bat-adlp-vf/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_live_ktest@xe_migrate@xe_migrate_sanity_kunit:
    - bat-adlp-vf:        NOTRUN -> [DMESG-FAIL][2] ([Intel XE#3890])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/bat-adlp-vf/igt@xe_live_ktest@xe_migrate@xe_migrate_sanity_kunit.html

  
#### Possible fixes ####

  * igt@xe_live_ktest@xe_dma_buf:
    - bat-adlp-vf:        [SKIP][3] ([Intel XE#4322]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/bat-adlp-vf/igt@xe_live_ktest@xe_dma_buf.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/bat-adlp-vf/igt@xe_live_ktest@xe_dma_buf.html

  * igt@xe_pat@pat-index-xelp@render:
    - bat-adlp-vf:        [DMESG-WARN][5] ([Intel XE#3970]) -> [PASS][6] +1 other test pass
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/bat-adlp-vf/igt@xe_pat@pat-index-xelp@render.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/bat-adlp-vf/igt@xe_pat@pat-index-xelp@render.html

  
#### Warnings ####

  * igt@xe_live_ktest@xe_bo:
    - bat-adlp-vf:        [SKIP][7] ([Intel XE#4322]) -> [SKIP][8] ([Intel XE#2229] / [Intel XE#455])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/bat-adlp-vf/igt@xe_live_ktest@xe_bo.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/bat-adlp-vf/igt@xe_live_ktest@xe_bo.html

  * igt@xe_live_ktest@xe_migrate:
    - bat-adlp-vf:        [SKIP][9] ([Intel XE#4322]) -> [DMESG-FAIL][10] ([Intel XE#3890])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/bat-adlp-vf/igt@xe_live_ktest@xe_migrate.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/bat-adlp-vf/igt@xe_live_ktest@xe_migrate.html

  
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#3890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3890
  [Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
  [Intel XE#4322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4322
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455


Build changes
-------------

  * IGT: IGT_8236 -> IGTPW_12628
  * Linux: xe-2679-4cc4e3d6ea1543688d62432dbe0fa750780fb262 -> xe-2682-88f261625e1d94c7eba789712b060b368989aea1

  IGTPW_12628: 12628
  IGT_8236: 8236
  xe-2679-4cc4e3d6ea1543688d62432dbe0fa750780fb262: 4cc4e3d6ea1543688d62432dbe0fa750780fb262
  xe-2682-88f261625e1d94c7eba789712b060b368989aea1: 88f261625e1d94c7eba789712b060b368989aea1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/index.html

[-- Attachment #2: Type: text/html, Size: 4439 bytes --]

✗ i915.CI.BAT: failure for CI run only

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5786 bytes --]

== Series Details ==

Series: CI run only
URL   : https://patchwork.freedesktop.org/series/145042/
State : failure

== Summary ==

CI Bug Log - changes from IGT_8236 -> IGTPW_12628
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_12628 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_12628, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/index.html

Participating hosts (42 -> 42)
------------------------------

  Additional (1): fi-kbl-7567u 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_12628:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@hangcheck:
    - bat-arlh-2:         [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8236/bat-arlh-2/igt@i915_selftest@live@hangcheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/bat-arlh-2/igt@i915_selftest@live@hangcheck.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-arlh-2:         [DMESG-FAIL][3] ([i915#12061]) -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8236/bat-arlh-2/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/bat-arlh-2/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in IGTPW_12628 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests:
    - bat-apl-1:          [PASS][5] -> [INCOMPLETE][6] ([i915#12904]) +1 other test incomplete
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8236/bat-apl-1/igt@dmabuf@all-tests.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/bat-apl-1/igt@dmabuf@all-tests.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-7567u:       NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/fi-kbl-7567u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-7567u:       NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/fi-kbl-7567u/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_selftest@live@late_gt_pm:
    - fi-cfl-8109u:       [PASS][9] -> [DMESG-WARN][10] ([i915#11621]) +132 other tests dmesg-warn
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8236/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html

  * igt@kms_dsc@dsc-basic:
    - fi-kbl-7567u:       NOTRUN -> [SKIP][11] +11 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/fi-kbl-7567u/igt@kms_dsc@dsc-basic.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-adlp-9:         [ABORT][12] -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8236/bat-adlp-9/igt@i915_selftest@live.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/bat-adlp-9/igt@i915_selftest@live.html
    - bat-jsl-3:          [INCOMPLETE][14] ([i915#12445] / [i915#13241]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8236/bat-jsl-3/igt@i915_selftest@live.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/bat-jsl-3/igt@i915_selftest@live.html

  * igt@i915_selftest@live@guc:
    - bat-adlp-9:         [ABORT][16] ([i915#13696]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8236/bat-adlp-9/igt@i915_selftest@live@guc.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/bat-adlp-9/igt@i915_selftest@live@guc.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-2:         [DMESG-FAIL][18] ([i915#12061]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8236/bat-arlh-2/igt@i915_selftest@live@workarounds.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/bat-arlh-2/igt@i915_selftest@live@workarounds.html
    - bat-arls-6:         [DMESG-FAIL][20] ([i915#12061]) -> [PASS][21] +1 other test pass
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8236/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/bat-arls-6/igt@i915_selftest@live@workarounds.html

  
  [i915#11621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11621
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12445]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12445
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#13241]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13241
  [i915#13696]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13696
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8236 -> IGTPW_12628
  * Linux: CI_DRM_16149 -> CI_DRM_16152

  CI-20190529: 20190529
  CI_DRM_16149: 4587c05996666a92af63f86ba410bae1dc940794 @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_16152: 5b90e253264600ca6750777faee5e96061ce6d8e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_12628: 12628
  IGT_8236: 8236

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12628/index.html

[-- Attachment #2: Type: text/html, Size: 6812 bytes --]

✗ Xe.CI.Full: failure for CI run only

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 90074 bytes --]

== Series Details ==

Series: CI run only
URL   : https://patchwork.freedesktop.org/series/145042/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8236_full -> XEIGTPW_12628_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_12628_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_12628_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_12628_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-180:
    - shard-bmg:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-7/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-1/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html

  * igt@xe_exec_compute_mode@many-userptr:
    - shard-dg2-set2:     NOTRUN -> [TIMEOUT][3]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@xe_exec_compute_mode@many-userptr.html

  * {igt@xe_oa@buffer-size} (NEW):
    - shard-dg2-set2:     NOTRUN -> [FAIL][4] +3 other tests fail
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@xe_oa@buffer-size.html

  
New tests
---------

  New tests have been introduced between XEIGT_8236_full and XEIGTPW_12628_full:

### New IGT tests (3) ###

  * igt@xe_oa@buffer-size:
    - Statuses : 1 fail(s) 1 pass(s)
    - Exec time: [2.79, 2.89] s

  * igt@xe_oa@buffer-size@rcs-0-128m:
    - Statuses : 1 fail(s) 1 pass(s)
    - Exec time: [2.79, 2.89] s

  * igt@xe_oa@oa-tlb-invalidate@rcs-0:
    - Statuses : 1 pass(s)
    - Exec time: [10.01] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_12628_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-read:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#1125])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2233])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#623])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1466])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-7/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][9] ([Intel XE#4330]) +10 other tests dmesg-warn
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-dp-4.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-hdmi-a-6-4-mc-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#3767]) +15 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-hdmi-a-6-4-mc-ccs.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-6-4-mc-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#2550] / [Intel XE#3767]) +15 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-6-4-mc-ccs.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#316]) +3 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#1407]) +4 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-3/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#3658])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2327]) +2 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#1124]) +10 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-5/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#610])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#610])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#1428])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#1124]) +14 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#1124]) +6 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#2191])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2314] / [Intel XE#2894])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#367]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-2-displays-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#367]) +3 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-3-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#367]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#3432]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#3432])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][29] ([Intel XE#455] / [Intel XE#787]) +44 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2887]) +10 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][31] ([Intel XE#787]) +145 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][32] -> [INCOMPLETE][33] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][34] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][35] ([Intel XE#1727] / [Intel XE#3113])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][36] ([Intel XE#3124])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#2907]) +2 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2652] / [Intel XE#787]) +30 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-1/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#2887]) +6 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][40] ([Intel XE#1152]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2325])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#306]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-3/igt@kms_chamelium_color@ctm-negative.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#306]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#2252]) +4 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-dg2-set2:     NOTRUN -> [SKIP][45] ([Intel XE#373]) +9 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#373]) +5 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2-set2:     NOTRUN -> [DMESG-FAIL][47] ([Intel XE#4330]) +1 other test dmesg-fail
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_content_protection@lic-type-0.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2321]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#308]) +4 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_cursor_crc@cursor-onscreen-512x170.html
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#2321]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#1424]) +4 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-2/igt@kms_cursor_crc@cursor-sliding-128x42.html
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2320]) +2 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-128x42.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2291])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#309])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - shard-dg2-set2:     [PASS][55] -> [DMESG-WARN][56] ([Intel XE#4330]) +26 other tests dmesg-warn
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-434/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][57] -> [SKIP][58] ([Intel XE#2291]) +5 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#309]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
    - shard-bmg:          NOTRUN -> [DMESG-WARN][60] ([Intel XE#877])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-dg2-set2:     [PASS][61] -> [SKIP][62] ([Intel XE#309]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-433/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#4210])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#4331])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#2244]) +2 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#2244]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_feature_discovery@psr2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#1135])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#1421]) +6 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [PASS][69] -> [SKIP][70] ([Intel XE#2316]) +4 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][71] -> [FAIL][72] ([Intel XE#301] / [Intel XE#3321])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-hdmi-a6-dp4.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-dp2-hdmi-a3:
    - shard-bmg:          NOTRUN -> [FAIL][73] ([Intel XE#3321])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][74] -> [FAIL][75] ([Intel XE#301]) +1 other test fail
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-panning:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#2316])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_flip@2x-flip-vs-panning.html

  * igt@kms_flip@2x-flip-vs-panning-interruptible:
    - shard-dg2-set2:     [PASS][77] -> [SKIP][78] ([Intel XE#310]) +2 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-463/igt@kms_flip@2x-flip-vs-panning-interruptible.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_flip@2x-flip-vs-panning-interruptible.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#310])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@flip-vs-rmfb:
    - shard-dg2-set2:     [PASS][80] -> [DMESG-WARN][81] ([Intel XE#2955])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-434/igt@kms_flip@flip-vs-rmfb.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-dg2-set2:     [PASS][82] -> [FAIL][83] ([Intel XE#2882]) +2 other tests fail
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#1397]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#1397] / [Intel XE#1745]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][86] ([Intel XE#455]) +19 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#1401] / [Intel XE#1745])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#1401])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][90] ([Intel XE#2293]) +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#4141]) +10 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
    - shard-dg2-set2:     [PASS][92] -> [SKIP][93] ([Intel XE#656]) +2 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#656]) +28 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#2312]) +8 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#2311]) +16 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][97] ([Intel XE#651]) +27 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#651]) +6 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][99] ([Intel XE#2313]) +16 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][100] ([Intel XE#653]) +28 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][101] ([Intel XE#656]) +17 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_hdr@static-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][102] ([Intel XE#1503])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-3/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][103] ([Intel XE#2927])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][104] ([Intel XE#2925])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
    - shard-lnl:          NOTRUN -> [SKIP][105] ([Intel XE#4090])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-7/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-bmg:          NOTRUN -> [SKIP][106] ([Intel XE#2486])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2-set2:     NOTRUN -> [SKIP][107] ([Intel XE#4359])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
    - shard-dg2-set2:     [PASS][108] -> [FAIL][109] ([Intel XE#616])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html

  * igt@kms_plane_cursor@overlay@pipe-d-hdmi-a-6-size-64:
    - shard-dg2-set2:     [PASS][110] -> [INCOMPLETE][111] ([Intel XE#3966])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_plane_cursor@overlay@pipe-d-hdmi-a-6-size-64.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_plane_cursor@overlay@pipe-d-hdmi-a-6-size-64.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-bmg:          NOTRUN -> [SKIP][112] ([Intel XE#2571])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c:
    - shard-lnl:          NOTRUN -> [SKIP][113] ([Intel XE#2763]) +11 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-7/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-a:
    - shard-bmg:          [PASS][114] -> [DMESG-WARN][115] ([Intel XE#877]) +1 other test dmesg-warn
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-a.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-a.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b:
    - shard-bmg:          NOTRUN -> [SKIP][116] ([Intel XE#2763]) +4 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][117] ([Intel XE#2763]) +2 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d:
    - shard-dg2-set2:     NOTRUN -> [SKIP][118] ([Intel XE#2763] / [Intel XE#455]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d.html

  * igt@kms_pm_backlight@fade:
    - shard-dg2-set2:     NOTRUN -> [SKIP][119] ([Intel XE#870])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_rpm@drm-resources-equal:
    - shard-dg2-set2:     [PASS][120] -> [DMESG-WARN][121] ([Intel XE#2042] / [Intel XE#4330])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@kms_pm_rpm@drm-resources-equal.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_pm_rpm@drm-resources-equal.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][122] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-dg2-set2:     NOTRUN -> [SKIP][123] ([Intel XE#836])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_pm_rpm@modeset-non-lpsp.html
    - shard-lnl:          NOTRUN -> [SKIP][124] ([Intel XE#1439] / [Intel XE#3141])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-8/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
    - shard-lnl:          NOTRUN -> [SKIP][125] ([Intel XE#2893]) +2 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][126] ([Intel XE#1489]) +10 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][127] ([Intel XE#1489]) +6 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][128] ([Intel XE#2850] / [Intel XE#929]) +9 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_psr@psr2-sprite-blt:
    - shard-bmg:          NOTRUN -> [SKIP][129] ([Intel XE#2234] / [Intel XE#2850]) +4 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-5/igt@kms_psr@psr2-sprite-blt.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-bmg:          NOTRUN -> [SKIP][130] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-1/igt@kms_rotation_crc@bad-pixel-format.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][131] ([Intel XE#3414]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_rotation_crc@bad-pixel-format.html
    - shard-lnl:          NOTRUN -> [SKIP][132] ([Intel XE#3414] / [Intel XE#3904]) +2 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-3/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][133] ([Intel XE#1435])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_setmode@clone-exclusive-crtc.html
    - shard-lnl:          NOTRUN -> [SKIP][134] ([Intel XE#1435])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-2/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-bmg:          [PASS][135] -> [SKIP][136] ([Intel XE#1435])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-5/igt@kms_setmode@invalid-clone-single-crtc.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][137] ([Intel XE#2426])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][138] ([Intel XE#1500])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-basic:
    - shard-bmg:          NOTRUN -> [SKIP][139] ([Intel XE#1499])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@kms_vrr@flip-basic.html

  * igt@kms_vrr@negative-basic:
    - shard-lnl:          NOTRUN -> [SKIP][140] ([Intel XE#1499])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-8/igt@kms_vrr@negative-basic.html

  * igt@testdisplay:
    - shard-dg2-set2:     [PASS][141] -> [DMESG-WARN][142] ([Intel XE#2705] / [Intel XE#4212])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-463/igt@testdisplay.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@testdisplay.html

  * igt@xe_compute_preempt@compute-preempt-many:
    - shard-dg2-set2:     NOTRUN -> [SKIP][143] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@xe_compute_preempt@compute-preempt-many.html

  * igt@xe_eudebug_online@stopped-thread:
    - shard-bmg:          NOTRUN -> [SKIP][144] ([Intel XE#2905]) +4 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@xe_eudebug_online@stopped-thread.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-nofree-samefd:
    - shard-lnl:          NOTRUN -> [SKIP][145] ([Intel XE#688]) +4 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@xe_evict_ccs@evict-overcommit-standalone-nofree-samefd.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][146] ([Intel XE#2322]) +6 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html

  * igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap:
    - shard-lnl:          NOTRUN -> [SKIP][147] ([Intel XE#1392]) +5 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html

  * igt@xe_exec_fault_mode@twice-userptr-rebind-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][148] ([Intel XE#288]) +23 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html

  * igt@xe_exec_sip_eudebug@breakpoint-writesip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][149] ([Intel XE#2905]) +14 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@xe_exec_sip_eudebug@breakpoint-writesip.html
    - shard-lnl:          NOTRUN -> [SKIP][150] ([Intel XE#2905]) +7 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-8/igt@xe_exec_sip_eudebug@breakpoint-writesip.html

  * igt@xe_exec_threads@threads-rebind-err:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][151] ([Intel XE#4330])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@xe_exec_threads@threads-rebind-err.html

  * igt@xe_gt_freq@freq_suspend:
    - shard-bmg:          [PASS][152] -> [DMESG-WARN][153] ([Intel XE#4330]) +6 other tests dmesg-warn
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-8/igt@xe_gt_freq@freq_suspend.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@xe_gt_freq@freq_suspend.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          NOTRUN -> [SKIP][154] ([Intel XE#586])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@xe_mmap@small-bar.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][155] ([Intel XE#512])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@xe_mmap@small-bar.html
    - shard-lnl:          NOTRUN -> [SKIP][156] ([Intel XE#512])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@xe_mmap@small-bar.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172], [PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179], [PASS][180], [PASS][181]) -> ([PASS][182], [PASS][183], [PASS][184], [PASS][185], [PASS][186], [PASS][187], [PASS][188], [PASS][189], [PASS][190], [PASS][191], [PASS][192], [PASS][193], [PASS][194], [PASS][195], [PASS][196], [PASS][197], [PASS][198], [PASS][199], [PASS][200], [PASS][201], [PASS][202], [SKIP][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207]) ([Intel XE#378])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-4/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-4/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-3/igt@xe_module_load@load.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-3/igt@xe_module_load@load.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-3/igt@xe_module_load@load.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-8/igt@xe_module_load@load.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-8/igt@xe_module_load@load.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-8/igt@xe_module_load@load.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-5/igt@xe_module_load@load.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-5/igt@xe_module_load@load.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-7/igt@xe_module_load@load.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-6/igt@xe_module_load@load.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-6/igt@xe_module_load@load.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-2/igt@xe_module_load@load.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-8/igt@xe_module_load@load.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-5/igt@xe_module_load@load.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-5/igt@xe_module_load@load.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-4/igt@xe_module_load@load.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-2/igt@xe_module_load@load.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-2/igt@xe_module_load@load.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-7/igt@xe_module_load@load.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-7/igt@xe_module_load@load.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-4/igt@xe_module_load@load.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-3/igt@xe_module_load@load.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-6/igt@xe_module_load@load.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-3/igt@xe_module_load@load.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-3/igt@xe_module_load@load.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-3/igt@xe_module_load@load.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-3/igt@xe_module_load@load.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-2/igt@xe_module_load@load.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-2/igt@xe_module_load@load.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-2/igt@xe_module_load@load.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-7/igt@xe_module_load@load.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-7/igt@xe_module_load@load.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@xe_module_load@load.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@xe_module_load@load.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@xe_module_load@load.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@xe_module_load@load.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-7/igt@xe_module_load@load.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@xe_module_load@load.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@xe_module_load@load.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@xe_module_load@load.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@xe_module_load@load.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@xe_module_load@load.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@xe_module_load@load.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-4/igt@xe_module_load@load.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@xe_module_load@load.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-8/igt@xe_module_load@load.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-8/igt@xe_module_load@load.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-8/igt@xe_module_load@load.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@xe_module_load@load.html
    - shard-bmg:          ([PASS][208], [PASS][209], [PASS][210], [PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232]) -> ([PASS][233], [PASS][234], [PASS][235], [PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [PASS][241], [SKIP][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248], [PASS][249], [PASS][250], [PASS][251], [PASS][252], [PASS][253], [PASS][254], [PASS][255], [PASS][256], [PASS][257], [PASS][258]) ([Intel XE#2457])
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-3/igt@xe_module_load@load.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-3/igt@xe_module_load@load.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-3/igt@xe_module_load@load.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-8/igt@xe_module_load@load.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-3/igt@xe_module_load@load.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-7/igt@xe_module_load@load.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-7/igt@xe_module_load@load.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-6/igt@xe_module_load@load.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-2/igt@xe_module_load@load.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-8/igt@xe_module_load@load.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-6/igt@xe_module_load@load.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-6/igt@xe_module_load@load.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-1/igt@xe_module_load@load.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-4/igt@xe_module_load@load.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-4/igt@xe_module_load@load.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-8/igt@xe_module_load@load.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-8/igt@xe_module_load@load.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-5/igt@xe_module_load@load.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-2/igt@xe_module_load@load.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-4/igt@xe_module_load@load.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-5/igt@xe_module_load@load.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-5/igt@xe_module_load@load.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-2/igt@xe_module_load@load.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-1/igt@xe_module_load@load.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-1/igt@xe_module_load@load.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-5/igt@xe_module_load@load.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@xe_module_load@load.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@xe_module_load@load.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@xe_module_load@load.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@xe_module_load@load.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@xe_module_load@load.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@xe_module_load@load.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@xe_module_load@load.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-3/igt@xe_module_load@load.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@xe_module_load@load.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@xe_module_load@load.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@xe_module_load@load.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@xe_module_load@load.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-3/igt@xe_module_load@load.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-3/igt@xe_module_load@load.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-1/igt@xe_module_load@load.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-1/igt@xe_module_load@load.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-1/igt@xe_module_load@load.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-8/igt@xe_module_load@load.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-8/igt@xe_module_load@load.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@xe_module_load@load.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@xe_module_load@load.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-5/igt@xe_module_load@load.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-5/igt@xe_module_load@load.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@xe_module_load@load.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@xe_module_load@load.html
    - shard-dg2-set2:     ([PASS][259], [PASS][260], [PASS][261], [PASS][262], [PASS][263], [PASS][264], [PASS][265], [PASS][266], [PASS][267], [PASS][268], [PASS][269], [PASS][270], [PASS][271], [PASS][272], [PASS][273], [PASS][274], [PASS][275], [PASS][276], [PASS][277], [PASS][278], [PASS][279], [PASS][280], [PASS][281], [PASS][282]) -> ([PASS][283], [PASS][284], [PASS][285], [PASS][286], [PASS][287], [PASS][288], [PASS][289], [PASS][290], [PASS][291], [PASS][292], [PASS][293], [PASS][294], [PASS][295], [PASS][296], [PASS][297], [PASS][298], [PASS][299], [PASS][300], [PASS][301], [PASS][302], [PASS][303], [SKIP][304], [PASS][305], [PASS][306], [PASS][307], [PASS][308]) ([Intel XE#378])
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@xe_module_load@load.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@xe_module_load@load.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@xe_module_load@load.html
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@xe_module_load@load.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@xe_module_load@load.html
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@xe_module_load@load.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-434/igt@xe_module_load@load.html
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-434/igt@xe_module_load@load.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@xe_module_load@load.html
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@xe_module_load@load.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@xe_module_load@load.html
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-433/igt@xe_module_load@load.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@xe_module_load@load.html
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@xe_module_load@load.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-434/igt@xe_module_load@load.html
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-434/igt@xe_module_load@load.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@xe_module_load@load.html
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-463/igt@xe_module_load@load.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-433/igt@xe_module_load@load.html
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-433/igt@xe_module_load@load.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-433/igt@xe_module_load@load.html
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-433/igt@xe_module_load@load.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-463/igt@xe_module_load@load.html
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-463/igt@xe_module_load@load.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@xe_module_load@load.html
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@xe_module_load@load.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@xe_module_load@load.html
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@xe_module_load@load.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@xe_module_load@load.html
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@xe_module_load@load.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@xe_module_load@load.html
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@xe_module_load@load.html
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@xe_module_load@load.html
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@xe_module_load@load.html
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@xe_module_load@load.html
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@xe_module_load@load.html
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@xe_module_load@load.html
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@xe_module_load@load.html
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@xe_module_load@load.html
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@xe_module_load@load.html
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@xe_module_load@load.html
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@xe_module_load@load.html
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@xe_module_load@load.html
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@xe_module_load@load.html
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@xe_module_load@load.html
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@xe_module_load@load.html
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@xe_module_load@load.html
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@xe_module_load@load.html
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@xe_module_load@load.html
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@xe_module_load@load.html

  * igt@xe_oa@oa-tlb-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][309] ([Intel XE#2248])
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@xe_oa@oa-tlb-invalidate.html
    - shard-bmg:          NOTRUN -> [SKIP][310] ([Intel XE#2248])
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-1/igt@xe_oa@oa-tlb-invalidate.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-dg2-set2:     NOTRUN -> [SKIP][311] ([Intel XE#2284] / [Intel XE#366])
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@xe_pm@d3cold-basic-exec.html
    - shard-bmg:          NOTRUN -> [SKIP][312] ([Intel XE#2284])
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pm@s3-vm-bind-unbind-all:
    - shard-dg2-set2:     [PASS][313] -> [DMESG-WARN][314] ([Intel XE#4330] / [Intel XE#569])
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-434/igt@xe_pm@s3-vm-bind-unbind-all.html
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@xe_pm@s3-vm-bind-unbind-all.html
    - shard-bmg:          [PASS][315] -> [DMESG-WARN][316] ([Intel XE#4330] / [Intel XE#569])
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-1/igt@xe_pm@s3-vm-bind-unbind-all.html
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-8/igt@xe_pm@s3-vm-bind-unbind-all.html

  * igt@xe_pm@s4-basic:
    - shard-dg2-set2:     NOTRUN -> [ABORT][317] ([Intel XE#4268]) +1 other test abort
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@xe_pm@s4-basic.html
    - shard-bmg:          NOTRUN -> [ABORT][318] ([Intel XE#4268]) +1 other test abort
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@xe_pm@s4-basic.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-dg2-set2:     NOTRUN -> [SKIP][319] ([Intel XE#579])
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@xe_pm@vram-d3cold-threshold.html
    - shard-lnl:          NOTRUN -> [SKIP][320] ([Intel XE#579])
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-7/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][321] ([Intel XE#944])
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@xe_query@multigpu-query-uc-fw-version-guc.html
    - shard-lnl:          NOTRUN -> [SKIP][322] ([Intel XE#944])
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@xe_query@multigpu-query-uc-fw-version-guc.html
    - shard-bmg:          NOTRUN -> [SKIP][323] ([Intel XE#944])
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_sriov_auto_provisioning@exclusive-ranges:
    - shard-bmg:          NOTRUN -> [SKIP][324] ([Intel XE#4130]) +1 other test skip
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
    - shard-lnl:          NOTRUN -> [SKIP][325] ([Intel XE#4130]) +1 other test skip
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-6/igt@xe_sriov_auto_provisioning@exclusive-ranges.html

  * igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][326] ([Intel XE#4130]) +2 other tests skip
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic:
    - shard-lnl:          [FAIL][327] ([Intel XE#3719] / [Intel XE#911]) -> [PASS][328] +3 other tests pass
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear:
    - shard-lnl:          [FAIL][329] ([Intel XE#911]) -> [PASS][330] +3 other tests pass
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-dg2-set2:     [SKIP][331] ([Intel XE#2191]) -> [PASS][332]
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-bmg:          [DMESG-WARN][333] ([Intel XE#4330]) -> [PASS][334] +34 other tests pass
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-1/igt@kms_cursor_crc@cursor-suspend.html
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_cursor_edge_walk@128x128-left-edge:
    - shard-dg2-set2:     [INCOMPLETE][335] -> [PASS][336] +3 other tests pass
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-434/igt@kms_cursor_edge_walk@128x128-left-edge.html
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_cursor_edge_walk@128x128-left-edge.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-dg2-set2:     [SKIP][337] ([Intel XE#309]) -> [PASS][338] +2 other tests pass
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@torture-move:
    - shard-bmg:          [INCOMPLETE][339] ([Intel XE#3226]) -> [PASS][340] +1 other test pass
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-7/igt@kms_cursor_legacy@torture-move.html
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_cursor_legacy@torture-move.html

  * igt@kms_dp_aux_dev:
    - shard-dg2-set2:     [SKIP][341] ([Intel XE#3009]) -> [PASS][342]
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_dp_aux_dev.html
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_dp_aux_dev.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-dg2-set2:     [SKIP][343] ([Intel XE#4331]) -> [PASS][344]
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_flip@2x-flip-vs-modeset:
    - shard-dg2-set2:     [SKIP][345] ([Intel XE#310]) -> [PASS][346] +2 other tests pass
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_flip@2x-flip-vs-modeset.html
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_flip@2x-flip-vs-modeset.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-bmg:          [SKIP][347] ([Intel XE#2316]) -> [PASS][348] +4 other tests pass
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-4/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@cd-hdmi-a6-dp4:
    - shard-dg2-set2:     [DMESG-WARN][349] ([Intel XE#4330]) -> [PASS][350] +44 other tests pass
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-434/igt@kms_flip@2x-flip-vs-suspend-interruptible@cd-hdmi-a6-dp4.html
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@kms_flip@2x-flip-vs-suspend-interruptible@cd-hdmi-a6-dp4.html

  * igt@kms_flip@flip-vs-dpms-off-vs-modeset:
    - shard-dg2-set2:     [DMESG-WARN][351] ([Intel XE#2955]) -> [PASS][352] +2 other tests pass
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-463/igt@kms_flip@flip-vs-dpms-off-vs-modeset.html
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_flip@flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg2-set2:     [INCOMPLETE][353] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][354]
   [353]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@kms_flip@flip-vs-suspend.html
   [354]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-lnl:          [FAIL][355] ([Intel XE#886]) -> [PASS][356] +1 other test pass
   [355]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [356]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-7/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-dp2:
    - shard-bmg:          [FAIL][357] ([Intel XE#2882]) -> [PASS][358] +1 other test pass
   [357]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-4/igt@kms_flip@plain-flip-ts-check-interruptible@a-dp2.html
   [358]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@kms_flip@plain-flip-ts-check-interruptible@a-dp2.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     [SKIP][359] ([Intel XE#656]) -> [PASS][360] +3 other tests pass
   [359]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html
   [360]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     [SKIP][361] ([Intel XE#455]) -> [PASS][362] +1 other test pass
   [361]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@kms_hdr@invalid-hdr.html
   [362]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg2-set2:     [SKIP][363] ([Intel XE#4328]) -> [PASS][364]
   [363]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [364]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format:
    - shard-bmg:          [DMESG-WARN][365] ([Intel XE#2566]) -> [PASS][366]
   [365]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-4/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format.html
   [366]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-1/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5:
    - shard-dg2-set2:     [DMESG-WARN][367] ([Intel XE#2566]) -> [PASS][368] +1 other test pass
   [367]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-463/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5.html
   [368]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-dg2-set2:     [DMESG-WARN][369] ([Intel XE#2042]) -> [PASS][370]
   [369]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-433/igt@kms_pm_rpm@system-suspend-modeset.html
   [370]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@xe_oa@closed-fd-and-unmapped-access:
    - shard-dg2-set2:     [SKIP][371] ([Intel XE#2541] / [Intel XE#3573]) -> [PASS][372] +23 other tests pass
   [371]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-433/igt@xe_oa@closed-fd-and-unmapped-access.html
   [372]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@xe_oa@closed-fd-and-unmapped-access.html

  * igt@xe_pm@s3-d3hot-basic-exec:
    - shard-bmg:          [DMESG-WARN][373] ([Intel XE#569]) -> [PASS][374] +5 other tests pass
   [373]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-8/igt@xe_pm@s3-d3hot-basic-exec.html
   [374]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-8/igt@xe_pm@s3-d3hot-basic-exec.html
    - shard-dg2-set2:     [DMESG-WARN][375] ([Intel XE#569]) -> [PASS][376] +4 other tests pass
   [375]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@xe_pm@s3-d3hot-basic-exec.html
   [376]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@xe_pm@s3-d3hot-basic-exec.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-d-hdmi-a-3:
    - shard-bmg:          [INCOMPLETE][377] -> [DMESG-WARN][378] ([Intel XE#4330]) +1 other test dmesg-warn
   [377]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-7/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-hdmi-a-3.html
   [378]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-7/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][379] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][380] ([Intel XE#787]) +14 other tests skip
   [379]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html
   [380]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-463/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          [SKIP][381] ([Intel XE#3433]) -> [SKIP][382] ([Intel XE#2669] / [Intel XE#3433]) +3 other tests skip
   [381]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html
   [382]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-lnl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][383] ([Intel XE#787]) -> [SKIP][384] ([Intel XE#455] / [Intel XE#787]) +6 other tests skip
   [383]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-6.html
   [384]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-bmg:          [DMESG-FAIL][385] ([Intel XE#4330]) -> [SKIP][386] ([Intel XE#2316])
   [385]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [386]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-bmg:          [SKIP][387] ([Intel XE#2316]) -> [FAIL][388] ([Intel XE#3321])
   [387]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [388]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-bmg:          [DMESG-WARN][389] ([Intel XE#4330]) -> [SKIP][390] ([Intel XE#2316])
   [389]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-3/igt@kms_flip@2x-nonexisting-fb.html
   [390]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][391] ([Intel XE#2312]) -> [SKIP][392] ([Intel XE#2311]) +11 other tests skip
   [391]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html
   [392]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [SKIP][393] ([Intel XE#656]) -> [SKIP][394] ([Intel XE#651]) +10 other tests skip
   [393]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html
   [394]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][395] ([Intel XE#2311]) -> [SKIP][396] ([Intel XE#2312]) +16 other tests skip
   [395]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [396]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     [SKIP][397] ([Intel XE#651]) -> [SKIP][398] ([Intel XE#656]) +7 other tests skip
   [397]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html
   [398]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt:
    - shard-dg2-set2:     [SKIP][399] ([Intel XE#656]) -> [DMESG-WARN][400] ([Intel XE#4330])
   [399]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html
   [400]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][401] ([Intel XE#2312]) -> [SKIP][402] ([Intel XE#4141]) +3 other tests skip
   [401]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
   [402]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][403] ([Intel XE#4141]) -> [SKIP][404] ([Intel XE#2312]) +5 other tests skip
   [403]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [404]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [SKIP][405] ([Intel XE#653]) -> [SKIP][406] ([Intel XE#656]) +5 other tests skip
   [405]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html
   [406]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          [SKIP][407] ([Intel XE#2313]) -> [SKIP][408] ([Intel XE#2312]) +18 other tests skip
   [407]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
   [408]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
    - shard-bmg:          [SKIP][409] ([Intel XE#2312]) -> [SKIP][410] ([Intel XE#2313]) +12 other tests skip
   [409]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html
   [410]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt:
    - shard-dg2-set2:     [SKIP][411] ([Intel XE#656]) -> [SKIP][412] ([Intel XE#653]) +7 other tests skip
   [411]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
   [412]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][413] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][414] ([Intel XE#3544])
   [413]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
   [414]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_plane_cursor@overlay:
    - shard-dg2-set2:     [DMESG-WARN][415] ([Intel XE#4330]) -> [INCOMPLETE][416] ([Intel XE#3966])
   [415]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-464/igt@kms_plane_cursor@overlay.html
   [416]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-433/igt@kms_plane_cursor@overlay.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2-set2:     [DMESG-WARN][417] ([Intel XE#4212]) -> [DMESG-WARN][418] ([Intel XE#2705] / [Intel XE#4212])
   [417]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8236/shard-dg2-466/igt@kms_plane_scaling@intel-max-src-size.html
   [418]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/shard-dg2-464/igt@kms_plane_scaling@intel-max-src-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1152]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1152
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1466
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2042]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2042
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2248]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2248
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2550]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2550
  [Intel XE#2566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2566
  [Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2955]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2955
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3433
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3719]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3719
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3767]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3767
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#3966]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3966
  [Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4210]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4210
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4268]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4268
  [Intel XE#4328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4328
  [Intel XE#4330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4330
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4359
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
  [Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#623]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/623
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8236 -> IGTPW_12628
  * Linux: xe-2679-4cc4e3d6ea1543688d62432dbe0fa750780fb262 -> xe-2682-88f261625e1d94c7eba789712b060b368989aea1

  IGTPW_12628: 12628
  IGT_8236: 8236
  xe-2679-4cc4e3d6ea1543688d62432dbe0fa750780fb262: 4cc4e3d6ea1543688d62432dbe0fa750780fb262
  xe-2682-88f261625e1d94c7eba789712b060b368989aea1: 88f261625e1d94c7eba789712b060b368989aea1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12628/index.html

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