From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 12/47] drm/i915: add intel_ddi_set_pipe_settings
Date: Tue, 2 Oct 2012 17:51:47 -0300 [thread overview]
Message-ID: <1349211142-4802-13-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1349211142-4802-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
In theory, all the DDI pipe settings should be set here, including
timing and M/N registers. For now, let's just set the DP MSA
attributes.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++++
drivers/gpu/drm/i915/intel_ddi.c | 33 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 4 +++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ec58a23..9318121 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4526,6 +4526,16 @@
#define PIPE_CLK_SEL_DISABLED (0x0<<29)
#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
+#define _PIPEA_MSA_MISC 0x60410
+#define _PIPEB_MSA_MISC 0x61410
+#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC)
+#define PIPE_MSA_SYNC_CLK (1<<0)
+#define PIPE_MSA_6_BPC (0<<5)
+#define PIPE_MSA_8_BPC (1<<5)
+#define PIPE_MSA_10_BPC (2<<5)
+#define PIPE_MSA_12_BPC (3<<5)
+#define PIPE_MSA_16_BPC (3<<5)
+
/* LCPLL Control */
#define LCPLL_CTL 0x130040
#define LCPLL_PLL_DISABLE (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cf1bb99..fc6679c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -827,6 +827,39 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
return true;
}
+void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ int type = intel_encoder->type;
+ uint32_t temp;
+
+ if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+
+ temp = PIPE_MSA_SYNC_CLK;
+ switch (intel_crtc->bpp) {
+ case 18:
+ temp |= PIPE_MSA_6_BPC;
+ break;
+ case 24:
+ temp |= PIPE_MSA_8_BPC;
+ break;
+ case 30:
+ temp |= PIPE_MSA_10_BPC;
+ break;
+ case 36:
+ temp |= PIPE_MSA_12_BPC;
+ break;
+ default:
+ WARN(1, "%d bpp unsupported by pipe DDI function\n",
+ intel_crtc->bpp);
+ }
+ I915_WRITE(PIPE_MSA_MISC(pipe), temp);
+ }
+}
+
void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5080b53..7f0016a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3218,8 +3218,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
*/
intel_crtc_load_lut(crtc);
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev)) {
+ intel_ddi_set_pipe_settings(crtc);
intel_ddi_enable_pipe_func(crtc);
+ }
intel_enable_pipe(dev_priv, pipe, is_pch_port);
intel_enable_plane(dev_priv, plane, pipe);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7e1e670..ed75a36 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -597,5 +597,6 @@ extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
extern void intel_ddi_pre_enable(struct intel_encoder *intel_encoder);
extern void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
+extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
#endif /* __INTEL_DRV_H__ */
--
1.7.10.4
next prev parent reply other threads:[~2012-10-02 20:53 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-02 20:51 [PATCH 00/47] Haswell clocking and HDMI fixes, DP and eDP support Paulo Zanoni
2012-10-02 20:51 ` [PATCH 01/47] drm/i915: rewrite the LCPLL code Paulo Zanoni
2012-10-03 16:47 ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 02/47] drm/i915: enable and disable DDI_FUNC_CTL at the right time Paulo Zanoni
2012-10-03 17:44 ` Lespiau, Damien
2012-10-04 20:15 ` Paulo Zanoni
2012-10-02 20:51 ` [PATCH 03/47] drm/i915: enable and disable PIPE_CLK_SEL " Paulo Zanoni
2012-10-04 11:28 ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 04/47] drm/i915: completely rewrite the Haswell PLL handling code Paulo Zanoni
2012-10-02 20:51 ` [PATCH 05/47] drm/i915: don't rely on previous values set on DDI_BUF_CTL Paulo Zanoni
2012-10-02 20:51 ` [PATCH 06/47] drm/i915: disable DDI_BUF_CTL at the correct time Paulo Zanoni
2012-10-02 20:51 ` [PATCH 07/47] drm/i915: add haswell_crtc_mode_set Paulo Zanoni
2012-10-04 14:38 ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 08/47] drm/i915: add proper CPU/PCH checks to crtc_mode_set functions Paulo Zanoni
2012-10-02 20:51 ` [PATCH 09/47] drm/i915: add haswell_set_pipeconf Paulo Zanoni
2012-10-04 14:36 ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 10/47] drm/i915: pipe and planes should be disabled on haswell_crtc_mode_set Paulo Zanoni
2012-10-04 14:14 ` Lespiau, Damien
2012-10-05 12:53 ` Paulo Zanoni
2012-10-05 13:15 ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 11/47] drm/i915: add DP support to intel_ddi_enable_pipe_func Paulo Zanoni
2012-10-02 20:51 ` Paulo Zanoni [this message]
2012-10-02 20:51 ` [PATCH 13/47] drm/i915: add DP support to intel_ddi_pll_mode_set Paulo Zanoni
2012-10-02 20:51 ` [PATCH 14/47] drm/i915: add DP support to intel_ddi_disable_port Paulo Zanoni
2012-10-02 20:51 ` [PATCH 15/47] drm/i915: add DP support to intel_ddi_mode_set Paulo Zanoni
2012-10-02 20:51 ` [PATCH 16/47] drm/i915: add basic Haswell DP link train bits Paulo Zanoni
2012-10-02 20:51 ` [PATCH 17/47] drm/i915: use TU_SIZE macro at intel_dp_set_m_n Paulo Zanoni
2012-10-02 20:51 ` [PATCH 18/47] drm/i915: fix Haswell DP M/N registers Paulo Zanoni
2012-10-02 20:51 ` [PATCH 19/47] drm/i915: fix DP AUX register definitions on Haswell Paulo Zanoni
2012-10-02 20:51 ` [PATCH 20/47] drm/i915: add DP support to intel_ddi_get_encoder_port Paulo Zanoni
2012-10-02 20:51 ` [PATCH 21/47] drm/i915: add DP support to intel_ddi_get_hw_state Paulo Zanoni
2012-10-02 20:51 ` [PATCH 22/47] drm/i915: add DP support to intel_enable_ddi Paulo Zanoni
2012-10-02 20:51 ` [PATCH 23/47] drm/i915: implement Haswell DP link train sequence Paulo Zanoni
2012-10-02 20:51 ` [PATCH 24/47] drm/i915: set the correct function pointers for Haswell DP Paulo Zanoni
2012-10-02 20:52 ` [PATCH 25/47] drm/i915: add TRANSCODER_EDP Paulo Zanoni
2012-10-02 20:52 ` [PATCH 26/47] drm/i915: convert PIPE_CLK_SEL to transcoder Paulo Zanoni
2012-10-02 20:52 ` [PATCH 27/47] drm/i915: convert DDI_FUNC_CTL " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 28/47] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state Paulo Zanoni
2012-10-02 20:52 ` [PATCH 29/47] drm/i915: convert PIPECONF to use transcoder instead of pipe Paulo Zanoni
2012-10-02 20:52 ` [PATCH 30/47] drm/i915: convert PIPE_MSA_MISC to transcoder Paulo Zanoni
2012-10-02 20:52 ` [PATCH 31/47] drm/i915: convert CPU M/N timings " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 32/47] drm/i915: convert pipe timing definitions " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 33/47] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP Paulo Zanoni
2012-10-02 20:52 ` [PATCH 34/47] drm/i915: select the correct pipe " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 35/47] drm/i915: set the correct eDP aux channel clock divider on DDI Paulo Zanoni
2012-10-02 20:52 ` [PATCH 36/47] drm/i915: set/unset the DDI eDP backlight Paulo Zanoni
2012-10-02 20:52 ` [PATCH 37/47] drm/i915: turn the eDP DDI panel on/off Paulo Zanoni
2012-10-02 20:52 ` [PATCH 38/47] drm/i915: enable DDI eDP Paulo Zanoni
2012-10-02 20:52 ` [PATCH 39/47] drm/i915: simplify assignments inside intel_dp.c Paulo Zanoni
2012-10-02 20:52 ` [PATCH 40/47] drm/i915: add intel_dp_to_dev and intel_hdmi_to_dev Paulo Zanoni
2012-10-02 20:52 ` [PATCH 41/47] drm/i915: create intel_digital_port and use it Paulo Zanoni
2012-10-02 20:52 ` [PATCH 42/47] drm/i915: remove encoder args from intel_{dp, hdmi}_add_properties Paulo Zanoni
2012-10-02 20:52 ` [PATCH 43/47] drm/i915: split intel_hdmi_init into encoder and connector pieces Paulo Zanoni
2012-10-02 20:52 ` [PATCH 44/47] drm/i915: split intel_dp_init " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 45/47] drm/i915: reset intel_encoder->type when DP or HDMI is detected Paulo Zanoni
2012-10-02 20:52 ` [PATCH 46/47] drm/i915: add intel_ddi_connector_get_hw_state Paulo Zanoni
2012-10-02 20:52 ` [PATCH 47/47] drm/i915: create the DDI encoder Paulo Zanoni
2012-10-05 15:05 ` [PATCH 00/10] Haswell pipe and clocking fixes Paulo Zanoni
2012-10-05 15:05 ` [PATCH 01/10] drm/i915: rewrite the LCPLL code Paulo Zanoni
2012-10-10 12:47 ` Lespiau, Damien
2012-10-10 12:53 ` Lespiau, Damien
2012-10-05 15:05 ` [PATCH 02/10] drm/i915: enable and disable DDI_FUNC_CTL at the right time Paulo Zanoni
2012-10-10 13:04 ` Lespiau, Damien
2012-10-05 15:05 ` [PATCH 03/10] drm/i915: enable and disable PIPE_CLK_SEL " Paulo Zanoni
2012-10-10 13:05 ` Lespiau, Damien
2012-10-05 15:05 ` [PATCH 04/10] drm/i915: add haswell_crtc_mode_set Paulo Zanoni
2012-10-10 13:07 ` Lespiau, Damien
2012-10-05 15:05 ` [PATCH 05/10] drm/i915: add proper CPU/PCH checks to crtc_mode_set functions Paulo Zanoni
2012-10-10 13:52 ` Lespiau, Damien
2012-10-05 15:05 ` [PATCH 06/10] drm/i915: add haswell_set_pipeconf Paulo Zanoni
2012-10-10 13:59 ` Lespiau, Damien
2012-10-05 15:05 ` [PATCH 07/10] drm/i915: completely rewrite the Haswell PLL handling code Paulo Zanoni
2012-10-10 14:22 ` Lespiau, Damien
2012-10-10 14:52 ` Daniel Vetter
2012-10-05 15:05 ` [PATCH 08/10] drm/i915: don't rely on previous values set on DDI_BUF_CTL Paulo Zanoni
2012-10-10 14:27 ` Lespiau, Damien
2012-10-10 14:56 ` Daniel Vetter
2012-10-10 18:18 ` Daniel Vetter
2012-10-05 15:06 ` [PATCH 09/10] drm/i915: disable DDI_BUF_CTL at the correct time Paulo Zanoni
2012-10-10 22:30 ` Lespiau, Damien
2012-10-05 15:06 ` [PATCH 10/10] drm/i915: pipe and planes should be disabled on haswell_crtc_mode_set Paulo Zanoni
2012-10-10 21:57 ` Lespiau, Damien
2012-10-10 22:47 ` Daniel Vetter
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