From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 05/10] drm/i915: add proper CPU/PCH checks to crtc_mode_set functions
Date: Fri, 5 Oct 2012 12:05:56 -0300 [thread overview]
Message-ID: <1349449561-3599-6-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1349449561-3599-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
On ironlake_crtc_mode_set, WARN if not using IBX or CPT.
On haswell_crtc_mode_set, only run IBX/CPT code on IBX/CPT. I am still
not sure whether IBX/CPT will be possible with a Haswell CPU, so leave
the code there for now and put a WARN in case we spot it.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 212 +++++++++++++++++++----------------
1 file changed, 115 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ef89132..213831f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5002,6 +5002,9 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
num_connectors++;
}
+ WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
+ "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
+
ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
&has_reduced_clock, &reduced_clock);
if (!ok) {
@@ -5027,12 +5030,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
drm_mode_debug_printmodeline(mode);
- /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
- * pre-Haswell/LPT generation */
- if (HAS_PCH_LPT(dev)) {
- DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
- pipe);
- } else if (!is_cpu_edp) {
+ /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
+ if (!is_cpu_edp) {
struct intel_pch_pll *pll;
pll = intel_get_pch_pll(intel_crtc, dpll, fp);
@@ -5155,7 +5154,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
int plane = intel_crtc->plane;
int num_connectors = 0;
intel_clock_t clock, reduced_clock;
- u32 dpll, fp = 0, fp2 = 0;
+ u32 dpll = 0, fp = 0, fp2 = 0;
bool ok, has_reduced_clock = false;
bool is_lvds = false, is_dp = false, is_cpu_edp = false;
struct intel_encoder *encoder;
@@ -5181,11 +5180,21 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
num_connectors++;
}
- ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
- &has_reduced_clock, &reduced_clock);
- if (!ok) {
- DRM_ERROR("Couldn't find PLL settings for mode!\n");
- return -EINVAL;
+ /* We are not sure yet this won't happen. */
+ WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
+ INTEL_PCH_TYPE(dev));
+
+ WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
+ num_connectors, pipe_name(pipe));
+
+ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+ ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
+ &has_reduced_clock,
+ &reduced_clock);
+ if (!ok) {
+ DRM_ERROR("Couldn't find PLL settings for mode!\n");
+ return -EINVAL;
+ }
}
/* Ensure that the cursor is valid for the new mode before changing... */
@@ -5196,104 +5205,112 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
if (is_lvds && dev_priv->lvds_dither)
dither = true;
- fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
- if (has_reduced_clock)
- fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
- reduced_clock.m2;
-
- dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
-
DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
drm_mode_debug_printmodeline(mode);
- /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
- * pre-Haswell/LPT generation */
- if (HAS_PCH_LPT(dev)) {
- DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
- pipe);
- } else if (!is_cpu_edp) {
- struct intel_pch_pll *pll;
+ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+ fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
+ if (has_reduced_clock)
+ fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
+ reduced_clock.m2;
+
+ dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
+ fp);
+
+ /* CPU eDP is the only output that doesn't need a PCH PLL of its
+ * own on pre-Haswell/LPT generation */
+ if (!is_cpu_edp) {
+ struct intel_pch_pll *pll;
+
+ pll = intel_get_pch_pll(intel_crtc, dpll, fp);
+ if (pll == NULL) {
+ DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
+ pipe);
+ return -EINVAL;
+ }
+ } else
+ intel_put_pch_pll(intel_crtc);
- pll = intel_get_pch_pll(intel_crtc, dpll, fp);
- if (pll == NULL) {
- DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
- pipe);
- return -EINVAL;
- }
- } else
- intel_put_pch_pll(intel_crtc);
+ /* The LVDS pin pair needs to be on before the DPLLs are
+ * enabled. This is an exception to the general rule that
+ * mode_set doesn't turn things on.
+ */
+ if (is_lvds) {
+ temp = I915_READ(PCH_LVDS);
+ temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
+ if (HAS_PCH_CPT(dev)) {
+ temp &= ~PORT_TRANS_SEL_MASK;
+ temp |= PORT_TRANS_SEL_CPT(pipe);
+ } else {
+ if (pipe == 1)
+ temp |= LVDS_PIPEB_SELECT;
+ else
+ temp &= ~LVDS_PIPEB_SELECT;
+ }
- /* The LVDS pin pair needs to be on before the DPLLs are enabled.
- * This is an exception to the general rule that mode_set doesn't turn
- * things on.
- */
- if (is_lvds) {
- temp = I915_READ(PCH_LVDS);
- temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
- if (HAS_PCH_CPT(dev)) {
- temp &= ~PORT_TRANS_SEL_MASK;
- temp |= PORT_TRANS_SEL_CPT(pipe);
- } else {
- if (pipe == 1)
- temp |= LVDS_PIPEB_SELECT;
+ /* set the corresponsding LVDS_BORDER bit */
+ temp |= dev_priv->lvds_border_bits;
+ /* Set the B0-B3 data pairs corresponding to whether
+ * we're going to set the DPLLs for dual-channel mode or
+ * not.
+ */
+ if (clock.p2 == 7)
+ temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
else
- temp &= ~LVDS_PIPEB_SELECT;
+ temp &= ~(LVDS_B0B3_POWER_UP |
+ LVDS_CLKB_POWER_UP);
+
+ /* It would be nice to set 24 vs 18-bit mode
+ * (LVDS_A3_POWER_UP) appropriately here, but we need to
+ * look more thoroughly into how panels behave in the
+ * two modes.
+ */
+ temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+ temp |= LVDS_HSYNC_POLARITY;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+ temp |= LVDS_VSYNC_POLARITY;
+ I915_WRITE(PCH_LVDS, temp);
}
-
- /* set the corresponsding LVDS_BORDER bit */
- temp |= dev_priv->lvds_border_bits;
- /* Set the B0-B3 data pairs corresponding to whether we're going to
- * set the DPLLs for dual-channel mode or not.
- */
- if (clock.p2 == 7)
- temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
- else
- temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
-
- /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
- * appropriately here, but we need to look more thoroughly into how
- * panels behave in the two modes.
- */
- temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
- if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
- temp |= LVDS_HSYNC_POLARITY;
- if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
- temp |= LVDS_VSYNC_POLARITY;
- I915_WRITE(PCH_LVDS, temp);
}
if (is_dp && !is_cpu_edp) {
intel_dp_set_m_n(crtc, mode, adjusted_mode);
} else {
- /* For non-DP output, clear any trans DP clock recovery setting.*/
- I915_WRITE(TRANSDATA_M1(pipe), 0);
- I915_WRITE(TRANSDATA_N1(pipe), 0);
- I915_WRITE(TRANSDPLINK_M1(pipe), 0);
- I915_WRITE(TRANSDPLINK_N1(pipe), 0);
- }
-
- if (intel_crtc->pch_pll) {
- I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
-
- /* Wait for the clocks to stabilize. */
- POSTING_READ(intel_crtc->pch_pll->pll_reg);
- udelay(150);
-
- /* The pixel multiplier can only be updated once the
- * DPLL is enabled and the clocks are stable.
- *
- * So write it again.
- */
- I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
+ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+ /* For non-DP output, clear any trans DP clock recovery
+ * setting.*/
+ I915_WRITE(TRANSDATA_M1(pipe), 0);
+ I915_WRITE(TRANSDATA_N1(pipe), 0);
+ I915_WRITE(TRANSDPLINK_M1(pipe), 0);
+ I915_WRITE(TRANSDPLINK_N1(pipe), 0);
+ }
}
intel_crtc->lowfreq_avail = false;
- if (intel_crtc->pch_pll) {
- if (is_lvds && has_reduced_clock && i915_powersave) {
- I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
- intel_crtc->lowfreq_avail = true;
- } else {
- I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
+ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+ if (intel_crtc->pch_pll) {
+ I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
+
+ /* Wait for the clocks to stabilize. */
+ POSTING_READ(intel_crtc->pch_pll->pll_reg);
+ udelay(150);
+
+ /* The pixel multiplier can only be updated once the
+ * DPLL is enabled and the clocks are stable.
+ *
+ * So write it again.
+ */
+ I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
+ }
+
+ if (intel_crtc->pch_pll) {
+ if (is_lvds && has_reduced_clock && i915_powersave) {
+ I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
+ intel_crtc->lowfreq_avail = true;
+ } else {
+ I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
+ }
}
}
@@ -5301,8 +5318,9 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
ironlake_set_m_n(crtc, mode, adjusted_mode);
- if (is_cpu_edp)
- ironlake_set_pll_edp(crtc, adjusted_mode->clock);
+ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+ if (is_cpu_edp)
+ ironlake_set_pll_edp(crtc, adjusted_mode->clock);
ironlake_set_pipeconf(crtc, adjusted_mode, dither);
--
1.7.11.4
next prev parent reply other threads:[~2012-10-05 15:06 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-02 20:51 [PATCH 00/47] Haswell clocking and HDMI fixes, DP and eDP support Paulo Zanoni
2012-10-02 20:51 ` [PATCH 01/47] drm/i915: rewrite the LCPLL code Paulo Zanoni
2012-10-03 16:47 ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 02/47] drm/i915: enable and disable DDI_FUNC_CTL at the right time Paulo Zanoni
2012-10-03 17:44 ` Lespiau, Damien
2012-10-04 20:15 ` Paulo Zanoni
2012-10-02 20:51 ` [PATCH 03/47] drm/i915: enable and disable PIPE_CLK_SEL " Paulo Zanoni
2012-10-04 11:28 ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 04/47] drm/i915: completely rewrite the Haswell PLL handling code Paulo Zanoni
2012-10-02 20:51 ` [PATCH 05/47] drm/i915: don't rely on previous values set on DDI_BUF_CTL Paulo Zanoni
2012-10-02 20:51 ` [PATCH 06/47] drm/i915: disable DDI_BUF_CTL at the correct time Paulo Zanoni
2012-10-02 20:51 ` [PATCH 07/47] drm/i915: add haswell_crtc_mode_set Paulo Zanoni
2012-10-04 14:38 ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 08/47] drm/i915: add proper CPU/PCH checks to crtc_mode_set functions Paulo Zanoni
2012-10-02 20:51 ` [PATCH 09/47] drm/i915: add haswell_set_pipeconf Paulo Zanoni
2012-10-04 14:36 ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 10/47] drm/i915: pipe and planes should be disabled on haswell_crtc_mode_set Paulo Zanoni
2012-10-04 14:14 ` Lespiau, Damien
2012-10-05 12:53 ` Paulo Zanoni
2012-10-05 13:15 ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 11/47] drm/i915: add DP support to intel_ddi_enable_pipe_func Paulo Zanoni
2012-10-02 20:51 ` [PATCH 12/47] drm/i915: add intel_ddi_set_pipe_settings Paulo Zanoni
2012-10-02 20:51 ` [PATCH 13/47] drm/i915: add DP support to intel_ddi_pll_mode_set Paulo Zanoni
2012-10-02 20:51 ` [PATCH 14/47] drm/i915: add DP support to intel_ddi_disable_port Paulo Zanoni
2012-10-02 20:51 ` [PATCH 15/47] drm/i915: add DP support to intel_ddi_mode_set Paulo Zanoni
2012-10-02 20:51 ` [PATCH 16/47] drm/i915: add basic Haswell DP link train bits Paulo Zanoni
2012-10-02 20:51 ` [PATCH 17/47] drm/i915: use TU_SIZE macro at intel_dp_set_m_n Paulo Zanoni
2012-10-02 20:51 ` [PATCH 18/47] drm/i915: fix Haswell DP M/N registers Paulo Zanoni
2012-10-02 20:51 ` [PATCH 19/47] drm/i915: fix DP AUX register definitions on Haswell Paulo Zanoni
2012-10-02 20:51 ` [PATCH 20/47] drm/i915: add DP support to intel_ddi_get_encoder_port Paulo Zanoni
2012-10-02 20:51 ` [PATCH 21/47] drm/i915: add DP support to intel_ddi_get_hw_state Paulo Zanoni
2012-10-02 20:51 ` [PATCH 22/47] drm/i915: add DP support to intel_enable_ddi Paulo Zanoni
2012-10-02 20:51 ` [PATCH 23/47] drm/i915: implement Haswell DP link train sequence Paulo Zanoni
2012-10-02 20:51 ` [PATCH 24/47] drm/i915: set the correct function pointers for Haswell DP Paulo Zanoni
2012-10-02 20:52 ` [PATCH 25/47] drm/i915: add TRANSCODER_EDP Paulo Zanoni
2012-10-02 20:52 ` [PATCH 26/47] drm/i915: convert PIPE_CLK_SEL to transcoder Paulo Zanoni
2012-10-02 20:52 ` [PATCH 27/47] drm/i915: convert DDI_FUNC_CTL " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 28/47] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state Paulo Zanoni
2012-10-02 20:52 ` [PATCH 29/47] drm/i915: convert PIPECONF to use transcoder instead of pipe Paulo Zanoni
2012-10-02 20:52 ` [PATCH 30/47] drm/i915: convert PIPE_MSA_MISC to transcoder Paulo Zanoni
2012-10-02 20:52 ` [PATCH 31/47] drm/i915: convert CPU M/N timings " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 32/47] drm/i915: convert pipe timing definitions " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 33/47] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP Paulo Zanoni
2012-10-02 20:52 ` [PATCH 34/47] drm/i915: select the correct pipe " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 35/47] drm/i915: set the correct eDP aux channel clock divider on DDI Paulo Zanoni
2012-10-02 20:52 ` [PATCH 36/47] drm/i915: set/unset the DDI eDP backlight Paulo Zanoni
2012-10-02 20:52 ` [PATCH 37/47] drm/i915: turn the eDP DDI panel on/off Paulo Zanoni
2012-10-02 20:52 ` [PATCH 38/47] drm/i915: enable DDI eDP Paulo Zanoni
2012-10-02 20:52 ` [PATCH 39/47] drm/i915: simplify assignments inside intel_dp.c Paulo Zanoni
2012-10-02 20:52 ` [PATCH 40/47] drm/i915: add intel_dp_to_dev and intel_hdmi_to_dev Paulo Zanoni
2012-10-02 20:52 ` [PATCH 41/47] drm/i915: create intel_digital_port and use it Paulo Zanoni
2012-10-02 20:52 ` [PATCH 42/47] drm/i915: remove encoder args from intel_{dp, hdmi}_add_properties Paulo Zanoni
2012-10-02 20:52 ` [PATCH 43/47] drm/i915: split intel_hdmi_init into encoder and connector pieces Paulo Zanoni
2012-10-02 20:52 ` [PATCH 44/47] drm/i915: split intel_dp_init " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 45/47] drm/i915: reset intel_encoder->type when DP or HDMI is detected Paulo Zanoni
2012-10-02 20:52 ` [PATCH 46/47] drm/i915: add intel_ddi_connector_get_hw_state Paulo Zanoni
2012-10-02 20:52 ` [PATCH 47/47] drm/i915: create the DDI encoder Paulo Zanoni
2012-10-05 15:05 ` [PATCH 00/10] Haswell pipe and clocking fixes Paulo Zanoni
2012-10-05 15:05 ` [PATCH 01/10] drm/i915: rewrite the LCPLL code Paulo Zanoni
2012-10-10 12:47 ` Lespiau, Damien
2012-10-10 12:53 ` Lespiau, Damien
2012-10-05 15:05 ` [PATCH 02/10] drm/i915: enable and disable DDI_FUNC_CTL at the right time Paulo Zanoni
2012-10-10 13:04 ` Lespiau, Damien
2012-10-05 15:05 ` [PATCH 03/10] drm/i915: enable and disable PIPE_CLK_SEL " Paulo Zanoni
2012-10-10 13:05 ` Lespiau, Damien
2012-10-05 15:05 ` [PATCH 04/10] drm/i915: add haswell_crtc_mode_set Paulo Zanoni
2012-10-10 13:07 ` Lespiau, Damien
2012-10-05 15:05 ` Paulo Zanoni [this message]
2012-10-10 13:52 ` [PATCH 05/10] drm/i915: add proper CPU/PCH checks to crtc_mode_set functions Lespiau, Damien
2012-10-05 15:05 ` [PATCH 06/10] drm/i915: add haswell_set_pipeconf Paulo Zanoni
2012-10-10 13:59 ` Lespiau, Damien
2012-10-05 15:05 ` [PATCH 07/10] drm/i915: completely rewrite the Haswell PLL handling code Paulo Zanoni
2012-10-10 14:22 ` Lespiau, Damien
2012-10-10 14:52 ` Daniel Vetter
2012-10-05 15:05 ` [PATCH 08/10] drm/i915: don't rely on previous values set on DDI_BUF_CTL Paulo Zanoni
2012-10-10 14:27 ` Lespiau, Damien
2012-10-10 14:56 ` Daniel Vetter
2012-10-10 18:18 ` Daniel Vetter
2012-10-05 15:06 ` [PATCH 09/10] drm/i915: disable DDI_BUF_CTL at the correct time Paulo Zanoni
2012-10-10 22:30 ` Lespiau, Damien
2012-10-05 15:06 ` [PATCH 10/10] drm/i915: pipe and planes should be disabled on haswell_crtc_mode_set Paulo Zanoni
2012-10-10 21:57 ` Lespiau, Damien
2012-10-10 22:47 ` Daniel Vetter
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