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From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 25/47] drm/i915: add TRANSCODER_EDP
Date: Tue,  2 Oct 2012 17:52:00 -0300	[thread overview]
Message-ID: <1349211142-4802-26-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1349211142-4802-1-git-send-email-przanoni@gmail.com>

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Before Haswell we used to have 3 pipes (A, B and C) and 3 transcoders
(A, B and C), and there was an 1:1 mapping on then. Because of this
mapping, every register that was actually part of the transcoder was
called PIPE_SOMETHING instead of TRANSCODER_SOMETHING and its
definition used the PIPE macro.

Starting from Haswell, we have 3 pipes (A, B and C) but 4 transcoders
(A, B, C and EDP). Transcoder EDP can be connected to any of the 3
pipes, and as its name says, it is used by EDP.

For now we're just creating the transcoder definitions and setting
transcoder to TRANSCODER_EDP on DDI eDP code, but none of the
registers was ported to use transcoder instead of pipe.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |    8 ++++++++
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |   20 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |    3 +++
 4 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc3761e..14ba368 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -58,6 +58,14 @@ enum pipe {
 };
 #define pipe_name(p) ((p) + 'A')
 
+enum transcoder {
+	TRANSCODER_A = 0,
+	TRANSCODER_B,
+	TRANSCODER_C,
+	TRANSCODER_EDP = 0xF,
+};
+#define transcoder_name(t) ((t) + 'A')
+
 enum plane {
 	PLANE_A = 0,
 	PLANE_B,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 982985c..de95698 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
 #define _I915_REG_H_
 
 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
 
 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a83cd99..0fccbe6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -927,6 +927,15 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 	return true;
 }
 
+enum transcoder pipe_to_transcoder(struct drm_i915_private *dev_priv,
+				   enum pipe pipe)
+{
+	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	return intel_crtc->transcoder;
+}
+
 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3336,6 +3345,9 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
 
 static void haswell_crtc_off(struct drm_crtc *crtc)
 {
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	intel_crtc->transcoder = intel_crtc->pipe;
 	intel_ddi_put_crtc_pll(crtc);
 }
 
@@ -5184,6 +5196,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
+	enum transcoder transcoder;
 	int num_connectors = 0;
 	intel_clock_t clock, reduced_clock;
 	u32 dpll = 0, fp = 0, fp2 = 0;
@@ -5212,6 +5225,12 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 		num_connectors++;
 	}
 
+	if (is_cpu_edp)
+		transcoder = TRANSCODER_EDP;
+	else
+		transcoder = pipe;
+	intel_crtc->transcoder = transcoder;
+
 	WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
 	     INTEL_PCH_TYPE(dev));
 
@@ -7769,6 +7788,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
 	/* Swap pipes & planes for FBC on pre-965 */
 	intel_crtc->pipe = pipe;
 	intel_crtc->plane = pipe;
+	intel_crtc->transcoder = pipe;
 	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
 		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
 		intel_crtc->plane = !pipe;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 95cbd67..ca06ebb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -185,6 +185,7 @@ struct intel_crtc {
 	struct drm_crtc base;
 	enum pipe pipe;
 	enum plane plane;
+	enum transcoder transcoder;
 	u8 lut_r[256], lut_g[256], lut_b[256];
 	/*
 	 * Whether the crtc and the connected output pipeline is active. Implies
@@ -491,6 +492,8 @@ extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 						    struct drm_crtc *crtc);
 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
+extern enum transcoder pipe_to_transcoder(struct drm_i915_private *dev_priv,
+					  enum pipe pipe);
 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 
-- 
1.7.10.4

  parent reply	other threads:[~2012-10-02 20:53 UTC|newest]

Thread overview: 83+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-02 20:51 [PATCH 00/47] Haswell clocking and HDMI fixes, DP and eDP support Paulo Zanoni
2012-10-02 20:51 ` [PATCH 01/47] drm/i915: rewrite the LCPLL code Paulo Zanoni
2012-10-03 16:47   ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 02/47] drm/i915: enable and disable DDI_FUNC_CTL at the right time Paulo Zanoni
2012-10-03 17:44   ` Lespiau, Damien
2012-10-04 20:15     ` Paulo Zanoni
2012-10-02 20:51 ` [PATCH 03/47] drm/i915: enable and disable PIPE_CLK_SEL " Paulo Zanoni
2012-10-04 11:28   ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 04/47] drm/i915: completely rewrite the Haswell PLL handling code Paulo Zanoni
2012-10-02 20:51 ` [PATCH 05/47] drm/i915: don't rely on previous values set on DDI_BUF_CTL Paulo Zanoni
2012-10-02 20:51 ` [PATCH 06/47] drm/i915: disable DDI_BUF_CTL at the correct time Paulo Zanoni
2012-10-02 20:51 ` [PATCH 07/47] drm/i915: add haswell_crtc_mode_set Paulo Zanoni
2012-10-04 14:38   ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 08/47] drm/i915: add proper CPU/PCH checks to crtc_mode_set functions Paulo Zanoni
2012-10-02 20:51 ` [PATCH 09/47] drm/i915: add haswell_set_pipeconf Paulo Zanoni
2012-10-04 14:36   ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 10/47] drm/i915: pipe and planes should be disabled on haswell_crtc_mode_set Paulo Zanoni
2012-10-04 14:14   ` Lespiau, Damien
2012-10-05 12:53     ` Paulo Zanoni
2012-10-05 13:15       ` Lespiau, Damien
2012-10-02 20:51 ` [PATCH 11/47] drm/i915: add DP support to intel_ddi_enable_pipe_func Paulo Zanoni
2012-10-02 20:51 ` [PATCH 12/47] drm/i915: add intel_ddi_set_pipe_settings Paulo Zanoni
2012-10-02 20:51 ` [PATCH 13/47] drm/i915: add DP support to intel_ddi_pll_mode_set Paulo Zanoni
2012-10-02 20:51 ` [PATCH 14/47] drm/i915: add DP support to intel_ddi_disable_port Paulo Zanoni
2012-10-02 20:51 ` [PATCH 15/47] drm/i915: add DP support to intel_ddi_mode_set Paulo Zanoni
2012-10-02 20:51 ` [PATCH 16/47] drm/i915: add basic Haswell DP link train bits Paulo Zanoni
2012-10-02 20:51 ` [PATCH 17/47] drm/i915: use TU_SIZE macro at intel_dp_set_m_n Paulo Zanoni
2012-10-02 20:51 ` [PATCH 18/47] drm/i915: fix Haswell DP M/N registers Paulo Zanoni
2012-10-02 20:51 ` [PATCH 19/47] drm/i915: fix DP AUX register definitions on Haswell Paulo Zanoni
2012-10-02 20:51 ` [PATCH 20/47] drm/i915: add DP support to intel_ddi_get_encoder_port Paulo Zanoni
2012-10-02 20:51 ` [PATCH 21/47] drm/i915: add DP support to intel_ddi_get_hw_state Paulo Zanoni
2012-10-02 20:51 ` [PATCH 22/47] drm/i915: add DP support to intel_enable_ddi Paulo Zanoni
2012-10-02 20:51 ` [PATCH 23/47] drm/i915: implement Haswell DP link train sequence Paulo Zanoni
2012-10-02 20:51 ` [PATCH 24/47] drm/i915: set the correct function pointers for Haswell DP Paulo Zanoni
2012-10-02 20:52 ` Paulo Zanoni [this message]
2012-10-02 20:52 ` [PATCH 26/47] drm/i915: convert PIPE_CLK_SEL to transcoder Paulo Zanoni
2012-10-02 20:52 ` [PATCH 27/47] drm/i915: convert DDI_FUNC_CTL " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 28/47] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state Paulo Zanoni
2012-10-02 20:52 ` [PATCH 29/47] drm/i915: convert PIPECONF to use transcoder instead of pipe Paulo Zanoni
2012-10-02 20:52 ` [PATCH 30/47] drm/i915: convert PIPE_MSA_MISC to transcoder Paulo Zanoni
2012-10-02 20:52 ` [PATCH 31/47] drm/i915: convert CPU M/N timings " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 32/47] drm/i915: convert pipe timing definitions " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 33/47] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP Paulo Zanoni
2012-10-02 20:52 ` [PATCH 34/47] drm/i915: select the correct pipe " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 35/47] drm/i915: set the correct eDP aux channel clock divider on DDI Paulo Zanoni
2012-10-02 20:52 ` [PATCH 36/47] drm/i915: set/unset the DDI eDP backlight Paulo Zanoni
2012-10-02 20:52 ` [PATCH 37/47] drm/i915: turn the eDP DDI panel on/off Paulo Zanoni
2012-10-02 20:52 ` [PATCH 38/47] drm/i915: enable DDI eDP Paulo Zanoni
2012-10-02 20:52 ` [PATCH 39/47] drm/i915: simplify assignments inside intel_dp.c Paulo Zanoni
2012-10-02 20:52 ` [PATCH 40/47] drm/i915: add intel_dp_to_dev and intel_hdmi_to_dev Paulo Zanoni
2012-10-02 20:52 ` [PATCH 41/47] drm/i915: create intel_digital_port and use it Paulo Zanoni
2012-10-02 20:52 ` [PATCH 42/47] drm/i915: remove encoder args from intel_{dp, hdmi}_add_properties Paulo Zanoni
2012-10-02 20:52 ` [PATCH 43/47] drm/i915: split intel_hdmi_init into encoder and connector pieces Paulo Zanoni
2012-10-02 20:52 ` [PATCH 44/47] drm/i915: split intel_dp_init " Paulo Zanoni
2012-10-02 20:52 ` [PATCH 45/47] drm/i915: reset intel_encoder->type when DP or HDMI is detected Paulo Zanoni
2012-10-02 20:52 ` [PATCH 46/47] drm/i915: add intel_ddi_connector_get_hw_state Paulo Zanoni
2012-10-02 20:52 ` [PATCH 47/47] drm/i915: create the DDI encoder Paulo Zanoni
2012-10-05 15:05 ` [PATCH 00/10] Haswell pipe and clocking fixes Paulo Zanoni
2012-10-05 15:05   ` [PATCH 01/10] drm/i915: rewrite the LCPLL code Paulo Zanoni
2012-10-10 12:47     ` Lespiau, Damien
2012-10-10 12:53       ` Lespiau, Damien
2012-10-05 15:05   ` [PATCH 02/10] drm/i915: enable and disable DDI_FUNC_CTL at the right time Paulo Zanoni
2012-10-10 13:04     ` Lespiau, Damien
2012-10-05 15:05   ` [PATCH 03/10] drm/i915: enable and disable PIPE_CLK_SEL " Paulo Zanoni
2012-10-10 13:05     ` Lespiau, Damien
2012-10-05 15:05   ` [PATCH 04/10] drm/i915: add haswell_crtc_mode_set Paulo Zanoni
2012-10-10 13:07     ` Lespiau, Damien
2012-10-05 15:05   ` [PATCH 05/10] drm/i915: add proper CPU/PCH checks to crtc_mode_set functions Paulo Zanoni
2012-10-10 13:52     ` Lespiau, Damien
2012-10-05 15:05   ` [PATCH 06/10] drm/i915: add haswell_set_pipeconf Paulo Zanoni
2012-10-10 13:59     ` Lespiau, Damien
2012-10-05 15:05   ` [PATCH 07/10] drm/i915: completely rewrite the Haswell PLL handling code Paulo Zanoni
2012-10-10 14:22     ` Lespiau, Damien
2012-10-10 14:52       ` Daniel Vetter
2012-10-05 15:05   ` [PATCH 08/10] drm/i915: don't rely on previous values set on DDI_BUF_CTL Paulo Zanoni
2012-10-10 14:27     ` Lespiau, Damien
2012-10-10 14:56       ` Daniel Vetter
2012-10-10 18:18         ` Daniel Vetter
2012-10-05 15:06   ` [PATCH 09/10] drm/i915: disable DDI_BUF_CTL at the correct time Paulo Zanoni
2012-10-10 22:30     ` Lespiau, Damien
2012-10-05 15:06   ` [PATCH 10/10] drm/i915: pipe and planes should be disabled on haswell_crtc_mode_set Paulo Zanoni
2012-10-10 21:57     ` Lespiau, Damien
2012-10-10 22:47       ` Daniel Vetter

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