Re: [PATCH 01/24] drm/i915: add Haswell DIP controls registers

[Jesse Barnes <jbarnes@virtuousgeek.org>]

On Thu, 26 Apr 2012 21:18:52 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Thu, Apr 26, 2012 at 03:20:56PM -0300, Eugeni Dodonov wrote:
> > Haswell has different DIP control registers and offsets.
> > 
> > Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> 
> Afaict hsw has a dip reg for every type of info frame, whereas older
> machines have one dip reg and a switch in the control reg. Can you please
> the definitions for the other regs here, too, and a big yelling FIXME
> comment in the second patch saying that this is a hack and Paulo needs to
> fix things up?
> -Daniel
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |   16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f1f4d8f..4f17b74 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3518,6 +3518,22 @@
> >  #define VLV_TVIDEO_DIP_GCP(pipe) \
> >  	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
> >  
> > +/* Haswell DIP controls */
> > +#define HSW_VIDEO_DIP_CTL_A			0x60200
> > +#define HSW_VIDEO_DIP_AVI_DATA_A	0x60220
> > +#define HSW_VIDEO_DIP_GCP_A			0x60210
> > +
> > +#define HSW_VIDEO_DIP_CTL_B			0x61200
> > +#define HSW_VIDEO_DIP_AVI_DATA_B	0x61220
> > +#define HSW_VIDEO_DIP_GCP_B			0x61210
> > +
> > +#define HSW_TVIDEO_DIP_CTL(pipe) \
> > +	 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
> > +#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
> > +	 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
> > +#define HSW_TVIDEO_DIP_GCP(pipe) \
> > +	_PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
> > +
> >  #define _TRANS_HTOTAL_B          0xe1000
> >  #define _TRANS_HBLANK_B          0xe1004
> >  #define _TRANS_HSYNC_B           0xe1008
> > -- 
> > 1.7.10

I'd just roll this patch into the patch that adds the HSW specific
infoframe functions...

-- 
Jesse Barnes, Intel Open Source Technology Center