Re: [PATCH 01/24] drm/i915: add Haswell DIP controls registers

[Jesse Barnes <jbarnes@virtuousgeek.org>]

On Thu, 26 Apr 2012 16:42:46 -0300
Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:

> Haswell has different DIP control registers and offsets.
> 
> v2: also add the new DIP frame registers, as suggested by Daniel Vetter.
> v2.1: fix a typo in HSW_VIDEO_DIP_VS_DATA name for 2nd register.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f1f4d8f..76e2233 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3518,6 +3518,40 @@
>  #define VLV_TVIDEO_DIP_GCP(pipe) \
>  	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
>  
> +/* Haswell DIP controls */
> +#define HSW_VIDEO_DIP_CTL_A		0x60200
> +#define HSW_VIDEO_DIP_AVI_DATA_A	0x60220
> +#define HSW_VIDEO_DIP_VS_DATA_A		0x60260
> +#define HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
> +#define HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
> +#define HSW_VIDEO_DIP_VSC_DATA_A	0x60320
> +#define HSW_VIDEO_DIP_AVI_ECC_A		0x60240
> +#define HSW_VIDEO_DIP_VS_ECC_A		0x60280
> +#define HSW_VIDEO_DIP_SPD_ECC_A		0x602C0
> +#define HSW_VIDEO_DIP_GMP_ECC_A		0x60300
> +#define HSW_VIDEO_DIP_VSC_ECC_A		0x60344
> +#define HSW_VIDEO_DIP_GCP_A		0x60210
> +
> +#define HSW_VIDEO_DIP_CTL_B		0x61200
> +#define HSW_VIDEO_DIP_AVI_DATA_B	0x61220
> +#define HSW_VIDEO_DIP_VS_DATA_B		0x61260
> +#define HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
> +#define HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
> +#define HSW_VIDEO_DIP_VSC_DATA_B	0x61320
> +#define HSW_VIDEO_DIP_BVI_ECC_B		0x61240
> +#define HSW_VIDEO_DIP_VS_ECC_B		0x61280
> +#define HSW_VIDEO_DIP_SPD_ECC_B		0x612C0
> +#define HSW_VIDEO_DIP_GMP_ECC_B		0x61300
> +#define HSW_VIDEO_DIP_VSC_ECC_B		0x61344
> +#define HSW_VIDEO_DIP_GCP_B		0x61210
> +
> +#define HSW_TVIDEO_DIP_CTL(pipe) \
> +	 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
> +#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
> +	 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
> +#define HSW_TVIDEO_DIP_GCP(pipe) \
> +	_PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
> +
>  #define _TRANS_HTOTAL_B          0xe1000
>  #define _TRANS_HBLANK_B          0xe1004
>  #define _TRANS_HSYNC_B           0xe1008

Offsets look good, I'd just add a switch statement to the infoframe
write function so we write the correct data regs...

-- 
Jesse Barnes, Intel Open Source Technology Center