Updated workaround & VLV fixes

Updated workaround & VLV fixes

[Jesse Barnes]

I still need to rework the dual dispatch and store dw workarounds based
on comments, but I think the others are ok now, and I included a couple
of fixes for VLV stuff in the bomb here too.

Thanks,
Jesse

[PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen

[Jesse Barnes]

Add a few regs needed for various clock gating init purposes and make
sure they don't fall into the display offset range on VLV.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |   17 +++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h |   11 +++++++++++
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a7837e5..205f61c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1128,6 +1128,23 @@ static bool IS_DISPLAYREG(u32 reg)
 	if (reg == GEN6_GDRST)
 		return false;
 
+	switch (reg) {
+	case _3D_CHICKEN3:
+	case IVB_CHICKEN3:
+	case GEN7_HALF_SLICE_CHICKEN1:
+	case GEN7_COMMON_SLICE_CHICKEN1:
+	case GEN7_L3CNTLREG1:
+	case GEN7_L3_CHICKEN_MODE_REGISTER:
+	case GEN7_ROW_CHICKEN2:
+	case GEN7_L3SQCREG4:
+	case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
+	case GEN6_MBCTL:
+	case GEN6_UCGCTL2:
+	case GEN7_UCGCTL4:
+		return false;
+	default:
+		break;
+	}
 	return true;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a828e90..7d133a1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -544,6 +544,8 @@
 #define IIR		0x020a4
 #define IMR		0x020a8
 #define ISR		0x020ac
+#define VLV_GUNIT_CLOCK_GATE	0x182060
+#define   GCFG_DIS		(1<<8)
 #define VLV_IIR_RW	0x182084
 #define VLV_IER		0x1820a0
 #define VLV_IIR		0x1820a4
@@ -4244,6 +4246,15 @@
 #define GEN7_L3LOG_BASE			0xB070
 #define GEN7_L3LOG_SIZE			0x80
 
+#define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
+#define GEN7_HALF_SLICE_CHICKEN1_IVB	0xf100
+#define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
+#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
+
+#define GEN7_ROW_CHICKEN2		0xe4f4
+#define GEN7_ROW_CHICKEN2_GT2		0xf4f4
+#define   DOP_CLOCK_GATING_DISABLE	(1<<0)
+
 #define G4X_AUD_VID_DID			0x62020
 #define INTEL_AUDIO_DEVCL		0x808629FB
 #define INTEL_AUDIO_DEVBLC		0x80862801
-- 
1.7.9.5

[PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV

[Jesse Barnes]

Needs to be set on every context restore as well, so set it as part of
the initial state so we can save/restore it.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |    1 +
 drivers/gpu/drm/i915/intel_pm.c |    2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7d133a1..58935a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3442,6 +3442,7 @@
 
 #define GEN7_L3CNTLREG1				0xB01C
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
+#define  GEN7_L3AGDIS				(1<<19)
 
 #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
 #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 82ca172..f7344c9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3614,7 +3614,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
 
 	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
-	I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
+	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
 	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
 
 	/* This is required by WaCatErrorRejectionIssue */
-- 
1.7.9.5

[PATCH 03/12] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB

[Jesse Barnes]

v2: use correct register

References: https://bugs.freedesktop.org/show_bug.cgi?id=50233
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |    1 +
 drivers/gpu/drm/i915/intel_pm.c |    8 +++++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58935a3..3b75052 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3446,6 +3446,7 @@
 
 #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
 #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
+#define  GEN7_WA_DOP_CLOCK_GATING_DISABLE			0x08000000
 
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f7344c9..6be5910 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3545,7 +3545,9 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_L3CNTLREG1,
 			GEN7_WA_FOR_GEN7_L3_CONTROL);
 	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
-			GEN7_WA_L3_CHICKEN_MODE);
+		   GEN7_WA_L3_CHICKEN_MODE);
+	I915_WRITE(GEN7_ROW_CHICKEN2,
+		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
 
 	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
 	 * gating disable must be set.  Failure to set it results in
@@ -3617,6 +3619,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
 	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
 
+	/* WaDisableDopClockGating */
+	I915_WRITE(GEN7_ROW_CHICKEN2,
+		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+
 	/* This is required by WaCatErrorRejectionIssue */
 	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
 		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
-- 
1.7.9.5

[PATCH 04/12] drm/i915: implement WaForceL3Serialization on VLV and IVB

[Jesse Barnes]

References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |    3 +++
 drivers/gpu/drm/i915/intel_pm.c |    8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b75052..c75539b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3448,6 +3448,9 @@
 #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
 #define  GEN7_WA_DOP_CLOCK_GATING_DISABLE			0x08000000
 
+#define GEN7_L3SQCREG4				0xb034
+#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
+
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6be5910..0659317 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3549,6 +3549,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_ROW_CHICKEN2,
 		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
 
+	/* WaForceL3Serialization */
+	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
+		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
+
 	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
 	 * gating disable must be set.  Failure to set it results in
 	 * flickering pixels due to Z write ordering failures after
@@ -3623,6 +3627,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_ROW_CHICKEN2,
 		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
 
+	/* WaForceL3Serialization */
+	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
+		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
+
 	/* This is required by WaCatErrorRejectionIssue */
 	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
 		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
-- 
1.7.9.5

[PATCH 05/12] drm/i915: implement WaGTEnableMiFlush on VLV

[Jesse Barnes]

We don't generally use MI_FLUSH these days, but this bit may affect
other flushing logic, so set it to be safe.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 984a0c5..1718c54 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -512,6 +512,9 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 			I915_WRITE(GFX_MODE_GEN7,
 				   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 				   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
+		if (IS_VALLEYVIEW(dev))
+			I915_WRITE(MI_MODE, I915_READ(MI_MODE) |
+				   _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE));
 	}
 
 	if (INTEL_INFO(dev)->gen >= 5) {
-- 
1.7.9.5

[PATCH 06/12] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV

[Jesse Barnes]

This allows us to get the right vblank interrupt frequency.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_pm.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0659317..828629b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3687,6 +3687,13 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
 		   SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
 		   PLANEA_FLIPDONE_INT_EN);
+
+	/*
+	 * WaDisableVLVClockGating_VBIIssue
+	 * Disable clock gating on th GCFG unit to prevent a delay
+	 * in the reporting of vblank events.
+	 */
+	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.7.9.5

[PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB

[Jesse Barnes]

Workaround for a culling optimization.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |    1 +
 drivers/gpu/drm/i915/intel_pm.c |    8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c75539b..3ceeb68 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -521,6 +521,7 @@
  */
 # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
 #define _3D_CHICKEN3	0x02090
+#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
 #define  _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
 
 #define MI_MODE		0x0209c
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 828629b..400dd05 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3533,6 +3533,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 
 	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
 
+	/* WaDisableEarlyCull */
+	I915_WRITE(_3D_CHICKEN3,
+		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
+
 	I915_WRITE(IVB_CHICKEN3,
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
 		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
@@ -3611,6 +3615,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 
 	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
 
+	/* WaDisableEarlyCull */
+	I915_WRITE(_3D_CHICKEN3,
+		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
+
 	I915_WRITE(IVB_CHICKEN3,
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
 		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
-- 
1.7.9.5

[PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB

[Jesse Barnes]

Workaround for dual port PS dispatch on GT1.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_pm.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 400dd05..ce8d7b2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3541,6 +3541,16 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
 		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
 
+	/* WaDisablePSDDualDispatchEnable */
+	if (IS_MOBILE(dev))
+		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
+			   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
+			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+	else
+		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB,
+			   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
+			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+
 	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
 	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
 		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
-- 
1.7.9.5

[PATCH 09/12] drm/i915: limit VLV IRQ enables to those we use

[Jesse Barnes]

To match IVB.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_irq.c |   18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d915126..096b387 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1957,6 +1957,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 	u32 enable_mask;
 	u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
 	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
+	u32 render_irqs;
 	u16 msid;
 
 	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
@@ -1996,21 +1997,12 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 	I915_WRITE(VLV_IIR, 0xffffffff);
 	I915_WRITE(VLV_IIR, 0xffffffff);
 
-	dev_priv->gt_irq_mask = ~0;
-
-	I915_WRITE(GTIIR, I915_READ(GTIIR));
 	I915_WRITE(GTIIR, I915_READ(GTIIR));
 	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
-	I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
-		   GT_GEN6_BLT_CS_ERROR_INTERRUPT |
-		   GT_GEN6_BLT_USER_INTERRUPT |
-		   GT_GEN6_BSD_USER_INTERRUPT |
-		   GT_GEN6_BSD_CS_ERROR_INTERRUPT |
-		   GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
-		   GT_PIPE_NOTIFY |
-		   GT_RENDER_CS_ERROR_INTERRUPT |
-		   GT_SYNC_STATUS |
-		   GT_USER_INTERRUPT);
+
+	render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
+		GEN6_BLITTER_USER_INTERRUPT;
+	I915_WRITE(GTIER, render_irqs);
 	POSTING_READ(GTIER);
 
 	/* ack & enable invalid PTE error interrupts */
-- 
1.7.9.5

[PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

[Jesse Barnes]

So store into the scratch space of the HWS to make sure the invalidate
occurs.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h         |    6 ++++--
 drivers/gpu/drm/i915/intel_ringbuffer.c |   22 ++++++++++++++++++----
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ceeb68..d98c989 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -241,8 +241,10 @@
  */
 #define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)
 #define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
-#define   MI_INVALIDATE_TLB	(1<<18)
-#define   MI_INVALIDATE_BSD	(1<<7)
+#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
+#define   MI_INVALIDATE_TLB		(1<<18)
+#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
+#define   MI_INVALIDATE_BSD		(1<<7)
 #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
 #define   MI_BATCH_NON_SECURE	(1)
 #define   MI_BATCH_NON_SECURE_I965 (1<<8)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1718c54..d3b7129 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1395,10 +1395,17 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
 		return ret;
 
 	cmd = MI_FLUSH_DW;
+	/*
+	 * Bspec vol 1c.5 - video engine command streamer:
+	 * "If ENABLED, all TLBs will be invalidated once the flush
+	 * operation is complete. This bit is only valid when the
+	 * Post-Sync Operation field is a value of 1h or 3h."
+	 */
 	if (invalidate & I915_GEM_GPU_DOMAINS)
-		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
+		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
+			MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
 	intel_ring_emit(ring, cmd);
-	intel_ring_emit(ring, 0);
+	intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << 3);
 	intel_ring_emit(ring, 0);
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
@@ -1436,10 +1443,17 @@ static int blt_ring_flush(struct intel_ring_buffer *ring,
 		return ret;
 
 	cmd = MI_FLUSH_DW;
+	/*
+	 * Bspec vol 1c.3 - blitter engine command streamer:
+	 * "If ENABLED, all TLBs will be invalidated once the flush
+	 * operation is complete. This bit is only valid when the
+	 * Post-Sync Operation field is a value of 1h or 3h."
+	 */
 	if (invalidate & I915_GEM_DOMAIN_RENDER)
-		cmd |= MI_INVALIDATE_TLB;
+		cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
+			MI_FLUSH_DW_OP_STOREDW;
 	intel_ring_emit(ring, cmd);
-	intel_ring_emit(ring, 0);
+	intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << 3);
 	intel_ring_emit(ring, 0);
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
-- 
1.7.9.5

[PATCH 11/12] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

[Jesse Barnes]

"If ENABLED, PIPE_CONTROL command will flush the in flight data  written
out by render engine to Global Observation point on flush done. Also
Requires stall bit ([20] of DW1) set."

So set the stall bit to ensure proper invalidation.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d3b7129..dac80df 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -246,7 +246,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
 		/*
 		 * TLB invalidate requires a post-sync write.
 		 */
-		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 	}
 
 	ret = intel_ring_begin(ring, 4);
-- 
1.7.9.5

[PATCH 12/12] drm/i915: set swizzling to none on VLV

[Jesse Barnes]

We don't have bit 6 swizzling on VLV, so this function is easy.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem_tiling.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 8093ecd..71084ed 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -92,7 +92,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
-	if (INTEL_INFO(dev)->gen >= 6) {
+	if (IS_VALLEYVIEW(dev)) {
+		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
+		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
+	} else if (INTEL_INFO(dev)->gen >= 6) {
 		uint32_t dimm_c0, dimm_c1;
 		dimm_c0 = I915_READ(MAD_DIMM_C0);
 		dimm_c1 = I915_READ(MAD_DIMM_C1);
-- 
1.7.9.5

Re: [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV

[Daniel Vetter]

On Tue, Oct 02, 2012 at 05:43:36PM -0500, Jesse Barnes wrote:
> Needs to be set on every context restore as well, so set it as part of
> the initial state so we can save/restore it.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    1 +
>  drivers/gpu/drm/i915/intel_pm.c |    2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7d133a1..58935a3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3442,6 +3442,7 @@
>  
>  #define GEN7_L3CNTLREG1				0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
> +#define  GEN7_L3AGDIS				(1<<19)
>  
>  #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
>  #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 82ca172..f7344c9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3614,7 +3614,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
>  
>  	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
> -	I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
> +	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);

tbh I don't like rmw magic register values, since that essentially means
that for suspend resume support we need either
- the bios restoring these magic values for us
- have a separate piece of save/restore code
- actually the read isn't required and there's nothing to restore in
  additions to the bits we're setting

All of which are a royal pain for long-term maintaince, especially since
our current suspend/resume code is already a fragile mess.

Can we do better and just write the right settings to this register
unconditionally?
-Daniel

>  	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
>  
>  	/* This is required by WaCatErrorRejectionIssue */
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV

[Ben Widawsky]

On Wed, 3 Oct 2012 01:01:07 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Tue, Oct 02, 2012 at 05:43:36PM -0500, Jesse Barnes wrote:
> > Needs to be set on every context restore as well, so set it as part
> > of the initial state so we can save/restore it.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |    1 +
> >  drivers/gpu/drm/i915/intel_pm.c |    2 +-
> >  2 files changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 7d133a1..58935a3 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3442,6 +3442,7 @@
> >  
> >  #define GEN7_L3CNTLREG1				0xB01C
> >  #define  GEN7_WA_FOR_GEN7_L3_CONTROL
> > 0x3C4FFF8C +#define  GEN7_L3AGDIS
> > (1<<19) 
> >  #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
> >  #define  GEN7_WA_L3_CHICKEN_MODE
> > 0x20000000 diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c index 82ca172..f7344c9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3614,7 +3614,7 @@ static void
> > valleyview_init_clock_gating(struct drm_device *dev)
> > GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 
> >  	/* WaApplyL3ControlAndL3ChickenMode requires those two on
> > Ivy Bridge */
> > -	I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
> > +	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) |
> > GEN7_L3AGDIS);
> 
> tbh I don't like rmw magic register values, since that essentially
> means that for suspend resume support we need either
> - the bios restoring these magic values for us
> - have a separate piece of save/restore code
> - actually the read isn't required and there's nothing to restore in
>   additions to the bits we're setting
> 
> All of which are a royal pain for long-term maintaince, especially
> since our current suspend/resume code is already a fragile mess.
> 
> Can we do better and just write the right settings to this register
> unconditionally?
> -Daniel

In theory that's true, but even the docs change occasionally on what
values we should set, so I don't think either is great. Also a comment
on one of the bits seem to suggest we should expect BIOS to be setting
this for us, however Jesse missed another workaround which I'll point
out to him now in person.

> 
> >  	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> > GEN7_WA_L3_CHICKEN_MODE); 
> >  	/* This is required by WaCatErrorRejectionIssue */
> > -- 
> > 1.7.9.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 



-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV

[Ben Widawsky]

On Tue, 2 Oct 2012 16:09:19 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On Wed, 3 Oct 2012 01:01:07 +0200
> Daniel Vetter <daniel@ffwll.ch> wrote:
> 
> > On Tue, Oct 02, 2012 at 05:43:36PM -0500, Jesse Barnes wrote:
> > > Needs to be set on every context restore as well, so set it as
> > > part of the initial state so we can save/restore it.
> > > 
> > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h |    1 +
> > >  drivers/gpu/drm/i915/intel_pm.c |    2 +-
> > >  2 files changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h index 7d133a1..58935a3 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3442,6 +3442,7 @@
> > >  
> > >  #define GEN7_L3CNTLREG1				0xB01C
> > >  #define  GEN7_WA_FOR_GEN7_L3_CONTROL
> > > 0x3C4FFF8C +#define  GEN7_L3AGDIS
> > > (1<<19) 
> > >  #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
> > >  #define  GEN7_WA_L3_CHICKEN_MODE
> > > 0x20000000 diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c index 82ca172..f7344c9 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3614,7 +3614,7 @@ static void
> > > valleyview_init_clock_gating(struct drm_device *dev)
> > > GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 
> > >  	/* WaApplyL3ControlAndL3ChickenMode requires those two on
> > > Ivy Bridge */
> > > -	I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
> > > +	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) |
> > > GEN7_L3AGDIS);
> > 
> > tbh I don't like rmw magic register values, since that essentially
> > means that for suspend resume support we need either
> > - the bios restoring these magic values for us
> > - have a separate piece of save/restore code
> > - actually the read isn't required and there's nothing to restore in
> >   additions to the bits we're setting
> > 
> > All of which are a royal pain for long-term maintaince, especially
> > since our current suspend/resume code is already a fragile mess.
> > 
> > Can we do better and just write the right settings to this register
> > unconditionally?
> > -Daniel
> 
> In theory that's true, but even the docs change occasionally on what
> values we should set, so I don't think either is great. Also a comment
> on one of the bits seem to suggest we should expect BIOS to be setting
> this for us, however Jesse missed another workaround which I'll point
> out to him now in person.
> 

On looking further it seems the magic bit Jesse is trying to set is
already set, but the original magic number came from Eugeni, and it
strays from the register default quite a bit.

> > 
> > >  	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> > > GEN7_WA_L3_CHICKEN_MODE); 
> > >  	/* This is required by WaCatErrorRejectionIssue */
> > > -- 
> > > 1.7.9.5
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> 
> 
> 



-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen

[Ben Widawsky]

On Tue,  2 Oct 2012 17:43:35 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> Add a few regs needed for various clock gating init purposes and make
> sure they don't fall into the display offset range on VLV.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |   17 +++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h |   11 +++++++++++
>  2 files changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c index a7837e5..205f61c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1128,6 +1128,23 @@ static bool IS_DISPLAYREG(u32 reg)
>  	if (reg == GEN6_GDRST)
>  		return false;
>  
> +	switch (reg) {
> +	case _3D_CHICKEN3:
> +	case IVB_CHICKEN3:
> +	case GEN7_HALF_SLICE_CHICKEN1:
> +	case GEN7_COMMON_SLICE_CHICKEN1:
> +	case GEN7_L3CNTLREG1:
> +	case GEN7_L3_CHICKEN_MODE_REGISTER:
> +	case GEN7_ROW_CHICKEN2:
> +	case GEN7_L3SQCREG4:
> +	case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
> +	case GEN6_MBCTL:
> +	case GEN6_UCGCTL2:
> +	case GEN7_UCGCTL4:
> +		return false;
> +	default:
> +		break;
> +	}
>  	return true;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index a828e90..7d133a1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -544,6 +544,8 @@
>  #define IIR		0x020a4
>  #define IMR		0x020a8
>  #define ISR		0x020ac
> +#define VLV_GUNIT_CLOCK_GATE	0x182060
> +#define   GCFG_DIS		(1<<8)
>  #define VLV_IIR_RW	0x182084
>  #define VLV_IER		0x1820a0
>  #define VLV_IIR		0x1820a4

This hunk doesn't really belong here, but not a big deal for me.

> @@ -4244,6 +4246,15 @@
>  #define GEN7_L3LOG_BASE			0xB070
>  #define GEN7_L3LOG_SIZE			0x80
>  
> +#define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
> +#define GEN7_HALF_SLICE_CHICKEN1_IVB	0xf100
> +#define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
> +#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
> +
> +#define GEN7_ROW_CHICKEN2		0xe4f4
> +#define GEN7_ROW_CHICKEN2_GT2		0xf4f4
> +#define   DOP_CLOCK_GATING_DISABLE	(1<<0)
> +
>  #define G4X_AUD_VID_DID			0x62020
>  #define INTEL_AUDIO_DEVCL		0x808629FB
>  #define INTEL_AUDIO_DEVBLC		0x80862801



-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 03/12] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB

[Ben Widawsky]

On Tue,  2 Oct 2012 17:43:37 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> v2: use correct register
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=50233
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    1 +
>  drivers/gpu/drm/i915/intel_pm.c |    8 +++++++-
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 58935a3..3b75052 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3446,6 +3446,7 @@
>  
>  #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
>  #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
> +#define  GEN7_WA_DOP_CLOCK_GATING_DISABLE			0x08000000


Looks like this doesn't belong in this patch.
>  
>  /* WaCatErrorRejectionIssue */
>  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f7344c9..6be5910 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3545,7 +3545,9 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_L3CNTLREG1,
>  			GEN7_WA_FOR_GEN7_L3_CONTROL);
>  	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> -			GEN7_WA_L3_CHICKEN_MODE);
> +		   GEN7_WA_L3_CHICKEN_MODE);
> +	I915_WRITE(GEN7_ROW_CHICKEN2,
> +		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>  
>  	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
>  	 * gating disable must be set.  Failure to set it results in
> @@ -3617,6 +3619,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
>  	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
>  
> +	/* WaDisableDopClockGating */
> +	I915_WRITE(GEN7_ROW_CHICKEN2,
> +		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> +
>  	/* This is required by WaCatErrorRejectionIssue */
>  	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>  		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |


I think you're missing the GT2 disable.

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 04/12] drm/i915: implement WaForceL3Serialization on VLV and IVB

[Ben Widawsky]

On Tue,  2 Oct 2012 17:43:38 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>


> ---
>  drivers/gpu/drm/i915/i915_reg.h |    3 +++
>  drivers/gpu/drm/i915/intel_pm.c |    8 ++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b75052..c75539b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3448,6 +3448,9 @@
>  #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
>  #define  GEN7_WA_DOP_CLOCK_GATING_DISABLE			0x08000000
>  
> +#define GEN7_L3SQCREG4				0xb034
> +#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> +
>  /* WaCatErrorRejectionIssue */
>  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
>  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6be5910..0659317 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3549,6 +3549,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_ROW_CHICKEN2,
>  		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>  
> +	/* WaForceL3Serialization */
> +	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> +		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> +
>  	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
>  	 * gating disable must be set.  Failure to set it results in
>  	 * flickering pixels due to Z write ordering failures after
> @@ -3623,6 +3627,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_ROW_CHICKEN2,
>  		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>  
> +	/* WaForceL3Serialization */
> +	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> +		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> +
>  	/* This is required by WaCatErrorRejectionIssue */
>  	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>  		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |



-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 05/12] drm/i915: implement WaGTEnableMiFlush on VLV

[Ben Widawsky]

On Tue,  2 Oct 2012 17:43:39 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> We don't generally use MI_FLUSH these days, but this bit may affect
> other flushing logic, so set it to be safe.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c |    3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 984a0c5..1718c54 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -512,6 +512,9 @@ static int init_render_ring(struct intel_ring_buffer *ring)
>  			I915_WRITE(GFX_MODE_GEN7,
>  				   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
>  				   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> +		if (IS_VALLEYVIEW(dev))
> +			I915_WRITE(MI_MODE, I915_READ(MI_MODE) |
> +				   _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE));
>  	}
>  
>  	if (INTEL_INFO(dev)->gen >= 5) {


The workaround itself calls for this to be set for snb->hsw. Why not do
them all?

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 06/12] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV

[Ben Widawsky]

On Tue,  2 Oct 2012 17:43:40 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> This allows us to get the right vblank interrupt frequency.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_pm.c |    7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0659317..828629b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3687,6 +3687,13 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  		   PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
>  		   SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
>  		   PLANEA_FLIPDONE_INT_EN);
> +
> +	/*
> +	 * WaDisableVLVClockGating_VBIIssue
> +	 * Disable clock gating on th GCFG unit to prevent a delay
> +	 * in the reporting of vblank events.
> +	 */
> +	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
>  }
>  
>  static void g4x_init_clock_gating(struct drm_device *dev)


This seems like only X0.


-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB

[Ben Widawsky]

On Tue,  2 Oct 2012 17:43:41 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> Workaround for a culling optimization.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    1 +
>  drivers/gpu/drm/i915/intel_pm.c |    8 ++++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c75539b..3ceeb68 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -521,6 +521,7 @@
>   */
>  # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
>  #define _3D_CHICKEN3	0x02090
> +#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
>  #define  _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
>  
>  #define MI_MODE		0x0209c
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 828629b..400dd05 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3533,6 +3533,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  
>  	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
>  
> +	/* WaDisableEarlyCull */
> +	I915_WRITE(_3D_CHICKEN3,
> +		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
> +
>  	I915_WRITE(IVB_CHICKEN3,
>  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
> @@ -3611,6 +3615,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  
>  	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
>  
> +	/* WaDisableEarlyCull */
> +	I915_WRITE(_3D_CHICKEN3,
> +		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
> +
>  	I915_WRITE(IVB_CHICKEN3,
>  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);

FYI: We need this for pre-production HSW also (while we have to use
those platforms).

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB

[Ben Widawsky]

On Tue,  2 Oct 2012 17:43:42 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> Workaround for dual port PS dispatch on GT1.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_pm.c |   10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 400dd05..ce8d7b2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3541,6 +3541,16 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
>  
> +	/* WaDisablePSDDualDispatchEnable */
> +	if (IS_MOBILE(dev))
> +		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> +			   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> +			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> +	else
> +		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB,
> +			   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> +			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> +
>  	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
>  	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
>  		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);

Seems like we need this on VLV too. Also, I can't find this register in
the bspec, which is annoying - but I see the w/a.

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 09/12] drm/i915: limit VLV IRQ enables to those we use

[Ben Widawsky]

On Tue,  2 Oct 2012 17:43:43 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> To match IVB.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_irq.c |   18 +++++-------------
>  1 file changed, 5 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d915126..096b387 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1957,6 +1957,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  	u32 enable_mask;
>  	u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
>  	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
> +	u32 render_irqs;
>  	u16 msid;
>  
>  	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
> @@ -1996,21 +1997,12 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  	I915_WRITE(VLV_IIR, 0xffffffff);
>  	I915_WRITE(VLV_IIR, 0xffffffff);
>  
> -	dev_priv->gt_irq_mask = ~0;
> -
> -	I915_WRITE(GTIIR, I915_READ(GTIIR));
>  	I915_WRITE(GTIIR, I915_READ(GTIIR));
>  	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
> -	I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
> -		   GT_GEN6_BLT_CS_ERROR_INTERRUPT |
> -		   GT_GEN6_BLT_USER_INTERRUPT |
> -		   GT_GEN6_BSD_USER_INTERRUPT |
> -		   GT_GEN6_BSD_CS_ERROR_INTERRUPT |
> -		   GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
> -		   GT_PIPE_NOTIFY |
> -		   GT_RENDER_CS_ERROR_INTERRUPT |
> -		   GT_SYNC_STATUS |
> -		   GT_USER_INTERRUPT);
> +
> +	render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
> +		GEN6_BLITTER_USER_INTERRUPT;
> +	I915_WRITE(GTIER, render_irqs);
>  	POSTING_READ(GTIER);
>  
>  	/* ack & enable invalid PTE error interrupts */

Were parity errors intentionally dropped? I think it's fine to drop it,
but maybe add it to the commit message.

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB

[Ben Widawsky]

On Tue, 2 Oct 2012 16:51:39 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On Tue,  2 Oct 2012 17:43:42 -0500
> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> 
> > Workaround for dual port PS dispatch on GT1.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c |   10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 400dd05..ce8d7b2 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3541,6 +3541,16 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> >  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
> >  
> > +	/* WaDisablePSDDualDispatchEnable */
> > +	if (IS_MOBILE(dev))
> > +		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> > +			   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> > +			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> > +	else
> > +		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB,
> > +			   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> > +			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> > +
> >  	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
> >  	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> >  		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> 
> Seems like we need this on VLV too. Also, I can't find this register in
> the bspec, which is annoying - but I see the w/a.
> 

Also IS_MOBILE should be IS_GT1


-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

[Ben Widawsky]

s/MI_FLUSH_SW/MI_FLUSH_DW/

On Tue,  2 Oct 2012 17:43:44 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> So store into the scratch space of the HWS to make sure the invalidate
> occurs.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         |    6 ++++--
>  drivers/gpu/drm/i915/intel_ringbuffer.c |   22 ++++++++++++++++++----
>  2 files changed, 22 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3ceeb68..d98c989 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -241,8 +241,10 @@
>   */
>  #define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)
>  #define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
> -#define   MI_INVALIDATE_TLB	(1<<18)
> -#define   MI_INVALIDATE_BSD	(1<<7)
> +#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
> +#define   MI_INVALIDATE_TLB		(1<<18)
> +#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
> +#define   MI_INVALIDATE_BSD		(1<<7)
>  #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
>  #define   MI_BATCH_NON_SECURE	(1)
>  #define   MI_BATCH_NON_SECURE_I965 (1<<8)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1718c54..d3b7129 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1395,10 +1395,17 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
>  		return ret;
>  
>  	cmd = MI_FLUSH_DW;
> +	/*
> +	 * Bspec vol 1c.5 - video engine command streamer:
> +	 * "If ENABLED, all TLBs will be invalidated once the flush
> +	 * operation is complete. This bit is only valid when the
> +	 * Post-Sync Operation field is a value of 1h or 3h."
> +	 */
>  	if (invalidate & I915_GEM_GPU_DOMAINS)
> -		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
> +		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
> +			MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
>  	intel_ring_emit(ring, cmd);
> -	intel_ring_emit(ring, 0);
> +	intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << 3);
>  	intel_ring_emit(ring, 0);
>  	intel_ring_emit(ring, MI_NOOP);
>  	intel_ring_advance(ring);
> @@ -1436,10 +1443,17 @@ static int blt_ring_flush(struct intel_ring_buffer *ring,
>  		return ret;
>  
>  	cmd = MI_FLUSH_DW;
> +	/*
> +	 * Bspec vol 1c.3 - blitter engine command streamer:
> +	 * "If ENABLED, all TLBs will be invalidated once the flush
> +	 * operation is complete. This bit is only valid when the
> +	 * Post-Sync Operation field is a value of 1h or 3h."
> +	 */
>  	if (invalidate & I915_GEM_DOMAIN_RENDER)
> -		cmd |= MI_INVALIDATE_TLB;
> +		cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
> +			MI_FLUSH_DW_OP_STOREDW;
>  	intel_ring_emit(ring, cmd);
> -	intel_ring_emit(ring, 0);
> +	intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << 3);
>  	intel_ring_emit(ring, 0);
>  	intel_ring_emit(ring, MI_NOOP);
>  	intel_ring_advance(ring);


Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 12/12] drm/i915: set swizzling to none on VLV

[Daniel Vetter]

On Tue, Oct 02, 2012 at 05:43:46PM -0500, Jesse Barnes wrote:
> We don't have bit 6 swizzling on VLV, so this function is easy.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Applied to -fixes, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

[Daniel Vetter]

On Tue, Oct 02, 2012 at 05:14:53PM -0700, Ben Widawsky wrote:
> s/MI_FLUSH_SW/MI_FLUSH_DW/

Applied, with spelling fixed. Thanks for patch&review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB

[Daniel Vetter]

On Tue, Oct 02, 2012 at 04:44:32PM -0700, Ben Widawsky wrote:
> On Tue,  2 Oct 2012 17:43:41 -0500
> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> 
> > Workaround for a culling optimization.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |    1 +
> >  drivers/gpu/drm/i915/intel_pm.c |    8 ++++++++
> >  2 files changed, 9 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c75539b..3ceeb68 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -521,6 +521,7 @@
> >   */
> >  # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
> >  #define _3D_CHICKEN3	0x02090
> > +#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
> >  #define  _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
> >  
> >  #define MI_MODE		0x0209c
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 828629b..400dd05 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3533,6 +3533,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >  
> >  	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
> >  
> > +	/* WaDisableEarlyCull */
> > +	I915_WRITE(_3D_CHICKEN3,
> > +		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
> > +
> >  	I915_WRITE(IVB_CHICKEN3,
> >  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> >  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
> > @@ -3611,6 +3615,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> >  
> >  	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
> >  
> > +	/* WaDisableEarlyCull */
> > +	I915_WRITE(_3D_CHICKEN3,
> > +		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
> > +
> >  	I915_WRITE(IVB_CHICKEN3,
> >  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> >  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
> 
> FYI: We need this for pre-production HSW also (while we have to use
> those platforms).
> 
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Picked up for -fixes, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 04/12] drm/i915: implement WaForceL3Serialization on VLV and IVB

[Daniel Vetter]

On Tue, Oct 02, 2012 at 04:32:44PM -0700, Ben Widawsky wrote:
> On Tue,  2 Oct 2012 17:43:38 -0500
> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> 
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

Picked up for -fixes, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

[Daniel Vetter]

On Wed, Oct 03, 2012 at 09:20:20AM +0200, Daniel Vetter wrote:
> On Tue, Oct 02, 2012 at 05:14:53PM -0700, Ben Widawsky wrote:
> > s/MI_FLUSH_SW/MI_FLUSH_DW/
> 
> Applied, with spelling fixed. Thanks for patch&review.

This hard-hangs my snb here when X starts (so probably on the very first
batch). Impressive!

I've dropped this one from -fixes. And since no one piped up that the
other w/a patches fix anything, I've moved those two I've merged already
to dinq.

Totally unrelated, I think I'll instate harsher rules for w/a patches:
1. w/a patches only go in through -fixes if they indeed fix an issue we
(or a bug reporter) can reproduce.
2. w/a patches need testcases, too. Either a register check added to i-g-t
or if it's a runtime thing, a runtime assert at a nice place (where
feasible, ofc).
3. I'll randomly stall patches to bring 2. up to par for existing
workarounds.

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

[Jesse Barnes]

On Thu, 4 Oct 2012 10:32:13 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Oct 03, 2012 at 09:20:20AM +0200, Daniel Vetter wrote:
> > On Tue, Oct 02, 2012 at 05:14:53PM -0700, Ben Widawsky wrote:
> > > s/MI_FLUSH_SW/MI_FLUSH_DW/
> > 
> > Applied, with spelling fixed. Thanks for patch&review.
> 
> This hard-hangs my snb here when X starts (so probably on the very first
> batch). Impressive!
> 
> I've dropped this one from -fixes. And since no one piped up that the
> other w/a patches fix anything, I've moved those two I've merged already
> to dinq.

Yeah not -fixes material.  But it fixes i-g-t on VLV and *should* fix
issues we may not have seen yet on IVB, so we need to figure this one
out.

> Totally unrelated, I think I'll instate harsher rules for w/a patches:
> 1. w/a patches only go in through -fixes if they indeed fix an issue we
> (or a bug reporter) can reproduce.

Yeah, that's fine.

> 2. w/a patches need testcases, too. Either a register check added to i-g-t
> or if it's a runtime thing, a runtime assert at a nice place (where
> feasible, ofc).

A register check isn't that useful imo.  A real test case would be
ideal, but given how hard some of these issues are to hit, it's
unrealistic to spend weeks writing a test case for a workaround that's
already been documented to fix a specific issue.

> 3. I'll randomly stall patches to bring 2. up to par for existing
> workarounds.

Btw if you want to take this to its logical conclusion, we also
shouldn't be "fixing" issues that are obvious from code review but
people haven't hit in practice (this goes for a good chunk of the code
churn in our driver involving cleanups and fixes for potential
non-issues).  And that's not even including test case development for
any patch claiming it fixes anything.

That said, I definitely agree we want to add more test cases.  Just
don't block applying known workaround fixes or other stuff on those
test cases.

Jesse

Re: [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

[Daniel Vetter]

On Thu, Oct 4, 2012 at 4:39 PM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>
>> 2. w/a patches need testcases, too. Either a register check added to i-g-t
>> or if it's a runtime thing, a runtime assert at a nice place (where
>> feasible, ofc).
>
> A register check isn't that useful imo.  A real test case would be
> ideal, but given how hard some of these issues are to hit, it's
> unrealistic to spend weeks writing a test case for a workaround that's
> already been documented to fix a specific issue.

That's pretty because of Ben's w/a patch to remove the w/a from the
part of the init sequence where the write sticks, and keep it at the
place where the write doesn't stick. Similarly, we've sometimes
managed to apply w/a not correctly after gpu reset or resume.

Exactly since for many of these we won't ever have a good test-case,
we should at least make sure that we actually succeed in setting the
right values everywhere. Shockingly, we've failed even at that :(

>> 3. I'll randomly stall patches to bring 2. up to par for existing
>> workarounds.
>
> Btw if you want to take this to its logical conclusion, we also
> shouldn't be "fixing" issues that are obvious from code review but
> people haven't hit in practice (this goes for a good chunk of the code
> churn in our driver involving cleanups and fixes for potential
> non-issues).  And that's not even including test case development for
> any patch claiming it fixes anything.

And most of those actually go through dinq, at least if the exact
impact is unclear and there's no testcase or bug to demonstrate the
issue. My gripes here are purely for pushing too much w/a patches to
-fixes, since both your patches and Ben's had regressions that hang
machines. Hence my grumpiness.

> That said, I definitely agree we want to add more test cases.  Just
> don't block applying known workaround fixes or other stuff on those
> test cases.

Sure, I'll usually try to come up with a random distribution not
biased against stuff that fixes real bugs ;-) But even for bugfixes I
want testcases first (as always, if feasible ofc), since ppl are so
easily distracted (and writing testcase is a royal pain).

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

[Jesse Barnes]

On Thu, 4 Oct 2012 16:49:42 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:
> > Btw if you want to take this to its logical conclusion, we also
> > shouldn't be "fixing" issues that are obvious from code review but
> > people haven't hit in practice (this goes for a good chunk of the code
> > churn in our driver involving cleanups and fixes for potential
> > non-issues).  And that's not even including test case development for
> > any patch claiming it fixes anything.
> 
> And most of those actually go through dinq, at least if the exact
> impact is unclear and there's no testcase or bug to demonstrate the
> issue. My gripes here are purely for pushing too much w/a patches to
> -fixes, since both your patches and Ben's had regressions that hang
> machines. Hence my grumpiness.

Yeah, not sure why you were pushing them straight to -fixes in the
first place. :)  -fixes is just for known bug fixes that people are
hitting, not speculative ones, especially workarounds we know work in
theory but haven't applied to a specific bug.  So we agree there.  I'm
hoping at least some of the known w/a's will be found to fix a known
bug report, then we can push to -fixes and/or stable as appropriate.

Jesse

Re: [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB

[Paulo Zanoni]

Hi

2012/10/2 Ben Widawsky <ben@bwidawsk.net>:
> On Tue,  2 Oct 2012 17:43:41 -0500
> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>
>> Workaround for a culling optimization.
>>
>> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h |    1 +
>>  drivers/gpu/drm/i915/intel_pm.c |    8 ++++++++
>>  2 files changed, 9 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c75539b..3ceeb68 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -521,6 +521,7 @@
>>   */
>>  # define _3D_CHICKEN2_WM_READ_PIPELINED                      (1 << 14)
>>  #define _3D_CHICKEN3 0x02090
>> +#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL          (1 << 10)
>>  #define  _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL                (1 << 5)
>>
>>  #define MI_MODE              0x0209c
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 828629b..400dd05 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -3533,6 +3533,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>>
>>       I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
>>
>> +     /* WaDisableEarlyCull */
>> +     I915_WRITE(_3D_CHICKEN3,
>> +                _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
>> +
>>       I915_WRITE(IVB_CHICKEN3,
>>                  CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>>                  CHICKEN3_DGMG_DONE_FIX_DISABLE);
>> @@ -3611,6 +3615,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>>
>>       I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
>>
>> +     /* WaDisableEarlyCull */
>> +     I915_WRITE(_3D_CHICKEN3,
>> +                _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
>> +
>>       I915_WRITE(IVB_CHICKEN3,
>>                  CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>>                  CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> FYI: We need this for pre-production HSW also (while we have to use
> those platforms).

At least on my docs this bit is listed for SNB and IVB only. After
this patch I get a GPU hang every time I boot the HSW machine. Maybe
we need this only for some specific pre-production machines, but not
all? (in this case, our docs need to be fixed)

>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
>
> --
> Ben Widawsky, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB

[Lespiau, Damien]

> At least on my docs this bit is listed for SNB and IVB only. After
> this patch I get a GPU hang every time I boot the HSW machine. Maybe
> we need this only for some specific pre-production machines, but not
> all? (in this case, our docs need to be fixed)

Ooops, config db for the details on pre-production HSW that need the
wa. Wasn't quite thinking it could hang the newer ones though.

-- 
Damien