* [PATCH 01/16] drm/i915: extract display_pipe_crc_update
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 02/16] drm/i915: add CRC #defines for ilk/snb Daniel Vetter
` (15 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
The ringbuffer update logic should always be the same, but different
platforms have different amounts of CRC registers. Hence extract it.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_irq.c | 30 +++++++++++++++++++++++-------
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8c9148c..df031bb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1190,7 +1190,10 @@ static void dp_aux_irq_handler(struct drm_device *dev)
}
#if defined(CONFIG_DEBUG_FS)
-static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
+static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe,
+ uint32_t crc0, uint32_t crc1,
+ uint32_t crc2, uint32_t crc3,
+ uint32_t crc4, uint32_t frame)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
@@ -1212,18 +1215,31 @@ static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
entry = &pipe_crc->entries[head];
- entry->frame = I915_READ(PIPEFRAME(pipe));
- entry->crc[0] = I915_READ(PIPE_CRC_RES_1_IVB(pipe));
- entry->crc[1] = I915_READ(PIPE_CRC_RES_2_IVB(pipe));
- entry->crc[2] = I915_READ(PIPE_CRC_RES_3_IVB(pipe));
- entry->crc[3] = I915_READ(PIPE_CRC_RES_4_IVB(pipe));
- entry->crc[4] = I915_READ(PIPE_CRC_RES_5_IVB(pipe));
+ entry->frame = frame;
+ entry->crc[0] = crc0;
+ entry->crc[1] = crc1;
+ entry->crc[2] = crc2;
+ entry->crc[3] = crc3;
+ entry->crc[4] = crc4;
head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
atomic_set(&pipe_crc->head, head);
wake_up_interruptible(&pipe_crc->wq);
}
+
+static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ display_pipe_crc_update(dev, pipe,
+ I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
+ I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
+ I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
+ I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
+ I915_READ(PIPE_CRC_RES_5_IVB(pipe)),
+ I915_READ(PIPEFRAME(pipe)));
+}
#else
static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
#endif
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 02/16] drm/i915: add CRC #defines for ilk/snb
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
2013-10-16 20:55 ` [PATCH 01/16] drm/i915: extract display_pipe_crc_update Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 03/16] drm/i915: wire up CRC interrupt " Daniel Vetter
` (14 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Also add a new _PIPE_INC macro which takes an base plus increment.
Much less likely to botch the job by missing an s/A/B/ somewhere.
v2: They've moved the bitfield. Argh!
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 46 +++++++++++++++++++++++++++++++----------
1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d01eaf..984bf9e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
#define _I915_REG_H_
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define _PIPE_INC(pipe, base, inc) ((base) + (pipe)*(inc))
#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
@@ -1844,19 +1845,31 @@
#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
-#define _PIPE_CRC_RES_1_A_IVB (dev_priv->info->display_mmio_offset + 0x60064)
-#define _PIPE_CRC_RES_2_A_IVB (dev_priv->info->display_mmio_offset + 0x60068)
-#define _PIPE_CRC_RES_3_A_IVB (dev_priv->info->display_mmio_offset + 0x6006c)
-#define _PIPE_CRC_RES_4_A_IVB (dev_priv->info->display_mmio_offset + 0x60070)
-#define _PIPE_CRC_RES_5_A_IVB (dev_priv->info->display_mmio_offset + 0x60074)
+#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
+#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
+#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
+/* embedded DP port on the north display block, reserved on ivb */
+#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
+#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
+#define _PIPE_CRC_RES_1_A_IVB 0x60064
+#define _PIPE_CRC_RES_2_A_IVB 0x60068
+#define _PIPE_CRC_RES_3_A_IVB 0x6006c
+#define _PIPE_CRC_RES_4_A_IVB 0x60070
+#define _PIPE_CRC_RES_5_A_IVB 0x60074
+
+#define _PIPE_CRC_RES_RED_A_ILK 0x60060
+#define _PIPE_CRC_RES_GREEN_A_ILK 0x60064
+#define _PIPE_CRC_RES_BLUE_A_ILK 0x60068
+#define _PIPE_CRC_RES_RES1_A_ILK 0x6006c
+#define _PIPE_CRC_RES_RES2_A_ILK 0x60080
/* Pipe B CRC regs */
-#define _PIPE_CRC_CTL_B (dev_priv->info->display_mmio_offset + 0x61050)
-#define _PIPE_CRC_RES_1_B_IVB (dev_priv->info->display_mmio_offset + 0x61064)
-#define _PIPE_CRC_RES_2_B_IVB (dev_priv->info->display_mmio_offset + 0x61068)
-#define _PIPE_CRC_RES_3_B_IVB (dev_priv->info->display_mmio_offset + 0x6106c)
-#define _PIPE_CRC_RES_4_B_IVB (dev_priv->info->display_mmio_offset + 0x61070)
-#define _PIPE_CRC_RES_5_B_IVB (dev_priv->info->display_mmio_offset + 0x61074)
+#define _PIPE_CRC_CTL_B 0x61050
+#define _PIPE_CRC_RES_1_B_IVB 0x61064
+#define _PIPE_CRC_RES_2_B_IVB 0x61068
+#define _PIPE_CRC_RES_3_B_IVB 0x6106c
+#define _PIPE_CRC_RES_4_B_IVB 0x61070
+#define _PIPE_CRC_RES_5_B_IVB 0x61074
#define PIPE_CRC_CTL(pipe) _PIPE(pipe, _PIPE_CRC_CTL_A, _PIPE_CRC_CTL_B)
#define PIPE_CRC_RES_1_IVB(pipe) \
@@ -1870,6 +1883,17 @@
#define PIPE_CRC_RES_5_IVB(pipe) \
_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
+#define PIPE_CRC_RES_RED_ILK(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_RED_A_ILK, 0x01000)
+#define PIPE_CRC_RES_GREEN_ILK(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A_ILK, 0x01000)
+#define PIPE_CRC_RES_BLUE_ILK(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A_ILK, 0x01000)
+#define PIPE_CRC_RES_RES1_ILK(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_ILK, 0x01000)
+#define PIPE_CRC_RES_RES2_ILK(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_ILK, 0x01000)
+
/* Pipe A timing regs */
#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000)
#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004)
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 03/16] drm/i915: wire up CRC interrupt for ilk/snb
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
2013-10-16 20:55 ` [PATCH 01/16] drm/i915: extract display_pipe_crc_update Daniel Vetter
2013-10-16 20:55 ` [PATCH 02/16] drm/i915: add CRC #defines for ilk/snb Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 04/16] drm/i915: use ->get_vblank_counter for the crc frame counter Daniel Vetter
` (13 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
We enable the interrupt unconditionally and only control it
through the enable bit in the CRC control register.
v2: Extract per-platform helpers to compute the register values.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 74 ++++++++++++++++++++++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 26 ++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 2 +
4 files changed, 84 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5fce5d8..323f58e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1914,6 +1914,7 @@ static const char * const pipe_crc_sources[] = {
"plane1",
"plane2",
"pf",
+ "pipe",
};
static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
@@ -1942,14 +1943,61 @@ static int display_crc_ctl_open(struct inode *inode, struct file *file)
return single_open(file, display_crc_ctl_show, dev);
}
+static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
+ uint32_t *val)
+{
+ switch (source) {
+ case INTEL_PIPE_CRC_SOURCE_PLANE1:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PLANE2:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PF:
+ return -EINVAL;
+ case INTEL_PIPE_CRC_SOURCE_PIPE:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
+ break;
+ default:
+ *val = 0;
+ break;
+ }
+
+ return 0;
+}
+
+static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
+ uint32_t *val)
+{
+ switch (source) {
+ case INTEL_PIPE_CRC_SOURCE_PLANE1:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PLANE2:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PF:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PIPE:
+ return -EINVAL;
+ default:
+ *val = 0;
+ break;
+ }
+
+ return 0;
+}
+
static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
enum intel_pipe_crc_source source)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
u32 val;
+ int ret;
- if (!IS_IVYBRIDGE(dev))
+ if (!(IS_IVYBRIDGE(dev) || IS_GEN5(dev) || IS_GEN6(dev)))
return -ENODEV;
if (pipe_crc->source == source)
@@ -1959,6 +2007,14 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
if (pipe_crc->source && source)
return -EINVAL;
+ if (IS_GEN5(dev) || IS_GEN6(dev))
+ ret = ilk_pipe_crc_ctl_reg(source, &val);
+ else
+ ret = ivb_pipe_crc_ctl_reg(source, &val);
+
+ if (ret != 0)
+ return ret;
+
/* none -> real source transition */
if (source) {
DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
@@ -1976,22 +2032,6 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
pipe_crc->source = source;
- switch (source) {
- case INTEL_PIPE_CRC_SOURCE_PLANE1:
- val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
- break;
- case INTEL_PIPE_CRC_SOURCE_PLANE2:
- val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
- break;
- case INTEL_PIPE_CRC_SOURCE_PF:
- val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
- break;
- case INTEL_PIPE_CRC_SOURCE_NONE:
- default:
- val = 0;
- break;
- }
-
I915_WRITE(PIPE_CRC_CTL(pipe), val);
POSTING_READ(PIPE_CRC_CTL(pipe));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e2bf930..09857f8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1222,6 +1222,7 @@ enum intel_pipe_crc_source {
INTEL_PIPE_CRC_SOURCE_PLANE1,
INTEL_PIPE_CRC_SOURCE_PLANE2,
INTEL_PIPE_CRC_SOURCE_PF,
+ INTEL_PIPE_CRC_SOURCE_PIPE,
INTEL_PIPE_CRC_SOURCE_MAX,
};
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index df031bb..36465ef 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1240,8 +1240,22 @@ static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
I915_READ(PIPE_CRC_RES_5_IVB(pipe)),
I915_READ(PIPEFRAME(pipe)));
}
+
+static void ilk_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ display_pipe_crc_update(dev, pipe,
+ I915_READ(PIPE_CRC_RES_RED_ILK(pipe)),
+ I915_READ(PIPE_CRC_RES_GREEN_ILK(pipe)),
+ I915_READ(PIPE_CRC_RES_BLUE_ILK(pipe)),
+ I915_READ(PIPE_CRC_RES_RES1_ILK(pipe)),
+ I915_READ(PIPE_CRC_RES_RES2_ILK(pipe)),
+ I915_READ(PIPEFRAME(pipe)));
+}
#else
static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
+static inline void ilk_pipe_crc_update(struct drm_device *dev, int pipe) {}
#endif
/* The RPS events need forcewake, so we add them to a work queue and mask their
@@ -1524,6 +1538,12 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
+ if (de_iir & DE_PIPEA_CRC_DONE)
+ ilk_pipe_crc_update(dev, PIPE_A);
+
+ if (de_iir & DE_PIPEB_CRC_DONE)
+ ilk_pipe_crc_update(dev, PIPE_B);
+
if (de_iir & DE_PLANEA_FLIP_DONE) {
intel_prepare_page_flip(dev, 0);
intel_finish_page_flip_plane(dev, 0);
@@ -2500,8 +2520,10 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
} else {
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
- DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
- DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
+ DE_AUX_CHANNEL_A |
+ DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
+ DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
+ DE_POISON);
extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 984bf9e1..8a62720 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3918,12 +3918,14 @@
#define DE_PIPEB_ODD_FIELD (1 << 13)
#define DE_PIPEB_LINE_COMPARE (1 << 12)
#define DE_PIPEB_VSYNC (1 << 11)
+#define DE_PIPEB_CRC_DONE (1 << 10)
#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
#define DE_PIPEA_VBLANK (1 << 7)
#define DE_PIPEA_EVEN_FIELD (1 << 6)
#define DE_PIPEA_ODD_FIELD (1 << 5)
#define DE_PIPEA_LINE_COMPARE (1 << 4)
#define DE_PIPEA_VSYNC (1 << 3)
+#define DE_PIPEA_CRC_DONE (1 << 2)
#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
/* More Ivybridge lolz */
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 04/16] drm/i915: use ->get_vblank_counter for the crc frame counter
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (2 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 03/16] drm/i915: wire up CRC interrupt " Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 05/16] drm/i915: wait one vblank when disabling CRCs Daniel Vetter
` (12 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Suggested by Ville.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_irq.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 36465ef..eaf1268 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1193,7 +1193,7 @@ static void dp_aux_irq_handler(struct drm_device *dev)
static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe,
uint32_t crc0, uint32_t crc1,
uint32_t crc2, uint32_t crc3,
- uint32_t crc4, uint32_t frame)
+ uint32_t crc4)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
@@ -1215,7 +1215,7 @@ static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe,
entry = &pipe_crc->entries[head];
- entry->frame = frame;
+ entry->frame = dev->driver->get_vblank_counter(dev, pipe);
entry->crc[0] = crc0;
entry->crc[1] = crc1;
entry->crc[2] = crc2;
@@ -1237,8 +1237,7 @@ static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
- I915_READ(PIPE_CRC_RES_5_IVB(pipe)),
- I915_READ(PIPEFRAME(pipe)));
+ I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
}
static void ilk_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
@@ -1250,8 +1249,7 @@ static void ilk_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
I915_READ(PIPE_CRC_RES_GREEN_ILK(pipe)),
I915_READ(PIPE_CRC_RES_BLUE_ILK(pipe)),
I915_READ(PIPE_CRC_RES_RES1_ILK(pipe)),
- I915_READ(PIPE_CRC_RES_RES2_ILK(pipe)),
- I915_READ(PIPEFRAME(pipe)));
+ I915_READ(PIPE_CRC_RES_RES2_ILK(pipe)));
}
#else
static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
--
1.8.4.rc3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 05/16] drm/i915: wait one vblank when disabling CRCs
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (3 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 04/16] drm/i915: use ->get_vblank_counter for the crc frame counter Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 06/16] drm/i915: fix CRC debugfs setup Daniel Vetter
` (11 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
This avoids a spurious spurious interrupt warning.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 323f58e..349f149 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2040,6 +2040,8 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
pipe_name(pipe));
+ intel_wait_for_vblank(dev, pipe);
+
kfree(pipe_crc->entries);
pipe_crc->entries = NULL;
}
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 06/16] drm/i915: fix CRC debugfs setup
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (4 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 05/16] drm/i915: wait one vblank when disabling CRCs Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 07/16] drm/i915: crc support for hsw Daniel Vetter
` (10 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
We've set up all files, but removed only those for which we have a
pipe. Which leaves the one for pipe C on machines with less than 2
pipes, breaking module reload.
v2: We can't get at the drm device this early (wtf), so just register
all the files and also remove them all again.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 349f149..bb55046 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2772,7 +2772,6 @@ int i915_debugfs_init(struct drm_minor *minor)
void i915_debugfs_cleanup(struct drm_minor *minor)
{
- struct drm_device *dev = minor->dev;
int i;
drm_debugfs_remove_files(i915_debugfs_list,
@@ -2781,7 +2780,7 @@ void i915_debugfs_cleanup(struct drm_minor *minor)
drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
1, minor);
- for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
+ for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
struct drm_info_list *info_list =
(struct drm_info_list *)&i915_pipe_crc_data[i];
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 07/16] drm/i915: crc support for hsw
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (5 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 06/16] drm/i915: fix CRC debugfs setup Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-17 10:53 ` Damien Lespiau
2013-10-16 20:55 ` [PATCH 08/16] drm/i915: Adjust CRC capture for pre-gen5/vlv Daniel Vetter
` (9 subsequent siblings)
16 siblings, 1 reply; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
hw designers decided to change the CRC registers and coalesce them all
into one. Otherwise nothing changed. I've opted for a new hsw_ version
to grab the crc sample since hsw+1 will have the same crc registers,
but different interrupt source registers. So this little helper
function will come handy there.
Also refactor the display error handler with a neat pipe loop.
v2: Use for_each_pipe.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 44 +++++++++++++++++++++----------------
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index bb55046..59c7653 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1997,7 +1997,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
u32 val;
int ret;
- if (!(IS_IVYBRIDGE(dev) || IS_GEN5(dev) || IS_GEN6(dev)))
+ if (!(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)))
return -ENODEV;
if (pipe_crc->source == source)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index eaf1268..156a1a4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1228,6 +1228,15 @@ static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe,
wake_up_interruptible(&pipe_crc->wq);
}
+static void hsw_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ display_pipe_crc_update(dev, pipe,
+ I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
+ 0, 0, 0, 0);
+}
+
static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1252,6 +1261,7 @@ static void ilk_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
I915_READ(PIPE_CRC_RES_RES2_ILK(pipe)));
}
#else
+static inline void hsw_pipe_crc_update(struct drm_device *dev, int pipe) {}
static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
static inline void ilk_pipe_crc_update(struct drm_device *dev, int pipe) {}
#endif
@@ -1418,30 +1428,26 @@ static void ivb_err_int_handler(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
u32 err_int = I915_READ(GEN7_ERR_INT);
+ enum pipe pipe;
if (err_int & ERR_INT_POISON)
DRM_ERROR("Poison interrupt\n");
- if (err_int & ERR_INT_FIFO_UNDERRUN_A)
- if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
- DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
-
- if (err_int & ERR_INT_FIFO_UNDERRUN_B)
- if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
- DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
-
- if (err_int & ERR_INT_FIFO_UNDERRUN_C)
- if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
- DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
-
- if (err_int & ERR_INT_PIPE_CRC_DONE_A)
- ivb_pipe_crc_update(dev, PIPE_A);
-
- if (err_int & ERR_INT_PIPE_CRC_DONE_B)
- ivb_pipe_crc_update(dev, PIPE_B);
+ for_each_pipe(pipe) {
+ if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
+ if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
+ false))
+ DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
+ pipe_name(pipe));
+ }
- if (err_int & ERR_INT_PIPE_CRC_DONE_C)
- ivb_pipe_crc_update(dev, PIPE_C);
+ if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
+ if (IS_IVYBRIDGE(dev))
+ ivb_pipe_crc_update(dev, pipe);
+ else
+ hsw_pipe_crc_update(dev, pipe);
+ }
+ }
I915_WRITE(GEN7_ERR_INT, err_int);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8a62720..cf277ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -728,6 +728,7 @@
#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
+#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 07/16] drm/i915: crc support for hsw
2013-10-16 20:55 ` [PATCH 07/16] drm/i915: crc support for hsw Daniel Vetter
@ 2013-10-17 10:53 ` Damien Lespiau
2013-10-17 13:06 ` Daniel Vetter
0 siblings, 1 reply; 32+ messages in thread
From: Damien Lespiau @ 2013-10-17 10:53 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Wed, Oct 16, 2013 at 10:55:52PM +0200, Daniel Vetter wrote:
> hw designers decided to change the CRC registers and coalesce them all
> into one. Otherwise nothing changed. I've opted for a new hsw_ version
> to grab the crc sample since hsw+1 will have the same crc registers,
> but different interrupt source registers. So this little helper
> function will come handy there.
>
> Also refactor the display error handler with a neat pipe loop.
>
> v2: Use for_each_pipe.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Patches 1-7 are:
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 07/16] drm/i915: crc support for hsw
2013-10-17 10:53 ` Damien Lespiau
@ 2013-10-17 13:06 ` Daniel Vetter
0 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-17 13:06 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Daniel Vetter, Intel Graphics Development
On Thu, Oct 17, 2013 at 11:53:49AM +0100, Damien Lespiau wrote:
> On Wed, Oct 16, 2013 at 10:55:52PM +0200, Daniel Vetter wrote:
> > hw designers decided to change the CRC registers and coalesce them all
> > into one. Otherwise nothing changed. I've opted for a new hsw_ version
> > to grab the crc sample since hsw+1 will have the same crc registers,
> > but different interrupt source registers. So this little helper
> > function will come handy there.
> >
> > Also refactor the display error handler with a neat pipe loop.
> >
> > v2: Use for_each_pipe.
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Patches 1-7 are:
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Thanks for the review, I've merged the patches thus far.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 08/16] drm/i915: Adjust CRC capture for pre-gen5/vlv
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (6 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 07/16] drm/i915: crc support for hsw Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 09/16] drm/i915: CRC source selection #defines for gmch/vlv chips Daniel Vetter
` (8 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Should work down to gen2. The #defines for the interrupt sources are
already there in PIPESTAT and are the same on all gmch platforms for
gen2 up to vlv.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_irq.c | 28 +++++++++++++++++++---------
drivers/gpu/drm/i915/i915_reg.h | 30 +++++++++++++++---------------
2 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 156a1a4..98f5ac3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1249,21 +1249,31 @@ static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
}
-static void ilk_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
+static void i9xx_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t res1, res2;
+
+ if (INTEL_INFO(dev)->gen >= 3)
+ res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
+ else
+ res1 = 0;
+
+ if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
+ res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
+ else
+ res2 = 0;
display_pipe_crc_update(dev, pipe,
- I915_READ(PIPE_CRC_RES_RED_ILK(pipe)),
- I915_READ(PIPE_CRC_RES_GREEN_ILK(pipe)),
- I915_READ(PIPE_CRC_RES_BLUE_ILK(pipe)),
- I915_READ(PIPE_CRC_RES_RES1_ILK(pipe)),
- I915_READ(PIPE_CRC_RES_RES2_ILK(pipe)));
+ I915_READ(PIPE_CRC_RES_RED(pipe)),
+ I915_READ(PIPE_CRC_RES_GREEN(pipe)),
+ I915_READ(PIPE_CRC_RES_BLUE(pipe)),
+ res1, res2);
}
#else
static inline void hsw_pipe_crc_update(struct drm_device *dev, int pipe) {}
static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
-static inline void ilk_pipe_crc_update(struct drm_device *dev, int pipe) {}
+static inline void i9xx_pipe_crc_update(struct drm_device *dev, int pipe) {}
#endif
/* The RPS events need forcewake, so we add them to a work queue and mask their
@@ -1543,10 +1553,10 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
if (de_iir & DE_PIPEA_CRC_DONE)
- ilk_pipe_crc_update(dev, PIPE_A);
+ i9xx_pipe_crc_update(dev, PIPE_A);
if (de_iir & DE_PIPEB_CRC_DONE)
- ilk_pipe_crc_update(dev, PIPE_B);
+ i9xx_pipe_crc_update(dev, PIPE_B);
if (de_iir & DE_PLANEA_FLIP_DONE) {
intel_prepare_page_flip(dev, 0);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cf277ac..7379bbd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1858,11 +1858,11 @@
#define _PIPE_CRC_RES_4_A_IVB 0x60070
#define _PIPE_CRC_RES_5_A_IVB 0x60074
-#define _PIPE_CRC_RES_RED_A_ILK 0x60060
-#define _PIPE_CRC_RES_GREEN_A_ILK 0x60064
-#define _PIPE_CRC_RES_BLUE_A_ILK 0x60068
-#define _PIPE_CRC_RES_RES1_A_ILK 0x6006c
-#define _PIPE_CRC_RES_RES2_A_ILK 0x60080
+#define _PIPE_CRC_RES_RED_A (dev_priv->info->display_mmio_offset + 0x60060)
+#define _PIPE_CRC_RES_GREEN_A (dev_priv->info->display_mmio_offset + 0x60064)
+#define _PIPE_CRC_RES_BLUE_A (dev_priv->info->display_mmio_offset + 0x60068)
+#define _PIPE_CRC_RES_RES1_A_I915 (dev_priv->info->display_mmio_offset + 0x6006c)
+#define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080)
/* Pipe B CRC regs */
#define _PIPE_CRC_CTL_B 0x61050
@@ -1884,16 +1884,16 @@
#define PIPE_CRC_RES_5_IVB(pipe) \
_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
-#define PIPE_CRC_RES_RED_ILK(pipe) \
- _PIPE_INC(pipe, _PIPE_CRC_RES_RED_A_ILK, 0x01000)
-#define PIPE_CRC_RES_GREEN_ILK(pipe) \
- _PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A_ILK, 0x01000)
-#define PIPE_CRC_RES_BLUE_ILK(pipe) \
- _PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A_ILK, 0x01000)
-#define PIPE_CRC_RES_RES1_ILK(pipe) \
- _PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_ILK, 0x01000)
-#define PIPE_CRC_RES_RES2_ILK(pipe) \
- _PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_ILK, 0x01000)
+#define PIPE_CRC_RES_RED(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_RED_A, 0x01000)
+#define PIPE_CRC_RES_GREEN(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A, 0x01000)
+#define PIPE_CRC_RES_BLUE(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A, 0x01000)
+#define PIPE_CRC_RES_RES1_I915(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_I915, 0x01000)
+#define PIPE_CRC_RES_RES2_G4X(pipe) \
+ _PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000)
/* Pipe A timing regs */
#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000)
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 09/16] drm/i915: CRC source selection #defines for gmch/vlv chips
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (7 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 08/16] drm/i915: Adjust CRC capture for pre-gen5/vlv Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 10/16] drm/i915: Wire up CRC interrupts for pre-gen5/vlv Daniel Vetter
` (7 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
A bit a mess, since with DP/TV outputs we can't use the pipe CRC.
Also, no plane CRCs, so we need to update the basic testcases.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7379bbd..ad8fe21 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1843,15 +1843,37 @@
/* Pipe A CRC regs */
#define _PIPE_CRC_CTL_A (dev_priv->info->display_mmio_offset + 0x60050)
#define PIPE_CRC_ENABLE (1 << 31)
+/* ivb+ source selection */
#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
+/* ilk+ source selection */
#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
/* embedded DP port on the north display block, reserved on ivb */
#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
+/* vlv source selection */
+#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
+#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
+#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
+/* with DP port the pipe source is invalid */
+#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
+#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
+#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
+/* gen3+ source selection */
+#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
+#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
+#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
+/* with DP/TV port the pipe source is invalid */
+#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
+#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
+#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
+#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
+#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
+/* gen2 doesn't have source selection bits */
+
#define _PIPE_CRC_RES_1_A_IVB 0x60064
#define _PIPE_CRC_RES_2_A_IVB 0x60068
#define _PIPE_CRC_RES_3_A_IVB 0x6006c
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 10/16] drm/i915: Wire up CRC interrupts for pre-gen5/vlv
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (8 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 09/16] drm/i915: CRC source selection #defines for gmch/vlv chips Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 11/16] drm/i915: Enable CRC interrupts on pre-gen5/vlv Daniel Vetter
` (6 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
And throw in a tiny for_each_pipe refactoring for gen2.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98f5ac3..b31e7ca 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1350,6 +1350,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
intel_prepare_page_flip(dev, pipe);
intel_finish_page_flip(dev, pipe);
}
+
+ if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
+ i9xx_pipe_crc_update(dev, pipe);
}
/* Consume port. Then clear IIR or we'll miss events */
@@ -2800,13 +2803,14 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
if (iir & I915_USER_INTERRUPT)
notify_ring(dev, &dev_priv->ring[RCS]);
- if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
- i8xx_handle_vblank(dev, 0, iir))
- flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
+ for_each_pipe(pipe) {
+ if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
+ i8xx_handle_vblank(dev, pipe, iir))
+ flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
- if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
- i8xx_handle_vblank(dev, 1, iir))
- flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
+ if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
+ i9xx_pipe_crc_update(dev, pipe);
+ }
iir = new_iir;
}
@@ -2999,6 +3003,9 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
blc_event = true;
+
+ if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
+ i9xx_pipe_crc_update(dev, pipe);
}
if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -3243,6 +3250,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
blc_event = true;
+
+ if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
+ i9xx_pipe_crc_update(dev, pipe);
}
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 11/16] drm/i915: Enable CRC interrupts on pre-gen5/vlv
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (9 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 10/16] drm/i915: Wire up CRC interrupts for pre-gen5/vlv Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-21 10:49 ` Ville Syrjälä
2013-10-16 20:55 ` [PATCH 12/16] drm/i915: Fix PIPE_CRC_CTL for vlv Daniel Vetter
` (5 subsequent siblings)
16 siblings, 1 reply; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b31e7ca..5c3baa0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2574,7 +2574,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
u32 enable_mask;
- u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
+ u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
+ PIPE_CRC_DONE_ENABLE;
unsigned long irqflags;
enable_mask = I915_DISPLAY_PORT_INTERRUPT;
@@ -2697,6 +2698,7 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
static int i8xx_irq_postinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ unsigned long irqflags;
I915_WRITE16(EMR,
~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -2717,6 +2719,13 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
I915_USER_INTERRUPT);
POSTING_READ16(IER);
+ /* Interrupt setup is already guaranteed to be single-threaded, this is
+ * just to make the assert_spin_locked check happy. */
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
+ i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
return 0;
}
@@ -2857,6 +2866,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
u32 enable_mask;
+ unsigned long irqflags;
I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -2892,6 +2902,13 @@ static int i915_irq_postinstall(struct drm_device *dev)
i915_enable_asle_pipestat(dev);
+ /* Interrupt setup is already guaranteed to be single-threaded, this is
+ * just to make the assert_spin_locked check happy. */
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
+ i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
return 0;
}
@@ -3105,6 +3122,8 @@ static int i965_irq_postinstall(struct drm_device *dev)
* just to make the assert_spin_locked check happy. */
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
+ i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
+ i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
/*
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 11/16] drm/i915: Enable CRC interrupts on pre-gen5/vlv
2013-10-16 20:55 ` [PATCH 11/16] drm/i915: Enable CRC interrupts on pre-gen5/vlv Daniel Vetter
@ 2013-10-21 10:49 ` Ville Syrjälä
2013-10-21 15:13 ` Daniel Vetter
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2013-10-21 10:49 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Wed, Oct 16, 2013 at 10:55:56PM +0200, Daniel Vetter wrote:
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b31e7ca..5c3baa0 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2574,7 +2574,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
> {
> drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> u32 enable_mask;
> - u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
> + u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
> + PIPE_CRC_DONE_ENABLE;
> unsigned long irqflags;
>
> enable_mask = I915_DISPLAY_PORT_INTERRUPT;
> @@ -2697,6 +2698,7 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
> static int i8xx_irq_postinstall(struct drm_device *dev)
> {
> drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> + unsigned long irqflags;
>
> I915_WRITE16(EMR,
> ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
> @@ -2717,6 +2719,13 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
> I915_USER_INTERRUPT);
> POSTING_READ16(IER);
>
> + /* Interrupt setup is already guaranteed to be single-threaded, this is
> + * just to make the assert_spin_locked check happy. */
> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> + i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
> + i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
Could use PIPE_A/B instead of raw numbers. Maybe a separate patch
to fix it all up since we're already using raw numbers in some
other places in i915_irq.c.
> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +
> return 0;
> }
>
> @@ -2857,6 +2866,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
> {
> drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> u32 enable_mask;
> + unsigned long irqflags;
>
> I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
>
> @@ -2892,6 +2902,13 @@ static int i915_irq_postinstall(struct drm_device *dev)
>
> i915_enable_asle_pipestat(dev);
>
> + /* Interrupt setup is already guaranteed to be single-threaded, this is
> + * just to make the assert_spin_locked check happy. */
> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> + i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
> + i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +
> return 0;
> }
>
> @@ -3105,6 +3122,8 @@ static int i965_irq_postinstall(struct drm_device *dev)
> * just to make the assert_spin_locked check happy. */
> spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
> + i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
> + i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>
> /*
> --
> 1.8.4.rc3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 11/16] drm/i915: Enable CRC interrupts on pre-gen5/vlv
2013-10-21 10:49 ` Ville Syrjälä
@ 2013-10-21 15:13 ` Daniel Vetter
0 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-21 15:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Daniel Vetter, Intel Graphics Development
On Mon, Oct 21, 2013 at 01:49:24PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 16, 2013 at 10:55:56PM +0200, Daniel Vetter wrote:
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++++++++-
> > 1 file changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index b31e7ca..5c3baa0 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2574,7 +2574,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
> > {
> > drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> > u32 enable_mask;
> > - u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
> > + u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
> > + PIPE_CRC_DONE_ENABLE;
> > unsigned long irqflags;
> >
> > enable_mask = I915_DISPLAY_PORT_INTERRUPT;
> > @@ -2697,6 +2698,7 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
> > static int i8xx_irq_postinstall(struct drm_device *dev)
> > {
> > drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> > + unsigned long irqflags;
> >
> > I915_WRITE16(EMR,
> > ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
> > @@ -2717,6 +2719,13 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
> > I915_USER_INTERRUPT);
> > POSTING_READ16(IER);
> >
> > + /* Interrupt setup is already guaranteed to be single-threaded, this is
> > + * just to make the assert_spin_locked check happy. */
> > + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> > + i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
> > + i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
>
> Could use PIPE_A/B instead of raw numbers. Maybe a separate patch
> to fix it all up since we're already using raw numbers in some
> other places in i915_irq.c.
Yeah, this is just for consistency. I'll do a follow-up patch to sprinkle
nice enums over i915_irq.c. There's also 1-2 places that would benefit
from a for_each_pipe loop.
-Daniel
>
> > + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> > +
> > return 0;
> > }
> >
> > @@ -2857,6 +2866,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
> > {
> > drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> > u32 enable_mask;
> > + unsigned long irqflags;
> >
> > I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
> >
> > @@ -2892,6 +2902,13 @@ static int i915_irq_postinstall(struct drm_device *dev)
> >
> > i915_enable_asle_pipestat(dev);
> >
> > + /* Interrupt setup is already guaranteed to be single-threaded, this is
> > + * just to make the assert_spin_locked check happy. */
> > + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> > + i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
> > + i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
> > + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> > +
> > return 0;
> > }
> >
> > @@ -3105,6 +3122,8 @@ static int i965_irq_postinstall(struct drm_device *dev)
> > * just to make the assert_spin_locked check happy. */
> > spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> > i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
> > + i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
> > + i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
> > spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> >
> > /*
> > --
> > 1.8.4.rc3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 12/16] drm/i915: Fix PIPE_CRC_CTL for vlv
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (10 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 11/16] drm/i915: Enable CRC interrupts on pre-gen5/vlv Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-21 10:50 ` Ville Syrjälä
2013-10-16 20:55 ` [PATCH 13/16] drm/i915: Add new CRC sources Daniel Vetter
` (4 subsequent siblings)
16 siblings, 1 reply; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
The PIPE_B #define was missing the display mmio offset. Use the
_PIPE_INC macro instead, it's simpler.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad8fe21..4e0f0b7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1887,14 +1887,13 @@
#define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080)
/* Pipe B CRC regs */
-#define _PIPE_CRC_CTL_B 0x61050
#define _PIPE_CRC_RES_1_B_IVB 0x61064
#define _PIPE_CRC_RES_2_B_IVB 0x61068
#define _PIPE_CRC_RES_3_B_IVB 0x6106c
#define _PIPE_CRC_RES_4_B_IVB 0x61070
#define _PIPE_CRC_RES_5_B_IVB 0x61074
-#define PIPE_CRC_CTL(pipe) _PIPE(pipe, _PIPE_CRC_CTL_A, _PIPE_CRC_CTL_B)
+#define PIPE_CRC_CTL(pipe) _PIPE_INC(pipe, _PIPE_CRC_CTL_A, 0x01000)
#define PIPE_CRC_RES_1_IVB(pipe) \
_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
#define PIPE_CRC_RES_2_IVB(pipe) \
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 12/16] drm/i915: Fix PIPE_CRC_CTL for vlv
2013-10-16 20:55 ` [PATCH 12/16] drm/i915: Fix PIPE_CRC_CTL for vlv Daniel Vetter
@ 2013-10-21 10:50 ` Ville Syrjälä
2013-10-21 15:15 ` Daniel Vetter
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2013-10-21 10:50 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Wed, Oct 16, 2013 at 10:55:57PM +0200, Daniel Vetter wrote:
> The PIPE_B #define was missing the display mmio offset. Use the
> _PIPE_INC macro instead, it's simpler.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ad8fe21..4e0f0b7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1887,14 +1887,13 @@
> #define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080)
>
> /* Pipe B CRC regs */
> -#define _PIPE_CRC_CTL_B 0x61050
> #define _PIPE_CRC_RES_1_B_IVB 0x61064
> #define _PIPE_CRC_RES_2_B_IVB 0x61068
> #define _PIPE_CRC_RES_3_B_IVB 0x6106c
> #define _PIPE_CRC_RES_4_B_IVB 0x61070
> #define _PIPE_CRC_RES_5_B_IVB 0x61074
Maybe use _PIPE_INC() for these IVB regs as well. They're the only CRC
regs left using _PIPE(), so they feel a bit out of place.
>
> -#define PIPE_CRC_CTL(pipe) _PIPE(pipe, _PIPE_CRC_CTL_A, _PIPE_CRC_CTL_B)
> +#define PIPE_CRC_CTL(pipe) _PIPE_INC(pipe, _PIPE_CRC_CTL_A, 0x01000)
> #define PIPE_CRC_RES_1_IVB(pipe) \
> _PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
> #define PIPE_CRC_RES_2_IVB(pipe) \
> --
> 1.8.4.rc3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 12/16] drm/i915: Fix PIPE_CRC_CTL for vlv
2013-10-21 10:50 ` Ville Syrjälä
@ 2013-10-21 15:15 ` Daniel Vetter
0 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-21 15:15 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Daniel Vetter, Intel Graphics Development
On Mon, Oct 21, 2013 at 01:50:03PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 16, 2013 at 10:55:57PM +0200, Daniel Vetter wrote:
> > The PIPE_B #define was missing the display mmio offset. Use the
> > _PIPE_INC macro instead, it's simpler.
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index ad8fe21..4e0f0b7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1887,14 +1887,13 @@
> > #define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080)
> >
> > /* Pipe B CRC regs */
> > -#define _PIPE_CRC_CTL_B 0x61050
> > #define _PIPE_CRC_RES_1_B_IVB 0x61064
> > #define _PIPE_CRC_RES_2_B_IVB 0x61068
> > #define _PIPE_CRC_RES_3_B_IVB 0x6106c
> > #define _PIPE_CRC_RES_4_B_IVB 0x61070
> > #define _PIPE_CRC_RES_5_B_IVB 0x61074
>
> Maybe use _PIPE_INC() for these IVB regs as well. They're the only CRC
> regs left using _PIPE(), so they feel a bit out of place.
The _PIPE_INC stuff is essentially just a "throw stuff at the wall and see
whether it sticks" test. The idea is that with the doc rework registers
for new platforms are already tightly grouped, so the base+increment is
easier to review. If people like it we could do a mass conversion (and
decently cut down the size of i915_reg.h). That would also help to make
the odd cases like vlv+1 stick out more.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 13/16] drm/i915: Add new CRC sources
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (11 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 12/16] drm/i915: Fix PIPE_CRC_CTL for vlv Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:55 ` [PATCH 14/16] drm/i915: Wire up CRC support for gen3/4 Daniel Vetter
` (3 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
On pre-gen5 and vlv we can't use the pipe source when TV-out or a DP
port is connected to the pipe. Hence we need to expose new CRC
sources.
Also simplify the existing pipe source platform code a bit by
rejecting all unhandled sources by default.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++------
drivers/gpu/drm/i915/i915_drv.h | 5 +++++
2 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 59c7653..c504c27 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1915,6 +1915,10 @@ static const char * const pipe_crc_sources[] = {
"plane2",
"pf",
"pipe",
+ "TV",
+ "DP-B",
+ "DP-C",
+ "DP-D",
};
static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
@@ -1953,14 +1957,14 @@ static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
case INTEL_PIPE_CRC_SOURCE_PLANE2:
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
break;
- case INTEL_PIPE_CRC_SOURCE_PF:
- return -EINVAL;
case INTEL_PIPE_CRC_SOURCE_PIPE:
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
break;
- default:
+ case INTEL_PIPE_CRC_SOURCE_NONE:
*val = 0;
break;
+ default:
+ return -EINVAL;
}
return 0;
@@ -1979,11 +1983,11 @@ static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
case INTEL_PIPE_CRC_SOURCE_PF:
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
break;
- case INTEL_PIPE_CRC_SOURCE_PIPE:
- return -EINVAL;
- default:
+ case INTEL_PIPE_CRC_SOURCE_NONE:
*val = 0;
break;
+ default:
+ return -EINVAL;
}
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 09857f8..4ba0a79 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1223,6 +1223,11 @@ enum intel_pipe_crc_source {
INTEL_PIPE_CRC_SOURCE_PLANE2,
INTEL_PIPE_CRC_SOURCE_PF,
INTEL_PIPE_CRC_SOURCE_PIPE,
+ /* TV/DP on pre-gen5/vlv can't use the pipe source. */
+ INTEL_PIPE_CRC_SOURCE_TV,
+ INTEL_PIPE_CRC_SOURCE_DP_B,
+ INTEL_PIPE_CRC_SOURCE_DP_C,
+ INTEL_PIPE_CRC_SOURCE_DP_D,
INTEL_PIPE_CRC_SOURCE_MAX,
};
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 14/16] drm/i915: Wire up CRC support for gen3/4
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (12 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 13/16] drm/i915: Add new CRC sources Daniel Vetter
@ 2013-10-16 20:55 ` Daniel Vetter
2013-10-16 20:56 ` [PATCH 15/16] drm/i915: Wire up gen2 CRC support Daniel Vetter
` (2 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:55 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 44 +++++++++++++++++++++++++++++++++++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c504c27..6de9e7e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1947,6 +1947,44 @@ static int display_crc_ctl_open(struct inode *inode, struct file *file)
return single_open(file, display_crc_ctl_show, dev);
}
+static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
+ enum intel_pipe_crc_source source,
+ uint32_t *val)
+{
+ switch (source) {
+ case INTEL_PIPE_CRC_SOURCE_PIPE:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_TV:
+ if (!SUPPORTS_TV(dev))
+ return -EINVAL;
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_DP_B:
+ if (!IS_G4X(dev))
+ return -EINVAL;
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_DP_C:
+ if (!IS_G4X(dev))
+ return -EINVAL;
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_DP_D:
+ if (!IS_G4X(dev))
+ return -EINVAL;
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_NONE:
+ *val = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
uint32_t *val)
{
@@ -2001,7 +2039,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
u32 val;
int ret;
- if (!(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)))
+ if (!(INTEL_INFO(dev)->gen >= 3 && !IS_VALLEYVIEW(dev)))
return -ENODEV;
if (pipe_crc->source == source)
@@ -2011,7 +2049,9 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
if (pipe_crc->source && source)
return -EINVAL;
- if (IS_GEN5(dev) || IS_GEN6(dev))
+ if (INTEL_INFO(dev)->gen < 5)
+ ret = i9xx_pipe_crc_ctl_reg(dev, source, &val);
+ else if (IS_GEN5(dev) || IS_GEN6(dev))
ret = ilk_pipe_crc_ctl_reg(source, &val);
else
ret = ivb_pipe_crc_ctl_reg(source, &val);
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 15/16] drm/i915: Wire up gen2 CRC support
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (13 preceding siblings ...)
2013-10-16 20:55 ` [PATCH 14/16] drm/i915: Wire up CRC support for gen3/4 Daniel Vetter
@ 2013-10-16 20:56 ` Daniel Vetter
2013-10-16 20:56 ` [PATCH 16/16] drm/i915: Wire up CRC for vlv Daniel Vetter
2013-10-21 12:08 ` [PATCH 00/16] CRC support for non-ivb Ville Syrjälä
16 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:56 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Really simple, and we don't even have working frame numbers.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6de9e7e..ff6970b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1947,6 +1947,20 @@ static int display_crc_ctl_open(struct inode *inode, struct file *file)
return single_open(file, display_crc_ctl_show, dev);
}
+static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
+ uint32_t *val)
+{
+ switch (source) {
+ case INTEL_PIPE_CRC_SOURCE_PIPE:
+ *val = PIPE_CRC_ENABLE;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
enum intel_pipe_crc_source source,
uint32_t *val)
@@ -2049,7 +2063,9 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
if (pipe_crc->source && source)
return -EINVAL;
- if (INTEL_INFO(dev)->gen < 5)
+ if (IS_GEN2(dev))
+ ret = i8xx_pipe_crc_ctl_reg(source, &val);
+ else if (INTEL_INFO(dev)->gen < 5)
ret = i9xx_pipe_crc_ctl_reg(dev, source, &val);
else if (IS_GEN5(dev) || IS_GEN6(dev))
ret = ilk_pipe_crc_ctl_reg(source, &val);
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 16/16] drm/i915: Wire up CRC for vlv
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (14 preceding siblings ...)
2013-10-16 20:56 ` [PATCH 15/16] drm/i915: Wire up gen2 CRC support Daniel Vetter
@ 2013-10-16 20:56 ` Daniel Vetter
2013-10-18 14:37 ` [PATCH 1/3] drm/i915: Wire up gen2 CRC support Daniel Vetter
2013-10-21 12:08 ` [PATCH 00/16] CRC support for non-ivb Ville Syrjälä
16 siblings, 1 reply; 32+ messages in thread
From: Daniel Vetter @ 2013-10-16 20:56 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ff6970b..5841b6f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1961,6 +1961,29 @@ static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
return 0;
}
+static int vlv_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
+ uint32_t *val)
+{
+ switch (source) {
+ case INTEL_PIPE_CRC_SOURCE_PIPE:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_DP_B:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_DP_C:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_NONE:
+ *val = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
enum intel_pipe_crc_source source,
uint32_t *val)
@@ -2067,6 +2090,8 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
ret = i8xx_pipe_crc_ctl_reg(source, &val);
else if (INTEL_INFO(dev)->gen < 5)
ret = i9xx_pipe_crc_ctl_reg(dev, source, &val);
+ else if (IS_VALLEYVIEW(dev))
+ ret = vlv_pipe_crc_ctl_reg(source, &val);
else if (IS_GEN5(dev) || IS_GEN6(dev))
ret = ilk_pipe_crc_ctl_reg(source, &val);
else
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 1/3] drm/i915: Wire up gen2 CRC support
2013-10-16 20:56 ` [PATCH 16/16] drm/i915: Wire up CRC for vlv Daniel Vetter
@ 2013-10-18 14:37 ` Daniel Vetter
2013-10-18 14:37 ` [PATCH 2/3] drm/i915: Wire up CRC for vlv Daniel Vetter
` (2 more replies)
0 siblings, 3 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-18 14:37 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Really simple, and we don't even have working frame numbers.
v2: Actually enable it ...
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e3f0980..3f4fd7c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1947,6 +1947,20 @@ static int display_crc_ctl_open(struct inode *inode, struct file *file)
return single_open(file, display_crc_ctl_show, dev);
}
+static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
+ uint32_t *val)
+{
+ switch (source) {
+ case INTEL_PIPE_CRC_SOURCE_PIPE:
+ *val = PIPE_CRC_ENABLE;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
enum intel_pipe_crc_source source,
uint32_t *val)
@@ -2039,7 +2053,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
u32 val;
int ret;
- if (!(INTEL_INFO(dev)->gen >= 3 && !IS_VALLEYVIEW(dev)))
+ if (IS_VALLEYVIEW(dev))
return -ENODEV;
if (pipe_crc->source == source)
@@ -2049,7 +2063,9 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
if (pipe_crc->source && source)
return -EINVAL;
- if (INTEL_INFO(dev)->gen < 5)
+ if (IS_GEN2(dev))
+ ret = i8xx_pipe_crc_ctl_reg(source, &val);
+ else if (INTEL_INFO(dev)->gen < 5)
ret = i9xx_pipe_crc_ctl_reg(dev, source, &val);
else if (IS_GEN5(dev) || IS_GEN6(dev))
ret = ilk_pipe_crc_ctl_reg(source, &val);
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 2/3] drm/i915: Wire up CRC for vlv
2013-10-18 14:37 ` [PATCH 1/3] drm/i915: Wire up gen2 CRC support Daniel Vetter
@ 2013-10-18 14:37 ` Daniel Vetter
2013-10-18 14:37 ` [PATCH 3/3] drm/i915: bikeshed the pipe CRC irq functions a bit Daniel Vetter
2013-10-21 10:22 ` [PATCH 1/3] drm/i915: Wire up gen2 CRC support Ville Syrjälä
2 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-18 14:37 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
v2: Actually enable it.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 28 +++++++++++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3f4fd7c..eb61c4b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1961,6 +1961,29 @@ static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
return 0;
}
+static int vlv_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
+ uint32_t *val)
+{
+ switch (source) {
+ case INTEL_PIPE_CRC_SOURCE_PIPE:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_DP_B:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_DP_C:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_NONE:
+ *val = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
enum intel_pipe_crc_source source,
uint32_t *val)
@@ -2053,9 +2076,6 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
u32 val;
int ret;
- if (IS_VALLEYVIEW(dev))
- return -ENODEV;
-
if (pipe_crc->source == source)
return 0;
@@ -2067,6 +2087,8 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
ret = i8xx_pipe_crc_ctl_reg(source, &val);
else if (INTEL_INFO(dev)->gen < 5)
ret = i9xx_pipe_crc_ctl_reg(dev, source, &val);
+ else if (IS_VALLEYVIEW(dev))
+ ret = vlv_pipe_crc_ctl_reg(source, &val);
else if (IS_GEN5(dev) || IS_GEN6(dev))
ret = ilk_pipe_crc_ctl_reg(source, &val);
else
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 3/3] drm/i915: bikeshed the pipe CRC irq functions a bit
2013-10-18 14:37 ` [PATCH 1/3] drm/i915: Wire up gen2 CRC support Daniel Vetter
2013-10-18 14:37 ` [PATCH 2/3] drm/i915: Wire up CRC for vlv Daniel Vetter
@ 2013-10-18 14:37 ` Daniel Vetter
2013-10-21 10:22 ` [PATCH 1/3] drm/i915: Wire up gen2 CRC support Ville Syrjälä
2 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-18 14:37 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
- Give them an _irq_handler postfix, like all the other irq stuff.
- Shuffle the DEBUG_FS=n dummy functions around a bit. This is prep
work to extract all the crc debug stuff into intel_display_testing.c
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_irq.c | 71 +++++++++++++++++++++--------------------
1 file changed, 37 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5c3baa0..8f7baad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1190,10 +1190,10 @@ static void dp_aux_irq_handler(struct drm_device *dev)
}
#if defined(CONFIG_DEBUG_FS)
-static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe,
- uint32_t crc0, uint32_t crc1,
- uint32_t crc2, uint32_t crc3,
- uint32_t crc4)
+static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
+ uint32_t crc0, uint32_t crc1,
+ uint32_t crc2, uint32_t crc3,
+ uint32_t crc4)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
@@ -1227,29 +1227,37 @@ static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe,
wake_up_interruptible(&pipe_crc->wq);
}
+#else
+static inline void
+display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
+ uint32_t crc0, uint32_t crc1,
+ uint32_t crc2, uint32_t crc3,
+ uint32_t crc4) {}
+#endif
+
-static void hsw_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
+static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- display_pipe_crc_update(dev, pipe,
- I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
- 0, 0, 0, 0);
+ display_pipe_crc_irq_handler(dev, pipe,
+ I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
+ 0, 0, 0, 0);
}
-static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
+static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- display_pipe_crc_update(dev, pipe,
- I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
- I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
- I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
- I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
- I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
+ display_pipe_crc_irq_handler(dev, pipe,
+ I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
+ I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
+ I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
+ I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
+ I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
}
-static void i9xx_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
+static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t res1, res2;
@@ -1264,17 +1272,12 @@ static void i9xx_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
else
res2 = 0;
- display_pipe_crc_update(dev, pipe,
- I915_READ(PIPE_CRC_RES_RED(pipe)),
- I915_READ(PIPE_CRC_RES_GREEN(pipe)),
- I915_READ(PIPE_CRC_RES_BLUE(pipe)),
- res1, res2);
+ display_pipe_crc_irq_handler(dev, pipe,
+ I915_READ(PIPE_CRC_RES_RED(pipe)),
+ I915_READ(PIPE_CRC_RES_GREEN(pipe)),
+ I915_READ(PIPE_CRC_RES_BLUE(pipe)),
+ res1, res2);
}
-#else
-static inline void hsw_pipe_crc_update(struct drm_device *dev, int pipe) {}
-static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
-static inline void i9xx_pipe_crc_update(struct drm_device *dev, int pipe) {}
-#endif
/* The RPS events need forcewake, so we add them to a work queue and mask their
* IMR bits until the work is done. Other interrupts can be processed without
@@ -1352,7 +1355,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
}
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
- i9xx_pipe_crc_update(dev, pipe);
+ i9xx_pipe_crc_irq_handler(dev, pipe);
}
/* Consume port. Then clear IIR or we'll miss events */
@@ -1456,9 +1459,9 @@ static void ivb_err_int_handler(struct drm_device *dev)
if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
if (IS_IVYBRIDGE(dev))
- ivb_pipe_crc_update(dev, pipe);
+ ivb_pipe_crc_irq_handler(dev, pipe);
else
- hsw_pipe_crc_update(dev, pipe);
+ hsw_pipe_crc_irq_handler(dev, pipe);
}
}
@@ -1556,10 +1559,10 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
if (de_iir & DE_PIPEA_CRC_DONE)
- i9xx_pipe_crc_update(dev, PIPE_A);
+ i9xx_pipe_crc_irq_handler(dev, PIPE_A);
if (de_iir & DE_PIPEB_CRC_DONE)
- i9xx_pipe_crc_update(dev, PIPE_B);
+ i9xx_pipe_crc_irq_handler(dev, PIPE_B);
if (de_iir & DE_PLANEA_FLIP_DONE) {
intel_prepare_page_flip(dev, 0);
@@ -2818,7 +2821,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
- i9xx_pipe_crc_update(dev, pipe);
+ i9xx_pipe_crc_irq_handler(dev, pipe);
}
iir = new_iir;
@@ -3022,7 +3025,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
blc_event = true;
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
- i9xx_pipe_crc_update(dev, pipe);
+ i9xx_pipe_crc_irq_handler(dev, pipe);
}
if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -3271,7 +3274,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
blc_event = true;
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
- i9xx_pipe_crc_update(dev, pipe);
+ i9xx_pipe_crc_irq_handler(dev, pipe);
}
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 1/3] drm/i915: Wire up gen2 CRC support
2013-10-18 14:37 ` [PATCH 1/3] drm/i915: Wire up gen2 CRC support Daniel Vetter
2013-10-18 14:37 ` [PATCH 2/3] drm/i915: Wire up CRC for vlv Daniel Vetter
2013-10-18 14:37 ` [PATCH 3/3] drm/i915: bikeshed the pipe CRC irq functions a bit Daniel Vetter
@ 2013-10-21 10:22 ` Ville Syrjälä
2013-10-21 15:17 ` Daniel Vetter
2 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2013-10-21 10:22 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Fri, Oct 18, 2013 at 04:37:05PM +0200, Daniel Vetter wrote:
> Really simple, and we don't even have working frame numbers.
>
> v2: Actually enable it ...
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index e3f0980..3f4fd7c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1947,6 +1947,20 @@ static int display_crc_ctl_open(struct inode *inode, struct file *file)
> return single_open(file, display_crc_ctl_show, dev);
> }
>
> +static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
> + uint32_t *val)
> +{
> + switch (source) {
> + case INTEL_PIPE_CRC_SOURCE_PIPE:
> + *val = PIPE_CRC_ENABLE;
On gen3+ the border is always included in the crc. Maybe we should
always include it on gen2 as well?
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
> enum intel_pipe_crc_source source,
> uint32_t *val)
> @@ -2039,7 +2053,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
> u32 val;
> int ret;
>
> - if (!(INTEL_INFO(dev)->gen >= 3 && !IS_VALLEYVIEW(dev)))
> + if (IS_VALLEYVIEW(dev))
> return -ENODEV;
>
> if (pipe_crc->source == source)
> @@ -2049,7 +2063,9 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
> if (pipe_crc->source && source)
> return -EINVAL;
>
> - if (INTEL_INFO(dev)->gen < 5)
> + if (IS_GEN2(dev))
> + ret = i8xx_pipe_crc_ctl_reg(source, &val);
> + else if (INTEL_INFO(dev)->gen < 5)
> ret = i9xx_pipe_crc_ctl_reg(dev, source, &val);
> else if (IS_GEN5(dev) || IS_GEN6(dev))
> ret = ilk_pipe_crc_ctl_reg(source, &val);
> --
> 1.8.4.rc3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 1/3] drm/i915: Wire up gen2 CRC support
2013-10-21 10:22 ` [PATCH 1/3] drm/i915: Wire up gen2 CRC support Ville Syrjälä
@ 2013-10-21 15:17 ` Daniel Vetter
2013-10-21 15:26 ` [PATCH] " Daniel Vetter
0 siblings, 1 reply; 32+ messages in thread
From: Daniel Vetter @ 2013-10-21 15:17 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Daniel Vetter, Intel Graphics Development
On Mon, Oct 21, 2013 at 01:22:40PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 18, 2013 at 04:37:05PM +0200, Daniel Vetter wrote:
> > Really simple, and we don't even have working frame numbers.
> >
> > v2: Actually enable it ...
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 20 ++++++++++++++++++--
> > 1 file changed, 18 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index e3f0980..3f4fd7c 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1947,6 +1947,20 @@ static int display_crc_ctl_open(struct inode *inode, struct file *file)
> > return single_open(file, display_crc_ctl_show, dev);
> > }
> >
> > +static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
> > + uint32_t *val)
> > +{
> > + switch (source) {
> > + case INTEL_PIPE_CRC_SOURCE_PIPE:
> > + *val = PIPE_CRC_ENABLE;
>
> On gen3+ the border is always included in the crc. Maybe we should
> always include it on gen2 as well?
I've considered but decided to go meh. But you're right, for consistency
we should enable the border on gen2, too. I'll resend.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread* [PATCH] drm/i915: Wire up gen2 CRC support
2013-10-21 15:17 ` Daniel Vetter
@ 2013-10-21 15:26 ` Daniel Vetter
2013-10-21 16:16 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Daniel Vetter @ 2013-10-21 15:26 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Really simple, and we don't even have working frame numbers.
v2: Actually enable it ...
v3: Review from Ville:
- Unconditionally enable the border in the CRC checksum for
consistency with gen3+.
- Handle the "none" source to be able to disable the CRC machinery
again.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 23 +++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e3f0980..9a4f168 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1947,6 +1947,23 @@ static int display_crc_ctl_open(struct inode *inode, struct file *file)
return single_open(file, display_crc_ctl_show, dev);
}
+static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
+ uint32_t *val)
+{
+ switch (source) {
+ case INTEL_PIPE_CRC_SOURCE_PIPE:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_NONE:
+ *val = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
enum intel_pipe_crc_source source,
uint32_t *val)
@@ -2039,7 +2056,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
u32 val;
int ret;
- if (!(INTEL_INFO(dev)->gen >= 3 && !IS_VALLEYVIEW(dev)))
+ if (IS_VALLEYVIEW(dev))
return -ENODEV;
if (pipe_crc->source == source)
@@ -2049,7 +2066,9 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
if (pipe_crc->source && source)
return -EINVAL;
- if (INTEL_INFO(dev)->gen < 5)
+ if (IS_GEN2(dev))
+ ret = i8xx_pipe_crc_ctl_reg(source, &val);
+ else if (INTEL_INFO(dev)->gen < 5)
ret = i9xx_pipe_crc_ctl_reg(dev, source, &val);
else if (IS_GEN5(dev) || IS_GEN6(dev))
ret = ilk_pipe_crc_ctl_reg(source, &val);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d8ef094..c97fc94 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1873,6 +1873,7 @@
#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
/* gen2 doesn't have source selection bits */
+#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
#define _PIPE_CRC_RES_1_A_IVB 0x60064
#define _PIPE_CRC_RES_2_A_IVB 0x60068
--
1.8.4.rc3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH] drm/i915: Wire up gen2 CRC support
2013-10-21 15:26 ` [PATCH] " Daniel Vetter
@ 2013-10-21 16:16 ` Ville Syrjälä
2013-10-21 16:35 ` Daniel Vetter
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2013-10-21 16:16 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Mon, Oct 21, 2013 at 05:26:38PM +0200, Daniel Vetter wrote:
> Really simple, and we don't even have working frame numbers.
>
> v2: Actually enable it ...
>
> v3: Review from Ville:
> - Unconditionally enable the border in the CRC checksum for
> consistency with gen3+.
> - Handle the "none" source to be able to disable the CRC machinery
> again.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 23 +++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index e3f0980..9a4f168 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1947,6 +1947,23 @@ static int display_crc_ctl_open(struct inode *inode, struct file *file)
> return single_open(file, display_crc_ctl_show, dev);
> }
>
> +static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
> + uint32_t *val)
> +{
> + switch (source) {
> + case INTEL_PIPE_CRC_SOURCE_PIPE:
> + *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
> + break;
> + case INTEL_PIPE_CRC_SOURCE_NONE:
> + *val = 0;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
> enum intel_pipe_crc_source source,
> uint32_t *val)
> @@ -2039,7 +2056,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
> u32 val;
> int ret;
>
> - if (!(INTEL_INFO(dev)->gen >= 3 && !IS_VALLEYVIEW(dev)))
> + if (IS_VALLEYVIEW(dev))
> return -ENODEV;
>
> if (pipe_crc->source == source)
> @@ -2049,7 +2066,9 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
> if (pipe_crc->source && source)
> return -EINVAL;
>
> - if (INTEL_INFO(dev)->gen < 5)
> + if (IS_GEN2(dev))
> + ret = i8xx_pipe_crc_ctl_reg(source, &val);
> + else if (INTEL_INFO(dev)->gen < 5)
> ret = i9xx_pipe_crc_ctl_reg(dev, source, &val);
> else if (IS_GEN5(dev) || IS_GEN6(dev))
> ret = ilk_pipe_crc_ctl_reg(source, &val);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d8ef094..c97fc94 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1873,6 +1873,7 @@
> #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
> #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
> /* gen2 doesn't have source selection bits */
> +#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
>
> #define _PIPE_CRC_RES_1_A_IVB 0x60064
> #define _PIPE_CRC_RES_2_A_IVB 0x60068
> --
> 1.8.4.rc3
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH] drm/i915: Wire up gen2 CRC support
2013-10-21 16:16 ` Ville Syrjälä
@ 2013-10-21 16:35 ` Daniel Vetter
0 siblings, 0 replies; 32+ messages in thread
From: Daniel Vetter @ 2013-10-21 16:35 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Daniel Vetter, Intel Graphics Development
On Mon, Oct 21, 2013 at 07:16:24PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 21, 2013 at 05:26:38PM +0200, Daniel Vetter wrote:
> > Really simple, and we don't even have working frame numbers.
> >
> > v2: Actually enable it ...
> >
> > v3: Review from Ville:
> > - Unconditionally enable the border in the CRC checksum for
> > consistency with gen3+.
> > - Handle the "none" source to be able to disable the CRC machinery
> > again.
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks for your review, I've merged all the patches to dinq.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 00/16] CRC support for non-ivb
2013-10-16 20:55 [PATCH 00/16] CRC support for non-ivb Daniel Vetter
` (15 preceding siblings ...)
2013-10-16 20:56 ` [PATCH 16/16] drm/i915: Wire up CRC for vlv Daniel Vetter
@ 2013-10-21 12:08 ` Ville Syrjälä
16 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2013-10-21 12:08 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Wed, Oct 16, 2013 at 10:55:45PM +0200, Daniel Vetter wrote:
> Hi all,
>
> I've stitched together basic CRC support for non-ivb platforms. Still need to do
> a bit more testing on this, but ignoring bugs this should be it. We also need to
> pimp the igt testcase a bit so that it falls back to the new PIPE source if the
> PLANE1 source isn't available.
>
> Review and comments highly welcome.
Apart from the three minor things I commented on, I couldn't find
any real problems with the series. So the remainder of the series is:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Cheers, Daniel
>
> Daniel Vetter (16):
> drm/i915: extract display_pipe_crc_update
> drm/i915: add CRC #defines for ilk/snb
> drm/i915: wire up CRC interrupt for ilk/snb
> drm/i915: use ->get_vblank_counter for the crc frame counter
> drm/i915: wait one vblank when disabling CRCs
> drm/i915: fix CRC debugfs setup
> drm/i915: crc support for hsw
> drm/i915: Adjust CRC capture for pre-gen5/vlv
> drm/i915: CRC source selection #defines for gmch/vlv chips
> drm/i915: Wire up CRC interrupts for pre-gen5/vlv
> drm/i915: Enable CRC interrupts on pre-gen5/vlv
> drm/i915: Fix PIPE_CRC_CTL for vlv
> drm/i915: Add new CRC sources
> drm/i915: Wire up CRC support for gen3/4
> drm/i915: Wire up gen2 CRC support
> drm/i915: Wire up CRC for vlv
>
> drivers/gpu/drm/i915/i915_debugfs.c | 164 +++++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/i915_drv.h | 6 ++
> drivers/gpu/drm/i915/i915_irq.c | 151 +++++++++++++++++++++++++--------
> drivers/gpu/drm/i915/i915_reg.h | 74 +++++++++++++---
> 4 files changed, 328 insertions(+), 67 deletions(-)
>
> --
> 1.8.4.rc3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 32+ messages in thread