* [Intel-gfx] [PATCH v2 01/27] drm/i915/xelpdp: Add XE_LPDP_FEATURES
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 16:04 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 02/27] drm/i915/lnl: Add display definitions Lucas De Marchi
` (26 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline
for Xe2_LPD and will allow to see the delta more easily.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_device.c | 60 ++++++++++++++++---
1 file changed, 52 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index c39f8a15d8aa..089674e2f1d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -710,18 +710,62 @@ static const struct intel_display_device_info xe_hpd_display = {
BIT(PORT_TC1),
};
+#define XE_LPDP_FEATURES \
+ .abox_mask = GENMASK(1, 0), \
+ .color = { \
+ .degamma_lut_size = 129, .gamma_lut_size = 1024, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
+ }, \
+ .dbuf.size = 4096, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
+ BIT(DBUF_S4), \
+ .has_cdclk_crawl = 1, \
+ .has_cdclk_squash = 1, \
+ .has_ddi = 1, \
+ .has_dp_mst = 1, \
+ .has_dsb = 1, \
+ .has_fpga_dbg = 1, \
+ .has_hotplug = 1, \
+ .has_ipc = 1, \
+ .has_psr = 1, \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_D] = PIPE_D_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ }, \
+ TGL_CURSOR_OFFSETS, \
+ \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
+ .__runtime_defaults.ip.ver = 13, \
+ .__runtime_defaults.has_dmc = 1, \
+ .__runtime_defaults.has_dsc = 1, \
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
+ .__runtime_defaults.has_hdcp = 1, \
+ .__runtime_defaults.pipe_mask = \
+ BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
+ BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
+
+
static const struct intel_display_device_info xe_lpdp_display = {
- XE_LPD_FEATURES,
- .has_cdclk_crawl = 1,
- .has_cdclk_squash = 1,
+ XE_LPDP_FEATURES,
.__runtime_defaults.ip.ver = 14,
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
- .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
- BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
};
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 01/27] drm/i915/xelpdp: Add XE_LPDP_FEATURES
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 01/27] drm/i915/xelpdp: Add XE_LPDP_FEATURES Lucas De Marchi
@ 2023-09-07 16:04 ` Matt Roper
2023-09-07 20:35 ` Lucas De Marchi
0 siblings, 1 reply; 62+ messages in thread
From: Matt Roper @ 2023-09-07 16:04 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 08:37:31AM -0700, Lucas De Marchi wrote:
> Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline
> for Xe2_LPD and will allow to see the delta more easily.
Would it be simpler to do
#define XE_LPDP_FEATURES \
XE_LPD_FEATURES \
/* additional deltas */
so that it's more obvious what the deltas between Xe_LPD -> Xe_LPD+ are
too?
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../drm/i915/display/intel_display_device.c | 60 ++++++++++++++++---
> 1 file changed, 52 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index c39f8a15d8aa..089674e2f1d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -710,18 +710,62 @@ static const struct intel_display_device_info xe_hpd_display = {
> BIT(PORT_TC1),
> };
>
> +#define XE_LPDP_FEATURES \
> + .abox_mask = GENMASK(1, 0), \
> + .color = { \
> + .degamma_lut_size = 129, .gamma_lut_size = 1024, \
> + .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> + DRM_COLOR_LUT_EQUAL_CHANNELS, \
> + }, \
> + .dbuf.size = 4096, \
> + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
> + BIT(DBUF_S4), \
> + .has_cdclk_crawl = 1, \
> + .has_cdclk_squash = 1, \
> + .has_ddi = 1, \
> + .has_dp_mst = 1, \
> + .has_dsb = 1, \
> + .has_fpga_dbg = 1, \
> + .has_hotplug = 1, \
> + .has_ipc = 1, \
> + .has_psr = 1, \
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + [TRANSCODER_C] = PIPE_C_OFFSET, \
> + [TRANSCODER_D] = PIPE_D_OFFSET, \
> + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
If we're expanding out the whole definition rather than defining this as
XE_LPD_FEATURES + deltas, then there's no need for the DSI here.
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> + [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
Or here.
> + }, \
> + TGL_CURSOR_OFFSETS, \
> + \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
> + .__runtime_defaults.ip.ver = 13, \
Xe_LPD+'s ip version is 14 rather than 13.
> + .__runtime_defaults.has_dmc = 1, \
> + .__runtime_defaults.has_dsc = 1, \
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
And the FBC is on A + B.
Matt
> + .__runtime_defaults.has_hdcp = 1, \
> + .__runtime_defaults.pipe_mask = \
> + BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
> + BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
> +
> +
> static const struct intel_display_device_info xe_lpdp_display = {
> - XE_LPD_FEATURES,
> - .has_cdclk_crawl = 1,
> - .has_cdclk_squash = 1,
> + XE_LPDP_FEATURES,
>
> .__runtime_defaults.ip.ver = 14,
> .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
> - BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> };
>
> /*
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 01/27] drm/i915/xelpdp: Add XE_LPDP_FEATURES
2023-09-07 16:04 ` Matt Roper
@ 2023-09-07 20:35 ` Lucas De Marchi
0 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 20:35 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 09:04:03AM -0700, Matt Roper wrote:
>On Thu, Sep 07, 2023 at 08:37:31AM -0700, Lucas De Marchi wrote:
>> Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline
>> for Xe2_LPD and will allow to see the delta more easily.
>
>Would it be simpler to do
>
> #define XE_LPDP_FEATURES \
> XE_LPD_FEATURES \
> /* additional deltas */
>
>so that it's more obvious what the deltas between Xe_LPD -> Xe_LPD+ are
>too?
remember the nightmare we had in i915 with multiple inheritance? In the
end we settled to have just one level - the struct has 1 _FEATURES and
overrides or set new fields. A _FEATURES is always the root, without
inheriting from others.
It may be more verbose, but it's easier to look for "is x enabled in
this platform?"
Lucas De Marchi
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 02/27] drm/i915/lnl: Add display definitions
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 01/27] drm/i915/xelpdp: Add XE_LPDP_FEATURES Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 16:10 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 03/27] drm/i915/xe2lpd: FBC is now supported on all pipes Lucas De Marchi
` (25 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi, Balasubramani Vivekanandan
From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Add Lunar Lake platform definitions for i915 display. The support for
LNL will be added to the xe driver, with i915 only driving the display
side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
i915 module.
v2: Use a LPDP_FEATURES macro (Matt Roper)
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 089674e2f1d2..feafb0f94b06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -768,6 +768,12 @@ static const struct intel_display_device_info xe_lpdp_display = {
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
};
+static const struct intel_display_device_info xe2_lpd_display = {
+ XE_LPDP_FEATURES,
+
+ .__runtime_defaults.ip.ver = 20,
+};
+
/*
* Separate detection for no display cases to keep the display id array simple.
*
@@ -847,6 +853,7 @@ static const struct {
const struct intel_display_device_info *display;
} gmdid_display_map[] = {
{ 14, 0, &xe_lpdp_display },
+ { 20, 0, &xe2_lpd_display },
};
static const struct intel_display_device_info *
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 02/27] drm/i915/lnl: Add display definitions
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 02/27] drm/i915/lnl: Add display definitions Lucas De Marchi
@ 2023-09-07 16:10 ` Matt Roper
2023-09-08 23:25 ` [Intel-gfx] [Intel-xe] " Lucas De Marchi
0 siblings, 1 reply; 62+ messages in thread
From: Matt Roper @ 2023-09-07 16:10 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe, Balasubramani Vivekanandan
On Thu, Sep 07, 2023 at 08:37:32AM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>
> Add Lunar Lake platform definitions for i915 display. The support for
> LNL will be added to the xe driver, with i915 only driving the display
> side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
> i915 module.
This final sentence no longer matches the patch. But it might be worth
adding a different sentence saying something like "Xe2 display is
derived from the Xe_LPD+ IP; additional feature deltas will be
introduced in subsequent patches."
>
> v2: Use a LPDP_FEATURES macro (Matt Roper)
>
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 089674e2f1d2..feafb0f94b06 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -768,6 +768,12 @@ static const struct intel_display_device_info xe_lpdp_display = {
> .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> };
>
> +static const struct intel_display_device_info xe2_lpd_display = {
> + XE_LPDP_FEATURES,
> +
> + .__runtime_defaults.ip.ver = 20,
There's no need to set a default value here, right? If we've managed to
match this IP block, we already read out the GMD ID version and matched
it against the table below. We'll be assigning the real value directly
and shouldn't need this for anything.
Matt
> +};
> +
> /*
> * Separate detection for no display cases to keep the display id array simple.
> *
> @@ -847,6 +853,7 @@ static const struct {
> const struct intel_display_device_info *display;
> } gmdid_display_map[] = {
> { 14, 0, &xe_lpdp_display },
> + { 20, 0, &xe2_lpd_display },
> };
>
> static const struct intel_display_device_info *
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v2 02/27] drm/i915/lnl: Add display definitions
2023-09-07 16:10 ` Matt Roper
@ 2023-09-08 23:25 ` Lucas De Marchi
2023-09-08 23:37 ` Matt Roper
0 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-08 23:25 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 09:10:44AM -0700, Matt Roper wrote:
>On Thu, Sep 07, 2023 at 08:37:32AM -0700, Lucas De Marchi wrote:
>> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>
>> Add Lunar Lake platform definitions for i915 display. The support for
>> LNL will be added to the xe driver, with i915 only driving the display
>> side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
>> i915 module.
>
>This final sentence no longer matches the patch. But it might be worth
>adding a different sentence saying something like "Xe2 display is
>derived from the Xe_LPD+ IP; additional feature deltas will be
>introduced in subsequent patches."
>
>>
>> v2: Use a LPDP_FEATURES macro (Matt Roper)
>>
>> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
>> index 089674e2f1d2..feafb0f94b06 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
>> @@ -768,6 +768,12 @@ static const struct intel_display_device_info xe_lpdp_display = {
>> .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
>> };
>>
>> +static const struct intel_display_device_info xe2_lpd_display = {
>> + XE_LPDP_FEATURES,
>> +
>> + .__runtime_defaults.ip.ver = 20,
>
>There's no need to set a default value here, right? If we've managed to
unless we have a broken check for display version before this is
initialized. I will give it a try and see what happens.
But if we remove it here, we should also remove on previous patch. As
far as I can see, it's true for Xe-LPD+ too. If we have a wrong check
for version, I'd rather prefer it broken and a loud warning than it
matching version 14 due to using the macro above.
Lucas De Marchi
>match this IP block, we already read out the GMD ID version and matched
>it against the table below. We'll be assigning the real value directly
>and shouldn't need this for anything.
>
>
>Matt
>
>> +};
>> +
>> /*
>> * Separate detection for no display cases to keep the display id array simple.
>> *
>> @@ -847,6 +853,7 @@ static const struct {
>> const struct intel_display_device_info *display;
>> } gmdid_display_map[] = {
>> { 14, 0, &xe_lpdp_display },
>> + { 20, 0, &xe2_lpd_display },
>> };
>>
>> static const struct intel_display_device_info *
>> --
>> 2.40.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v2 02/27] drm/i915/lnl: Add display definitions
2023-09-08 23:25 ` [Intel-gfx] [Intel-xe] " Lucas De Marchi
@ 2023-09-08 23:37 ` Matt Roper
0 siblings, 0 replies; 62+ messages in thread
From: Matt Roper @ 2023-09-08 23:37 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Fri, Sep 08, 2023 at 06:25:04PM -0500, Lucas De Marchi wrote:
> On Thu, Sep 07, 2023 at 09:10:44AM -0700, Matt Roper wrote:
> > On Thu, Sep 07, 2023 at 08:37:32AM -0700, Lucas De Marchi wrote:
> > > From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > >
> > > Add Lunar Lake platform definitions for i915 display. The support for
> > > LNL will be added to the xe driver, with i915 only driving the display
> > > side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
> > > i915 module.
> >
> > This final sentence no longer matches the patch. But it might be worth
> > adding a different sentence saying something like "Xe2 display is
> > derived from the Xe_LPD+ IP; additional feature deltas will be
> > introduced in subsequent patches."
> >
> > >
> > > v2: Use a LPDP_FEATURES macro (Matt Roper)
> > >
> > > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++++++
> > > 1 file changed, 7 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> > > index 089674e2f1d2..feafb0f94b06 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> > > @@ -768,6 +768,12 @@ static const struct intel_display_device_info xe_lpdp_display = {
> > > .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> > > };
> > >
> > > +static const struct intel_display_device_info xe2_lpd_display = {
> > > + XE_LPDP_FEATURES,
> > > +
> > > + .__runtime_defaults.ip.ver = 20,
> >
> > There's no need to set a default value here, right? If we've managed to
>
> unless we have a broken check for display version before this is
> initialized. I will give it a try and see what happens.
>
> But if we remove it here, we should also remove on previous patch. As
> far as I can see, it's true for Xe-LPD+ too. If we have a wrong check
> for version, I'd rather prefer it broken and a loud warning than it
> matching version 14 due to using the macro above.
Agreed, we shouldn't have it on Xe_LPD+ either. I meant to mention
that, but I guess I forgot.
Matt
>
> Lucas De Marchi
>
> > match this IP block, we already read out the GMD ID version and matched
> > it against the table below. We'll be assigning the real value directly
> > and shouldn't need this for anything.
> >
> >
> > Matt
> >
> > > +};
> > > +
> > > /*
> > > * Separate detection for no display cases to keep the display id array simple.
> > > *
> > > @@ -847,6 +853,7 @@ static const struct {
> > > const struct intel_display_device_info *display;
> > > } gmdid_display_map[] = {
> > > { 14, 0, &xe_lpdp_display },
> > > + { 20, 0, &xe2_lpd_display },
> > > };
> > >
> > > static const struct intel_display_device_info *
> > > --
> > > 2.40.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 03/27] drm/i915/xe2lpd: FBC is now supported on all pipes
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 01/27] drm/i915/xelpdp: Add XE_LPDP_FEATURES Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 02/27] drm/i915/lnl: Add display definitions Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-08 8:54 ` [Intel-gfx] [Intel-xe] " Govindapillai, Vinod
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 04/27] drm/i915: Re-order if/else ladder in intel_detect_pch() Lucas De Marchi
` (24 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi, Matt Roper
From: Matt Roper <matthew.d.roper@intel.com>
FBC is no longer limited by pipe: add the defines for pipes B and C that
will be used by platforms supporting FBC on such pipes.
Bspec: 68881, 68904
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index feafb0f94b06..652e35ed7789 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -772,6 +772,9 @@ static const struct intel_display_device_info xe2_lpd_display = {
XE_LPDP_FEATURES,
.__runtime_defaults.ip.ver = 20,
+ .__runtime_defaults.fbc_mask =
+ BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
+ BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
};
/*
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 4adb98afe6ff..6720ec8ee8a2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -20,6 +20,8 @@ struct intel_plane_state;
enum intel_fbc_id {
INTEL_FBC_A,
INTEL_FBC_B,
+ INTEL_FBC_C,
+ INTEL_FBC_D,
I915_MAX_FBCS,
};
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v2 03/27] drm/i915/xe2lpd: FBC is now supported on all pipes
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 03/27] drm/i915/xe2lpd: FBC is now supported on all pipes Lucas De Marchi
@ 2023-09-08 8:54 ` Govindapillai, Vinod
0 siblings, 0 replies; 62+ messages in thread
From: Govindapillai, Vinod @ 2023-09-08 8:54 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
De Marchi, Lucas
Cc: Roper, Matthew D
On Thu, 2023-09-07 at 08:37 -0700, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> FBC is no longer limited by pipe: add the defines for pipes B and C that
> will be used by platforms supporting FBC on such pipes.
>
> Bspec: 68881, 68904
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
> drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
> 2 files changed, 5 insertions(+)
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index feafb0f94b06..652e35ed7789 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -772,6 +772,9 @@ static const struct intel_display_device_info xe2_lpd_display = {
> XE_LPDP_FEATURES,
>
> .__runtime_defaults.ip.ver = 20,
> + .__runtime_defaults.fbc_mask =
> + BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
> + BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 4adb98afe6ff..6720ec8ee8a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -20,6 +20,8 @@ struct intel_plane_state;
> enum intel_fbc_id {
> INTEL_FBC_A,
> INTEL_FBC_B,
> + INTEL_FBC_C,
> + INTEL_FBC_D,
>
> I915_MAX_FBCS,
> };
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 04/27] drm/i915: Re-order if/else ladder in intel_detect_pch()
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (2 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 03/27] drm/i915/xe2lpd: FBC is now supported on all pipes Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH Lucas De Marchi
` (23 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Matt Roper, Lucas De Marchi
Follow the convention of checking the last platform first and reword the
comment to convey there are more platforms than just DG1.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/soc/intel_pch.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index 19a8f27c404e..dfffdfa50b97 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -218,13 +218,16 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
unsigned short id;
enum intel_pch pch_type;
- /* DG1 has south engine display on the same PCI device */
- if (IS_DG1(dev_priv)) {
- dev_priv->pch_type = PCH_DG1;
- return;
- } else if (IS_DG2(dev_priv)) {
+ /*
+ * South display engine on the same PCI device: just assign the fake
+ * PCH.
+ */
+ if (IS_DG2(dev_priv)) {
dev_priv->pch_type = PCH_DG2;
return;
+ } else if (IS_DG1(dev_priv)) {
+ dev_priv->pch_type = PCH_DG1;
+ return;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (3 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 04/27] drm/i915: Re-order if/else ladder in intel_detect_pch() Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 17:04 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 06/27] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation Lucas De Marchi
` (22 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Gustavo Sousa <gustavo.sousa@intel.com>
Xe2_LPD has sourth display on the same SOC. As such, define a new fake
PCH entry for it.
v2: Match on display IP version rather than on platform (Matt Roper)
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index dfffdfa50b97..240beafb38ed 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -222,7 +222,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
* South display engine on the same PCI device: just assign the fake
* PCH.
*/
- if (IS_DG2(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ dev_priv->pch_type = PCH_LNL;
+ return;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->pch_type = PCH_DG2;
return;
} else if (IS_DG1(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
index 32aff5a70d04..1b03ea60a7a8 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.h
+++ b/drivers/gpu/drm/i915/soc/intel_pch.h
@@ -30,6 +30,7 @@ enum intel_pch {
/* Fake PCHs, functionality handled on the same PCI dev */
PCH_DG1 = 1024,
PCH_DG2,
+ PCH_LNL,
};
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
@@ -66,6 +67,7 @@ enum intel_pch {
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH Lucas De Marchi
@ 2023-09-07 17:04 ` Matt Roper
2023-09-07 20:43 ` Lucas De Marchi
0 siblings, 1 reply; 62+ messages in thread
From: Matt Roper @ 2023-09-07 17:04 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 08:37:35AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
>
> Xe2_LPD has sourth display on the same SOC. As such, define a new fake
s/sourth/south/
You might also want to drop the word "same" from the description here
since NDE and SDE are technically on different dies in this case (NDE is
on the compute die, whereas SDE is on the SoC die). To be 100% accurate
we'd want to identify SDE behavior via the PICA's GMD_ID (since PICA
also lives on the SoC die for this platform). But since we've just been
able to get by so far with just matching PICA behavior on the display
version rather than on its own version, we can just use display version
for this as well, at least for now. We may need to revisit this all
down the road once we have platforms with more possible combinations of
these components. Of course we really need to rework the SDE handling
in general (and break its assumption that SDE behavior is tied to PCH on
modern platforms), but that's work for a future patch series.
I was originally wondering if we could just reuse PCH_MTP here, but it
looks like there's one place where we setup HPD interrupts that needs
different handling. So this should be good enough for now, and we can
revisit the whole SDE design separately down the road.
With the minor commit message fix above,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> PCH entry for it.
>
> v2: Match on display IP version rather than on platform (Matt Roper)
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
> drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
> index dfffdfa50b97..240beafb38ed 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.c
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
> @@ -222,7 +222,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
> * South display engine on the same PCI device: just assign the fake
> * PCH.
> */
> - if (IS_DG2(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) >= 20) {
> + dev_priv->pch_type = PCH_LNL;
> + return;
> + } else if (IS_DG2(dev_priv)) {
> dev_priv->pch_type = PCH_DG2;
> return;
> } else if (IS_DG1(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
> index 32aff5a70d04..1b03ea60a7a8 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.h
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.h
> @@ -30,6 +30,7 @@ enum intel_pch {
> /* Fake PCHs, functionality handled on the same PCI dev */
> PCH_DG1 = 1024,
> PCH_DG2,
> + PCH_LNL,
> };
>
> #define INTEL_PCH_DEVICE_ID_MASK 0xff80
> @@ -66,6 +67,7 @@ enum intel_pch {
>
> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
> +#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
> #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
> #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
> #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
2023-09-07 17:04 ` Matt Roper
@ 2023-09-07 20:43 ` Lucas De Marchi
2023-09-08 0:57 ` Matt Roper
0 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 20:43 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 10:04:42AM -0700, Matt Roper wrote:
>On Thu, Sep 07, 2023 at 08:37:35AM -0700, Lucas De Marchi wrote:
>> From: Gustavo Sousa <gustavo.sousa@intel.com>
>>
>> Xe2_LPD has sourth display on the same SOC. As such, define a new fake
>
>s/sourth/south/
>
>You might also want to drop the word "same" from the description here
>since NDE and SDE are technically on different dies in this case (NDE is
>on the compute die, whereas SDE is on the SoC die). To be 100% accurate
>we'd want to identify SDE behavior via the PICA's GMD_ID (since PICA
>also lives on the SoC die for this platform). But since we've just been
I'd not re-architect this based on where the PICA lives as it seems very
easy to change in future.... tying the SDE behavior to the PICA behavior
because they are on the same die, doesn't seem very future proof.
Here the real reason for the change is that from the SW perspective they
are under the same PCI device and there's no reason to look for a
different one. Maybe rewording it a "Xe2_LPD has south display on the
same PCI device" would be simpler?
Lucas De Marchi
>able to get by so far with just matching PICA behavior on the display
>version rather than on its own version, we can just use display version
>for this as well, at least for now. We may need to revisit this all
>down the road once we have platforms with more possible combinations of
>these components. Of course we really need to rework the SDE handling
>in general (and break its assumption that SDE behavior is tied to PCH on
>modern platforms), but that's work for a future patch series.
>
>I was originally wondering if we could just reuse PCH_MTP here, but it
>looks like there's one place where we setup HPD interrupts that needs
>different handling. So this should be good enough for now, and we can
>revisit the whole SDE design separately down the road.
>
>With the minor commit message fix above,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>
>> PCH entry for it.
>>
>> v2: Match on display IP version rather than on platform (Matt Roper)
>>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>> ---
>> drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
>> drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
>> 2 files changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
>> index dfffdfa50b97..240beafb38ed 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_pch.c
>> +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
>> @@ -222,7 +222,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
>> * South display engine on the same PCI device: just assign the fake
>> * PCH.
>> */
>> - if (IS_DG2(dev_priv)) {
>> + if (DISPLAY_VER(dev_priv) >= 20) {
>> + dev_priv->pch_type = PCH_LNL;
>> + return;
>> + } else if (IS_DG2(dev_priv)) {
>> dev_priv->pch_type = PCH_DG2;
>> return;
>> } else if (IS_DG1(dev_priv)) {
>> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
>> index 32aff5a70d04..1b03ea60a7a8 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_pch.h
>> +++ b/drivers/gpu/drm/i915/soc/intel_pch.h
>> @@ -30,6 +30,7 @@ enum intel_pch {
>> /* Fake PCHs, functionality handled on the same PCI dev */
>> PCH_DG1 = 1024,
>> PCH_DG2,
>> + PCH_LNL,
>> };
>>
>> #define INTEL_PCH_DEVICE_ID_MASK 0xff80
>> @@ -66,6 +67,7 @@ enum intel_pch {
>>
>> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
>> #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
>> +#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
>> #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
>> #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
>> #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
>> --
>> 2.40.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
2023-09-07 20:43 ` Lucas De Marchi
@ 2023-09-08 0:57 ` Matt Roper
2023-09-08 4:07 ` Lucas De Marchi
2023-09-08 5:39 ` Ville Syrjälä
0 siblings, 2 replies; 62+ messages in thread
From: Matt Roper @ 2023-09-08 0:57 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 03:43:59PM -0500, Lucas De Marchi wrote:
> On Thu, Sep 07, 2023 at 10:04:42AM -0700, Matt Roper wrote:
> > On Thu, Sep 07, 2023 at 08:37:35AM -0700, Lucas De Marchi wrote:
> > > From: Gustavo Sousa <gustavo.sousa@intel.com>
> > >
> > > Xe2_LPD has sourth display on the same SOC. As such, define a new fake
> >
> > s/sourth/south/
> >
> > You might also want to drop the word "same" from the description here
> > since NDE and SDE are technically on different dies in this case (NDE is
> > on the compute die, whereas SDE is on the SoC die). To be 100% accurate
> > we'd want to identify SDE behavior via the PICA's GMD_ID (since PICA
> > also lives on the SoC die for this platform). But since we've just been
>
> I'd not re-architect this based on where the PICA lives as it seems very
> easy to change in future.... tying the SDE behavior to the PICA behavior
> because they are on the same die, doesn't seem very future proof.
The point is that tying it to any one thing for every platform is
incorrect; figuring out a) which die is relevant to SDE behavior and b)
how to fingerprint the variant and stepping of that die is very platform
specific. Art specifically suggested using the PICA ID in cases where
the PICA lives on the die that we need to fingerprint but the NDE does
not. But again, that's not a silver bullet that can be used on every
single platform. Nor is using the ISA bus ID like we've done for a long
time. Nor is using the display version. Nor is using just the PCI ID.
There's no single answer here, which is why we need a major rethink of
our strategy at some point in the future. But that overhaul can wait
for a future series; I just want to make sure that the commit messages
here aren't causing further confusion.
>
> Here the real reason for the change is that from the SW perspective they
> are under the same PCI device and there's no reason to look for a
> different one. Maybe rewording it a "Xe2_LPD has south display on the
> same PCI device" would be simpler?
No, that would be even less correct; PCI device isn't really related to
any of this. Obviously at the register level, everything our driver
cares about (NDE, SDE, GT, etc.) is accessed through the same PCI device
(e.g., 00:02.0 on an igpu). Under the hood the various pieces of that
PCI device (NDE, SDE, render GT, media GT, etc.) might be located
together on a single chip, or may be spread across different dies. When
spread across different dies, those dies can be mixed-and-matched in
various ways (and it seems like hardware design is trending toward more
flexibility in mix-and-match).
The register interface to the SDE (i.e., which registers exist and what
bitfields they have inside) hasn't had any meaningful changes in a long
time. And if it does change in the future, the _interface_ changes are
probably more tied to the display IP version than to anything else.
However there's some important SDE handling that the driver needs to do
that may vary based on the identity of the specific die that's
responsible for doing SDE I/O on a given platform. I.e., there may be
I/O-related defects+workarounds that require special SDE programming
when a certain die variant and/or stepping is present. There can also
be differences in how lanes are physically wired up, resulting in pin
mapping changes. In these cases we need to be able to fingerprint the
identity of the specific die handling the I/O (which might be a compute
die, an SoC die, and IOE die, a PCH die, etc.) and make our decisions
accordingly. If the SDE I/O happens on the same die as the north
display functionality, then using the display version might be an
effective way to fingerprint. If the SDE I/O happens on a different die
from the NDE, but on the same die the PICA lives on, the display
architects suggested using the PICA ID in that case. If neither of
those cases are true, then we may need to look at PCI IDs or something.
In the past, the PCH was often where the SDE I/O responsibility was so
we needed a way to identify exactly which PCH variant was present. The
"PCH ID" that we try to match on during driver startup is entirely
unrelated to the SDE; it's just a random bus that we know was always
part of every PCH and always present in the same predictable PCI slot,
so it's handy for identification purposes. The fact that we're still
looking at the ISA bus on MTL today is 100% wrong because most (maybe
all?) MTL platforms don't even have a PCH (so that ISA bus might be on a
different die that we really don't care about at all). For MTL I
believe the NDE and the SDE's I/O are both on the same SoC die, so we
should really just be making our decisions based on IP version and/or
graphics device ID. If I remember correctly, LNL moved the NDE display
to the compute die, but left the PICA on the SoC die. So assuming the
SoC die is still where the I/O happens (I don't have the platform docs
open at the moment), the PICA ID could potentially be used to
fingerprint the die for the purposes of die-specific workarounds. It
might even vary between different SKUs of LNL, MTL, etc. so we really
need to dig into the platform specs to figure out the right course of
action (the graphics bspec doesn't cover that high-level platform
layout).
Matt
>
> Lucas De Marchi
>
> > able to get by so far with just matching PICA behavior on the display
> > version rather than on its own version, we can just use display version
> > for this as well, at least for now. We may need to revisit this all
> > down the road once we have platforms with more possible combinations of
> > these components. Of course we really need to rework the SDE handling
> > in general (and break its assumption that SDE behavior is tied to PCH on
> > modern platforms), but that's work for a future patch series.
> >
> > I was originally wondering if we could just reuse PCH_MTP here, but it
> > looks like there's one place where we setup HPD interrupts that needs
> > different handling. So this should be good enough for now, and we can
> > revisit the whole SDE design separately down the road.
> >
> > With the minor commit message fix above,
> >
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> >
> >
> > > PCH entry for it.
> > >
> > > v2: Match on display IP version rather than on platform (Matt Roper)
> > >
> > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >
> > > ---
> > > drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
> > > drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
> > > 2 files changed, 6 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
> > > index dfffdfa50b97..240beafb38ed 100644
> > > --- a/drivers/gpu/drm/i915/soc/intel_pch.c
> > > +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
> > > @@ -222,7 +222,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
> > > * South display engine on the same PCI device: just assign the fake
> > > * PCH.
> > > */
> > > - if (IS_DG2(dev_priv)) {
> > > + if (DISPLAY_VER(dev_priv) >= 20) {
> > > + dev_priv->pch_type = PCH_LNL;
> > > + return;
> > > + } else if (IS_DG2(dev_priv)) {
> > > dev_priv->pch_type = PCH_DG2;
> > > return;
> > > } else if (IS_DG1(dev_priv)) {
> > > diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
> > > index 32aff5a70d04..1b03ea60a7a8 100644
> > > --- a/drivers/gpu/drm/i915/soc/intel_pch.h
> > > +++ b/drivers/gpu/drm/i915/soc/intel_pch.h
> > > @@ -30,6 +30,7 @@ enum intel_pch {
> > > /* Fake PCHs, functionality handled on the same PCI dev */
> > > PCH_DG1 = 1024,
> > > PCH_DG2,
> > > + PCH_LNL,
> > > };
> > >
> > > #define INTEL_PCH_DEVICE_ID_MASK 0xff80
> > > @@ -66,6 +67,7 @@ enum intel_pch {
> > >
> > > #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> > > #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
> > > +#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
> > > #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
> > > #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
> > > #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
> > > --
> > > 2.40.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
2023-09-08 0:57 ` Matt Roper
@ 2023-09-08 4:07 ` Lucas De Marchi
2023-09-08 5:39 ` Ville Syrjälä
1 sibling, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-08 4:07 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 05:57:19PM -0700, Matt Roper wrote:
>On Thu, Sep 07, 2023 at 03:43:59PM -0500, Lucas De Marchi wrote:
>> On Thu, Sep 07, 2023 at 10:04:42AM -0700, Matt Roper wrote:
>> > On Thu, Sep 07, 2023 at 08:37:35AM -0700, Lucas De Marchi wrote:
>> > > From: Gustavo Sousa <gustavo.sousa@intel.com>
>> > >
>> > > Xe2_LPD has sourth display on the same SOC. As such, define a new fake
>> >
>> > s/sourth/south/
>> >
>> > You might also want to drop the word "same" from the description here
>> > since NDE and SDE are technically on different dies in this case (NDE is
>> > on the compute die, whereas SDE is on the SoC die). To be 100% accurate
>> > we'd want to identify SDE behavior via the PICA's GMD_ID (since PICA
>> > also lives on the SoC die for this platform). But since we've just been
>>
>> I'd not re-architect this based on where the PICA lives as it seems very
>> easy to change in future.... tying the SDE behavior to the PICA behavior
>> because they are on the same die, doesn't seem very future proof.
>
>The point is that tying it to any one thing for every platform is
>incorrect; figuring out a) which die is relevant to SDE behavior and b)
>how to fingerprint the variant and stepping of that die is very platform
>specific. Art specifically suggested using the PICA ID in cases where
>the PICA lives on the die that we need to fingerprint but the NDE does
>not. But again, that's not a silver bullet that can be used on every
>single platform. Nor is using the ISA bus ID like we've done for a long
>time. Nor is using the display version. Nor is using just the PCI ID.
>There's no single answer here, which is why we need a major rethink of
this contradicts what you said above that "To be 100% accurate we'd want
to identify SDE behavior via the PICA's GMD_ID". That is not true because
if what you are using to fingerprint SDE's behavior change from platform
to platform, then you can't decide anymore on what to use to fingerprint
it. At that point we'd better request a SDE id to be added.
>our strategy at some point in the future. But that overhaul can wait
>for a future series; I just want to make sure that the commit messages
>here aren't causing further confusion.
>
>>
>> Here the real reason for the change is that from the SW perspective they
>> are under the same PCI device and there's no reason to look for a
>> different one. Maybe rewording it a "Xe2_LPD has south display on the
>> same PCI device" would be simpler?
>
>No, that would be even less correct; PCI device isn't really related to
>any of this. Obviously at the register level, everything our driver
>cares about (NDE, SDE, GT, etc.) is accessed through the same PCI device
>(e.g., 00:02.0 on an igpu). Under the hood the various pieces of that
>PCI device (NDE, SDE, render GT, media GT, etc.) might be located
>together on a single chip, or may be spread across different dies. When
>spread across different dies, those dies can be mixed-and-matched in
>various ways (and it seems like hardware design is trending toward more
>flexibility in mix-and-match).
>
>The register interface to the SDE (i.e., which registers exist and what
>bitfields they have inside) hasn't had any meaningful changes in a long
>time. And if it does change in the future, the _interface_ changes are
>probably more tied to the display IP version than to anything else.
>However there's some important SDE handling that the driver needs to do
>that may vary based on the identity of the specific die that's
>responsible for doing SDE I/O on a given platform. I.e., there may be
which only happens to be on the same die where PICA is. *On LNL*.
>I/O-related defects+workarounds that require special SDE programming
>when a certain die variant and/or stepping is present. There can also
>be differences in how lanes are physically wired up, resulting in pin
>mapping changes. In these cases we need to be able to fingerprint the
>identity of the specific die handling the I/O (which might be a compute
>die, an SoC die, and IOE die, a PCH die, etc.) and make our decisions
>accordingly. If the SDE I/O happens on the same die as the north
>display functionality, then using the display version might be an
>effective way to fingerprint. If the SDE I/O happens on a different die
>from the NDE, but on the same die the PICA lives on, the display
>architects suggested using the PICA ID in that case. If neither of
>those cases are true, then we may need to look at PCI IDs or something.
I think that's a different read of what was discussed. My read was more
in the lines of "if you really need that, you can use the PICA ID". With
no guarantee of this being future-proof. That's why we decided it made
no sense to change now.
>
>In the past, the PCH was often where the SDE I/O responsibility was so
>we needed a way to identify exactly which PCH variant was present. The
>"PCH ID" that we try to match on during driver startup is entirely
>unrelated to the SDE; it's just a random bus that we know was always
>part of every PCH and always present in the same predictable PCI slot,
>so it's handy for identification purposes. The fact that we're still
>looking at the ISA bus on MTL today is 100% wrong because most (maybe
I agree here: MTL shouldn't be using that just like LNL is not.
>all?) MTL platforms don't even have a PCH (so that ISA bus might be on a
>different die that we really don't care about at all). For MTL I
>believe the NDE and the SDE's I/O are both on the same SoC die, so we
>should really just be making our decisions based on IP version and/or
>graphics device ID. If I remember correctly, LNL moved the NDE display
>to the compute die, but left the PICA on the SoC die. So assuming the
>SoC die is still where the I/O happens (I don't have the platform docs
>open at the moment), the PICA ID could potentially be used to
>fingerprint the die for the purposes of die-specific workarounds. It
>might even vary between different SKUs of LNL, MTL, etc. so we really
>need to dig into the platform specs to figure out the right course of
>action (the graphics bspec doesn't cover that high-level platform
>layout).
That's where we disagree... you seem to prefer it more fine grained
while I'm perfectly happy with keeping it simpler and coarse until
the day we need it. For LNL we have Panel Control, GMBUS DDC, HPD, SDE
interrupts, GPSB, TCSS, PHYs and PICA on the SoC die, but those
IO interfaces could very well be on a separate die
I think we have to agree to disagree here and move on. What about the
following?
drm/i915/xe2lpd: Add fake PCH
Xe2_LPD doesn't have south display engine on a PCH, it's actually
on the SoC die (while north display engine is on compute die). As
such it makes no sense to go through the PCI devices looking for
an ISA bridge.
For the places we currently use a PCH check, it's enough for
now to just check the north display version. Use that to define
a fake PCH to be used across the driver.
Lucas De Marchi
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
2023-09-08 0:57 ` Matt Roper
2023-09-08 4:07 ` Lucas De Marchi
@ 2023-09-08 5:39 ` Ville Syrjälä
2023-09-08 5:51 ` Lucas De Marchi
1 sibling, 1 reply; 62+ messages in thread
From: Ville Syrjälä @ 2023-09-08 5:39 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi, intel-xe
On Thu, Sep 07, 2023 at 05:57:19PM -0700, Matt Roper wrote:
> On Thu, Sep 07, 2023 at 03:43:59PM -0500, Lucas De Marchi wrote:
> > On Thu, Sep 07, 2023 at 10:04:42AM -0700, Matt Roper wrote:
> > > On Thu, Sep 07, 2023 at 08:37:35AM -0700, Lucas De Marchi wrote:
> > > > From: Gustavo Sousa <gustavo.sousa@intel.com>
> > > >
> > > > Xe2_LPD has sourth display on the same SOC. As such, define a new fake
> > >
> > > s/sourth/south/
> > >
> > > You might also want to drop the word "same" from the description here
> > > since NDE and SDE are technically on different dies in this case (NDE is
> > > on the compute die, whereas SDE is on the SoC die). To be 100% accurate
> > > we'd want to identify SDE behavior via the PICA's GMD_ID (since PICA
> > > also lives on the SoC die for this platform). But since we've just been
> >
> > I'd not re-architect this based on where the PICA lives as it seems very
> > easy to change in future.... tying the SDE behavior to the PICA behavior
> > because they are on the same die, doesn't seem very future proof.
>
> The point is that tying it to any one thing for every platform is
> incorrect; figuring out a) which die is relevant to SDE behavior and b)
> how to fingerprint the variant and stepping of that die is very platform
> specific. Art specifically suggested using the PICA ID in cases where
> the PICA lives on the die that we need to fingerprint but the NDE does
> not. But again, that's not a silver bullet that can be used on every
> single platform. Nor is using the ISA bus ID like we've done for a long
> time. Nor is using the display version. Nor is using just the PCI ID.
> There's no single answer here, which is why we need a major rethink of
> our strategy at some point in the future. But that overhaul can wait
> for a future series; I just want to make sure that the commit messages
> here aren't causing further confusion.
>
> >
> > Here the real reason for the change is that from the SW perspective they
> > are under the same PCI device and there's no reason to look for a
> > different one. Maybe rewording it a "Xe2_LPD has south display on the
> > same PCI device" would be simpler?
>
> No, that would be even less correct; PCI device isn't really related to
> any of this. Obviously at the register level, everything our driver
> cares about (NDE, SDE, GT, etc.) is accessed through the same PCI device
> (e.g., 00:02.0 on an igpu). Under the hood the various pieces of that
> PCI device (NDE, SDE, render GT, media GT, etc.) might be located
> together on a single chip, or may be spread across different dies. When
> spread across different dies, those dies can be mixed-and-matched in
> various ways (and it seems like hardware design is trending toward more
> flexibility in mix-and-match).
>
> The register interface to the SDE (i.e., which registers exist and what
> bitfields they have inside) hasn't had any meaningful changes in a long
> time. And if it does change in the future, the _interface_ changes are
> probably more tied to the display IP version than to anything else.
> However there's some important SDE handling that the driver needs to do
> that may vary based on the identity of the specific die that's
> responsible for doing SDE I/O on a given platform. I.e., there may be
> I/O-related defects+workarounds that require special SDE programming
> when a certain die variant and/or stepping is present. There can also
> be differences in how lanes are physically wired up, resulting in pin
> mapping changes. In these cases we need to be able to fingerprint the
> identity of the specific die handling the I/O (which might be a compute
> die, an SoC die, and IOE die, a PCH die, etc.) and make our decisions
> accordingly. If the SDE I/O happens on the same die as the north
> display functionality, then using the display version might be an
> effective way to fingerprint. If the SDE I/O happens on a different die
> from the NDE, but on the same die the PICA lives on, the display
> architects suggested using the PICA ID in that case. If neither of
> those cases are true, then we may need to look at PCI IDs or something.
>
> In the past, the PCH was often where the SDE I/O responsibility was so
> we needed a way to identify exactly which PCH variant was present. The
> "PCH ID" that we try to match on during driver startup is entirely
> unrelated to the SDE; it's just a random bus that we know was always
> part of every PCH and always present in the same predictable PCI slot,
> so it's handy for identification purposes. The fact that we're still
> looking at the ISA bus on MTL today is 100% wrong because most (maybe
> all?) MTL platforms don't even have a PCH (so that ISA bus might be on a
> different die that we really don't care about at all). For MTL I
> believe the NDE and the SDE's I/O are both on the same SoC die, so we
> should really just be making our decisions based on IP version and/or
> graphics device ID.
I think ideally SDE would have its own IP version/etc. we could
use to identify it.
I'm not really sure why we even started down this "fake PCH" route
since we never added that for BXT/GLK either, and they managed just
fine without it despite keeping a bunch of the logic in the SDE
register range (instead of moving it back to the NDE range).
> If I remember correctly, LNL moved the NDE display
> to the compute die, but left the PICA on the SoC die. So assuming the
> SoC die is still where the I/O happens (I don't have the platform docs
> open at the moment), the PICA ID could potentially be used to
> fingerprint the die for the purposes of die-specific workarounds. It
> might even vary between different SKUs of LNL, MTL, etc. so we really
> need to dig into the platform specs to figure out the right course of
> action (the graphics bspec doesn't cover that high-level platform
> layout).
>
>
> Matt
>
> >
> > Lucas De Marchi
> >
> > > able to get by so far with just matching PICA behavior on the display
> > > version rather than on its own version, we can just use display version
> > > for this as well, at least for now. We may need to revisit this all
> > > down the road once we have platforms with more possible combinations of
> > > these components. Of course we really need to rework the SDE handling
> > > in general (and break its assumption that SDE behavior is tied to PCH on
> > > modern platforms), but that's work for a future patch series.
> > >
> > > I was originally wondering if we could just reuse PCH_MTP here, but it
> > > looks like there's one place where we setup HPD interrupts that needs
> > > different handling. So this should be good enough for now, and we can
> > > revisit the whole SDE design separately down the road.
> > >
> > > With the minor commit message fix above,
> > >
> > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > >
> > >
> > > > PCH entry for it.
> > > >
> > > > v2: Match on display IP version rather than on platform (Matt Roper)
> > > >
> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > >
> > > > ---
> > > > drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
> > > > drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
> > > > 2 files changed, 6 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
> > > > index dfffdfa50b97..240beafb38ed 100644
> > > > --- a/drivers/gpu/drm/i915/soc/intel_pch.c
> > > > +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
> > > > @@ -222,7 +222,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
> > > > * South display engine on the same PCI device: just assign the fake
> > > > * PCH.
> > > > */
> > > > - if (IS_DG2(dev_priv)) {
> > > > + if (DISPLAY_VER(dev_priv) >= 20) {
> > > > + dev_priv->pch_type = PCH_LNL;
> > > > + return;
> > > > + } else if (IS_DG2(dev_priv)) {
> > > > dev_priv->pch_type = PCH_DG2;
> > > > return;
> > > > } else if (IS_DG1(dev_priv)) {
> > > > diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
> > > > index 32aff5a70d04..1b03ea60a7a8 100644
> > > > --- a/drivers/gpu/drm/i915/soc/intel_pch.h
> > > > +++ b/drivers/gpu/drm/i915/soc/intel_pch.h
> > > > @@ -30,6 +30,7 @@ enum intel_pch {
> > > > /* Fake PCHs, functionality handled on the same PCI dev */
> > > > PCH_DG1 = 1024,
> > > > PCH_DG2,
> > > > + PCH_LNL,
> > > > };
> > > >
> > > > #define INTEL_PCH_DEVICE_ID_MASK 0xff80
> > > > @@ -66,6 +67,7 @@ enum intel_pch {
> > > >
> > > > #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> > > > #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
> > > > +#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
> > > > #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
> > > > #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
> > > > #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
> > > > --
> > > > 2.40.1
> > > >
> > >
> > > --
> > > Matt Roper
> > > Graphics Software Engineer
> > > Linux GPU Platform Enablement
> > > Intel Corporation
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
2023-09-08 5:39 ` Ville Syrjälä
@ 2023-09-08 5:51 ` Lucas De Marchi
2023-09-08 5:56 ` Ville Syrjälä
0 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-08 5:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Matt Roper, intel-xe
On Fri, Sep 08, 2023 at 08:39:48AM +0300, Ville Syrjälä wrote:
>On Thu, Sep 07, 2023 at 05:57:19PM -0700, Matt Roper wrote:
>> On Thu, Sep 07, 2023 at 03:43:59PM -0500, Lucas De Marchi wrote:
>> > On Thu, Sep 07, 2023 at 10:04:42AM -0700, Matt Roper wrote:
>> > > On Thu, Sep 07, 2023 at 08:37:35AM -0700, Lucas De Marchi wrote:
>> > > > From: Gustavo Sousa <gustavo.sousa@intel.com>
>> > > >
>> > > > Xe2_LPD has sourth display on the same SOC. As such, define a new fake
>> > >
>> > > s/sourth/south/
>> > >
>> > > You might also want to drop the word "same" from the description here
>> > > since NDE and SDE are technically on different dies in this case (NDE is
>> > > on the compute die, whereas SDE is on the SoC die). To be 100% accurate
>> > > we'd want to identify SDE behavior via the PICA's GMD_ID (since PICA
>> > > also lives on the SoC die for this platform). But since we've just been
>> >
>> > I'd not re-architect this based on where the PICA lives as it seems very
>> > easy to change in future.... tying the SDE behavior to the PICA behavior
>> > because they are on the same die, doesn't seem very future proof.
>>
>> The point is that tying it to any one thing for every platform is
>> incorrect; figuring out a) which die is relevant to SDE behavior and b)
>> how to fingerprint the variant and stepping of that die is very platform
>> specific. Art specifically suggested using the PICA ID in cases where
>> the PICA lives on the die that we need to fingerprint but the NDE does
>> not. But again, that's not a silver bullet that can be used on every
>> single platform. Nor is using the ISA bus ID like we've done for a long
>> time. Nor is using the display version. Nor is using just the PCI ID.
>> There's no single answer here, which is why we need a major rethink of
>> our strategy at some point in the future. But that overhaul can wait
>> for a future series; I just want to make sure that the commit messages
>> here aren't causing further confusion.
>>
>> >
>> > Here the real reason for the change is that from the SW perspective they
>> > are under the same PCI device and there's no reason to look for a
>> > different one. Maybe rewording it a "Xe2_LPD has south display on the
>> > same PCI device" would be simpler?
>>
>> No, that would be even less correct; PCI device isn't really related to
>> any of this. Obviously at the register level, everything our driver
>> cares about (NDE, SDE, GT, etc.) is accessed through the same PCI device
>> (e.g., 00:02.0 on an igpu). Under the hood the various pieces of that
>> PCI device (NDE, SDE, render GT, media GT, etc.) might be located
>> together on a single chip, or may be spread across different dies. When
>> spread across different dies, those dies can be mixed-and-matched in
>> various ways (and it seems like hardware design is trending toward more
>> flexibility in mix-and-match).
>>
>> The register interface to the SDE (i.e., which registers exist and what
>> bitfields they have inside) hasn't had any meaningful changes in a long
>> time. And if it does change in the future, the _interface_ changes are
>> probably more tied to the display IP version than to anything else.
>> However there's some important SDE handling that the driver needs to do
>> that may vary based on the identity of the specific die that's
>> responsible for doing SDE I/O on a given platform. I.e., there may be
>> I/O-related defects+workarounds that require special SDE programming
>> when a certain die variant and/or stepping is present. There can also
>> be differences in how lanes are physically wired up, resulting in pin
>> mapping changes. In these cases we need to be able to fingerprint the
>> identity of the specific die handling the I/O (which might be a compute
>> die, an SoC die, and IOE die, a PCH die, etc.) and make our decisions
>> accordingly. If the SDE I/O happens on the same die as the north
>> display functionality, then using the display version might be an
>> effective way to fingerprint. If the SDE I/O happens on a different die
>> from the NDE, but on the same die the PICA lives on, the display
>> architects suggested using the PICA ID in that case. If neither of
>> those cases are true, then we may need to look at PCI IDs or something.
>>
>> In the past, the PCH was often where the SDE I/O responsibility was so
>> we needed a way to identify exactly which PCH variant was present. The
>> "PCH ID" that we try to match on during driver startup is entirely
>> unrelated to the SDE; it's just a random bus that we know was always
>> part of every PCH and always present in the same predictable PCI slot,
>> so it's handy for identification purposes. The fact that we're still
>> looking at the ISA bus on MTL today is 100% wrong because most (maybe
>> all?) MTL platforms don't even have a PCH (so that ISA bus might be on a
>> different die that we really don't care about at all). For MTL I
>> believe the NDE and the SDE's I/O are both on the same SoC die, so we
>> should really just be making our decisions based on IP version and/or
>> graphics device ID.
>
>I think ideally SDE would have its own IP version/etc. we could
>use to identify it.
maybe some future platform
>
>I'm not really sure why we even started down this "fake PCH" route
>since we never added that for BXT/GLK either, and they managed just
it was originally done for the discrete cards, I think DG1, and got
extended to the next ones. Differently than BXT/GLK it doesn't work
at all to try finding the ISA bridge as that would end up matching the
wrong one.
Lucas De Marchi
>fine without it despite keeping a bunch of the logic in the SDE
>register range (instead of moving it back to the NDE range).
>
>> If I remember correctly, LNL moved the NDE display
>> to the compute die, but left the PICA on the SoC die. So assuming the
>> SoC die is still where the I/O happens (I don't have the platform docs
>> open at the moment), the PICA ID could potentially be used to
>> fingerprint the die for the purposes of die-specific workarounds. It
>> might even vary between different SKUs of LNL, MTL, etc. so we really
>> need to dig into the platform specs to figure out the right course of
>> action (the graphics bspec doesn't cover that high-level platform
>> layout).
>>
>>
>> Matt
>>
>> >
>> > Lucas De Marchi
>> >
>> > > able to get by so far with just matching PICA behavior on the display
>> > > version rather than on its own version, we can just use display version
>> > > for this as well, at least for now. We may need to revisit this all
>> > > down the road once we have platforms with more possible combinations of
>> > > these components. Of course we really need to rework the SDE handling
>> > > in general (and break its assumption that SDE behavior is tied to PCH on
>> > > modern platforms), but that's work for a future patch series.
>> > >
>> > > I was originally wondering if we could just reuse PCH_MTP here, but it
>> > > looks like there's one place where we setup HPD interrupts that needs
>> > > different handling. So this should be good enough for now, and we can
>> > > revisit the whole SDE design separately down the road.
>> > >
>> > > With the minor commit message fix above,
>> > >
>> > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>> > >
>> > >
>> > > > PCH entry for it.
>> > > >
>> > > > v2: Match on display IP version rather than on platform (Matt Roper)
>> > > >
>> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > >
>> > > > ---
>> > > > drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
>> > > > drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
>> > > > 2 files changed, 6 insertions(+), 1 deletion(-)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
>> > > > index dfffdfa50b97..240beafb38ed 100644
>> > > > --- a/drivers/gpu/drm/i915/soc/intel_pch.c
>> > > > +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
>> > > > @@ -222,7 +222,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
>> > > > * South display engine on the same PCI device: just assign the fake
>> > > > * PCH.
>> > > > */
>> > > > - if (IS_DG2(dev_priv)) {
>> > > > + if (DISPLAY_VER(dev_priv) >= 20) {
>> > > > + dev_priv->pch_type = PCH_LNL;
>> > > > + return;
>> > > > + } else if (IS_DG2(dev_priv)) {
>> > > > dev_priv->pch_type = PCH_DG2;
>> > > > return;
>> > > > } else if (IS_DG1(dev_priv)) {
>> > > > diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
>> > > > index 32aff5a70d04..1b03ea60a7a8 100644
>> > > > --- a/drivers/gpu/drm/i915/soc/intel_pch.h
>> > > > +++ b/drivers/gpu/drm/i915/soc/intel_pch.h
>> > > > @@ -30,6 +30,7 @@ enum intel_pch {
>> > > > /* Fake PCHs, functionality handled on the same PCI dev */
>> > > > PCH_DG1 = 1024,
>> > > > PCH_DG2,
>> > > > + PCH_LNL,
>> > > > };
>> > > >
>> > > > #define INTEL_PCH_DEVICE_ID_MASK 0xff80
>> > > > @@ -66,6 +67,7 @@ enum intel_pch {
>> > > >
>> > > > #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
>> > > > #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
>> > > > +#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
>> > > > #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
>> > > > #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
>> > > > #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
>> > > > --
>> > > > 2.40.1
>> > > >
>> > >
>> > > --
>> > > Matt Roper
>> > > Graphics Software Engineer
>> > > Linux GPU Platform Enablement
>> > > Intel Corporation
>>
>> --
>> Matt Roper
>> Graphics Software Engineer
>> Linux GPU Platform Enablement
>> Intel Corporation
>
>--
>Ville Syrjälä
>Intel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
2023-09-08 5:51 ` Lucas De Marchi
@ 2023-09-08 5:56 ` Ville Syrjälä
2023-09-08 6:03 ` [Intel-gfx] [Intel-xe] " Ville Syrjälä
0 siblings, 1 reply; 62+ messages in thread
From: Ville Syrjälä @ 2023-09-08 5:56 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Matt Roper, intel-xe
On Fri, Sep 08, 2023 at 12:51:09AM -0500, Lucas De Marchi wrote:
> On Fri, Sep 08, 2023 at 08:39:48AM +0300, Ville Syrjälä wrote:
> >On Thu, Sep 07, 2023 at 05:57:19PM -0700, Matt Roper wrote:
> >> On Thu, Sep 07, 2023 at 03:43:59PM -0500, Lucas De Marchi wrote:
> >> > On Thu, Sep 07, 2023 at 10:04:42AM -0700, Matt Roper wrote:
> >> > > On Thu, Sep 07, 2023 at 08:37:35AM -0700, Lucas De Marchi wrote:
> >> > > > From: Gustavo Sousa <gustavo.sousa@intel.com>
> >> > > >
> >> > > > Xe2_LPD has sourth display on the same SOC. As such, define a new fake
> >> > >
> >> > > s/sourth/south/
> >> > >
> >> > > You might also want to drop the word "same" from the description here
> >> > > since NDE and SDE are technically on different dies in this case (NDE is
> >> > > on the compute die, whereas SDE is on the SoC die). To be 100% accurate
> >> > > we'd want to identify SDE behavior via the PICA's GMD_ID (since PICA
> >> > > also lives on the SoC die for this platform). But since we've just been
> >> >
> >> > I'd not re-architect this based on where the PICA lives as it seems very
> >> > easy to change in future.... tying the SDE behavior to the PICA behavior
> >> > because they are on the same die, doesn't seem very future proof.
> >>
> >> The point is that tying it to any one thing for every platform is
> >> incorrect; figuring out a) which die is relevant to SDE behavior and b)
> >> how to fingerprint the variant and stepping of that die is very platform
> >> specific. Art specifically suggested using the PICA ID in cases where
> >> the PICA lives on the die that we need to fingerprint but the NDE does
> >> not. But again, that's not a silver bullet that can be used on every
> >> single platform. Nor is using the ISA bus ID like we've done for a long
> >> time. Nor is using the display version. Nor is using just the PCI ID.
> >> There's no single answer here, which is why we need a major rethink of
> >> our strategy at some point in the future. But that overhaul can wait
> >> for a future series; I just want to make sure that the commit messages
> >> here aren't causing further confusion.
> >>
> >> >
> >> > Here the real reason for the change is that from the SW perspective they
> >> > are under the same PCI device and there's no reason to look for a
> >> > different one. Maybe rewording it a "Xe2_LPD has south display on the
> >> > same PCI device" would be simpler?
> >>
> >> No, that would be even less correct; PCI device isn't really related to
> >> any of this. Obviously at the register level, everything our driver
> >> cares about (NDE, SDE, GT, etc.) is accessed through the same PCI device
> >> (e.g., 00:02.0 on an igpu). Under the hood the various pieces of that
> >> PCI device (NDE, SDE, render GT, media GT, etc.) might be located
> >> together on a single chip, or may be spread across different dies. When
> >> spread across different dies, those dies can be mixed-and-matched in
> >> various ways (and it seems like hardware design is trending toward more
> >> flexibility in mix-and-match).
> >>
> >> The register interface to the SDE (i.e., which registers exist and what
> >> bitfields they have inside) hasn't had any meaningful changes in a long
> >> time. And if it does change in the future, the _interface_ changes are
> >> probably more tied to the display IP version than to anything else.
> >> However there's some important SDE handling that the driver needs to do
> >> that may vary based on the identity of the specific die that's
> >> responsible for doing SDE I/O on a given platform. I.e., there may be
> >> I/O-related defects+workarounds that require special SDE programming
> >> when a certain die variant and/or stepping is present. There can also
> >> be differences in how lanes are physically wired up, resulting in pin
> >> mapping changes. In these cases we need to be able to fingerprint the
> >> identity of the specific die handling the I/O (which might be a compute
> >> die, an SoC die, and IOE die, a PCH die, etc.) and make our decisions
> >> accordingly. If the SDE I/O happens on the same die as the north
> >> display functionality, then using the display version might be an
> >> effective way to fingerprint. If the SDE I/O happens on a different die
> >> from the NDE, but on the same die the PICA lives on, the display
> >> architects suggested using the PICA ID in that case. If neither of
> >> those cases are true, then we may need to look at PCI IDs or something.
> >>
> >> In the past, the PCH was often where the SDE I/O responsibility was so
> >> we needed a way to identify exactly which PCH variant was present. The
> >> "PCH ID" that we try to match on during driver startup is entirely
> >> unrelated to the SDE; it's just a random bus that we know was always
> >> part of every PCH and always present in the same predictable PCI slot,
> >> so it's handy for identification purposes. The fact that we're still
> >> looking at the ISA bus on MTL today is 100% wrong because most (maybe
> >> all?) MTL platforms don't even have a PCH (so that ISA bus might be on a
> >> different die that we really don't care about at all). For MTL I
> >> believe the NDE and the SDE's I/O are both on the same SoC die, so we
> >> should really just be making our decisions based on IP version and/or
> >> graphics device ID.
> >
> >I think ideally SDE would have its own IP version/etc. we could
> >use to identify it.
>
> maybe some future platform
>
> >
> >I'm not really sure why we even started down this "fake PCH" route
> >since we never added that for BXT/GLK either, and they managed just
>
> it was originally done for the discrete cards, I think DG1, and got
> extended to the next ones. Differently than BXT/GLK it doesn't work
> at all to try finding the ISA bridge as that would end up matching the
> wrong one.
BXT/GLK don't look for the ISA bridge either. Well, they do, but
they won't find a matching one and thus we're left with PCH_NONE.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Intel-gfx] [Intel-xe] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
2023-09-08 5:56 ` Ville Syrjälä
@ 2023-09-08 6:03 ` Ville Syrjälä
2023-09-08 13:13 ` Lucas De Marchi
0 siblings, 1 reply; 62+ messages in thread
From: Ville Syrjälä @ 2023-09-08 6:03 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Matt Roper, intel-xe
On Fri, Sep 08, 2023 at 08:56:53AM +0300, Ville Syrjälä wrote:
> On Fri, Sep 08, 2023 at 12:51:09AM -0500, Lucas De Marchi wrote:
> > On Fri, Sep 08, 2023 at 08:39:48AM +0300, Ville Syrjälä wrote:
> > >On Thu, Sep 07, 2023 at 05:57:19PM -0700, Matt Roper wrote:
> > >> On Thu, Sep 07, 2023 at 03:43:59PM -0500, Lucas De Marchi wrote:
> > >> > On Thu, Sep 07, 2023 at 10:04:42AM -0700, Matt Roper wrote:
> > >> > > On Thu, Sep 07, 2023 at 08:37:35AM -0700, Lucas De Marchi wrote:
> > >> > > > From: Gustavo Sousa <gustavo.sousa@intel.com>
> > >> > > >
> > >> > > > Xe2_LPD has sourth display on the same SOC. As such, define a new fake
> > >> > >
> > >> > > s/sourth/south/
> > >> > >
> > >> > > You might also want to drop the word "same" from the description here
> > >> > > since NDE and SDE are technically on different dies in this case (NDE is
> > >> > > on the compute die, whereas SDE is on the SoC die). To be 100% accurate
> > >> > > we'd want to identify SDE behavior via the PICA's GMD_ID (since PICA
> > >> > > also lives on the SoC die for this platform). But since we've just been
> > >> >
> > >> > I'd not re-architect this based on where the PICA lives as it seems very
> > >> > easy to change in future.... tying the SDE behavior to the PICA behavior
> > >> > because they are on the same die, doesn't seem very future proof.
> > >>
> > >> The point is that tying it to any one thing for every platform is
> > >> incorrect; figuring out a) which die is relevant to SDE behavior and b)
> > >> how to fingerprint the variant and stepping of that die is very platform
> > >> specific. Art specifically suggested using the PICA ID in cases where
> > >> the PICA lives on the die that we need to fingerprint but the NDE does
> > >> not. But again, that's not a silver bullet that can be used on every
> > >> single platform. Nor is using the ISA bus ID like we've done for a long
> > >> time. Nor is using the display version. Nor is using just the PCI ID.
> > >> There's no single answer here, which is why we need a major rethink of
> > >> our strategy at some point in the future. But that overhaul can wait
> > >> for a future series; I just want to make sure that the commit messages
> > >> here aren't causing further confusion.
> > >>
> > >> >
> > >> > Here the real reason for the change is that from the SW perspective they
> > >> > are under the same PCI device and there's no reason to look for a
> > >> > different one. Maybe rewording it a "Xe2_LPD has south display on the
> > >> > same PCI device" would be simpler?
> > >>
> > >> No, that would be even less correct; PCI device isn't really related to
> > >> any of this. Obviously at the register level, everything our driver
> > >> cares about (NDE, SDE, GT, etc.) is accessed through the same PCI device
> > >> (e.g., 00:02.0 on an igpu). Under the hood the various pieces of that
> > >> PCI device (NDE, SDE, render GT, media GT, etc.) might be located
> > >> together on a single chip, or may be spread across different dies. When
> > >> spread across different dies, those dies can be mixed-and-matched in
> > >> various ways (and it seems like hardware design is trending toward more
> > >> flexibility in mix-and-match).
> > >>
> > >> The register interface to the SDE (i.e., which registers exist and what
> > >> bitfields they have inside) hasn't had any meaningful changes in a long
> > >> time. And if it does change in the future, the _interface_ changes are
> > >> probably more tied to the display IP version than to anything else.
> > >> However there's some important SDE handling that the driver needs to do
> > >> that may vary based on the identity of the specific die that's
> > >> responsible for doing SDE I/O on a given platform. I.e., there may be
> > >> I/O-related defects+workarounds that require special SDE programming
> > >> when a certain die variant and/or stepping is present. There can also
> > >> be differences in how lanes are physically wired up, resulting in pin
> > >> mapping changes. In these cases we need to be able to fingerprint the
> > >> identity of the specific die handling the I/O (which might be a compute
> > >> die, an SoC die, and IOE die, a PCH die, etc.) and make our decisions
> > >> accordingly. If the SDE I/O happens on the same die as the north
> > >> display functionality, then using the display version might be an
> > >> effective way to fingerprint. If the SDE I/O happens on a different die
> > >> from the NDE, but on the same die the PICA lives on, the display
> > >> architects suggested using the PICA ID in that case. If neither of
> > >> those cases are true, then we may need to look at PCI IDs or something.
> > >>
> > >> In the past, the PCH was often where the SDE I/O responsibility was so
> > >> we needed a way to identify exactly which PCH variant was present. The
> > >> "PCH ID" that we try to match on during driver startup is entirely
> > >> unrelated to the SDE; it's just a random bus that we know was always
> > >> part of every PCH and always present in the same predictable PCI slot,
> > >> so it's handy for identification purposes. The fact that we're still
> > >> looking at the ISA bus on MTL today is 100% wrong because most (maybe
> > >> all?) MTL platforms don't even have a PCH (so that ISA bus might be on a
> > >> different die that we really don't care about at all). For MTL I
> > >> believe the NDE and the SDE's I/O are both on the same SoC die, so we
> > >> should really just be making our decisions based on IP version and/or
> > >> graphics device ID.
> > >
> > >I think ideally SDE would have its own IP version/etc. we could
> > >use to identify it.
> >
> > maybe some future platform
> >
> > >
> > >I'm not really sure why we even started down this "fake PCH" route
> > >since we never added that for BXT/GLK either, and they managed just
> >
> > it was originally done for the discrete cards, I think DG1, and got
> > extended to the next ones. Differently than BXT/GLK it doesn't work
> > at all to try finding the ISA bridge as that would end up matching the
> > wrong one.
>
> BXT/GLK don't look for the ISA bridge either. Well, they do, but
> they won't find a matching one and thus we're left with PCH_NONE.
I guess we can also blame bspec for this mess a bit since for
BXT/GLK it actually documents the SDE registers in the north
display section, whereas everything else that has SDE registers
documents them in the south display section.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Intel-gfx] [Intel-xe] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
2023-09-08 6:03 ` [Intel-gfx] [Intel-xe] " Ville Syrjälä
@ 2023-09-08 13:13 ` Lucas De Marchi
0 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-08 13:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Matt Roper, intel-xe
On Fri, Sep 08, 2023 at 09:03:40AM +0300, Ville Syrjälä wrote:
>On Fri, Sep 08, 2023 at 08:56:53AM +0300, Ville Syrjälä wrote:
>> On Fri, Sep 08, 2023 at 12:51:09AM -0500, Lucas De Marchi wrote:
>> > On Fri, Sep 08, 2023 at 08:39:48AM +0300, Ville Syrjälä wrote:
>> > >On Thu, Sep 07, 2023 at 05:57:19PM -0700, Matt Roper wrote:
>> > >> On Thu, Sep 07, 2023 at 03:43:59PM -0500, Lucas De Marchi wrote:
>> > >> > On Thu, Sep 07, 2023 at 10:04:42AM -0700, Matt Roper wrote:
>> > >> > > On Thu, Sep 07, 2023 at 08:37:35AM -0700, Lucas De Marchi wrote:
>> > >> > > > From: Gustavo Sousa <gustavo.sousa@intel.com>
>> > >> > > >
>> > >> > > > Xe2_LPD has sourth display on the same SOC. As such, define a new fake
>> > >> > >
>> > >> > > s/sourth/south/
>> > >> > >
>> > >> > > You might also want to drop the word "same" from the description here
>> > >> > > since NDE and SDE are technically on different dies in this case (NDE is
>> > >> > > on the compute die, whereas SDE is on the SoC die). To be 100% accurate
>> > >> > > we'd want to identify SDE behavior via the PICA's GMD_ID (since PICA
>> > >> > > also lives on the SoC die for this platform). But since we've just been
>> > >> >
>> > >> > I'd not re-architect this based on where the PICA lives as it seems very
>> > >> > easy to change in future.... tying the SDE behavior to the PICA behavior
>> > >> > because they are on the same die, doesn't seem very future proof.
>> > >>
>> > >> The point is that tying it to any one thing for every platform is
>> > >> incorrect; figuring out a) which die is relevant to SDE behavior and b)
>> > >> how to fingerprint the variant and stepping of that die is very platform
>> > >> specific. Art specifically suggested using the PICA ID in cases where
>> > >> the PICA lives on the die that we need to fingerprint but the NDE does
>> > >> not. But again, that's not a silver bullet that can be used on every
>> > >> single platform. Nor is using the ISA bus ID like we've done for a long
>> > >> time. Nor is using the display version. Nor is using just the PCI ID.
>> > >> There's no single answer here, which is why we need a major rethink of
>> > >> our strategy at some point in the future. But that overhaul can wait
>> > >> for a future series; I just want to make sure that the commit messages
>> > >> here aren't causing further confusion.
>> > >>
>> > >> >
>> > >> > Here the real reason for the change is that from the SW perspective they
>> > >> > are under the same PCI device and there's no reason to look for a
>> > >> > different one. Maybe rewording it a "Xe2_LPD has south display on the
>> > >> > same PCI device" would be simpler?
>> > >>
>> > >> No, that would be even less correct; PCI device isn't really related to
>> > >> any of this. Obviously at the register level, everything our driver
>> > >> cares about (NDE, SDE, GT, etc.) is accessed through the same PCI device
>> > >> (e.g., 00:02.0 on an igpu). Under the hood the various pieces of that
>> > >> PCI device (NDE, SDE, render GT, media GT, etc.) might be located
>> > >> together on a single chip, or may be spread across different dies. When
>> > >> spread across different dies, those dies can be mixed-and-matched in
>> > >> various ways (and it seems like hardware design is trending toward more
>> > >> flexibility in mix-and-match).
>> > >>
>> > >> The register interface to the SDE (i.e., which registers exist and what
>> > >> bitfields they have inside) hasn't had any meaningful changes in a long
>> > >> time. And if it does change in the future, the _interface_ changes are
>> > >> probably more tied to the display IP version than to anything else.
>> > >> However there's some important SDE handling that the driver needs to do
>> > >> that may vary based on the identity of the specific die that's
>> > >> responsible for doing SDE I/O on a given platform. I.e., there may be
>> > >> I/O-related defects+workarounds that require special SDE programming
>> > >> when a certain die variant and/or stepping is present. There can also
>> > >> be differences in how lanes are physically wired up, resulting in pin
>> > >> mapping changes. In these cases we need to be able to fingerprint the
>> > >> identity of the specific die handling the I/O (which might be a compute
>> > >> die, an SoC die, and IOE die, a PCH die, etc.) and make our decisions
>> > >> accordingly. If the SDE I/O happens on the same die as the north
>> > >> display functionality, then using the display version might be an
>> > >> effective way to fingerprint. If the SDE I/O happens on a different die
>> > >> from the NDE, but on the same die the PICA lives on, the display
>> > >> architects suggested using the PICA ID in that case. If neither of
>> > >> those cases are true, then we may need to look at PCI IDs or something.
>> > >>
>> > >> In the past, the PCH was often where the SDE I/O responsibility was so
>> > >> we needed a way to identify exactly which PCH variant was present. The
>> > >> "PCH ID" that we try to match on during driver startup is entirely
>> > >> unrelated to the SDE; it's just a random bus that we know was always
>> > >> part of every PCH and always present in the same predictable PCI slot,
>> > >> so it's handy for identification purposes. The fact that we're still
>> > >> looking at the ISA bus on MTL today is 100% wrong because most (maybe
>> > >> all?) MTL platforms don't even have a PCH (so that ISA bus might be on a
>> > >> different die that we really don't care about at all). For MTL I
>> > >> believe the NDE and the SDE's I/O are both on the same SoC die, so we
>> > >> should really just be making our decisions based on IP version and/or
>> > >> graphics device ID.
>> > >
>> > >I think ideally SDE would have its own IP version/etc. we could
>> > >use to identify it.
>> >
>> > maybe some future platform
>> >
>> > >
>> > >I'm not really sure why we even started down this "fake PCH" route
>> > >since we never added that for BXT/GLK either, and they managed just
>> >
>> > it was originally done for the discrete cards, I think DG1, and got
>> > extended to the next ones. Differently than BXT/GLK it doesn't work
>> > at all to try finding the ISA bridge as that would end up matching the
>> > wrong one.
>>
>> BXT/GLK don't look for the ISA bridge either. Well, they do, but
>> they won't find a matching one and thus we're left with PCH_NONE.
>
>I guess we can also blame bspec for this mess a bit since for
>BXT/GLK it actually documents the SDE registers in the north
>display section, whereas everything else that has SDE registers
>documents them in the south display section.
yes, in the bxt/glk it looks for it, finds nothing, and we handle the
PCH_NONE case throughout the code. When this was introduced for DG1 it
was basically "oh, we can't follow the same pattern because we will find
something and it will be the wrong one". For LNL we are going the same
fake pch route introduced by the discrete cards because SDE and PCH have
nothing to do with each other and we can't of course leave it as PCH_NONE
as that would actually go through the BXT/GLK path, that is not what we
want.
Lucas De Marchi
>
>--
>Ville Syrjälä
>Intel
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 06/27] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (4 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 07/27] drm/i915/display: Consolidate saved port bits in intel_digital_port Lucas De Marchi
` (21 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi, Matt Roper
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
We now start calculating relative plane data rate for cursor plane as
well, as instructed by BSpec and also treat cursor plane same way as
other planes, when doing allocation, i.e not using fixed allocation for
cursor anymore.
Bspec: 68907
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 6 +++---
drivers/gpu/drm/i915/display/skl_watermark.c | 16 +++++++++-------
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 60a492e186ab..d7a0bd686e49 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -214,9 +214,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
int width, height;
unsigned int rel_data_rate;
- if (plane->id == PLANE_CURSOR)
- return 0;
-
if (!plane_state->uapi.visible)
return 0;
@@ -244,6 +241,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
rel_data_rate = width * height * fb->format->cpp[color_plane];
+ if (plane->id == PLANE_CURSOR)
+ return rel_data_rate;
+
return intel_adjusted_rate(&plane_state->uapi.src,
&plane_state->uapi.dst,
rel_data_rate);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 063929a42a42..64a122d3c9c0 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
u64 data_rate = 0;
for_each_plane_id_on_crtc(crtc, plane_id) {
- if (plane_id == PLANE_CURSOR)
+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
continue;
data_rate += crtc_state->rel_data_rate[plane_id];
@@ -1514,10 +1514,12 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
return 0;
/* Allocate fixed number of blocks for cursor. */
- cursor_size = skl_cursor_allocation(crtc_state, num_active);
- iter.size -= cursor_size;
- skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
- alloc->end - cursor_size, alloc->end);
+ if (DISPLAY_VER(i915) < 20) {
+ cursor_size = skl_cursor_allocation(crtc_state, num_active);
+ iter.size -= cursor_size;
+ skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
+ alloc->end - cursor_size, alloc->end);
+ }
iter.data_rate = skl_total_relative_data_rate(crtc_state);
@@ -1531,7 +1533,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- if (plane_id == PLANE_CURSOR) {
+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20) {
const struct skl_ddb_entry *ddb =
&crtc_state->wm.skl.plane_ddb[plane_id];
@@ -1579,7 +1581,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- if (plane_id == PLANE_CURSOR)
+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
continue;
if (DISPLAY_VER(i915) < 11 &&
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 07/27] drm/i915/display: Consolidate saved port bits in intel_digital_port
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (5 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 06/27] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 08/27] drm/i915/xe2lpd: Move D2D enable/disable Lucas De Marchi
` (20 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Clint Taylor <clinton.a.taylor@intel.com>
We use multiple variables for HDMI and DisplayPort to store the value of
DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
to just one in struct intel_digital_port. This is a preparation step for
future changes in D2D enable/disable sequence for xe2lpd that need to
save some additional bits.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
2 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 690e1e02aba8..75a2da5d0c9e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -325,26 +325,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum phy phy = intel_port_to_phy(i915, encoder->port);
/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
- intel_dp->DP = dig_port->saved_port_bits |
+ dig_port->saved_port_bits |=
DDI_PORT_WIDTH(crtc_state->lane_count) |
DDI_BUF_TRANS_SELECT(0);
if (DISPLAY_VER(i915) >= 14) {
if (intel_dp_is_uhbr(crtc_state))
- intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
+ dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
else
- intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
+ dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
}
if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
- intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
+ dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
if (!intel_tc_port_in_tbt_alt_mode(dig_port))
- intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+ dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
}
@@ -1450,7 +1449,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
int level = intel_ddi_level(encoder, crtc_state, 0);
enum port port = encoder->port;
u32 signal_levels;
@@ -1467,10 +1466,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
signal_levels);
- intel_dp->DP &= ~DDI_BUF_EMP_MASK;
- intel_dp->DP |= signal_levels;
+ dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
+ dig_port->saved_port_bits |= signal_levels;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
}
@@ -3145,7 +3144,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
struct drm_connector *connector = conn_state->connector;
enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
- u32 buf_ctl;
if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
crtc_state->hdmi_high_tmds_clock_ratio,
@@ -3211,7 +3209,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
* is filled with lane count, already set in the crtc_state.
* The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
*/
- buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
+ dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
if (DISPLAY_VER(dev_priv) >= 14) {
u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
u32 port_buf = 0;
@@ -3224,13 +3222,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
- buf_ctl |= DDI_PORT_WIDTH(lane_count);
+ dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
} else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
- buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+ dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
- intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
intel_wait_ddi_buf_active(dev_priv, port);
@@ -3448,8 +3446,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
mtl_port_buf_ctl_program(encoder, crtc_state);
/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
- intel_dp->DP |= DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+ dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
/* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
@@ -3499,8 +3497,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
(intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
adlp_tbt_to_dp_alt_switch_wa(encoder);
- intel_dp->DP |= DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+ dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
intel_wait_ddi_buf_active(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2206b45bc78c..fdf71185cb00 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6017,7 +6017,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
intel_dp->pps.active_pipe = INVALID_PIPE;
/* Preserve the current hw state. */
- intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
+ dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
intel_dp->attached_connector = intel_connector;
if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 08/27] drm/i915/xe2lpd: Move D2D enable/disable
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (6 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 07/27] drm/i915/display: Consolidate saved port bits in intel_digital_port Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 09/27] drm/i915/xe2lpd: Move registers to PICA Lucas De Marchi
` (19 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Matt Roper, Lucas De Marchi
Bits to enable/disable and check state for D2D moved from
XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL (now named DDI_CTL_DE in the spec).
Make the functions mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic
to work with multiple reg location and bitfield layout.
v2: Set/Clear XE2LPD_DDI_BUF_D2D_LINK_ENABLE in saved_port_bits when
enabling/disabling D2D so DDI_BUF_CTL is correctly programmed in
other places without overriding these bits (Clint)
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 46 +++++++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 75a2da5d0c9e..53d8f13f8471 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2355,14 +2355,25 @@ static void
mtl_ddi_enable_d2d(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum port port = encoder->port;
+ i915_reg_t reg;
+ u32 set_bits, wait_bits;
+
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ reg = DDI_BUF_CTL(port);
+ set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+ dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ } else {
+ reg = XELPDP_PORT_BUF_CTL1(port);
+ set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+ wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+ }
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
- XELPDP_PORT_BUF_D2D_LINK_ENABLE);
-
- if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
- XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
- drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
+ intel_de_rmw(dev_priv, reg, 0, set_bits);
+ if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
+ drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
port_name(port));
}
}
@@ -2808,14 +2819,25 @@ static void
mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum port port = encoder->port;
+ i915_reg_t reg;
+ u32 clr_bits, wait_bits;
+
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ reg = DDI_BUF_CTL(port);
+ clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+ dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ } else {
+ reg = XELPDP_PORT_BUF_CTL1(port);
+ clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+ wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+ }
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
- XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
-
- if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
- XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
- drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
+ intel_de_rmw(dev_priv, reg, clr_bits, 0);
+ if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
+ drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
port_name(port));
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e00e4d569ba9..2f5dd5361263 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5678,6 +5678,8 @@ enum skl_power_gate {
/* Known as DDI_CTL_DE in MTL+ */
#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
#define DDI_BUF_CTL_ENABLE (1 << 31)
+#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
+#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
#define DDI_BUF_EMP_MASK (0xf << 24)
#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 09/27] drm/i915/xe2lpd: Move registers to PICA
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (7 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 08/27] drm/i915/xe2lpd: Move D2D enable/disable Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 17:52 ` Matt Roper
2023-09-08 13:05 ` [Intel-gfx] [Intel-xe] " Gustavo Sousa
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 10/27] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST Lucas De Marchi
` (18 subsequent siblings)
27 siblings, 2 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
Some registers for DDI A/B moved to PICA and now follow the same format
as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
- Share the implementation between xe2lpd and previous
platforms: there are minor layout changes, it's mostly the
register location that changed
- Handle offsets after TC ports
v2:
- Explain better the trick to use just the second range (Matt Roper)
- Add missing conversions after rebase (Matt Roper)
- Use macro instead of inline function, avoiding includes in the
header (Jani)
- Prefix old macros with underscore so they don't get used by mistake,
and name the new ones using the previous names
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 83 ++++++++++---------
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 57 +++++++++++--
drivers/gpu/drm/i915/display/intel_ddi.c | 20 +++--
drivers/gpu/drm/i915/display/intel_tc.c | 16 ++--
4 files changed, 114 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index e6d3027c821d..0ea00feb1ace 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -100,7 +100,7 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
enum port port, int lane)
{
- intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+ intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
}
@@ -108,10 +108,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, i
{
enum phy phy = intel_port_to_phy(i915, port);
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
@@ -163,7 +163,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port,
enum phy phy = intel_port_to_phy(i915, port);
if (__intel_de_wait_for_register(i915,
- XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+ XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_MSGBUS_TIMEOUT_FAST_US,
@@ -199,7 +199,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
@@ -208,7 +208,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
XELPDP_PORT_M2P_COMMAND_READ |
XELPDP_PORT_M2P_ADDRESS(addr));
@@ -259,7 +259,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
@@ -268,14 +268,14 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
(committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
XELPDP_PORT_M2P_DATA(data) |
XELPDP_PORT_M2P_ADDRESS(addr));
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
@@ -288,7 +288,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
if (ack < 0)
return ack;
- } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) &
+ } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane)) &
XELPDP_PORT_P2M_ERROR_SET)) {
drm_dbg_kms(&i915->drm,
"PHY %c Error occurred during write command.\n", phy_name(phy));
@@ -2470,7 +2470,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u32 val = 0;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
+ XELPDP_PORT_REVERSAL,
lane_reversal ? XELPDP_PORT_REVERSAL : 0);
if (lane_reversal)
@@ -2490,7 +2491,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
else
val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
XELPDP_SSC_ENABLE_PLLB, val);
@@ -2523,15 +2524,16 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
u8 lane_mask, u8 state)
{
enum phy phy = intel_port_to_phy(i915, port);
+ i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(i915, port);
int lane;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ intel_de_rmw(i915, buf_ctl2_reg,
intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
intel_cx0_get_powerdown_state(lane_mask, state));
/* Wait for pending transactions.*/
for_each_cx0_lane_in_mask(lane_mask, lane)
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
@@ -2540,12 +2542,12 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
intel_cx0_bus_reset(i915, port, lane);
}
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ intel_de_rmw(i915, buf_ctl2_reg,
intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
intel_cx0_get_powerdown_update(lane_mask));
/* Update Timeout Value */
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
+ if (__intel_de_wait_for_register(i915, buf_ctl2_reg,
intel_cx0_get_powerdown_update(lane_mask), 0,
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
@@ -2554,10 +2556,10 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
{
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
XELPDP_POWER_STATE_READY_MASK,
XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(i915, port),
XELPDP_POWER_STATE_ACTIVE_MASK |
XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
@@ -2602,28 +2604,28 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
XELPDP_LANE_PHY_CURRENT_STATUS(1))
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(i915, port),
XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
lane_pipe_reset);
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(i915, port),
lane_phy_current_status, lane_phy_current_status,
XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
intel_cx0_get_pclk_refclk_request(owned_lane_mask),
intel_cx0_get_pclk_refclk_request(lane_mask));
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
intel_cx0_get_pclk_refclk_ack(lane_mask),
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
@@ -2634,9 +2636,10 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
CX0_P2_STATE_RESET);
intel_cx0_setup_powerdown(i915, port);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0);
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 0);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status,
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ lane_phy_current_status,
XELPDP_PORT_RESET_END_TIMEOUT))
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
@@ -2765,12 +2768,12 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
* 8. Set PORT_CLOCK_CTL register PCLK PLL Request
* LN<Lane for maxPCLK> to "1" to enable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_request(maxpclk_lane));
/* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_ack(maxpclk_lane),
XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
@@ -2790,7 +2793,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u32 clock;
- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+ u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
@@ -2843,11 +2846,11 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
*/
val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
val |= XELPDP_FORWARD_CLOCK_UNGATE;
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
/* 2. Read back PORT_CLOCK_CTL REGISTER */
- val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+ val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
/*
* 3. Follow the Display Voltage Frequency Switching - Sequence
@@ -2858,10 +2861,10 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
*/
val |= XELPDP_TBT_CLOCK_REQUEST;
- intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
+ intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_TBT_CLOCK_ACK,
XELPDP_TBT_CLOCK_ACK,
100, 0, NULL))
@@ -2913,7 +2916,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
* 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
* to "0" to disable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
@@ -2923,7 +2926,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
/*
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
*/
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
@@ -2936,9 +2939,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
*/
/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK, 0);
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
intel_cx0_phy_transaction_end(encoder, wakeref);
@@ -2957,11 +2960,11 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
/*
* 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_TBT_CLOCK_REQUEST, 0);
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
@@ -2974,7 +2977,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
/*
* 5. Program PORT CLOCK CTRL register to disable and gate clocks
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK |
XELPDP_FORWARD_CLOCK_UNGATE, 0);
@@ -3001,7 +3004,7 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
* TODO: Determine the PLL type from the SW state, once MTL PLL
* handling is done via the standard shared DPLL framework.
*/
- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+ u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index b2db4cc366d6..faff81fa8438 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -7,16 +7,39 @@
#define __INTEL_CX0_PHY_REGS_H__
#include "i915_reg_defs.h"
+#include "intel_display_limits.h"
+
+/*
+ * Wrapper macro to convert from port number to the index used in some of the
+ * registers. For Display version 20 and above it converts the port number to a
+ * single range, starting with the TC offsets. When used together with
+ * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second
+ * range. Example:
+ *
+ * PORT_TC1 -> PORT_TC1
+ * PORT_TC2 -> PORT_TC2
+ * PORT_TC3 -> PORT_TC3
+ * PORT_TC4 -> PORT_TC4
+ * PORT_A -> PORT_TC4 + 1
+ * PORT_B -> PORT_TC4 + 2
+ * ...
+ */
+#define __xe2lpd_port_idx(port) \
+ (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
-#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
+#define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
@@ -27,11 +50,16 @@
#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
-#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+
+#define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
+#define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
@@ -54,11 +82,15 @@
#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
-#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_BUF_CTL1(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_BUF_CTL1_LN0_A, \
_XELPDP_PORT_BUF_CTL1_LN0_B, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC2))
+#define XELPDP_PORT_BUF_CTL1(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_BUF_CTL1(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_BUF_CTL1(port))
#define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
#define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
@@ -75,12 +107,15 @@
#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
-#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_BUF_CTL1_LN0_A, \
_XELPDP_PORT_BUF_CTL1_LN0_B, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
-
+#define XELPDP_PORT_BUF_CTL2(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_BUF_CTL2(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_BUF_CTL2(port))
#define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30))
#define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28))
#define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24))
@@ -95,11 +130,15 @@
#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
-#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_BUF_CTL3(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_BUF_CTL1_LN0_A, \
_XELPDP_PORT_BUF_CTL1_LN0_B, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
+#define XELPDP_PORT_BUF_CTL3(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_BUF_CTL3(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_BUF_CTL3(port))
#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
@@ -127,11 +166,15 @@
#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
-#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_CLOCK_CTL(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_CLOCK_CTL_A, \
_XELPDP_PORT_CLOCK_CTL_B, \
_XELPDP_PORT_CLOCK_CTL_USBC1, \
_XELPDP_PORT_CLOCK_CTL_USBC2))
+#define XELPDP_PORT_CLOCK_CTL(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_CLOCK_CTL(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_CLOCK_CTL(port))
#define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4))
#define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4))
#define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 53d8f13f8471..2509785daf7b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -177,7 +177,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
int ret;
/* FIXME: find out why Bspec's 100us timeout is too short */
- ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
+ ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) &
XELPDP_PORT_BUF_PHY_IDLE), 10000);
if (ret)
drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
@@ -225,7 +225,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
}
if (DISPLAY_VER(dev_priv) >= 14)
- ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
+ ret = _wait_for(!(intel_de_read(dev_priv,
+ XELPDP_PORT_BUF_CTL1(dev_priv, port)) &
+ XELPDP_PORT_BUF_PHY_IDLE),
timeout_us, 10, 10);
else
ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
@@ -2366,7 +2368,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
} else {
- reg = XELPDP_PORT_BUF_CTL1(port);
+ reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);
set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
}
@@ -2386,7 +2388,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
enum port port = encoder->port;
u32 val;
- val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
+ val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
val &= ~XELPDP_PORT_WIDTH_MASK;
val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
@@ -2399,7 +2401,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
val |= XELPDP_PORT_REVERSAL;
- intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
+ intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val);
}
static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
@@ -2410,7 +2412,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
XELPDP_PORT_BUF_IO_SELECT_TBT, val);
}
@@ -2830,7 +2832,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
} else {
- reg = XELPDP_PORT_BUF_CTL1(port);
+ reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);
clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
}
@@ -2968,7 +2970,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
/* De-select Thunderbolt */
if (DISPLAY_VER(dev_priv) >= 14)
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port),
XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
}
@@ -3241,7 +3243,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
port_buf |= XELPDP_PORT_REVERSAL;
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port),
XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 3c94bbcb5497..678693978892 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -958,10 +958,11 @@ xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc)
{
struct drm_i915_private *i915 = tc_to_i915(tc);
enum port port = tc->dig_port->base.port;
+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
assert_tc_cold_blocked(tc);
- return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TCSS_POWER_STATE;
+ return intel_de_read(i915, reg) & XELPDP_TCSS_POWER_STATE;
}
static bool
@@ -984,16 +985,17 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool ena
{
struct drm_i915_private *i915 = tc_to_i915(tc);
enum port port = tc->dig_port->base.port;
+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
u32 val;
assert_tc_cold_blocked(tc);
- val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
+ val = intel_de_read(i915, reg);
if (enable)
val |= XELPDP_TCSS_POWER_REQUEST;
else
val &= ~XELPDP_TCSS_POWER_REQUEST;
- intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
+ intel_de_write(i915, reg, val);
}
static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
@@ -1020,26 +1022,28 @@ static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
{
struct drm_i915_private *i915 = tc_to_i915(tc);
enum port port = tc->dig_port->base.port;
+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
u32 val;
assert_tc_cold_blocked(tc);
- val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
+ val = intel_de_read(i915, reg);
if (take)
val |= XELPDP_TC_PHY_OWNERSHIP;
else
val &= ~XELPDP_TC_PHY_OWNERSHIP;
- intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
+ intel_de_write(i915, reg, val);
}
static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc)
{
struct drm_i915_private *i915 = tc_to_i915(tc);
enum port port = tc->dig_port->base.port;
+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
assert_tc_cold_blocked(tc);
- return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TC_PHY_OWNERSHIP;
+ return intel_de_read(i915, reg) & XELPDP_TC_PHY_OWNERSHIP;
}
static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc)
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 09/27] drm/i915/xe2lpd: Move registers to PICA
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 09/27] drm/i915/xe2lpd: Move registers to PICA Lucas De Marchi
@ 2023-09-07 17:52 ` Matt Roper
2023-09-08 13:05 ` [Intel-gfx] [Intel-xe] " Gustavo Sousa
1 sibling, 0 replies; 62+ messages in thread
From: Matt Roper @ 2023-09-07 17:52 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 08:37:39AM -0700, Lucas De Marchi wrote:
> Some registers for DDI A/B moved to PICA and now follow the same format
> as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
>
> - Share the implementation between xe2lpd and previous
> platforms: there are minor layout changes, it's mostly the
> register location that changed
> - Handle offsets after TC ports
>
> v2:
> - Explain better the trick to use just the second range (Matt Roper)
> - Add missing conversions after rebase (Matt Roper)
> - Use macro instead of inline function, avoiding includes in the
> header (Jani)
> - Prefix old macros with underscore so they don't get used by mistake,
> and name the new ones using the previous names
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 83 ++++++++++---------
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 57 +++++++++++--
> drivers/gpu/drm/i915/display/intel_ddi.c | 20 +++--
> drivers/gpu/drm/i915/display/intel_tc.c | 16 ++--
> 4 files changed, 114 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index e6d3027c821d..0ea00feb1ace 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -100,7 +100,7 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
> static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
> enum port port, int lane)
> {
> - intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
> + intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
> 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
> }
>
> @@ -108,10 +108,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, i
> {
> enum phy phy = intel_port_to_phy(i915, port);
>
> - intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_RESET);
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_RESET,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
> @@ -163,7 +163,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port,
> enum phy phy = intel_port_to_phy(i915, port);
>
> if (__intel_de_wait_for_register(i915,
> - XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
> + XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
> XELPDP_PORT_P2M_RESPONSE_READY,
> XELPDP_PORT_P2M_RESPONSE_READY,
> XELPDP_MSGBUS_TIMEOUT_FAST_US,
> @@ -199,7 +199,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
> int ack;
> u32 val;
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_dbg_kms(&i915->drm,
> @@ -208,7 +208,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
> return -ETIMEDOUT;
> }
>
> - intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING |
> XELPDP_PORT_M2P_COMMAND_READ |
> XELPDP_PORT_M2P_ADDRESS(addr));
> @@ -259,7 +259,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
> int ack;
> u32 val;
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_dbg_kms(&i915->drm,
> @@ -268,14 +268,14 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
> return -ETIMEDOUT;
> }
>
> - intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING |
> (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
> XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
> XELPDP_PORT_M2P_DATA(data) |
> XELPDP_PORT_M2P_ADDRESS(addr));
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_dbg_kms(&i915->drm,
> @@ -288,7 +288,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
> ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
> if (ack < 0)
> return ack;
> - } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) &
> + } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane)) &
> XELPDP_PORT_P2M_ERROR_SET)) {
> drm_dbg_kms(&i915->drm,
> "PHY %c Error occurred during write command.\n", phy_name(phy));
> @@ -2470,7 +2470,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u32 val = 0;
>
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
> + XELPDP_PORT_REVERSAL,
> lane_reversal ? XELPDP_PORT_REVERSAL : 0);
>
> if (lane_reversal)
> @@ -2490,7 +2491,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> else
> val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
>
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
> XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
> XELPDP_SSC_ENABLE_PLLB, val);
> @@ -2523,15 +2524,16 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
> u8 lane_mask, u8 state)
> {
> enum phy phy = intel_port_to_phy(i915, port);
> + i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(i915, port);
> int lane;
>
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + intel_de_rmw(i915, buf_ctl2_reg,
> intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
> intel_cx0_get_powerdown_state(lane_mask, state));
>
> /* Wait for pending transactions.*/
> for_each_cx0_lane_in_mask(lane_mask, lane)
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_dbg_kms(&i915->drm,
> @@ -2540,12 +2542,12 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
> intel_cx0_bus_reset(i915, port, lane);
> }
>
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + intel_de_rmw(i915, buf_ctl2_reg,
> intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
> intel_cx0_get_powerdown_update(lane_mask));
>
> /* Update Timeout Value */
> - if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> + if (__intel_de_wait_for_register(i915, buf_ctl2_reg,
> intel_cx0_get_powerdown_update(lane_mask), 0,
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
> drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> @@ -2554,10 +2556,10 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
>
> static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
> {
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
> XELPDP_POWER_STATE_READY_MASK,
> XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(i915, port),
> XELPDP_POWER_STATE_ACTIVE_MASK |
> XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
> XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
> @@ -2602,28 +2604,28 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
> XELPDP_LANE_PHY_CURRENT_STATUS(1))
> : XELPDP_LANE_PHY_CURRENT_STATUS(0);
>
> - if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(i915, port),
> XELPDP_PORT_BUF_SOC_PHY_READY,
> XELPDP_PORT_BUF_SOC_PHY_READY,
> XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
> drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
> phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
>
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
> XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
> lane_pipe_reset);
>
> - if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(i915, port),
> lane_phy_current_status, lane_phy_current_status,
> XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
> drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
>
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
> intel_cx0_get_pclk_refclk_request(owned_lane_mask),
> intel_cx0_get_pclk_refclk_request(lane_mask));
>
> - if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
> intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
> intel_cx0_get_pclk_refclk_ack(lane_mask),
> XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
> @@ -2634,9 +2636,10 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
> CX0_P2_STATE_RESET);
> intel_cx0_setup_powerdown(i915, port);
>
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0);
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 0);
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status,
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(i915, port),
> + lane_phy_current_status,
> XELPDP_PORT_RESET_END_TIMEOUT))
> drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
> phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
> @@ -2765,12 +2768,12 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
> * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
> * LN<Lane for maxPCLK> to "1" to enable PLL.
> */
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
> intel_cx0_get_pclk_pll_request(maxpclk_lane));
>
> /* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
> - if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
> intel_cx0_get_pclk_pll_ack(maxpclk_lane),
> XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
> @@ -2790,7 +2793,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u32 clock;
> - u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> + u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
>
> clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
>
> @@ -2843,11 +2846,11 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> */
> val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
> val |= XELPDP_FORWARD_CLOCK_UNGATE;
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
>
> /* 2. Read back PORT_CLOCK_CTL REGISTER */
> - val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> + val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
>
> /*
> * 3. Follow the Display Voltage Frequency Switching - Sequence
> @@ -2858,10 +2861,10 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
> */
> val |= XELPDP_TBT_CLOCK_REQUEST;
> - intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
> + intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);
>
> /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
> - if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_TBT_CLOCK_ACK,
> XELPDP_TBT_CLOCK_ACK,
> 100, 0, NULL))
> @@ -2913,7 +2916,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
> * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
> * to "0" to disable PLL.
> */
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
> intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
>
> @@ -2923,7 +2926,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
> /*
> * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
> */
> - if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
> intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
> XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
> @@ -2936,9 +2939,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
> */
>
> /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_DDI_CLOCK_SELECT_MASK, 0);
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_FORWARD_CLOCK_UNGATE, 0);
>
> intel_cx0_phy_transaction_end(encoder, wakeref);
> @@ -2957,11 +2960,11 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> /*
> * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
> */
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_TBT_CLOCK_REQUEST, 0);
>
> /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
> - if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
> drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
> encoder->base.base.id, encoder->base.name, phy_name(phy));
> @@ -2974,7 +2977,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> /*
> * 5. Program PORT CLOCK CTRL register to disable and gate clocks
> */
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_DDI_CLOCK_SELECT_MASK |
> XELPDP_FORWARD_CLOCK_UNGATE, 0);
>
> @@ -3001,7 +3004,7 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
> * TODO: Determine the PLL type from the SW state, once MTL PLL
> * handling is done via the standard shared DPLL framework.
> */
> - u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> + u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
> u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
>
> if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index b2db4cc366d6..faff81fa8438 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -7,16 +7,39 @@
> #define __INTEL_CX0_PHY_REGS_H__
>
> #include "i915_reg_defs.h"
> +#include "intel_display_limits.h"
> +
> +/*
> + * Wrapper macro to convert from port number to the index used in some of the
> + * registers. For Display version 20 and above it converts the port number to a
> + * single range, starting with the TC offsets. When used together with
> + * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second
> + * range. Example:
> + *
> + * PORT_TC1 -> PORT_TC1
> + * PORT_TC2 -> PORT_TC2
> + * PORT_TC3 -> PORT_TC3
> + * PORT_TC4 -> PORT_TC4
> + * PORT_A -> PORT_TC4 + 1
> + * PORT_B -> PORT_TC4 + 2
> + * ...
> + */
> +#define __xe2lpd_port_idx(port) \
> + (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
>
> #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
> #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
> #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
> #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
> -#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
> +#define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \
> + (DISPLAY_VER(i915__) >= 20 ? \
> + _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \
> + _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
> #define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
> #define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
> #define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
> @@ -27,11 +50,16 @@
> #define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
> #define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
> #define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
> -#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +
> +#define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
> +#define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \
> + (DISPLAY_VER(i915__) >= 20 ? \
> + _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \
> + _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
> #define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
> #define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
> #define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
> @@ -54,11 +82,15 @@
> #define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
> #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
> #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
> -#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define _XELPDP_PORT_BUF_CTL1(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_A, \
> _XELPDP_PORT_BUF_CTL1_LN0_B, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC2))
> +#define XELPDP_PORT_BUF_CTL1(i915__, port) \
> + (DISPLAY_VER(i915__) >= 20 ? \
> + _XELPDP_PORT_BUF_CTL1(__xe2lpd_port_idx(port)) : \
> + _XELPDP_PORT_BUF_CTL1(port))
> #define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
> #define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
> #define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
> @@ -75,12 +107,15 @@
> #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
> #define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
>
> -#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_A, \
> _XELPDP_PORT_BUF_CTL1_LN0_B, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
> -
> +#define XELPDP_PORT_BUF_CTL2(i915__, port) \
> + (DISPLAY_VER(i915__) >= 20 ? \
> + _XELPDP_PORT_BUF_CTL2(__xe2lpd_port_idx(port)) : \
> + _XELPDP_PORT_BUF_CTL2(port))
> #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30))
> #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28))
> #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24))
> @@ -95,11 +130,15 @@
> #define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
> #define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
>
> -#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define _XELPDP_PORT_BUF_CTL3(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_A, \
> _XELPDP_PORT_BUF_CTL1_LN0_B, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
> +#define XELPDP_PORT_BUF_CTL3(i915__, port) \
> + (DISPLAY_VER(i915__) >= 20 ? \
> + _XELPDP_PORT_BUF_CTL3(__xe2lpd_port_idx(port)) : \
> + _XELPDP_PORT_BUF_CTL3(port))
> #define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
> #define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
> #define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
> @@ -127,11 +166,15 @@
> #define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
> #define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
> #define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
> -#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +#define _XELPDP_PORT_CLOCK_CTL(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_CLOCK_CTL_A, \
> _XELPDP_PORT_CLOCK_CTL_B, \
> _XELPDP_PORT_CLOCK_CTL_USBC1, \
> _XELPDP_PORT_CLOCK_CTL_USBC2))
> +#define XELPDP_PORT_CLOCK_CTL(i915__, port) \
> + (DISPLAY_VER(i915__) >= 20 ? \
> + _XELPDP_PORT_CLOCK_CTL(__xe2lpd_port_idx(port)) : \
> + _XELPDP_PORT_CLOCK_CTL(port))
> #define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4))
> #define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4))
> #define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4))
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 53d8f13f8471..2509785daf7b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -177,7 +177,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
> int ret;
>
> /* FIXME: find out why Bspec's 100us timeout is too short */
> - ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
> + ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) &
> XELPDP_PORT_BUF_PHY_IDLE), 10000);
> if (ret)
> drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
> @@ -225,7 +225,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
> }
>
> if (DISPLAY_VER(dev_priv) >= 14)
> - ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
> + ret = _wait_for(!(intel_de_read(dev_priv,
> + XELPDP_PORT_BUF_CTL1(dev_priv, port)) &
> + XELPDP_PORT_BUF_PHY_IDLE),
> timeout_us, 10, 10);
> else
> ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
> @@ -2366,7 +2368,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
> wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> } else {
> - reg = XELPDP_PORT_BUF_CTL1(port);
> + reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);
> set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> }
> @@ -2386,7 +2388,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
> enum port port = encoder->port;
> u32 val;
>
> - val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
> + val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
> val &= ~XELPDP_PORT_WIDTH_MASK;
> val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
>
> @@ -2399,7 +2401,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
> if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
> val |= XELPDP_PORT_REVERSAL;
>
> - intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
> + intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val);
> }
>
> static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
> @@ -2410,7 +2412,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>
> val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
> XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
> XELPDP_PORT_BUF_IO_SELECT_TBT, val);
> }
>
> @@ -2830,7 +2832,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
> wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> } else {
> - reg = XELPDP_PORT_BUF_CTL1(port);
> + reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);
> clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> }
> @@ -2968,7 +2970,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>
> /* De-select Thunderbolt */
> if (DISPLAY_VER(dev_priv) >= 14)
> - intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
> + intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port),
> XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
> }
>
> @@ -3241,7 +3243,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
> port_buf |= XELPDP_PORT_REVERSAL;
>
> - intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> + intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port),
> XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
>
> dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 3c94bbcb5497..678693978892 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -958,10 +958,11 @@ xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc)
> {
> struct drm_i915_private *i915 = tc_to_i915(tc);
> enum port port = tc->dig_port->base.port;
> + i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
>
> assert_tc_cold_blocked(tc);
>
> - return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TCSS_POWER_STATE;
> + return intel_de_read(i915, reg) & XELPDP_TCSS_POWER_STATE;
> }
>
> static bool
> @@ -984,16 +985,17 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool ena
> {
> struct drm_i915_private *i915 = tc_to_i915(tc);
> enum port port = tc->dig_port->base.port;
> + i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
> u32 val;
>
> assert_tc_cold_blocked(tc);
>
> - val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
> + val = intel_de_read(i915, reg);
> if (enable)
> val |= XELPDP_TCSS_POWER_REQUEST;
> else
> val &= ~XELPDP_TCSS_POWER_REQUEST;
> - intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
> + intel_de_write(i915, reg, val);
> }
>
> static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
> @@ -1020,26 +1022,28 @@ static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
> {
> struct drm_i915_private *i915 = tc_to_i915(tc);
> enum port port = tc->dig_port->base.port;
> + i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
> u32 val;
>
> assert_tc_cold_blocked(tc);
>
> - val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
> + val = intel_de_read(i915, reg);
> if (take)
> val |= XELPDP_TC_PHY_OWNERSHIP;
> else
> val &= ~XELPDP_TC_PHY_OWNERSHIP;
> - intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
> + intel_de_write(i915, reg, val);
> }
>
> static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc)
> {
> struct drm_i915_private *i915 = tc_to_i915(tc);
> enum port port = tc->dig_port->base.port;
> + i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
>
> assert_tc_cold_blocked(tc);
>
> - return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TC_PHY_OWNERSHIP;
> + return intel_de_read(i915, reg) & XELPDP_TC_PHY_OWNERSHIP;
> }
>
> static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc)
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v2 09/27] drm/i915/xe2lpd: Move registers to PICA
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 09/27] drm/i915/xe2lpd: Move registers to PICA Lucas De Marchi
2023-09-07 17:52 ` Matt Roper
@ 2023-09-08 13:05 ` Gustavo Sousa
1 sibling, 0 replies; 62+ messages in thread
From: Gustavo Sousa @ 2023-09-08 13:05 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx, intel-xe; +Cc: Lucas De Marchi
Quoting Lucas De Marchi (2023-09-07 12:37:39-03:00)
>Some registers for DDI A/B moved to PICA and now follow the same format
>as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
>
> - Share the implementation between xe2lpd and previous
> platforms: there are minor layout changes, it's mostly the
> register location that changed
> - Handle offsets after TC ports
>
>v2:
> - Explain better the trick to use just the second range (Matt Roper)
> - Add missing conversions after rebase (Matt Roper)
> - Use macro instead of inline function, avoiding includes in the
> header (Jani)
> - Prefix old macros with underscore so they don't get used by mistake,
> and name the new ones using the previous names
>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
git show --word-diff made it very easy to review this :-)
Heads-up: this will need to be also applied to the recent addition of
XELPDP_PORT_MSGBUS_TIMER.
With the above suggestion,
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 83 ++++++++++---------
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 57 +++++++++++--
> drivers/gpu/drm/i915/display/intel_ddi.c | 20 +++--
> drivers/gpu/drm/i915/display/intel_tc.c | 16 ++--
> 4 files changed, 114 insertions(+), 62 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index e6d3027c821d..0ea00feb1ace 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -100,7 +100,7 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
> static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
> enum port port, int lane)
> {
>- intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
>+ intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
> 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
> }
>
>@@ -108,10 +108,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, i
> {
> enum phy phy = intel_port_to_phy(i915, port);
>
>- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
>+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_RESET);
>
>- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
>+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_RESET,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
>@@ -163,7 +163,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port,
> enum phy phy = intel_port_to_phy(i915, port);
>
> if (__intel_de_wait_for_register(i915,
>- XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
>+ XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
> XELPDP_PORT_P2M_RESPONSE_READY,
> XELPDP_PORT_P2M_RESPONSE_READY,
> XELPDP_MSGBUS_TIMEOUT_FAST_US,
>@@ -199,7 +199,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
> int ack;
> u32 val;
>
>- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
>+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_dbg_kms(&i915->drm,
>@@ -208,7 +208,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
> return -ETIMEDOUT;
> }
>
>- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
>+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING |
> XELPDP_PORT_M2P_COMMAND_READ |
> XELPDP_PORT_M2P_ADDRESS(addr));
>@@ -259,7 +259,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
> int ack;
> u32 val;
>
>- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
>+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_dbg_kms(&i915->drm,
>@@ -268,14 +268,14 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
> return -ETIMEDOUT;
> }
>
>- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
>+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING |
> (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
> XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
> XELPDP_PORT_M2P_DATA(data) |
> XELPDP_PORT_M2P_ADDRESS(addr));
>
>- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
>+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_dbg_kms(&i915->drm,
>@@ -288,7 +288,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
> ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
> if (ack < 0)
> return ack;
>- } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) &
>+ } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane)) &
> XELPDP_PORT_P2M_ERROR_SET)) {
> drm_dbg_kms(&i915->drm,
> "PHY %c Error occurred during write command.\n", phy_name(phy));
>@@ -2470,7 +2470,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u32 val = 0;
>
>- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
>+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
>+ XELPDP_PORT_REVERSAL,
> lane_reversal ? XELPDP_PORT_REVERSAL : 0);
>
> if (lane_reversal)
>@@ -2490,7 +2491,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> else
> val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
>
>- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
> XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
> XELPDP_SSC_ENABLE_PLLB, val);
>@@ -2523,15 +2524,16 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
> u8 lane_mask, u8 state)
> {
> enum phy phy = intel_port_to_phy(i915, port);
>+ i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(i915, port);
> int lane;
>
>- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
>+ intel_de_rmw(i915, buf_ctl2_reg,
> intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
> intel_cx0_get_powerdown_state(lane_mask, state));
>
> /* Wait for pending transactions.*/
> for_each_cx0_lane_in_mask(lane_mask, lane)
>- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
>+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_dbg_kms(&i915->drm,
>@@ -2540,12 +2542,12 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
> intel_cx0_bus_reset(i915, port, lane);
> }
>
>- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
>+ intel_de_rmw(i915, buf_ctl2_reg,
> intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
> intel_cx0_get_powerdown_update(lane_mask));
>
> /* Update Timeout Value */
>- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
>+ if (__intel_de_wait_for_register(i915, buf_ctl2_reg,
> intel_cx0_get_powerdown_update(lane_mask), 0,
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
> drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
>@@ -2554,10 +2556,10 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
>
> static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
> {
>- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
>+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
> XELPDP_POWER_STATE_READY_MASK,
> XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
>- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
>+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(i915, port),
> XELPDP_POWER_STATE_ACTIVE_MASK |
> XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
> XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
>@@ -2602,28 +2604,28 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
> XELPDP_LANE_PHY_CURRENT_STATUS(1))
> : XELPDP_LANE_PHY_CURRENT_STATUS(0);
>
>- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
>+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(i915, port),
> XELPDP_PORT_BUF_SOC_PHY_READY,
> XELPDP_PORT_BUF_SOC_PHY_READY,
> XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
> drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
> phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
>
>- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
>+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
> XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
> lane_pipe_reset);
>
>- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
>+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(i915, port),
> lane_phy_current_status, lane_phy_current_status,
> XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
> drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
>
>- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
>+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
> intel_cx0_get_pclk_refclk_request(owned_lane_mask),
> intel_cx0_get_pclk_refclk_request(lane_mask));
>
>- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
>+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
> intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
> intel_cx0_get_pclk_refclk_ack(lane_mask),
> XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
>@@ -2634,9 +2636,10 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
> CX0_P2_STATE_RESET);
> intel_cx0_setup_powerdown(i915, port);
>
>- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0);
>+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 0);
>
>- if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status,
>+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(i915, port),
>+ lane_phy_current_status,
> XELPDP_PORT_RESET_END_TIMEOUT))
> drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
> phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
>@@ -2765,12 +2768,12 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
> * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
> * LN<Lane for maxPCLK> to "1" to enable PLL.
> */
>- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
> intel_cx0_get_pclk_pll_request(maxpclk_lane));
>
> /* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
>- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
> intel_cx0_get_pclk_pll_ack(maxpclk_lane),
> XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
>@@ -2790,7 +2793,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u32 clock;
>- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
>+ u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
>
> clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
>
>@@ -2843,11 +2846,11 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> */
> val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
> val |= XELPDP_FORWARD_CLOCK_UNGATE;
>- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
>
> /* 2. Read back PORT_CLOCK_CTL REGISTER */
>- val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
>+ val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
>
> /*
> * 3. Follow the Display Voltage Frequency Switching - Sequence
>@@ -2858,10 +2861,10 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
> */
> val |= XELPDP_TBT_CLOCK_REQUEST;
>- intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
>+ intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);
>
> /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
>- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_TBT_CLOCK_ACK,
> XELPDP_TBT_CLOCK_ACK,
> 100, 0, NULL))
>@@ -2913,7 +2916,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
> * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
> * to "0" to disable PLL.
> */
>- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
> intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
>
>@@ -2923,7 +2926,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
> /*
> * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
> */
>- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
> intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
> XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
>@@ -2936,9 +2939,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
> */
>
> /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
>- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_DDI_CLOCK_SELECT_MASK, 0);
>- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_FORWARD_CLOCK_UNGATE, 0);
>
> intel_cx0_phy_transaction_end(encoder, wakeref);
>@@ -2957,11 +2960,11 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> /*
> * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
> */
>- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_TBT_CLOCK_REQUEST, 0);
>
> /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
>- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
> drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
> encoder->base.base.id, encoder->base.name, phy_name(phy));
>@@ -2974,7 +2977,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> /*
> * 5. Program PORT CLOCK CTRL register to disable and gate clocks
> */
>- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
>+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> XELPDP_DDI_CLOCK_SELECT_MASK |
> XELPDP_FORWARD_CLOCK_UNGATE, 0);
>
>@@ -3001,7 +3004,7 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
> * TODO: Determine the PLL type from the SW state, once MTL PLL
> * handling is done via the standard shared DPLL framework.
> */
>- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
>+ u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
> u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
>
> if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>index b2db4cc366d6..faff81fa8438 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>@@ -7,16 +7,39 @@
> #define __INTEL_CX0_PHY_REGS_H__
>
> #include "i915_reg_defs.h"
>+#include "intel_display_limits.h"
>+
>+/*
>+ * Wrapper macro to convert from port number to the index used in some of the
>+ * registers. For Display version 20 and above it converts the port number to a
>+ * single range, starting with the TC offsets. When used together with
>+ * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second
>+ * range. Example:
>+ *
>+ * PORT_TC1 -> PORT_TC1
>+ * PORT_TC2 -> PORT_TC2
>+ * PORT_TC3 -> PORT_TC3
>+ * PORT_TC4 -> PORT_TC4
>+ * PORT_A -> PORT_TC4 + 1
>+ * PORT_B -> PORT_TC4 + 2
>+ * ...
>+ */
>+#define __xe2lpd_port_idx(port) \
>+ (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
>
> #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
> #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
> #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
> #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
>-#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>+#define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
>+#define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \
>+ (DISPLAY_VER(i915__) >= 20 ? \
>+ _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \
>+ _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
> #define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
> #define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
> #define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
>@@ -27,11 +50,16 @@
> #define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
> #define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
> #define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
>-#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>+
>+#define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
>+#define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \
>+ (DISPLAY_VER(i915__) >= 20 ? \
>+ _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \
>+ _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
> #define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
> #define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
> #define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
>@@ -54,11 +82,15 @@
> #define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
> #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
> #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
>-#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>+#define _XELPDP_PORT_BUF_CTL1(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_A, \
> _XELPDP_PORT_BUF_CTL1_LN0_B, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC2))
>+#define XELPDP_PORT_BUF_CTL1(i915__, port) \
>+ (DISPLAY_VER(i915__) >= 20 ? \
>+ _XELPDP_PORT_BUF_CTL1(__xe2lpd_port_idx(port)) : \
>+ _XELPDP_PORT_BUF_CTL1(port))
> #define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
> #define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
> #define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
>@@ -75,12 +107,15 @@
> #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
> #define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
>
>-#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>+#define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_A, \
> _XELPDP_PORT_BUF_CTL1_LN0_B, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
>-
>+#define XELPDP_PORT_BUF_CTL2(i915__, port) \
>+ (DISPLAY_VER(i915__) >= 20 ? \
>+ _XELPDP_PORT_BUF_CTL2(__xe2lpd_port_idx(port)) : \
>+ _XELPDP_PORT_BUF_CTL2(port))
> #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30))
> #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28))
> #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24))
>@@ -95,11 +130,15 @@
> #define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
> #define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
>
>-#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>+#define _XELPDP_PORT_BUF_CTL3(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_A, \
> _XELPDP_PORT_BUF_CTL1_LN0_B, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
>+#define XELPDP_PORT_BUF_CTL3(i915__, port) \
>+ (DISPLAY_VER(i915__) >= 20 ? \
>+ _XELPDP_PORT_BUF_CTL3(__xe2lpd_port_idx(port)) : \
>+ _XELPDP_PORT_BUF_CTL3(port))
> #define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
> #define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
> #define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
>@@ -127,11 +166,15 @@
> #define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
> #define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
> #define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
>-#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
>+#define _XELPDP_PORT_CLOCK_CTL(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> _XELPDP_PORT_CLOCK_CTL_A, \
> _XELPDP_PORT_CLOCK_CTL_B, \
> _XELPDP_PORT_CLOCK_CTL_USBC1, \
> _XELPDP_PORT_CLOCK_CTL_USBC2))
>+#define XELPDP_PORT_CLOCK_CTL(i915__, port) \
>+ (DISPLAY_VER(i915__) >= 20 ? \
>+ _XELPDP_PORT_CLOCK_CTL(__xe2lpd_port_idx(port)) : \
>+ _XELPDP_PORT_CLOCK_CTL(port))
> #define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4))
> #define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4))
> #define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4))
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 53d8f13f8471..2509785daf7b 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -177,7 +177,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
> int ret;
>
> /* FIXME: find out why Bspec's 100us timeout is too short */
>- ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
>+ ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) &
> XELPDP_PORT_BUF_PHY_IDLE), 10000);
> if (ret)
> drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
>@@ -225,7 +225,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
> }
>
> if (DISPLAY_VER(dev_priv) >= 14)
>- ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
>+ ret = _wait_for(!(intel_de_read(dev_priv,
>+ XELPDP_PORT_BUF_CTL1(dev_priv, port)) &
>+ XELPDP_PORT_BUF_PHY_IDLE),
> timeout_us, 10, 10);
> else
> ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
>@@ -2366,7 +2368,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
> wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> } else {
>- reg = XELPDP_PORT_BUF_CTL1(port);
>+ reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);
> set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> }
>@@ -2386,7 +2388,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
> enum port port = encoder->port;
> u32 val;
>
>- val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
>+ val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
> val &= ~XELPDP_PORT_WIDTH_MASK;
> val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
>
>@@ -2399,7 +2401,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
> if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
> val |= XELPDP_PORT_REVERSAL;
>
>- intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
>+ intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val);
> }
>
> static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>@@ -2410,7 +2412,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
>
> val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
> XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
>- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
>+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
> XELPDP_PORT_BUF_IO_SELECT_TBT, val);
> }
>
>@@ -2830,7 +2832,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
> wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> } else {
>- reg = XELPDP_PORT_BUF_CTL1(port);
>+ reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);
> clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> }
>@@ -2968,7 +2970,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>
> /* De-select Thunderbolt */
> if (DISPLAY_VER(dev_priv) >= 14)
>- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
>+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port),
> XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
> }
>
>@@ -3241,7 +3243,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
> port_buf |= XELPDP_PORT_REVERSAL;
>
>- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
>+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port),
> XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
>
> dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
>diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
>index 3c94bbcb5497..678693978892 100644
>--- a/drivers/gpu/drm/i915/display/intel_tc.c
>+++ b/drivers/gpu/drm/i915/display/intel_tc.c
>@@ -958,10 +958,11 @@ xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc)
> {
> struct drm_i915_private *i915 = tc_to_i915(tc);
> enum port port = tc->dig_port->base.port;
>+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
>
> assert_tc_cold_blocked(tc);
>
>- return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TCSS_POWER_STATE;
>+ return intel_de_read(i915, reg) & XELPDP_TCSS_POWER_STATE;
> }
>
> static bool
>@@ -984,16 +985,17 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool ena
> {
> struct drm_i915_private *i915 = tc_to_i915(tc);
> enum port port = tc->dig_port->base.port;
>+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
> u32 val;
>
> assert_tc_cold_blocked(tc);
>
>- val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
>+ val = intel_de_read(i915, reg);
> if (enable)
> val |= XELPDP_TCSS_POWER_REQUEST;
> else
> val &= ~XELPDP_TCSS_POWER_REQUEST;
>- intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
>+ intel_de_write(i915, reg, val);
> }
>
> static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
>@@ -1020,26 +1022,28 @@ static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
> {
> struct drm_i915_private *i915 = tc_to_i915(tc);
> enum port port = tc->dig_port->base.port;
>+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
> u32 val;
>
> assert_tc_cold_blocked(tc);
>
>- val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
>+ val = intel_de_read(i915, reg);
> if (take)
> val |= XELPDP_TC_PHY_OWNERSHIP;
> else
> val &= ~XELPDP_TC_PHY_OWNERSHIP;
>- intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
>+ intel_de_write(i915, reg, val);
> }
>
> static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc)
> {
> struct drm_i915_private *i915 = tc_to_i915(tc);
> enum port port = tc->dig_port->base.port;
>+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
>
> assert_tc_cold_blocked(tc);
>
>- return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TC_PHY_OWNERSHIP;
>+ return intel_de_read(i915, reg) & XELPDP_TC_PHY_OWNERSHIP;
> }
>
> static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc)
>--
>2.40.1
>
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 10/27] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (8 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 09/27] drm/i915/xe2lpd: Move registers to PICA Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 11/27] drm/i915/xe2lpd: Register DE_RRMR has been removed Lucas De Marchi
` (17 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi, Matt Roper
From: Matt Roper <matthew.d.roper@intel.com>
Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers
like PLANE_AUX_DIST. However we currently have HAS_FLAT_CCS hardcoded
to 0 since compression isn't ready; we need to make sure this doesn't
cause the display code to go back to trying to write this register.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 517df2aa7a91..a73294e190df 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1247,7 +1247,7 @@ icl_plane_update_noarm(struct intel_plane *plane,
}
/* FLAT CCS doesn't need to program AUX_DIST */
- if (!HAS_FLAT_CCS(dev_priv))
+ if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20)
intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
skl_plane_aux_dist(plane_state, color_plane));
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 11/27] drm/i915/xe2lpd: Register DE_RRMR has been removed
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (9 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 10/27] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well Lucas De Marchi
` (16 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Matt Roper, Lucas De Marchi
From: Clint Taylor <clinton.a.taylor@intel.com>
Do not read DE_RRMR register after display version 20. This register
contains display state information during GFX state dumps.
Bspec: 69456
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4008bb09fdb5..a28681c15354 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1757,7 +1757,7 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
struct intel_uncore *uncore = gt->_gt->uncore;
struct drm_i915_private *i915 = uncore->i915;
- if (GRAPHICS_VER(i915) >= 6)
+ if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)
gt->derrmr = intel_uncore_read(uncore, DERRMR);
if (GRAPHICS_VER(i915) >= 8)
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (10 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 11/27] drm/i915/xe2lpd: Register DE_RRMR has been removed Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 16:53 ` Vodapalli, Ravi Kumar
` (3 more replies)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 13/27] drm/i915/xe2lpd: Add DC state support Lucas De Marchi
` (15 subsequent siblings)
27 siblings, 4 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Add Display Power Well for LNL platform, mostly it is same as MTL
platform so reused the code
Changes are:
1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
logic xelpdp_aux_power_well_ops functions.
2. PGPICA1 contains type-C capable port slices which requires the well
to power powered up, so added new power well definition for PGPICA1
FIXME: make this commit and "drm/i915/xe2lpd: Move registers to PICA"
to use a similar approach how the ranges are handled
BSpec: 68886
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../i915/display/intel_display_power_map.c | 36 ++++++++++-
.../i915/display/intel_display_power_well.c | 63 ++++++++++++++++++-
.../i915/display/intel_display_power_well.h | 1 +
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 26 ++++++++
4 files changed, 122 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 0f1b93d139ca..31c11586ede5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1536,6 +1536,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
};
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
+ POWER_DOMAIN_PORT_DDI_LANES_TC1,
+ POWER_DOMAIN_PORT_DDI_LANES_TC2,
+ POWER_DOMAIN_PORT_DDI_LANES_TC3,
+ POWER_DOMAIN_PORT_DDI_LANES_TC4,
+ POWER_DOMAIN_AUX_USBC1,
+ POWER_DOMAIN_AUX_USBC2,
+ POWER_DOMAIN_AUX_USBC3,
+ POWER_DOMAIN_AUX_USBC4,
+ POWER_DOMAIN_AUX_TBT1,
+ POWER_DOMAIN_AUX_TBT2,
+ POWER_DOMAIN_AUX_TBT3,
+ POWER_DOMAIN_AUX_TBT4,
+ POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
+ {
+ .instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
+ &xe2lpd_pwdoms_pica_tc,
+ .id = DISP_PW_ID_NONE),
+ ),
+ .ops = &xe2lpd_pica_power_well_ops,
+ },
+};
+
+static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
+ I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
+};
+
static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
@@ -1643,7 +1675,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
return 0;
}
- if (DISPLAY_VER(i915) >= 14)
+ if (DISPLAY_VER(i915) >= 20)
+ return set_power_wells(power_domains, xe2lpd_power_wells);
+ else if (DISPLAY_VER(i915) >= 14)
return set_power_wells(power_domains, xelpdp_power_wells);
else if (IS_DG2(i915))
return set_power_wells(power_domains, xehpd_power_wells);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 820b7d41a0a8..24fd35d5e4e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1800,7 +1800,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
icl_tc_port_assert_ref_held(dev_priv, power_well,
aux_ch_to_digital_port(dev_priv, aux_ch));
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ intel_de_rmw(dev_priv, aux_ch_ctl,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
@@ -1818,7 +1822,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
{
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ intel_de_rmw(dev_priv, aux_ch_ctl,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
0);
usleep_range(10, 30);
@@ -1828,11 +1836,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+ i915_reg_t aux_ch_ctl;
- return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
+ aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ return intel_de_read(dev_priv, aux_ch_ctl) &
XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
}
+static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_REQUEST,
+ XE2LPD_PICA_CTL_POWER_REQUEST);
+
+ if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+ drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
+
+ drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
+ }
+}
+
+static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_REQUEST,
+ 0);
+
+ if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+ drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
+
+ drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
+ }
+}
+
+static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
+ XE2LPD_PICA_CTL_POWER_STATUS;
+}
+
const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -1952,3 +2002,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
.disable = xelpdp_aux_power_well_disable,
.is_enabled = xelpdp_aux_power_well_enabled,
};
+
+const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = xe2lpd_pica_power_well_enable,
+ .disable = xe2lpd_pica_power_well_disable,
+ .is_enabled = xe2lpd_pica_power_well_enabled,
+};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index a8736588314d..9357a9a73c06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
extern const struct i915_power_well_ops icl_ddi_power_well_ops;
extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
+extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
index 5185345277c7..2dfc721e1bbd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
@@ -83,4 +83,30 @@
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
+#define _XE2LPD_DPA_AUX_CH_CTL 0x16fa10
+#define _XE2LPD_DPB_AUX_CH_CTL 0x16fc10
+#define _XE2LPD_DPA_AUX_CH_DATA1 0x16fa14
+#define _XE2LPD_DPB_AUX_CH_DATA1 0x16fc14
+#define XE2LPD_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
+ _XE2LPD_DPA_AUX_CH_CTL, \
+ _XE2LPD_DPB_AUX_CH_CTL, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_CTL, \
+ _XELPDP_USBC2_AUX_CH_CTL, \
+ _XELPDP_USBC3_AUX_CH_CTL, \
+ _XELPDP_USBC4_AUX_CH_CTL))
+#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
+ _XE2LPD_DPA_AUX_CH_DATA1, \
+ _XE2LPD_DPB_AUX_CH_DATA1, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_DATA1, \
+ _XELPDP_USBC2_AUX_CH_DATA1, \
+ _XELPDP_USBC3_AUX_CH_DATA1, \
+ _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+
+/* PICA Power Well Control register for Xe2 platforms*/
+#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
+#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
+#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30)
+
#endif /* __INTEL_DP_AUX_REGS_H__ */
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well Lucas De Marchi
@ 2023-09-07 16:53 ` Vodapalli, Ravi Kumar
2023-09-07 16:55 ` Vodapalli, Ravi Kumar
` (2 subsequent siblings)
3 siblings, 0 replies; 62+ messages in thread
From: Vodapalli, Ravi Kumar @ 2023-09-07 16:53 UTC (permalink / raw)
To: Lucas De Marchi, intel-xe, intel-gfx
Looks Good.
Reviewed-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Thanks,
Ravi Kumar V
On 9/7/2023 9:07 PM, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>
> Add Display Power Well for LNL platform, mostly it is same as MTL
> platform so reused the code
>
> Changes are:
> 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
> logic xelpdp_aux_power_well_ops functions.
> 2. PGPICA1 contains type-C capable port slices which requires the well
> to power powered up, so added new power well definition for PGPICA1
>
> FIXME: make this commit and "drm/i915/xe2lpd: Move registers to PICA"
> to use a similar approach how the ranges are handled
>
> BSpec: 68886
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../i915/display/intel_display_power_map.c | 36 ++++++++++-
> .../i915/display/intel_display_power_well.c | 63 ++++++++++++++++++-
> .../i915/display/intel_display_power_well.h | 1 +
> .../gpu/drm/i915/display/intel_dp_aux_regs.h | 26 ++++++++
> 4 files changed, 122 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 0f1b93d139ca..31c11586ede5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1536,6 +1536,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
> I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> };
>
> +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
> + POWER_DOMAIN_PORT_DDI_LANES_TC1,
> + POWER_DOMAIN_PORT_DDI_LANES_TC2,
> + POWER_DOMAIN_PORT_DDI_LANES_TC3,
> + POWER_DOMAIN_PORT_DDI_LANES_TC4,
> + POWER_DOMAIN_AUX_USBC1,
> + POWER_DOMAIN_AUX_USBC2,
> + POWER_DOMAIN_AUX_USBC3,
> + POWER_DOMAIN_AUX_USBC4,
> + POWER_DOMAIN_AUX_TBT1,
> + POWER_DOMAIN_AUX_TBT2,
> + POWER_DOMAIN_AUX_TBT3,
> + POWER_DOMAIN_AUX_TBT4,
> + POWER_DOMAIN_INIT);
> +
> +static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
> + {
> + .instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
> + &xe2lpd_pwdoms_pica_tc,
> + .id = DISP_PW_ID_NONE),
> + ),
> + .ops = &xe2lpd_pica_power_well_ops,
> + },
> +};
> +
> +static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
> + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> + I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> + I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> + I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
> +};
> +
> static void init_power_well_domains(const struct i915_power_well_instance *inst,
> struct i915_power_well *power_well)
> {
> @@ -1643,7 +1675,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
> return 0;
> }
>
> - if (DISPLAY_VER(i915) >= 14)
> + if (DISPLAY_VER(i915) >= 20)
> + return set_power_wells(power_domains, xe2lpd_power_wells);
> + else if (DISPLAY_VER(i915) >= 14)
> return set_power_wells(power_domains, xelpdp_power_wells);
> else if (IS_DG2(i915))
> return set_power_wells(power_domains, xehpd_power_wells);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 820b7d41a0a8..24fd35d5e4e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1800,7 +1800,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
> icl_tc_port_assert_ref_held(dev_priv, power_well,
> aux_ch_to_digital_port(dev_priv, aux_ch));
>
> - intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> + i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> + XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> + XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> + intel_de_rmw(dev_priv, aux_ch_ctl,
> XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
>
> @@ -1818,7 +1822,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
> {
> enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
>
> - intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> + i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> + XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> + XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> + intel_de_rmw(dev_priv, aux_ch_ctl,
> XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> 0);
> usleep_range(10, 30);
> @@ -1828,11 +1836,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> + i915_reg_t aux_ch_ctl;
>
> - return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
> + aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> + XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> + XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> + return intel_de_read(dev_priv, aux_ch_ctl) &
> XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
> }
>
> +static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_REQUEST,
> + XE2LPD_PICA_CTL_POWER_REQUEST);
> +
> + if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> + drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
> +
> + drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
> + }
> +}
> +
> +static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_REQUEST,
> + 0);
> +
> + if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> + drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
> +
> + drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
> + }
> +}
> +
> +static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
> + XE2LPD_PICA_CTL_POWER_STATUS;
> +}
> +
> const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> .enable = i9xx_always_on_power_well_noop,
> @@ -1952,3 +2002,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
> .disable = xelpdp_aux_power_well_disable,
> .is_enabled = xelpdp_aux_power_well_enabled,
> };
> +
> +const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = xe2lpd_pica_power_well_enable,
> + .disable = xe2lpd_pica_power_well_disable,
> + .is_enabled = xe2lpd_pica_power_well_enabled,
> +};
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index a8736588314d..9357a9a73c06 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
> extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
> extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
> +extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> index 5185345277c7..2dfc721e1bbd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> @@ -83,4 +83,30 @@
> #define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
> #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
>
> +#define _XE2LPD_DPA_AUX_CH_CTL 0x16fa10
> +#define _XE2LPD_DPB_AUX_CH_CTL 0x16fc10
> +#define _XE2LPD_DPA_AUX_CH_DATA1 0x16fa14
> +#define _XE2LPD_DPB_AUX_CH_DATA1 0x16fc14
> +#define XE2LPD_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
> + _XE2LPD_DPA_AUX_CH_CTL, \
> + _XE2LPD_DPB_AUX_CH_CTL, \
> + 0, /* port/aux_ch C is non-existent */ \
> + _XELPDP_USBC1_AUX_CH_CTL, \
> + _XELPDP_USBC2_AUX_CH_CTL, \
> + _XELPDP_USBC3_AUX_CH_CTL, \
> + _XELPDP_USBC4_AUX_CH_CTL))
> +#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
> + _XE2LPD_DPA_AUX_CH_DATA1, \
> + _XE2LPD_DPB_AUX_CH_DATA1, \
> + 0, /* port/aux_ch C is non-existent */ \
> + _XELPDP_USBC1_AUX_CH_DATA1, \
> + _XELPDP_USBC2_AUX_CH_DATA1, \
> + _XELPDP_USBC3_AUX_CH_DATA1, \
> + _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
> +
> +/* PICA Power Well Control register for Xe2 platforms*/
> +#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
> +#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
> +#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30)
> +
> #endif /* __INTEL_DP_AUX_REGS_H__ */
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well Lucas De Marchi
2023-09-07 16:53 ` Vodapalli, Ravi Kumar
@ 2023-09-07 16:55 ` Vodapalli, Ravi Kumar
2023-09-07 16:56 ` Vodapalli, Ravi Kumar
2023-09-07 17:57 ` Matt Roper
3 siblings, 0 replies; 62+ messages in thread
From: Vodapalli, Ravi Kumar @ 2023-09-07 16:55 UTC (permalink / raw)
To: De Marchi, Lucas, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
[-- Attachment #1: Type: text/plain, Size: 11107 bytes --]
Looks Good.
Reviewed-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com><mailto:ravi.kumar.vodapalli@intel.com>
Thanks,
Ravi Kumar V
On 9/7/2023 9:07 PM, Lucas De Marchi wrote:
From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com><mailto:ravi.kumar.vodapalli@intel.com>
Add Display Power Well for LNL platform, mostly it is same as MTL
platform so reused the code
Changes are:
1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
logic xelpdp_aux_power_well_ops functions.
2. PGPICA1 contains type-C capable port slices which requires the well
to power powered up, so added new power well definition for PGPICA1
FIXME: make this commit and "drm/i915/xe2lpd: Move registers to PICA"
to use a similar approach how the ranges are handled
BSpec: 68886
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com><mailto:ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com><mailto:gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com><mailto:lucas.demarchi@intel.com>
---
.../i915/display/intel_display_power_map.c | 36 ++++++++++-
.../i915/display/intel_display_power_well.c | 63 ++++++++++++++++++-
.../i915/display/intel_display_power_well.h | 1 +
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 26 ++++++++
4 files changed, 122 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 0f1b93d139ca..31c11586ede5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1536,6 +1536,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
};
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
+ POWER_DOMAIN_PORT_DDI_LANES_TC1,
+ POWER_DOMAIN_PORT_DDI_LANES_TC2,
+ POWER_DOMAIN_PORT_DDI_LANES_TC3,
+ POWER_DOMAIN_PORT_DDI_LANES_TC4,
+ POWER_DOMAIN_AUX_USBC1,
+ POWER_DOMAIN_AUX_USBC2,
+ POWER_DOMAIN_AUX_USBC3,
+ POWER_DOMAIN_AUX_USBC4,
+ POWER_DOMAIN_AUX_TBT1,
+ POWER_DOMAIN_AUX_TBT2,
+ POWER_DOMAIN_AUX_TBT3,
+ POWER_DOMAIN_AUX_TBT4,
+ POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
+ {
+ .instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
+ &xe2lpd_pwdoms_pica_tc,
+ .id = DISP_PW_ID_NONE),
+ ),
+ .ops = &xe2lpd_pica_power_well_ops,
+ },
+};
+
+static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
+ I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
+};
+
static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
@@ -1643,7 +1675,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
return 0;
}
- if (DISPLAY_VER(i915) >= 14)
+ if (DISPLAY_VER(i915) >= 20)
+ return set_power_wells(power_domains, xe2lpd_power_wells);
+ else if (DISPLAY_VER(i915) >= 14)
return set_power_wells(power_domains, xelpdp_power_wells);
else if (IS_DG2(i915))
return set_power_wells(power_domains, xehpd_power_wells);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 820b7d41a0a8..24fd35d5e4e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1800,7 +1800,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
icl_tc_port_assert_ref_held(dev_priv, power_well,
aux_ch_to_digital_port(dev_priv, aux_ch));
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ intel_de_rmw(dev_priv, aux_ch_ctl,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
@@ -1818,7 +1822,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
{
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ intel_de_rmw(dev_priv, aux_ch_ctl,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
0);
usleep_range(10, 30);
@@ -1828,11 +1836,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+ i915_reg_t aux_ch_ctl;
- return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
+ aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ return intel_de_read(dev_priv, aux_ch_ctl) &
XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
}
+static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_REQUEST,
+ XE2LPD_PICA_CTL_POWER_REQUEST);
+
+ if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+ drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
+
+ drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
+ }
+}
+
+static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_REQUEST,
+ 0);
+
+ if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+ drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
+
+ drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
+ }
+}
+
+static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
+ XE2LPD_PICA_CTL_POWER_STATUS;
+}
+
const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -1952,3 +2002,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
.disable = xelpdp_aux_power_well_disable,
.is_enabled = xelpdp_aux_power_well_enabled,
};
+
+const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = xe2lpd_pica_power_well_enable,
+ .disable = xe2lpd_pica_power_well_disable,
+ .is_enabled = xe2lpd_pica_power_well_enabled,
+};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index a8736588314d..9357a9a73c06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
extern const struct i915_power_well_ops icl_ddi_power_well_ops;
extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
+extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
index 5185345277c7..2dfc721e1bbd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
@@ -83,4 +83,30 @@
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
+#define _XE2LPD_DPA_AUX_CH_CTL 0x16fa10
+#define _XE2LPD_DPB_AUX_CH_CTL 0x16fc10
+#define _XE2LPD_DPA_AUX_CH_DATA1 0x16fa14
+#define _XE2LPD_DPB_AUX_CH_DATA1 0x16fc14
+#define XE2LPD_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
+ _XE2LPD_DPA_AUX_CH_CTL, \
+ _XE2LPD_DPB_AUX_CH_CTL, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_CTL, \
+ _XELPDP_USBC2_AUX_CH_CTL, \
+ _XELPDP_USBC3_AUX_CH_CTL, \
+ _XELPDP_USBC4_AUX_CH_CTL))
+#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
+ _XE2LPD_DPA_AUX_CH_DATA1, \
+ _XE2LPD_DPB_AUX_CH_DATA1, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_DATA1, \
+ _XELPDP_USBC2_AUX_CH_DATA1, \
+ _XELPDP_USBC3_AUX_CH_DATA1, \
+ _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+
+/* PICA Power Well Control register for Xe2 platforms*/
+#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
+#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
+#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30)
+
#endif /* __INTEL_DP_AUX_REGS_H__ */
[-- Attachment #2: Type: text/html, Size: 25806 bytes --]
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well Lucas De Marchi
2023-09-07 16:53 ` Vodapalli, Ravi Kumar
2023-09-07 16:55 ` Vodapalli, Ravi Kumar
@ 2023-09-07 16:56 ` Vodapalli, Ravi Kumar
2023-09-07 17:57 ` Matt Roper
3 siblings, 0 replies; 62+ messages in thread
From: Vodapalli, Ravi Kumar @ 2023-09-07 16:56 UTC (permalink / raw)
To: De Marchi, Lucas, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
[-- Attachment #1: Type: text/plain, Size: 11110 bytes --]
Looks Good.
Reviewed-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com><mailto:ravi.kumar.vodapalli@intel.com>
Thanks,
Ravi Kumar V On 9/7/2023 9:07 PM, Lucas De Marchi wrote:
From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com><mailto:ravi.kumar.vodapalli@intel.com>
Add Display Power Well for LNL platform, mostly it is same as MTL
platform so reused the code
Changes are:
1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
logic xelpdp_aux_power_well_ops functions.
2. PGPICA1 contains type-C capable port slices which requires the well
to power powered up, so added new power well definition for PGPICA1
FIXME: make this commit and "drm/i915/xe2lpd: Move registers to PICA"
to use a similar approach how the ranges are handled
BSpec: 68886
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com><mailto:ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com><mailto:gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com><mailto:lucas.demarchi@intel.com>
---
.../i915/display/intel_display_power_map.c | 36 ++++++++++-
.../i915/display/intel_display_power_well.c | 63 ++++++++++++++++++-
.../i915/display/intel_display_power_well.h | 1 +
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 26 ++++++++
4 files changed, 122 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 0f1b93d139ca..31c11586ede5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1536,6 +1536,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
};
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
+ POWER_DOMAIN_PORT_DDI_LANES_TC1,
+ POWER_DOMAIN_PORT_DDI_LANES_TC2,
+ POWER_DOMAIN_PORT_DDI_LANES_TC3,
+ POWER_DOMAIN_PORT_DDI_LANES_TC4,
+ POWER_DOMAIN_AUX_USBC1,
+ POWER_DOMAIN_AUX_USBC2,
+ POWER_DOMAIN_AUX_USBC3,
+ POWER_DOMAIN_AUX_USBC4,
+ POWER_DOMAIN_AUX_TBT1,
+ POWER_DOMAIN_AUX_TBT2,
+ POWER_DOMAIN_AUX_TBT3,
+ POWER_DOMAIN_AUX_TBT4,
+ POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
+ {
+ .instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
+ &xe2lpd_pwdoms_pica_tc,
+ .id = DISP_PW_ID_NONE),
+ ),
+ .ops = &xe2lpd_pica_power_well_ops,
+ },
+};
+
+static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
+ I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
+};
+
static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
@@ -1643,7 +1675,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
return 0;
}
- if (DISPLAY_VER(i915) >= 14)
+ if (DISPLAY_VER(i915) >= 20)
+ return set_power_wells(power_domains, xe2lpd_power_wells);
+ else if (DISPLAY_VER(i915) >= 14)
return set_power_wells(power_domains, xelpdp_power_wells);
else if (IS_DG2(i915))
return set_power_wells(power_domains, xehpd_power_wells);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 820b7d41a0a8..24fd35d5e4e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1800,7 +1800,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
icl_tc_port_assert_ref_held(dev_priv, power_well,
aux_ch_to_digital_port(dev_priv, aux_ch));
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ intel_de_rmw(dev_priv, aux_ch_ctl,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
@@ -1818,7 +1822,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
{
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ intel_de_rmw(dev_priv, aux_ch_ctl,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
0);
usleep_range(10, 30);
@@ -1828,11 +1836,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+ i915_reg_t aux_ch_ctl;
- return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
+ aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ return intel_de_read(dev_priv, aux_ch_ctl) &
XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
}
+static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_REQUEST,
+ XE2LPD_PICA_CTL_POWER_REQUEST);
+
+ if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+ drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
+
+ drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
+ }
+}
+
+static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_REQUEST,
+ 0);
+
+ if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+ drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
+
+ drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
+ }
+}
+
+static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
+ XE2LPD_PICA_CTL_POWER_STATUS;
+}
+
const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -1952,3 +2002,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
.disable = xelpdp_aux_power_well_disable,
.is_enabled = xelpdp_aux_power_well_enabled,
};
+
+const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = xe2lpd_pica_power_well_enable,
+ .disable = xe2lpd_pica_power_well_disable,
+ .is_enabled = xe2lpd_pica_power_well_enabled,
+};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index a8736588314d..9357a9a73c06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
extern const struct i915_power_well_ops icl_ddi_power_well_ops;
extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
+extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
index 5185345277c7..2dfc721e1bbd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
@@ -83,4 +83,30 @@
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
+#define _XE2LPD_DPA_AUX_CH_CTL 0x16fa10
+#define _XE2LPD_DPB_AUX_CH_CTL 0x16fc10
+#define _XE2LPD_DPA_AUX_CH_DATA1 0x16fa14
+#define _XE2LPD_DPB_AUX_CH_DATA1 0x16fc14
+#define XE2LPD_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
+ _XE2LPD_DPA_AUX_CH_CTL, \
+ _XE2LPD_DPB_AUX_CH_CTL, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_CTL, \
+ _XELPDP_USBC2_AUX_CH_CTL, \
+ _XELPDP_USBC3_AUX_CH_CTL, \
+ _XELPDP_USBC4_AUX_CH_CTL))
+#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
+ _XE2LPD_DPA_AUX_CH_DATA1, \
+ _XE2LPD_DPB_AUX_CH_DATA1, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_DATA1, \
+ _XELPDP_USBC2_AUX_CH_DATA1, \
+ _XELPDP_USBC3_AUX_CH_DATA1, \
+ _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+
+/* PICA Power Well Control register for Xe2 platforms*/
+#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
+#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
+#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30)
+
#endif /* __INTEL_DP_AUX_REGS_H__ */
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well Lucas De Marchi
` (2 preceding siblings ...)
2023-09-07 16:56 ` Vodapalli, Ravi Kumar
@ 2023-09-07 17:57 ` Matt Roper
2023-09-07 19:24 ` Lucas De Marchi
3 siblings, 1 reply; 62+ messages in thread
From: Matt Roper @ 2023-09-07 17:57 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 08:37:42AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>
> Add Display Power Well for LNL platform, mostly it is same as MTL
> platform so reused the code
>
> Changes are:
> 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
> logic xelpdp_aux_power_well_ops functions.
> 2. PGPICA1 contains type-C capable port slices which requires the well
> to power powered up, so added new power well definition for PGPICA1
>
> FIXME: make this commit and "drm/i915/xe2lpd: Move registers to PICA"
> to use a similar approach how the ranges are handled
Is this FIXME still planned before we apply this? Or are you expecting
to do it as a follow-up commit later?
Matt
>
> BSpec: 68886
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../i915/display/intel_display_power_map.c | 36 ++++++++++-
> .../i915/display/intel_display_power_well.c | 63 ++++++++++++++++++-
> .../i915/display/intel_display_power_well.h | 1 +
> .../gpu/drm/i915/display/intel_dp_aux_regs.h | 26 ++++++++
> 4 files changed, 122 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 0f1b93d139ca..31c11586ede5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1536,6 +1536,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
> I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> };
>
> +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
> + POWER_DOMAIN_PORT_DDI_LANES_TC1,
> + POWER_DOMAIN_PORT_DDI_LANES_TC2,
> + POWER_DOMAIN_PORT_DDI_LANES_TC3,
> + POWER_DOMAIN_PORT_DDI_LANES_TC4,
> + POWER_DOMAIN_AUX_USBC1,
> + POWER_DOMAIN_AUX_USBC2,
> + POWER_DOMAIN_AUX_USBC3,
> + POWER_DOMAIN_AUX_USBC4,
> + POWER_DOMAIN_AUX_TBT1,
> + POWER_DOMAIN_AUX_TBT2,
> + POWER_DOMAIN_AUX_TBT3,
> + POWER_DOMAIN_AUX_TBT4,
> + POWER_DOMAIN_INIT);
> +
> +static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
> + {
> + .instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
> + &xe2lpd_pwdoms_pica_tc,
> + .id = DISP_PW_ID_NONE),
> + ),
> + .ops = &xe2lpd_pica_power_well_ops,
> + },
> +};
> +
> +static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
> + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> + I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> + I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> + I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
> +};
> +
> static void init_power_well_domains(const struct i915_power_well_instance *inst,
> struct i915_power_well *power_well)
> {
> @@ -1643,7 +1675,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
> return 0;
> }
>
> - if (DISPLAY_VER(i915) >= 14)
> + if (DISPLAY_VER(i915) >= 20)
> + return set_power_wells(power_domains, xe2lpd_power_wells);
> + else if (DISPLAY_VER(i915) >= 14)
> return set_power_wells(power_domains, xelpdp_power_wells);
> else if (IS_DG2(i915))
> return set_power_wells(power_domains, xehpd_power_wells);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 820b7d41a0a8..24fd35d5e4e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1800,7 +1800,11 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
> icl_tc_port_assert_ref_held(dev_priv, power_well,
> aux_ch_to_digital_port(dev_priv, aux_ch));
>
> - intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> + i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> + XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> + XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> + intel_de_rmw(dev_priv, aux_ch_ctl,
> XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
>
> @@ -1818,7 +1822,11 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
> {
> enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
>
> - intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> + i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> + XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> + XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> + intel_de_rmw(dev_priv, aux_ch_ctl,
> XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> 0);
> usleep_range(10, 30);
> @@ -1828,11 +1836,53 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> + i915_reg_t aux_ch_ctl;
>
> - return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
> + aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> + XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> + XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> + return intel_de_read(dev_priv, aux_ch_ctl) &
> XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
> }
>
> +static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_REQUEST,
> + XE2LPD_PICA_CTL_POWER_REQUEST);
> +
> + if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> + drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
> +
> + drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
> + }
> +}
> +
> +static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_REQUEST,
> + 0);
> +
> + if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> + drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
> +
> + drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
> + }
> +}
> +
> +static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
> + XE2LPD_PICA_CTL_POWER_STATUS;
> +}
> +
> const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> .enable = i9xx_always_on_power_well_noop,
> @@ -1952,3 +2002,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
> .disable = xelpdp_aux_power_well_disable,
> .is_enabled = xelpdp_aux_power_well_enabled,
> };
> +
> +const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = xe2lpd_pica_power_well_enable,
> + .disable = xe2lpd_pica_power_well_disable,
> + .is_enabled = xe2lpd_pica_power_well_enabled,
> +};
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index a8736588314d..9357a9a73c06 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
> extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
> extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
> +extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> index 5185345277c7..2dfc721e1bbd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> @@ -83,4 +83,30 @@
> #define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
> #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
>
> +#define _XE2LPD_DPA_AUX_CH_CTL 0x16fa10
> +#define _XE2LPD_DPB_AUX_CH_CTL 0x16fc10
> +#define _XE2LPD_DPA_AUX_CH_DATA1 0x16fa14
> +#define _XE2LPD_DPB_AUX_CH_DATA1 0x16fc14
> +#define XE2LPD_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
> + _XE2LPD_DPA_AUX_CH_CTL, \
> + _XE2LPD_DPB_AUX_CH_CTL, \
> + 0, /* port/aux_ch C is non-existent */ \
> + _XELPDP_USBC1_AUX_CH_CTL, \
> + _XELPDP_USBC2_AUX_CH_CTL, \
> + _XELPDP_USBC3_AUX_CH_CTL, \
> + _XELPDP_USBC4_AUX_CH_CTL))
> +#define XE2LPD_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
> + _XE2LPD_DPA_AUX_CH_DATA1, \
> + _XE2LPD_DPB_AUX_CH_DATA1, \
> + 0, /* port/aux_ch C is non-existent */ \
> + _XELPDP_USBC1_AUX_CH_DATA1, \
> + _XELPDP_USBC2_AUX_CH_DATA1, \
> + _XELPDP_USBC3_AUX_CH_DATA1, \
> + _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
> +
> +/* PICA Power Well Control register for Xe2 platforms*/
> +#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
> +#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
> +#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30)
> +
> #endif /* __INTEL_DP_AUX_REGS_H__ */
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well
2023-09-07 17:57 ` Matt Roper
@ 2023-09-07 19:24 ` Lucas De Marchi
0 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 19:24 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 10:57:41AM -0700, Matt Roper wrote:
>On Thu, Sep 07, 2023 at 08:37:42AM -0700, Lucas De Marchi wrote:
>> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>>
>> Add Display Power Well for LNL platform, mostly it is same as MTL
>> platform so reused the code
>>
>> Changes are:
>> 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
>> logic xelpdp_aux_power_well_ops functions.
>> 2. PGPICA1 contains type-C capable port slices which requires the well
>> to power powered up, so added new power well definition for PGPICA1
>>
>> FIXME: make this commit and "drm/i915/xe2lpd: Move registers to PICA"
>> to use a similar approach how the ranges are handled
>
>Is this FIXME still planned before we apply this? Or are you expecting
>to do it as a follow-up commit later?
Before applying. What I'm looking for here is to get agreement on the
approach done in "drm/i915/xe2lpd: Move registers to PICA" as it changed
from v1 (even outside the feedback received).
Lucas De Marchi
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 13/27] drm/i915/xe2lpd: Add DC state support
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (11 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 14/27] drm/i915/display: Remove FBC capability from fused off pipes Lucas De Marchi
` (14 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi, Matt Roper
From: Matt Roper <matthew.d.roper@intel.com>
Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists). The
overall programming and requirements to enter DC states are similar to
those of Xe_LPD+ although AUX transactions do not require DC5/DC6 exit
as they did previously.
Bspec: 68851, 68857, 68886, 69115
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
.../gpu/drm/i915/display/intel_display_power.c | 4 +++-
.../drm/i915/display/intel_display_power_map.c | 18 ++++++++++++++++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 68cf5e6b0b46..a0d90a613ab3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -943,7 +943,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
if (!HAS_DISPLAY(dev_priv))
return 0;
- if (IS_DG2(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 20)
+ max_dc = 2;
+ else if (IS_DG2(dev_priv))
max_dc = 1;
else if (IS_DG1(dev_priv))
max_dc = 3;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 31c11586ede5..10948b3964ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1561,9 +1561,27 @@ static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
},
};
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off,
+ POWER_DOMAIN_DC_OFF,
+ XELPD_PW_C_POWER_DOMAINS,
+ XELPD_PW_D_POWER_DOMAINS,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = {
+ {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &xe2lpd_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
+ .ops = &gen9_dc_off_power_well_ops,
+ },
+};
+
static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff),
I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
};
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 14/27] drm/i915/display: Remove FBC capability from fused off pipes
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (12 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 13/27] drm/i915/xe2lpd: Add DC state support Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-08 8:55 ` [Intel-gfx] [Intel-xe] " Govindapillai, Vinod
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 15/27] FIXME: drm/i915/xe2lpd: Add support for DP aux channels Lucas De Marchi
` (13 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Matt Roper, Lucas De Marchi
From: Clint Taylor <clinton.a.taylor@intel.com>
If a particular pipe is disabled by fuse also remove the FBC for that
pipe.
Bspec: 69464
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 652e35ed7789..dc6cbd8bb31d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1024,16 +1024,19 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
display_runtime->pipe_mask &= ~BIT(PIPE_B);
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
}
if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
display_runtime->pipe_mask &= ~BIT(PIPE_C);
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
}
if (DISPLAY_VER(i915) >= 12 &&
(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
display_runtime->pipe_mask &= ~BIT(PIPE_D);
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
}
if (!display_runtime->pipe_mask)
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v2 14/27] drm/i915/display: Remove FBC capability from fused off pipes
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 14/27] drm/i915/display: Remove FBC capability from fused off pipes Lucas De Marchi
@ 2023-09-08 8:55 ` Govindapillai, Vinod
0 siblings, 0 replies; 62+ messages in thread
From: Govindapillai, Vinod @ 2023-09-08 8:55 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
De Marchi, Lucas
Cc: Roper, Matthew D
On Thu, 2023-09-07 at 08:37 -0700, Lucas De Marchi wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> If a particular pipe is disabled by fuse also remove the FBC for that
> pipe.
>
> Bspec: 69464
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 652e35ed7789..dc6cbd8bb31d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1024,16 +1024,19 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
> if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
> display_runtime->pipe_mask &= ~BIT(PIPE_B);
> display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
> + display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
> }
> if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
> display_runtime->pipe_mask &= ~BIT(PIPE_C);
> display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> + display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
> }
>
> if (DISPLAY_VER(i915) >= 12 &&
> (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
> display_runtime->pipe_mask &= ~BIT(PIPE_D);
> display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
> + display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
> }
>
> if (!display_runtime->pipe_mask)
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 15/27] FIXME: drm/i915/xe2lpd: Add support for DP aux channels
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (13 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 14/27] drm/i915/display: Remove FBC capability from fused off pipes Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 16/27] drm/i915/xe2lpd: Handle port AUX interrupts Lucas De Marchi
` (12 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Gustavo Sousa <gustavo.sousa@intel.com>
The location of aux channels registers for Xe2 display changed w.r.t.
the previous version.
FIXME: make this commit and "drm/i915/xe2lpd: Move registers to PICA"
to use a similar approach
BSpec: 69010
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 ++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 2d173bd495a3..929cada982ac 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -714,6 +714,44 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
}
}
+static i915_reg_t xe2lpd_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ return XE2LPD_DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return XE2LPD_DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t xe2lpd_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ return XE2LPD_DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return XE2LPD_DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
void intel_dp_aux_fini(struct intel_dp *intel_dp)
{
if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
@@ -729,7 +767,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
struct intel_encoder *encoder = &dig_port->base;
enum aux_ch aux_ch = dig_port->aux_ch;
- if (DISPLAY_VER(dev_priv) >= 14) {
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ intel_dp->aux_ch_ctl_reg = xe2lpd_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = xe2lpd_aux_data_reg;
+ } else if (DISPLAY_VER(dev_priv) >= 14) {
intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
} else if (DISPLAY_VER(dev_priv) >= 12) {
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 16/27] drm/i915/xe2lpd: Handle port AUX interrupts
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (14 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 15/27] FIXME: drm/i915/xe2lpd: Add support for DP aux channels Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 17/27] drm/i915/xe2lpd: Read pin assignment from IOM Lucas De Marchi
` (11 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi, Matt Roper
From: Gustavo Sousa <gustavo.sousa@intel.com>
Differently from previous version, Xe2_LPD groups all port AUX interrupt
bits into PICA interrupt registers.
While at it, drop some trailing newlines.
BSpec: 68958, 69697
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 5 ++---
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 62ce55475554..bff4a76310c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(dev_priv) >= 20)
+ return 0;
+ else if (DISPLAY_VER(dev_priv) >= 14)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB;
else if (DISPLAY_VER(dev_priv) >= 13)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 95a7ea94f417..3398cc21bd26 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -514,6 +514,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
u32 pin_mask = 0, long_mask = 0;
+ if (DISPLAY_VER(i915) >= 20)
+ trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
+
for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
u32 val;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f5dd5361263..2f115d339913 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4467,13 +4467,12 @@
#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
-
#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
-
#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
-
+#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
+#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 17/27] drm/i915/xe2lpd: Read pin assignment from IOM
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (15 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 16/27] drm/i915/xe2lpd: Handle port AUX interrupts Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-08 6:55 ` Kahola, Mika
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 18/27] drm/i915/xe2lpd: Enable odd size and panning for planar yuv Lucas De Marchi
` (10 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi, Matt Roper, Luca Coelho
From: Luca Coelho <luciano.coelho@intel.com>
Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.
We use the pin assignment to decide the maximum lane count. So, to
support this change, add a new lnl_tc_port_get_max_lane_count() function
that reads from the TCSS_DDI_STATUS register and decides the maximum
lane count based on that.
BSpec: 69594
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 678693978892..e9ced251c170 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
}
+static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ intel_wakeref_t wakeref;
+ u32 val, pin_assignment;
+
+ with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+ val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
+
+ pin_assignment =
+ REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
+
+ switch (pin_assignment) {
+ default:
+ MISSING_CASE(pin_assignment);
+ fallthrough;
+ case DP_PIN_ASSIGNMENT_D:
+ return 2;
+ case DP_PIN_ASSIGNMENT_C:
+ case DP_PIN_ASSIGNMENT_E:
+ return 4;
+ }
+}
+
static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -348,6 +373,9 @@ int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
assert_tc_cold_blocked(tc);
+ if (DISPLAY_VER(i915) >= 20)
+ return lnl_tc_port_get_max_lane_count(dig_port);
+
if (DISPLAY_VER(i915) >= 14)
return mtl_tc_port_get_max_lane_count(dig_port);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f115d339913..efcf1461988f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6351,6 +6351,7 @@ enum skl_power_gate {
#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
_TCSS_DDI_STATUS_1, \
_TCSS_DDI_STATUS_2))
+#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
#define TCSS_DDI_STATUS_READY REG_BIT(2)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 17/27] drm/i915/xe2lpd: Read pin assignment from IOM
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 17/27] drm/i915/xe2lpd: Read pin assignment from IOM Lucas De Marchi
@ 2023-09-08 6:55 ` Kahola, Mika
0 siblings, 0 replies; 62+ messages in thread
From: Kahola, Mika @ 2023-09-08 6:55 UTC (permalink / raw)
To: De Marchi, Lucas, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Roper, Matthew D, Coelho, Luciano
> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Thursday, September 7, 2023 6:38 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Coelho, Luciano <luciano.coelho@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: [PATCH v2 17/27] drm/i915/xe2lpd: Read pin assignment from IOM
>
> From: Luca Coelho <luciano.coelho@intel.com>
>
> Starting from display version 20, we need to read the pin assignment from the IOM TCSS_DDI_STATUS register instead of reading it
> from the FIA.
>
> We use the pin assignment to decide the maximum lane count. So, to support this change, add a new
> lnl_tc_port_get_max_lane_count() function that reads from the TCSS_DDI_STATUS register and decides the maximum lane count
> based on that.
>
> BSpec: 69594
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 678693978892..e9ced251c170 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
> }
>
> +static int lnl_tc_port_get_max_lane_count(struct intel_digital_port
> +*dig_port) {
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> + intel_wakeref_t wakeref;
> + u32 val, pin_assignment;
> +
> + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> + val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
> +
> + pin_assignment =
> + REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
> +
> + switch (pin_assignment) {
> + default:
> + MISSING_CASE(pin_assignment);
> + fallthrough;
> + case DP_PIN_ASSIGNMENT_D:
> + return 2;
> + case DP_PIN_ASSIGNMENT_C:
> + case DP_PIN_ASSIGNMENT_E:
> + return 4;
> + }
> +}
> +
> static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ -348,6 +373,9 @@ int
> intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
>
> assert_tc_cold_blocked(tc);
>
> + if (DISPLAY_VER(i915) >= 20)
> + return lnl_tc_port_get_max_lane_count(dig_port);
> +
> if (DISPLAY_VER(i915) >= 14)
> return mtl_tc_port_get_max_lane_count(dig_port);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2f115d339913..efcf1461988f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6351,6 +6351,7 @@ enum skl_power_gate {
> #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
> _TCSS_DDI_STATUS_1, \
> _TCSS_DDI_STATUS_2))
> +#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
> #define TCSS_DDI_STATUS_READY REG_BIT(2)
> #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
> #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
> --
> 2.40.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 18/27] drm/i915/xe2lpd: Enable odd size and panning for planar yuv
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (16 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 17/27] drm/i915/xe2lpd: Read pin assignment from IOM Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 19/27] drm/i915/xe2lpd: Add support for HPD Lucas De Marchi
` (9 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi, Juha-Pekka Heikkilä
From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Enable odd size and panning for planar yuv formats.
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d7a0bd686e49..b1074350616c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -981,6 +981,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
hsub = 2;
vsub = 2;
+ } else if (DISPLAY_VER(i915) >= 20 &&
+ intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+ /*
+ * This allows NV12 and P0xx formats to have odd size and/or odd
+ * source coordinates on DISPLAY_VER(i915) >= 20
+ */
+ hsub = 1;
+ vsub = 1;
} else {
hsub = fb->format->hsub;
vsub = fb->format->vsub;
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 19/27] drm/i915/xe2lpd: Add support for HPD
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (17 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 18/27] drm/i915/xe2lpd: Enable odd size and panning for planar yuv Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 20:42 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 20/27] drm/i915/xe2lpd: Extend Wa_15010685871 Lucas De Marchi
` (8 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Gustavo Sousa <gustavo.sousa@intel.com>
Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
extra programming for hotplug inversion and DDI HPD filter duration is
not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
prefer to fork it into a new function for Xe2_LPD instead of adding a
platform check.
v2: Add extra bspec reference and fix missing else (Matt Roper)
BSpec: 68970, 69940
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/display/intel_hotplug_irq.c | 21 +++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 3398cc21bd26..f07047e9cb30 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -163,7 +163,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
(!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
return;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
+ hpd->pch_hpd = hpd_mtp;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
hpd->pch_hpd = hpd_sde_dg1;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
hpd->pch_hpd = hpd_mtp;
@@ -1063,6 +1065,19 @@ static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
mtp_tc_hpd_detection_setup(i915);
}
+static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
+{
+ u32 hotplug_irqs, enabled_irqs;
+
+ enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
+
+ ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
+
+ mtp_ddi_hpd_detection_setup(i915);
+ mtp_tc_hpd_detection_setup(i915);
+}
+
static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
{
return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
@@ -1122,7 +1137,9 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
xelpdp_pica_hpd_detection_setup(i915);
- if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
+ xe2lpd_sde_hpd_irq_setup(i915);
+ else if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
mtp_hpd_irq_setup(i915);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 19/27] drm/i915/xe2lpd: Add support for HPD
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 19/27] drm/i915/xe2lpd: Add support for HPD Lucas De Marchi
@ 2023-09-07 20:42 ` Matt Roper
0 siblings, 0 replies; 62+ messages in thread
From: Matt Roper @ 2023-09-07 20:42 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 08:37:49AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
>
> Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
> extra programming for hotplug inversion and DDI HPD filter duration is
> not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
> prefer to fork it into a new function for Xe2_LPD instead of adding a
> platform check.
>
> v2: Add extra bspec reference and fix missing else (Matt Roper)
>
> BSpec: 68970, 69940
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
This matches the spec, so
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
However the programming of SHPD_FILTER_CNT on Meteor Lake was never
something that was documented in the bspec; it looks like it was added
in 4948738e296c ("drm/i915/hotplug: Reduce SHPD_FILTER to 250us") and
tracing back the discussion there is looks like we decided we didn't
like the steps that were actually suggested for Wa_14013120569 and just
decided to do our own thing rather than working with the hardware team
to clarify/update/fix the officially documented workaround. Even
ignoring the fact that that wasn't an appropriate process for handling
workarounds, Wa_14013120569 (which was the true impetus here) isn't
listed as applying to MTL either, so we probably shouldn't really be
programming SHPD_FILTER_CNT in mtp_hpd_irq_setup either.
Matt
> ---
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 21 +++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index 3398cc21bd26..f07047e9cb30 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -163,7 +163,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
> return;
>
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
> + hpd->pch_hpd = hpd_mtp;
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> hpd->pch_hpd = hpd_sde_dg1;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
> hpd->pch_hpd = hpd_mtp;
> @@ -1063,6 +1065,19 @@ static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
> mtp_tc_hpd_detection_setup(i915);
> }
>
> +static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
> +{
> + u32 hotplug_irqs, enabled_irqs;
> +
> + enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
> +
> + ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
> +
> + mtp_ddi_hpd_detection_setup(i915);
> + mtp_tc_hpd_detection_setup(i915);
> +}
> +
> static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
> {
> return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
> @@ -1122,7 +1137,9 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
>
> xelpdp_pica_hpd_detection_setup(i915);
>
> - if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
> + if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
> + xe2lpd_sde_hpd_irq_setup(i915);
> + else if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
> mtp_hpd_irq_setup(i915);
> }
>
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 20/27] drm/i915/xe2lpd: Extend Wa_15010685871
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (18 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 19/27] drm/i915/xe2lpd: Add support for HPD Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 20:52 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 21/27] drm/i915/lnl: Add gmbus/ddc support Lucas De Marchi
` (7 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
Xe2_LPD also needs workaround 15010685871. While adding the new display
version, also re-order the condition to follow the convention of new
version first.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad5251ba6fe1..cfd01050f7f1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1841,9 +1841,10 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
{
- return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0)) &&
- dev_priv->display.cdclk.hw.vco > 0 &&
- HAS_CDCLK_SQUASH(dev_priv));
+ return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) ||
+ DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) ||
+ IS_DG2(dev_priv)) && dev_priv->display.cdclk.hw.vco > 0 &&
+ HAS_CDCLK_SQUASH(dev_priv);
}
static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 20/27] drm/i915/xe2lpd: Extend Wa_15010685871
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 20/27] drm/i915/xe2lpd: Extend Wa_15010685871 Lucas De Marchi
@ 2023-09-07 20:52 ` Matt Roper
0 siblings, 0 replies; 62+ messages in thread
From: Matt Roper @ 2023-09-07 20:52 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 08:37:50AM -0700, Lucas De Marchi wrote:
> Xe2_LPD also needs workaround 15010685871. While adding the new display
> version, also re-order the condition to follow the convention of new
> version first.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ad5251ba6fe1..cfd01050f7f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1841,9 +1841,10 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
>
> static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
> {
> - return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0)) &&
> - dev_priv->display.cdclk.hw.vco > 0 &&
> - HAS_CDCLK_SQUASH(dev_priv));
> + return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) ||
> + DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) ||
> + IS_DG2(dev_priv)) && dev_priv->display.cdclk.hw.vco > 0 &&
> + HAS_CDCLK_SQUASH(dev_priv);
Since this workaround seems to be needed on every squashing platform
from version 13 to version 20, we could probably even simplify down to
IS_DISPLAY_IP_RANGE(dev_priv, IP_VER(13, 0), IP_VER(20, 0)) && ...
The only risk would be if some refresh platform shows up in the future
in the middle of that range in the future and doesn't need the
workaround, but I'm not sure how likely that is at this point.
That IP range would also technically capture ADL-P (version 13.0), but
since the workaround is also conditional on HAS_CDCLK_SQUASH, it will be
filtered out by that check. If you decide to keep the three platform/IP
checks separate, then you can instead drop the HAS_CDCLK_SQUASH part of
the condition since all affected platforms have squashing support (which
is what the workaround is reprogramming).
Up to you as to whether you'd rather consolidate the range or drop the
redundant HAS_CDCLK_SQUASH condition, but either way,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> }
>
> static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 21/27] drm/i915/lnl: Add gmbus/ddc support
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (19 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 20/27] drm/i915/xe2lpd: Extend Wa_15010685871 Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 22/27] drm/i915/lnl: Add CDCLK table Lucas De Marchi
` (6 subsequent siblings)
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Matt Roper, Lucas De Marchi
LNL's south display uses the same table as MTP. Check for LNL's fake PCH
to make it consistent with the other checks.
The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
other cases, uses the same as the previous platform.
Bspec: 68971, 20124
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 3 ++-
drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 858c959f7bab..1555769762f6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2194,7 +2194,8 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
const u8 *ddc_pin_map;
int i, n_entries;
- if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||
+ IS_ALDERLAKE_P(i915)) {
ddc_pin_map = adlp_ddc_pin_map;
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
} else if (IS_ALDERLAKE_S(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index e95ddb580ef6..801fabbccf7e 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
const struct gmbus_pin *pins;
size_t size;
- if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
+ pins = gmbus_pins_mtp;
+ size = ARRAY_SIZE(gmbus_pins_mtp);
+ } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
pins = gmbus_pins_dg2;
size = ARRAY_SIZE(gmbus_pins_dg2);
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 22/27] drm/i915/lnl: Add CDCLK table
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (20 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 21/27] drm/i915/lnl: Add gmbus/ddc support Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 21:52 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 23/27] drm/i915/lnl: Start using CDCLK through PLL Lucas De Marchi
` (5 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Add a new Lunar Lake CDCLK table from BSpec and also a helper function
in order to be able to find lowest possible CDCLK.
v2:
- Remove mdclk from the table as it's not needed (Matt Roper)
- Update waveform values to the latest from spec (Matt Roper)
- Rename functions and calculation to match by pixel rate (Lucas)
Bspec: 68861
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 55 +++++++++++++++++++++-
1 file changed, 53 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cfd01050f7f1..7307af2a4af5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1382,6 +1382,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals lnl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
+ { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
+ { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -2504,12 +2529,35 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
}
}
+static int
+xe2lpd_cdclk_match_by_pixel_rate(struct drm_i915_private *i915, int pixel_rate)
+{
+ const struct intel_cdclk_vals *table = i915->display.cdclk.table;
+ int i;
+
+ for (i = 0; table[i].refclk; i++) {
+ if (table[i].refclk != i915->display.cdclk.hw.ref)
+ continue;
+
+ if (table[i].refclk * table[i].ratio >= pixel_rate)
+ return table[i].cdclk;
+ }
+
+ drm_WARN(&i915->drm, 1,
+ "Cannot satisfy pixel rate %d with refclk %u\n",
+ pixel_rate, i915->display.cdclk.hw.ref);
+
+ return 0;
+}
+
static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int pixel_rate = crtc_state->pixel_rate;
- if (DISPLAY_VER(dev_priv) >= 10)
+ if (DISPLAY_VER(dev_priv) >= 20)
+ return xe2lpd_cdclk_match_by_pixel_rate(dev_priv, pixel_rate);
+ else if (DISPLAY_VER(dev_priv) >= 10)
return DIV_ROUND_UP(pixel_rate, 2);
else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
@@ -3591,7 +3639,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (DISPLAY_VER(dev_priv) >= 14) {
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = lnl_cdclk_table;
+ } else if (DISPLAY_VER(dev_priv) >= 14) {
dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
dev_priv->display.cdclk.table = mtl_cdclk_table;
} else if (IS_DG2(dev_priv)) {
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 22/27] drm/i915/lnl: Add CDCLK table
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 22/27] drm/i915/lnl: Add CDCLK table Lucas De Marchi
@ 2023-09-07 21:52 ` Matt Roper
2023-09-07 22:48 ` Matt Roper
0 siblings, 1 reply; 62+ messages in thread
From: Matt Roper @ 2023-09-07 21:52 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 08:37:52AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Add a new Lunar Lake CDCLK table from BSpec and also a helper function
> in order to be able to find lowest possible CDCLK.
>
> v2:
> - Remove mdclk from the table as it's not needed (Matt Roper)
> - Update waveform values to the latest from spec (Matt Roper)
> - Rename functions and calculation to match by pixel rate (Lucas)
>
> Bspec: 68861
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 55 +++++++++++++++++++++-
> 1 file changed, 53 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index cfd01050f7f1..7307af2a4af5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1382,6 +1382,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> {}
> };
>
> +static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> + { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> + { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> + { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> + { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> + { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> + { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> + { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> + { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> + { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> + { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> + { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> + { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> + {}
> +};
> +
> static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> {
> const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> @@ -2504,12 +2529,35 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> }
> }
>
> +static int
> +xe2lpd_cdclk_match_by_pixel_rate(struct drm_i915_private *i915, int pixel_rate)
> +{
> + const struct intel_cdclk_vals *table = i915->display.cdclk.table;
> + int i;
> +
> + for (i = 0; table[i].refclk; i++) {
> + if (table[i].refclk != i915->display.cdclk.hw.ref)
> + continue;
> +
> + if (table[i].refclk * table[i].ratio >= pixel_rate)
> + return table[i].cdclk;
> + }
> +
> + drm_WARN(&i915->drm, 1,
> + "Cannot satisfy pixel rate %d with refclk %u\n",
> + pixel_rate, i915->display.cdclk.hw.ref);
> +
> + return 0;
> +}
> +
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int pixel_rate = crtc_state->pixel_rate;
>
> - if (DISPLAY_VER(dev_priv) >= 10)
> + if (DISPLAY_VER(dev_priv) >= 20)
> + return xe2lpd_cdclk_match_by_pixel_rate(dev_priv, pixel_rate);
Is this actually what we want to be doing? Generally this function
returns a minimum possible value cdclk value that could support the
pixel rate (e.g., pixel_rate / 2 on modern platforms), without caring
(yet) about the set of cdclk values that the platform is capable of
generating. We then do some additional CRTC-level or device-level
adjustments to that minimum in intel_crtc_compute_min_cdclk and
intel_compute_min_cdclk, and only at the very end of the process (in
bxt_calc_cdclk) do we go into the table to find the lowest possible
clock greater than or equal to the adjusted minimum we had calculated.
From what I can see, the minimum cdclk (as far as this specific function
is concerned) should still be half the pixel rate on Xe2 (bspec 68858:
"Pipe maximum pixel rate = 2 * CDCLK frequency * Pipe Ratio"). The only
thing that really changes with all the mdclk stuff is that cdclk and
mdclk are no longer fundamentally locked together in hardware; that's
why the table of possible cdclk settings in the bspec now has additional
rows where the cdclk value ranges anywhere from mdclk/4 to mdclk/2
(whereas on previous platforms every single row corresponded to an
mdclk/2 value).
tl;dr: I don't think we want/need this hunk of the patch.
Matt
> + else if (DISPLAY_VER(dev_priv) >= 10)
> return DIV_ROUND_UP(pixel_rate, 2);
> else if (DISPLAY_VER(dev_priv) == 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> @@ -3591,7 +3639,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
> */
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> {
> - if (DISPLAY_VER(dev_priv) >= 14) {
> + if (DISPLAY_VER(dev_priv) >= 20) {
> + dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> + dev_priv->display.cdclk.table = lnl_cdclk_table;
> + } else if (DISPLAY_VER(dev_priv) >= 14) {
> dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> dev_priv->display.cdclk.table = mtl_cdclk_table;
> } else if (IS_DG2(dev_priv)) {
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 22/27] drm/i915/lnl: Add CDCLK table
2023-09-07 21:52 ` Matt Roper
@ 2023-09-07 22:48 ` Matt Roper
0 siblings, 0 replies; 62+ messages in thread
From: Matt Roper @ 2023-09-07 22:48 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 02:52:06PM -0700, Matt Roper wrote:
> On Thu, Sep 07, 2023 at 08:37:52AM -0700, Lucas De Marchi wrote:
> > From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> >
> > Add a new Lunar Lake CDCLK table from BSpec and also a helper function
> > in order to be able to find lowest possible CDCLK.
> >
> > v2:
> > - Remove mdclk from the table as it's not needed (Matt Roper)
> > - Update waveform values to the latest from spec (Matt Roper)
> > - Rename functions and calculation to match by pixel rate (Lucas)
> >
> > Bspec: 68861
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 55 +++++++++++++++++++++-
> > 1 file changed, 53 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index cfd01050f7f1..7307af2a4af5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1382,6 +1382,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> > {}
> > };
> >
> > +static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> > + { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> > + { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > + { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> > + { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> > + { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> > + { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> > + { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> > + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> > + { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> > + { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> > + { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> > + { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> > + { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> > + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> > + { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> > + { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> > + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> > + { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > + { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > + {}
> > +};
> > +
> > static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> > {
> > const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> > @@ -2504,12 +2529,35 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> > }
> > }
> >
> > +static int
> > +xe2lpd_cdclk_match_by_pixel_rate(struct drm_i915_private *i915, int pixel_rate)
> > +{
> > + const struct intel_cdclk_vals *table = i915->display.cdclk.table;
> > + int i;
> > +
> > + for (i = 0; table[i].refclk; i++) {
> > + if (table[i].refclk != i915->display.cdclk.hw.ref)
> > + continue;
> > +
> > + if (table[i].refclk * table[i].ratio >= pixel_rate)
> > + return table[i].cdclk;
> > + }
> > +
> > + drm_WARN(&i915->drm, 1,
> > + "Cannot satisfy pixel rate %d with refclk %u\n",
> > + pixel_rate, i915->display.cdclk.hw.ref);
> > +
> > + return 0;
> > +}
> > +
> > static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > int pixel_rate = crtc_state->pixel_rate;
> >
> > - if (DISPLAY_VER(dev_priv) >= 10)
> > + if (DISPLAY_VER(dev_priv) >= 20)
> > + return xe2lpd_cdclk_match_by_pixel_rate(dev_priv, pixel_rate);
>
> Is this actually what we want to be doing? Generally this function
> returns a minimum possible value cdclk value that could support the
> pixel rate (e.g., pixel_rate / 2 on modern platforms), without caring
> (yet) about the set of cdclk values that the platform is capable of
> generating. We then do some additional CRTC-level or device-level
> adjustments to that minimum in intel_crtc_compute_min_cdclk and
> intel_compute_min_cdclk, and only at the very end of the process (in
> bxt_calc_cdclk) do we go into the table to find the lowest possible
> clock greater than or equal to the adjusted minimum we had calculated.
>
> From what I can see, the minimum cdclk (as far as this specific function
> is concerned) should still be half the pixel rate on Xe2 (bspec 68858:
> "Pipe maximum pixel rate = 2 * CDCLK frequency * Pipe Ratio"). The only
> thing that really changes with all the mdclk stuff is that cdclk and
> mdclk are no longer fundamentally locked together in hardware; that's
> why the table of possible cdclk settings in the bspec now has additional
> rows where the cdclk value ranges anywhere from mdclk/4 to mdclk/2
> (whereas on previous platforms every single row corresponded to an
> mdclk/2 value).
>
> tl;dr: I don't think we want/need this hunk of the patch.
>
BTW, completely unrelated to this LNL-specific patch, but since I'm
looking at this area of the code again, I'm questioning whether the
general logic in bxt_cdclk_cd2x_div_sel is correct for platforms that
have squashing (DG2, MTL, LNL, etc.). Now that we can reach multiple
effective cdclk values with a single PLL ratio / VCO setting, it seems
like this logic can no longer going to properly derive the CD2X divider
from VCO. And we seem to be relying on that function to program
the divider in CDCLK_CTL rather than using the value that was provided
in the table.
If I remember correctly there were some unexplained underruns seen on
DG2 before we hacked the cdclk to a higher value than expected; maybe
this is the explanation for that? Sometimes you'd get lucky and wind up
with the right divider in the end, other times you'd select it
incorrectly and wind up with something that didn't match the value
specified in the table.
Matt
>
> Matt
>
> > + else if (DISPLAY_VER(dev_priv) >= 10)
> > return DIV_ROUND_UP(pixel_rate, 2);
> > else if (DISPLAY_VER(dev_priv) == 9 ||
> > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > @@ -3591,7 +3639,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
> > */
> > void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> > {
> > - if (DISPLAY_VER(dev_priv) >= 14) {
> > + if (DISPLAY_VER(dev_priv) >= 20) {
> > + dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> > + dev_priv->display.cdclk.table = lnl_cdclk_table;
> > + } else if (DISPLAY_VER(dev_priv) >= 14) {
> > dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> > dev_priv->display.cdclk.table = mtl_cdclk_table;
> > } else if (IS_DG2(dev_priv)) {
> > --
> > 2.40.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 23/27] drm/i915/lnl: Start using CDCLK through PLL
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (21 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 22/27] drm/i915/lnl: Add CDCLK table Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 22:13 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 24/27] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf Lucas De Marchi
` (4 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Introduce correspondent definitions and for choosing between CD2X CDCLK
and PLL CDCLK as a source. All the entries in cdclk table for xe2lpd are
defined with PLL CDCLK as source, so simply set it.
v2:
- Remove unneeded comment and use REG_BIT() (Matt Roper)
- Rename CDCLK_SOURCE_SEL_CDCLK_PLL() to MDCLK_SOURCE_SEL_CDCLK_PLL
to match spec (Lucas)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 9 +++++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7307af2a4af5..abe845906c7c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1906,8 +1906,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
dg2_cdclk_squash_program(dev_priv, waveform);
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
- bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
- skl_cdclk_decimal(cdclk);
+ bxt_cdclk_cd2x_pipe(dev_priv, pipe);
/*
* Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -1916,6 +1915,12 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
cdclk >= 500000)
val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+
+ if (DISPLAY_VER(dev_priv) >= 20)
+ val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
+ else
+ val |= skl_cdclk_decimal(cdclk);
+
intel_de_write(dev_priv, CDCLK_CTL, val);
if (pipe != INVALID_PIPE)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index efcf1461988f..c59eb411cf06 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5884,6 +5884,7 @@ enum skl_power_gate {
#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
+#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_BIT(25)
#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
#define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
#define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 23/27] drm/i915/lnl: Start using CDCLK through PLL
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 23/27] drm/i915/lnl: Start using CDCLK through PLL Lucas De Marchi
@ 2023-09-07 22:13 ` Matt Roper
0 siblings, 0 replies; 62+ messages in thread
From: Matt Roper @ 2023-09-07 22:13 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 08:37:53AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Introduce correspondent definitions and for choosing between CD2X CDCLK
> and PLL CDCLK as a source. All the entries in cdclk table for xe2lpd are
> defined with PLL CDCLK as source, so simply set it.
There should probably be some mention of removing the cdclk value field
as well since it's technically unrelated to the clock source stuff
described above.
With an extra sentence added,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Matt
>
> v2:
> - Remove unneeded comment and use REG_BIT() (Matt Roper)
> - Rename CDCLK_SOURCE_SEL_CDCLK_PLL() to MDCLK_SOURCE_SEL_CDCLK_PLL
> to match spec (Lucas)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 9 +++++++--
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 7307af2a4af5..abe845906c7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1906,8 +1906,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> dg2_cdclk_squash_program(dev_priv, waveform);
>
> val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
> - bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> - skl_cdclk_decimal(cdclk);
> + bxt_cdclk_cd2x_pipe(dev_priv, pipe);
>
> /*
> * Disable SSA Precharge when CD clock frequency < 500 MHz,
> @@ -1916,6 +1915,12 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
> cdclk >= 500000)
> val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> +
> + if (DISPLAY_VER(dev_priv) >= 20)
> + val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
> + else
> + val |= skl_cdclk_decimal(cdclk);
> +
> intel_de_write(dev_priv, CDCLK_CTL, val);
>
> if (pipe != INVALID_PIPE)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index efcf1461988f..c59eb411cf06 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5884,6 +5884,7 @@ enum skl_power_gate {
> #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
> #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
> #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
> +#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_BIT(25)
> #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
> #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
> #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 24/27] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (22 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 23/27] drm/i915/lnl: Start using CDCLK through PLL Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-08 22:43 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 25/27] drm/i915/lnl: Add support for CDCLK initialization sequence Lucas De Marchi
` (3 subsequent siblings)
27 siblings, 1 reply; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
change.
Previsouly DBuf state and CDCLK were not anyhow coupled together. Now
at compute stage when we know which CDCLK/MDCLK we are going to use, we
need to update the DBuf state with that ratio, being properly encoded,
so that it gets written to those registers, once DBuf state is being
update. The criteria for updating DBuf state is also a CDCLK/MDCLK ratio
change now.
v2:
- Remove condition check for display version 20 since it's compatible
with previous versions (Matt Roper)
- Squash the serialization of global state when mdclk_cdclk_ratio
changes
Bspec: 68864, 69482, 69445
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 28 +++++++++++++++++++
drivers/gpu/drm/i915/display/skl_watermark.c | 28 ++++++++++++++++---
drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
.../gpu/drm/i915/display/skl_watermark_regs.h | 2 ++
4 files changed, 55 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index abe845906c7c..677a50c28dae 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -39,6 +39,7 @@
#include "intel_pcode.h"
#include "intel_psr.h"
#include "intel_vdsc.h"
+#include "skl_watermark.h"
#include "vlv_sideband.h"
/**
@@ -1800,6 +1801,16 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
return vco == ~0;
}
+/* Return the MBUS_CTL's encoding of the mdclk/cdclk ratio */
+static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config)
+{
+ if (DISPLAY_VER(i915) >= 20)
+ return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk) - 1;
+
+ return 1;
+}
+
static int cdclk_squash_divider(u16 waveform)
{
return hweight16(waveform ?: 0xffff);
@@ -2735,6 +2746,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
struct intel_crtc_state *crtc_state;
int min_cdclk, i;
enum pipe pipe;
+ struct intel_dbuf_state *new_dbuf_state;
+ struct intel_dbuf_state *old_dbuf_state;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
int ret;
@@ -2768,6 +2781,21 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
}
}
+ new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+ old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+ if (new_dbuf_state && old_dbuf_state) {
+ new_dbuf_state->mdclk_cdclk_ratio =
+ get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
+
+ if (new_dbuf_state->mdclk_cdclk_ratio != old_dbuf_state->mdclk_cdclk_ratio) {
+ int ret;
+
+ ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
+ if (ret)
+ return ret;
+ }
+ }
+
min_cdclk = max(cdclk_state->force_min_cdclk,
cdclk_state->bw_min_cdclk);
for_each_pipe(dev_priv, pipe)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 64a122d3c9c0..1fefb02876c8 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3472,6 +3472,16 @@ int intel_dbuf_init(struct drm_i915_private *i915)
return 0;
}
+static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+ int mdclk_cdclk_ratio,
+ int mbus_joined)
+{
+ if (mbus_joined)
+ return (mdclk_cdclk_ratio << 1) + 1;
+
+ return mdclk_cdclk_ratio;
+}
+
/*
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
* update the request state of all DBUS slices.
@@ -3483,10 +3493,16 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
enum dbuf_slice slice;
const struct intel_dbuf_state *dbuf_state =
intel_atomic_get_new_dbuf_state(state);
+ int tracker_state_service;
if (!HAS_MBUS_JOINING(i915))
return;
+ tracker_state_service =
+ get_mbus_mdclk_cdclk_ratio(i915,
+ dbuf_state->mdclk_cdclk_ratio,
+ dbuf_state->joined_mbus);
+
/*
* TODO: Implement vblank synchronized MBUS joining changes.
* Must be properly coordinated with dbuf reprogramming.
@@ -3494,13 +3510,15 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
if (dbuf_state->joined_mbus) {
mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
MBUS_JOIN_PIPE_SELECT_NONE;
- dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
} else {
mbus_ctl = MBUS_HASHING_MODE_2x2 |
MBUS_JOIN_PIPE_SELECT_NONE;
- dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
}
+ dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(tracker_state_service);
+
+ mbus_ctl |= MBUS_TRANS_THROTTLE_MIN_SELECT(dbuf_state->mdclk_cdclk_ratio);
+
intel_de_rmw(i915, MBUS_CTL,
MBUS_HASHING_MODE_MASK | MBUS_JOIN |
MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
@@ -3521,7 +3539,8 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
if (!new_dbuf_state ||
(new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
- new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+ new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+ new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
return;
WARN_ON(!new_dbuf_state->base.changed);
@@ -3542,7 +3561,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
if (!new_dbuf_state ||
(new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
- new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+ new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+ new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
return;
WARN_ON(!new_dbuf_state->base.changed);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index f91a3d4ddc07..54db5c7d517e 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -56,6 +56,7 @@ struct intel_dbuf_state {
u8 slices[I915_MAX_PIPES];
u8 enabled_slices;
u8 active_pipes;
+ u8 mdclk_cdclk_ratio;
bool joined_mbus;
};
diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
index 628c5920ad49..4c820f1d351d 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
@@ -38,6 +38,8 @@
#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
+#define MBUS_TRANS_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
+#define MBUS_TRANS_THROTTLE_MIN_SELECT(ratio) REG_FIELD_PREP(MBUS_TRANS_THROTTLE_MIN_MASK, ratio)
#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 24/27] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 24/27] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf Lucas De Marchi
@ 2023-09-08 22:43 ` Matt Roper
2023-09-11 8:06 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 62+ messages in thread
From: Matt Roper @ 2023-09-08 22:43 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 08:37:54AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
> between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
> change.
>
> Previsouly DBuf state and CDCLK were not anyhow coupled together. Now
> at compute stage when we know which CDCLK/MDCLK we are going to use, we
> need to update the DBuf state with that ratio, being properly encoded,
> so that it gets written to those registers, once DBuf state is being
> update. The criteria for updating DBuf state is also a CDCLK/MDCLK ratio
> change now.
>
> v2:
> - Remove condition check for display version 20 since it's compatible
> with previous versions (Matt Roper)
> - Squash the serialization of global state when mdclk_cdclk_ratio
> changes
I'm not sure I follow the serialization change here; can you add some
more explanation of that to the commit message? If the mdclk:cdclk
ratio changes then that means we're changing the cdclk (either on its
own if only the squashing waveform is changing, or along with the mdclk
if the PLL is also getting reprogrammed). In either case we should
already be serializing in intel_cdclk_need_serialize() due to the cdclk
change, right? Is the new check added here actually important somehow?
Matt
>
> Bspec: 68864, 69482, 69445
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 28 +++++++++++++++++++
> drivers/gpu/drm/i915/display/skl_watermark.c | 28 ++++++++++++++++---
> drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
> .../gpu/drm/i915/display/skl_watermark_regs.h | 2 ++
> 4 files changed, 55 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index abe845906c7c..677a50c28dae 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -39,6 +39,7 @@
> #include "intel_pcode.h"
> #include "intel_psr.h"
> #include "intel_vdsc.h"
> +#include "skl_watermark.h"
> #include "vlv_sideband.h"
>
> /**
> @@ -1800,6 +1801,16 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
> return vco == ~0;
> }
>
> +/* Return the MBUS_CTL's encoding of the mdclk/cdclk ratio */
> +static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> + const struct intel_cdclk_config *cdclk_config)
> +{
> + if (DISPLAY_VER(i915) >= 20)
> + return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk) - 1;
> +
> + return 1;
> +}
> +
> static int cdclk_squash_divider(u16 waveform)
> {
> return hweight16(waveform ?: 0xffff);
> @@ -2735,6 +2746,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> struct intel_crtc_state *crtc_state;
> int min_cdclk, i;
> enum pipe pipe;
> + struct intel_dbuf_state *new_dbuf_state;
> + struct intel_dbuf_state *old_dbuf_state;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> int ret;
> @@ -2768,6 +2781,21 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> }
> }
>
> + new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> + old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> + if (new_dbuf_state && old_dbuf_state) {
> + new_dbuf_state->mdclk_cdclk_ratio =
> + get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
> +
> + if (new_dbuf_state->mdclk_cdclk_ratio != old_dbuf_state->mdclk_cdclk_ratio) {
> + int ret;
> +
> + ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
> + if (ret)
> + return ret;
> + }
> + }
> +
> min_cdclk = max(cdclk_state->force_min_cdclk,
> cdclk_state->bw_min_cdclk);
> for_each_pipe(dev_priv, pipe)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 64a122d3c9c0..1fefb02876c8 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3472,6 +3472,16 @@ int intel_dbuf_init(struct drm_i915_private *i915)
> return 0;
> }
>
> +static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> + int mdclk_cdclk_ratio,
> + int mbus_joined)
> +{
> + if (mbus_joined)
> + return (mdclk_cdclk_ratio << 1) + 1;
> +
> + return mdclk_cdclk_ratio;
> +}
> +
> /*
> * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
> * update the request state of all DBUS slices.
> @@ -3483,10 +3493,16 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
> enum dbuf_slice slice;
> const struct intel_dbuf_state *dbuf_state =
> intel_atomic_get_new_dbuf_state(state);
> + int tracker_state_service;
>
> if (!HAS_MBUS_JOINING(i915))
> return;
>
> + tracker_state_service =
> + get_mbus_mdclk_cdclk_ratio(i915,
> + dbuf_state->mdclk_cdclk_ratio,
> + dbuf_state->joined_mbus);
> +
> /*
> * TODO: Implement vblank synchronized MBUS joining changes.
> * Must be properly coordinated with dbuf reprogramming.
> @@ -3494,13 +3510,15 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
> if (dbuf_state->joined_mbus) {
> mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
> MBUS_JOIN_PIPE_SELECT_NONE;
> - dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
> } else {
> mbus_ctl = MBUS_HASHING_MODE_2x2 |
> MBUS_JOIN_PIPE_SELECT_NONE;
> - dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
> }
>
> + dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(tracker_state_service);
> +
> + mbus_ctl |= MBUS_TRANS_THROTTLE_MIN_SELECT(dbuf_state->mdclk_cdclk_ratio);
> +
> intel_de_rmw(i915, MBUS_CTL,
> MBUS_HASHING_MODE_MASK | MBUS_JOIN |
> MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
> @@ -3521,7 +3539,8 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
>
> if (!new_dbuf_state ||
> (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> - new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> + new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> + new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
> return;
>
> WARN_ON(!new_dbuf_state->base.changed);
> @@ -3542,7 +3561,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
>
> if (!new_dbuf_state ||
> (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> - new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> + new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> + new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
> return;
>
> WARN_ON(!new_dbuf_state->base.changed);
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> index f91a3d4ddc07..54db5c7d517e 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> @@ -56,6 +56,7 @@ struct intel_dbuf_state {
> u8 slices[I915_MAX_PIPES];
> u8 enabled_slices;
> u8 active_pipes;
> + u8 mdclk_cdclk_ratio;
> bool joined_mbus;
> };
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> index 628c5920ad49..4c820f1d351d 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> @@ -38,6 +38,8 @@
> #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
> #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
> #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
> +#define MBUS_TRANS_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
> +#define MBUS_TRANS_THROTTLE_MIN_SELECT(ratio) REG_FIELD_PREP(MBUS_TRANS_THROTTLE_MIN_MASK, ratio)
> #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
> #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
>
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 24/27] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
2023-09-08 22:43 ` Matt Roper
@ 2023-09-11 8:06 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 62+ messages in thread
From: Lisovskiy, Stanislav @ 2023-09-11 8:06 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi, intel-xe
On Fri, Sep 08, 2023 at 03:43:03PM -0700, Matt Roper wrote:
> On Thu, Sep 07, 2023 at 08:37:54AM -0700, Lucas De Marchi wrote:
> > From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> >
> > When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
> > between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
> > change.
> >
> > Previsouly DBuf state and CDCLK were not anyhow coupled together. Now
> > at compute stage when we know which CDCLK/MDCLK we are going to use, we
> > need to update the DBuf state with that ratio, being properly encoded,
> > so that it gets written to those registers, once DBuf state is being
> > update. The criteria for updating DBuf state is also a CDCLK/MDCLK ratio
> > change now.
> >
> > v2:
> > - Remove condition check for display version 20 since it's compatible
> > with previous versions (Matt Roper)
> > - Squash the serialization of global state when mdclk_cdclk_ratio
> > changes
>
> I'm not sure I follow the serialization change here; can you add some
> more explanation of that to the commit message? If the mdclk:cdclk
> ratio changes then that means we're changing the cdclk (either on its
> own if only the squashing waveform is changing, or along with the mdclk
> if the PLL is also getting reprogrammed). In either case we should
> already be serializing in intel_cdclk_need_serialize() due to the cdclk
> change, right? Is the new check added here actually important somehow?
I agree, in theory whenever mdclk:cdclk ratio changes, we also probably
would be changing cdclk as well, so it is just based on our rule:
"whenever global data changes, we lock the global state", "whenever
hw needs to be written, we serialize the global state".
Calling this twice, just adds all crtcs into state, if it wasn't already
there, so shouldn't be harmful(anyway we have other places, where we might
call this again) however we can remove it also.
I have written this patch, somewhile ago, at least now I can't recall any
other reasons or cases when mdclk:cdclk ratio might change..
However I see that there is that other function called get_mbus_mdclk_cdclk_ratio
and its result is used for writing DBUF_CTL_S* regs and it seems to depend not
only on mdclk:cdclk ratio, but also if mbus_join is enabled or not.
Could be that we actually need to make sure, we serialize in that case?
Stan
>
>
> Matt
>
> >
> > Bspec: 68864, 69482, 69445
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 28 +++++++++++++++++++
> > drivers/gpu/drm/i915/display/skl_watermark.c | 28 ++++++++++++++++---
> > drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
> > .../gpu/drm/i915/display/skl_watermark_regs.h | 2 ++
> > 4 files changed, 55 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index abe845906c7c..677a50c28dae 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -39,6 +39,7 @@
> > #include "intel_pcode.h"
> > #include "intel_psr.h"
> > #include "intel_vdsc.h"
> > +#include "skl_watermark.h"
> > #include "vlv_sideband.h"
> >
> > /**
> > @@ -1800,6 +1801,16 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
> > return vco == ~0;
> > }
> >
> > +/* Return the MBUS_CTL's encoding of the mdclk/cdclk ratio */
> > +static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> > + const struct intel_cdclk_config *cdclk_config)
> > +{
> > + if (DISPLAY_VER(i915) >= 20)
> > + return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk) - 1;
> > +
> > + return 1;
> > +}
> > +
> > static int cdclk_squash_divider(u16 waveform)
> > {
> > return hweight16(waveform ?: 0xffff);
> > @@ -2735,6 +2746,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> > struct intel_crtc_state *crtc_state;
> > int min_cdclk, i;
> > enum pipe pipe;
> > + struct intel_dbuf_state *new_dbuf_state;
> > + struct intel_dbuf_state *old_dbuf_state;
> >
> > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> > int ret;
> > @@ -2768,6 +2781,21 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> > }
> > }
> >
> > + new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> > + old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> > + if (new_dbuf_state && old_dbuf_state) {
> > + new_dbuf_state->mdclk_cdclk_ratio =
> > + get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
> > +
> > + if (new_dbuf_state->mdclk_cdclk_ratio != old_dbuf_state->mdclk_cdclk_ratio) {
> > + int ret;
> > +
> > + ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
> > + if (ret)
> > + return ret;
> > + }
> > + }
> > +
> > min_cdclk = max(cdclk_state->force_min_cdclk,
> > cdclk_state->bw_min_cdclk);
> > for_each_pipe(dev_priv, pipe)
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index 64a122d3c9c0..1fefb02876c8 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -3472,6 +3472,16 @@ int intel_dbuf_init(struct drm_i915_private *i915)
> > return 0;
> > }
> >
> > +static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> > + int mdclk_cdclk_ratio,
> > + int mbus_joined)
> > +{
> > + if (mbus_joined)
> > + return (mdclk_cdclk_ratio << 1) + 1;
> > +
> > + return mdclk_cdclk_ratio;
> > +}
> > +
> > /*
> > * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
> > * update the request state of all DBUS slices.
> > @@ -3483,10 +3493,16 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
> > enum dbuf_slice slice;
> > const struct intel_dbuf_state *dbuf_state =
> > intel_atomic_get_new_dbuf_state(state);
> > + int tracker_state_service;
> >
> > if (!HAS_MBUS_JOINING(i915))
> > return;
> >
> > + tracker_state_service =
> > + get_mbus_mdclk_cdclk_ratio(i915,
> > + dbuf_state->mdclk_cdclk_ratio,
> > + dbuf_state->joined_mbus);
> > +
> > /*
> > * TODO: Implement vblank synchronized MBUS joining changes.
> > * Must be properly coordinated with dbuf reprogramming.
> > @@ -3494,13 +3510,15 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
> > if (dbuf_state->joined_mbus) {
> > mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
> > MBUS_JOIN_PIPE_SELECT_NONE;
> > - dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
> > } else {
> > mbus_ctl = MBUS_HASHING_MODE_2x2 |
> > MBUS_JOIN_PIPE_SELECT_NONE;
> > - dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
> > }
> >
> > + dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(tracker_state_service);
> > +
> > + mbus_ctl |= MBUS_TRANS_THROTTLE_MIN_SELECT(dbuf_state->mdclk_cdclk_ratio);
> > +
> > intel_de_rmw(i915, MBUS_CTL,
> > MBUS_HASHING_MODE_MASK | MBUS_JOIN |
> > MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
> > @@ -3521,7 +3539,8 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> >
> > if (!new_dbuf_state ||
> > (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> > - new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> > + new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> > + new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
> > return;
> >
> > WARN_ON(!new_dbuf_state->base.changed);
> > @@ -3542,7 +3561,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> >
> > if (!new_dbuf_state ||
> > (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> > - new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> > + new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> > + new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
> > return;
> >
> > WARN_ON(!new_dbuf_state->base.changed);
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> > index f91a3d4ddc07..54db5c7d517e 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> > @@ -56,6 +56,7 @@ struct intel_dbuf_state {
> > u8 slices[I915_MAX_PIPES];
> > u8 enabled_slices;
> > u8 active_pipes;
> > + u8 mdclk_cdclk_ratio;
> > bool joined_mbus;
> > };
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> > index 628c5920ad49..4c820f1d351d 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> > @@ -38,6 +38,8 @@
> > #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
> > #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
> > #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
> > +#define MBUS_TRANS_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
> > +#define MBUS_TRANS_THROTTLE_MIN_SELECT(ratio) REG_FIELD_PREP(MBUS_TRANS_THROTTLE_MIN_MASK, ratio)
> > #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
> > #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
> >
> > --
> > 2.40.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 25/27] drm/i915/lnl: Add support for CDCLK initialization sequence
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (23 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 24/27] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 16:55 ` Vodapalli, Ravi Kumar
2023-09-08 22:17 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 26/27] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane Lucas De Marchi
` (2 subsequent siblings)
27 siblings, 2 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Add CDCLK initialization sequence changes and CDCLK set frequency
sequence for LNL platform. It's mostly the same as MTL, but with some
additional programming for the squash and crawling steps when
when a change in mdclk/cdclk ratio is observed.
v2: Remove wrong changes for bxt_cdclk_cd2x_pipe() (Matt Roper)
BSpec: 68846, 68864
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 51 +++++++++++++++++++++-
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 677a50c28dae..dfefc971b733 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -40,6 +40,7 @@
#include "intel_psr.h"
#include "intel_vdsc.h"
#include "skl_watermark.h"
+#include "skl_watermark_regs.h"
#include "vlv_sideband.h"
/**
@@ -1811,6 +1812,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
return 1;
}
+static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config)
+{
+ int min_throttle_val;
+ int min_tracker_state;
+ enum dbuf_slice slice;
+ int mdclk_cdclk_div_ratio;
+ int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
+
+ mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
+
+ min_throttle_val = MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
+
+ intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK, min_throttle_val);
+
+ if (mbus_join)
+ mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
+
+ min_tracker_state = DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
+
+ for_each_dbuf_slice(i915, slice)
+ intel_de_rmw(i915, DBUF_CTL_S(slice),
+ DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+ min_tracker_state);
+}
+
+static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config,
+ u16 waveform)
+{
+ if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
+ /* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
+ lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+
+ dg2_cdclk_squash_program(i915, waveform);
+
+ if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
+ /* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
+ lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+}
+
static int cdclk_squash_divider(u16 waveform)
{
return hweight16(waveform ?: 0xffff);
@@ -1913,8 +1955,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
else
clock = cdclk;
- if (HAS_CDCLK_SQUASH(dev_priv))
- dg2_cdclk_squash_program(dev_priv, waveform);
+ if (HAS_CDCLK_SQUASH(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 20)
+ lnl_cdclk_squash_program(dev_priv, cdclk_config,
+ waveform);
+ else
+ dg2_cdclk_squash_program(dev_priv, waveform);
+ }
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
bxt_cdclk_cd2x_pipe(dev_priv, pipe);
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 25/27] drm/i915/lnl: Add support for CDCLK initialization sequence
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 25/27] drm/i915/lnl: Add support for CDCLK initialization sequence Lucas De Marchi
@ 2023-09-07 16:55 ` Vodapalli, Ravi Kumar
2023-09-08 22:17 ` Matt Roper
1 sibling, 0 replies; 62+ messages in thread
From: Vodapalli, Ravi Kumar @ 2023-09-07 16:55 UTC (permalink / raw)
To: De Marchi, Lucas, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Looks Good.
Reviewed-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Thanks,
Ravi Kumar V
-----Original Message-----
From: De Marchi, Lucas <lucas.demarchi@intel.com>
Sent: Thursday, September 7, 2023 9:08 PM
To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Vodapalli, Ravi Kumar <ravi.kumar.vodapalli@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
Subject: [PATCH v2 25/27] drm/i915/lnl: Add support for CDCLK initialization sequence
From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Add CDCLK initialization sequence changes and CDCLK set frequency sequence for LNL platform. It's mostly the same as MTL, but with some additional programming for the squash and crawling steps when when a change in mdclk/cdclk ratio is observed.
v2: Remove wrong changes for bxt_cdclk_cd2x_pipe() (Matt Roper)
BSpec: 68846, 68864
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 51 +++++++++++++++++++++-
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 677a50c28dae..dfefc971b733 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -40,6 +40,7 @@
#include "intel_psr.h"
#include "intel_vdsc.h"
#include "skl_watermark.h"
+#include "skl_watermark_regs.h"
#include "vlv_sideband.h"
/**
@@ -1811,6 +1812,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
return 1;
}
+static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config) {
+ int min_throttle_val;
+ int min_tracker_state;
+ enum dbuf_slice slice;
+ int mdclk_cdclk_div_ratio;
+ int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
+
+ mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
+
+ min_throttle_val =
+MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
+
+ intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK,
+min_throttle_val);
+
+ if (mbus_join)
+ mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
+
+ min_tracker_state =
+DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
+
+ for_each_dbuf_slice(i915, slice)
+ intel_de_rmw(i915, DBUF_CTL_S(slice),
+ DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+ min_tracker_state);
+}
+
+static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config,
+ u16 waveform)
+{
+ if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
+ /* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
+ lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+
+ dg2_cdclk_squash_program(i915, waveform);
+
+ if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
+ /* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
+ lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config); }
+
static int cdclk_squash_divider(u16 waveform) {
return hweight16(waveform ?: 0xffff);
@@ -1913,8 +1955,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
else
clock = cdclk;
- if (HAS_CDCLK_SQUASH(dev_priv))
- dg2_cdclk_squash_program(dev_priv, waveform);
+ if (HAS_CDCLK_SQUASH(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 20)
+ lnl_cdclk_squash_program(dev_priv, cdclk_config,
+ waveform);
+ else
+ dg2_cdclk_squash_program(dev_priv, waveform);
+ }
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
bxt_cdclk_cd2x_pipe(dev_priv, pipe);
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v2 25/27] drm/i915/lnl: Add support for CDCLK initialization sequence
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 25/27] drm/i915/lnl: Add support for CDCLK initialization sequence Lucas De Marchi
2023-09-07 16:55 ` Vodapalli, Ravi Kumar
@ 2023-09-08 22:17 ` Matt Roper
1 sibling, 0 replies; 62+ messages in thread
From: Matt Roper @ 2023-09-08 22:17 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Thu, Sep 07, 2023 at 08:37:55AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>
> Add CDCLK initialization sequence changes and CDCLK set frequency
The title and first line of this commit message don't seem to really
match the patch anymore. The changes here aren't about the
"initialization sequence" (which I assume refers to something that
happens suring driver init), but rather to the steps we take every time
we reprogram the cdclk.
> sequence for LNL platform. It's mostly the same as MTL, but with some
> additional programming for the squash and crawling steps when
> when a change in mdclk/cdclk ratio is observed.
>
> v2: Remove wrong changes for bxt_cdclk_cd2x_pipe() (Matt Roper)
>
> BSpec: 68846, 68864
Related to the above, I don't see anything on 68846 that relates to the
changes in this patch.
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 51 +++++++++++++++++++++-
> 1 file changed, 49 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 677a50c28dae..dfefc971b733 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -40,6 +40,7 @@
> #include "intel_psr.h"
> #include "intel_vdsc.h"
> #include "skl_watermark.h"
> +#include "skl_watermark_regs.h"
> #include "vlv_sideband.h"
>
> /**
> @@ -1811,6 +1812,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> return 1;
> }
>
> +static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
> + const struct intel_cdclk_config *cdclk_config)
> +{
> + int min_throttle_val;
> + int min_tracker_state;
> + enum dbuf_slice slice;
> + int mdclk_cdclk_div_ratio;
> + int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
> +
> + mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
> +
> + min_throttle_val = MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
> +
> + intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK, min_throttle_val);
> +
> + if (mbus_join)
> + mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
> +
> + min_tracker_state = DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
> +
> + for_each_dbuf_slice(i915, slice)
> + intel_de_rmw(i915, DBUF_CTL_S(slice),
> + DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> + min_tracker_state);
> +}
> +
> +static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
> + const struct intel_cdclk_config *cdclk_config,
> + u16 waveform)
> +{
> + if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
> + /* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
> + lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
> +
> + dg2_cdclk_squash_program(i915, waveform);
> +
> + if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
> + /* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
> + lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
> +}
> +
> static int cdclk_squash_divider(u16 waveform)
> {
> return hweight16(waveform ?: 0xffff);
> @@ -1913,8 +1955,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> else
> clock = cdclk;
>
> - if (HAS_CDCLK_SQUASH(dev_priv))
> - dg2_cdclk_squash_program(dev_priv, waveform);
> + if (HAS_CDCLK_SQUASH(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) >= 20)
Since everything going forward is expected to support squashing, it may
be cleaner to flatten this into a single if/else ladder:
if (DISPLAY_VER(dev_priv) >= 20)
...lnl_cdclk_squash_program...
else if (HAS_CDCLK_SQUASH(dev_priv))
...dg2_cdclk_squash_program...
Aside from the commit message/title and the ladder flattening, the
actual logic of the patch looks correct, so
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
with those fixed.
Matt
> + lnl_cdclk_squash_program(dev_priv, cdclk_config,
> + waveform);
> + else
> + dg2_cdclk_squash_program(dev_priv, waveform);
> + }
>
> val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
> bxt_cdclk_cd2x_pipe(dev_priv, pipe);
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v2 26/27] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (24 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 25/27] drm/i915/lnl: Add support for CDCLK initialization sequence Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 27/27] drm/i915/xe2lpd: Update mbus on post plane updates Lucas De Marchi
2023-09-07 19:39 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable Lunar Lake display (rev3) Patchwork
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Previously we always updated DBuf MBUS CTL and DBUF CTL regs after
CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like
that anymore. According to BSpec, we have to first update DBuf regs and
then write CDCLK regs, when CDCLK is decreased, which we do in post
plane.
So now we do CDCLK post plane update only after DBuf regs are
written (CDCLK/MDCLK separation requires MDCLK/CDCLK ratio to be written
to DBuf regs).
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 83e1bc858b9f..b0455d5d9bfd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7039,7 +7039,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.funcs.display->commit_modeset_enables(state);
- if (state->modeset)
+ if (state->modeset && DISPLAY_VER(dev_priv) < 20)
intel_set_cdclk_post_plane_update(state);
intel_wait_for_vblank_workers(state);
@@ -7086,6 +7086,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_dbuf_post_plane_update(state);
intel_psr_post_plane_update(state);
+ if (state->modeset && DISPLAY_VER(dev_priv) >= 20)
+ intel_set_cdclk_post_plane_update(state);
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
intel_post_plane_update(state, crtc);
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v2 27/27] drm/i915/xe2lpd: Update mbus on post plane updates
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (25 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 26/27] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane Lucas De Marchi
@ 2023-09-07 15:37 ` Lucas De Marchi
2023-09-07 19:39 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable Lunar Lake display (rev3) Patchwork
27 siblings, 0 replies; 62+ messages in thread
From: Lucas De Marchi @ 2023-09-07 15:37 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Lucas De Marchi
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
According to BSpec we need to write the MBUS CTL and DBUF CTL both for
increasing CDCLK case (pre plane) and for decreasing CDCLK case (post
plane). Make sure those updates are in place for Xe2-LPD.
Since the mbus update is not only on pre-enable anymore, also rename the
function accordingly.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1fefb02876c8..955a8fb7ba19 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3486,7 +3486,7 @@ static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
* update the request state of all DBUS slices.
*/
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+static void update_mbus(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl, dbuf_min_tracker_val;
@@ -3545,7 +3545,7 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
- update_mbus_pre_enable(state);
+ update_mbus(state);
gen9_dbuf_slices_update(i915,
old_dbuf_state->enabled_slices |
new_dbuf_state->enabled_slices);
@@ -3567,6 +3567,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
+ if (DISPLAY_VER(i915) >= 20)
+ update_mbus(state);
+
gen9_dbuf_slices_update(i915,
new_dbuf_state->enabled_slices);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable Lunar Lake display (rev3)
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
` (26 preceding siblings ...)
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 27/27] drm/i915/xe2lpd: Update mbus on post plane updates Lucas De Marchi
@ 2023-09-07 19:39 ` Patchwork
27 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2023-09-07 19:39 UTC (permalink / raw)
To: Vodapalli, Ravi Kumar; +Cc: intel-gfx
== Series Details ==
Series: Enable Lunar Lake display (rev3)
URL : https://patchwork.freedesktop.org/series/122799/
State : failure
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/122799/revisions/3/mbox/ not applied
Applying: drm/i915/xelpdp: Add XE_LPDP_FEATURES
Applying: drm/i915/lnl: Add display definitions
Applying: drm/i915/xe2lpd: FBC is now supported on all pipes
Applying: drm/i915: Re-order if/else ladder in intel_detect_pch()
Applying: drm/i915/xe2lpd: Add fake PCH
Applying: drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
Applying: drm/i915/display: Consolidate saved port bits in intel_digital_port
Applying: drm/i915/xe2lpd: Move D2D enable/disable
Applying: drm/i915/xe2lpd: Move registers to PICA
Applying: drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
Applying: drm/i915/xe2lpd: Register DE_RRMR has been removed
Applying: FIXME: drm/i915/xe2lpd: Add display power well
Applying: drm/i915/xe2lpd: Add DC state support
Applying: drm/i915/display: Remove FBC capability from fused off pipes
Applying: FIXME: drm/i915/xe2lpd: Add support for DP aux channels
Applying: drm/i915/xe2lpd: Handle port AUX interrupts
Applying: drm/i915/xe2lpd: Read pin assignment from IOM
Applying: drm/i915/xe2lpd: Enable odd size and panning for planar yuv
Applying: drm/i915/xe2lpd: Add support for HPD
Applying: drm/i915/xe2lpd: Extend Wa_15010685871
Applying: drm/i915/lnl: Add gmbus/ddc support
Applying: drm/i915/lnl: Add CDCLK table
Applying: drm/i915/lnl: Start using CDCLK through PLL
Applying: drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
Applying: drm/i915/lnl: Add support for CDCLK initialization sequence
error: corrupt patch at line 83
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0025 drm/i915/lnl: Add support for CDCLK initialization sequence
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced
^ permalink raw reply [flat|nested] 62+ messages in thread