Re: [PATCH 6/9] cxl/port: Move dport RAS setup to dport add time

[Jonathan Cameron <jonathan.cameron@huawei.com>]

On Wed, 21 Jan 2026 19:33:27 -0800
Dan Williams <dan.j.williams@intel.com> wrote:

> Towards the end goal of making all CXL RAS capability handling uniform
> across host bridge ports, upstream switch ports, and endpoint ports, move
> dport RAS setup. Move it to cxl_switch_port_probe() context for switch / VH
> dports (via cxl_port_add_dport()) and cxl_endpoint_port_probe() context for
> an RCH dport. Rename the RAS setup helper to devm_cxl_dport_ras_setup() for
> symmetry with devm_cxl_switch_port_decoders_setup().
> 
> Only the RCH version needs to be exported and the cxl_test mocking can be
> deleted with a dev_is_pci() check on the dport_dev.
> 
Comment below that doesn't really have anything to do with this patch
and can be ignored.

Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>

> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
>  drivers/cxl/core/core.h       |  8 ++++++++
>  drivers/cxl/cxlpci.h          |  8 ++++----
>  drivers/cxl/core/port.c       | 10 +++-------
>  drivers/cxl/core/ras.c        | 30 ++++++++++++++++++------------
>  drivers/cxl/mem.c             |  2 --
>  drivers/cxl/port.c            | 12 ++++++++++++
>  tools/testing/cxl/test/mock.c | 12 ------------
>  tools/testing/cxl/Kbuild      |  1 -
>  8 files changed, 45 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index 422531799af2..fb1461c07648 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -144,6 +144,12 @@ int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c);
>  int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,
>  					struct access_coordinate *c);
>  
> +static inline struct device *dport_to_host(struct cxl_dport *dport)
> +{
> +	if (is_cxl_root(dport->port))
> +		return dport->port->uport_dev;
> +	return &dport->port->dev;

Obviously really applies to earlier patch but maybe it's worth 

	struct cxl_port *port = &dport->port;

	if (is_cxl_root(port))
		return port->uport_dev;
	return port->dev;

I'm not sure it really adds that much but is the sort of thing
someone will post a patch 'tidying up' later.

> +}