Re: [PATCH 7/9] cxl/port: Map CXL Endpoint Port and CXL Switch Port RAS registers

[<dan.j.williams@intel.com>]

Jonathan Cameron wrote:
> On Wed, 21 Jan 2026 19:33:28 -0800
> Dan Williams <dan.j.williams@intel.com> wrote:
> 
> > From: Terry Bowman <terry.bowman@amd.com>
> > 
> > In preparation for CXL VH (Virtual Host) topology protocol error handling,
> > add RAS capability registered mapping for all ports in a CXL VH topology.
> > This includes the RAS capabilities of Switch Upstream Ports, Switch
> > Downstream Ports, Host Bridge Ports ("upstream"), and Root Ports
> > ("downstream")
> > 
> > Update cxl_port_add_dport() to map the upstream RAS capability on first
> > 'dport' attach.
> 
> I'm struggling to see how this maps the endpoint registers (or at least
> how it changes that). So maybe the patch title has become incorrect?

It is time travelling a bit. The new / common devm_cxl_port_ras_setup() helper is
going to be reused for endpoint RAS register mapping in a subsequent
patch. So this can be renamed:

cxl/port: Map Port RAS registers

...and clarify that Switch Ports are covered in this patch and a later
patch adds Endpoint support.