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From: <dan.j.williams@intel.com>
To: Jonathan Cameron <jonathan.cameron@huawei.com>,
	Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dave@stgolabs.net>,
	<dave.jiang@intel.com>, <alison.schofield@intel.com>,
	<ira.weiny@intel.com>, <terry.bowman@amd.com>
Subject: Re: [PATCH 4/9] cxl/port: Move decoder setup before dport creation
Date: Thu, 22 Jan 2026 13:42:16 -0800	[thread overview]
Message-ID: <697299b871241_3095100a7@dwillia2-mobl4.notmuch> (raw)
In-Reply-To: <20260122130755.000016e4@huawei.com>

Jonathan Cameron wrote:
> On Wed, 21 Jan 2026 19:33:25 -0800
> Dan Williams <dan.j.williams@intel.com> wrote:
> 
> > There are port setup actions that run on first dport arrival, and there are
> > setup actions that run per dport.
> > 
> > RAS register setup is a future additional setup action to run per-port
> > (once the first dport arrives), and each dport also has RAS registers to
> > map.
> > 
> > Before adding that, flip the order of "first dport" and "per-dport"
> > actions. This makes allocation symmetric with teardown, "first dport"
> > actions unwind after last dport removed. It also allows for using a devres
> > group to collect the unrelated decoder, RAS, and dport setup actions into
> > one group release action.
> > 
> > The new cxl_port_open_group() collects "first dport" and "per-dport" into
> > one group that can be released on any failure. This group's lifetime only
> > needs to span the short duration of cxl_port_add_dport() to cleanup all
> > potential damage from failing to add a dport. Contrast that to the "dport"
> > devres group that is called upon to destruct fully formed dport objects.
> > 
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> 
> Trivial stuff only.  Took me a while to get my head around the temporary
> group usage, but having done so it seems correct to me.  I poked the
> various paths fairly heavily to be sure they all worked out after
> thinking there was a bug due to a misread :(
> 
> Either way on suggestions below.
> 
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> > ---
> >  drivers/cxl/core/port.c | 43 +++++++++++++++++++++++++++++------------
> >  1 file changed, 31 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> > index f2723bf948e2..f69395ea0c14 100644
> > --- a/drivers/cxl/core/port.c
> > +++ b/drivers/cxl/core/port.c
> > @@ -1650,10 +1650,24 @@ static bool dport_exists(struct cxl_port *port, struct device *dport_dev)
> >  	return false;
> >  }
> >  
> > -DEFINE_FREE(del_cxl_dport, struct cxl_dport *, if (!IS_ERR_OR_NULL(_T)) del_dport(_T))
> > +static void *cxl_port_open_group(struct cxl_port *port)
> > +{
> > +	return devres_open_group(&port->dev, port, GFP_KERNEL);
> So only reason you are using port as the ID is so there is just one thing
> to pass to the DEFINE_FREE() callback. Fair enough, but...

Right, and it avoids needing to wade through the cleverness of defining
a new CLASS() with a 'fat' pointer that contains the devm host and the
group. I.e. similar to DEFINE_LOCK_GUARD_0.

> > +}
> > +
> > +/* note this implicitly casts @port_group back to its @port */
> > +DEFINE_FREE(cxl_port_release_group, struct cxl_port *,
> > +	    if (_T) devres_release_group(&_T->dev, _T))
> > +
> > +static void cxl_port_remove_group(struct cxl_port *port, void *port_group)
> > +{
> > +	devres_remove_group(&port->dev, port_group);
> 
> To keep this inline with the DEFINE_FREE(), I'd pass in only one parameter.
> Can in theory be either of them but to me port_group is more
> consistent. Then cast that to get the struct cxl_port *

I would sooner go the other way and skip the open/remove wrappers
altogether. Because it just adds to the confusion of what is happening.
The DEFINE_FREE() needs a comment for its cleverness, but unlike the
dport case this port group can just be idiomatic
devres_{open,remove}_group().

I will do the "dr_group" rename of the local pointer though which also
fits better with not wrapping devres_{open,remove}_group() for this case.

  reply	other threads:[~2026-01-22 21:42 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-22  3:33 [PATCH 0/9] cxl/port: Unify RAS setup across port types Dan Williams
2026-01-22  3:33 ` [PATCH 1/9] cxl/port: Cleanup handling of the nr_dports 0 -> 1 transition Dan Williams
2026-01-22 11:32   ` Jonathan Cameron
2026-01-22 19:58     ` dan.j.williams
2026-01-22 16:45   ` Dave Jiang
2026-01-22  3:33 ` [PATCH 2/9] cxl/port: Reduce number of @dport variables in cxl_port_add_dport() Dan Williams
2026-01-22 11:39   ` Jonathan Cameron
2026-01-22 20:02     ` dan.j.williams
2026-01-22 16:54   ` Dave Jiang
2026-01-22  3:33 ` [PATCH 3/9] cxl/port: Cleanup dport removal with a devres group Dan Williams
2026-01-22 11:59   ` Jonathan Cameron
2026-01-22 20:43     ` dan.j.williams
2026-01-23 12:14       ` Jonathan Cameron
2026-01-23 12:24         ` Jonathan Cameron
2026-01-30 23:58         ` dan.j.williams
2026-01-22  3:33 ` [PATCH 4/9] cxl/port: Move decoder setup before dport creation Dan Williams
2026-01-22 13:07   ` Jonathan Cameron
2026-01-22 21:42     ` dan.j.williams [this message]
2026-01-22 20:38   ` Dave Jiang
2026-01-22  3:33 ` [PATCH 5/9] cxl/port: Move dport probe operations to a driver event Dan Williams
2026-01-22 14:44   ` Jonathan Cameron
2026-01-22 21:53     ` dan.j.williams
2026-01-22  3:33 ` [PATCH 6/9] cxl/port: Move dport RAS setup to dport add time Dan Williams
2026-01-22 15:00   ` Jonathan Cameron
2026-01-22 21:56     ` dan.j.williams
2026-01-22 21:06   ` Dave Jiang
2026-01-22  3:33 ` [PATCH 7/9] cxl/port: Map CXL Endpoint Port and CXL Switch Port RAS registers Dan Williams
2026-01-22 15:25   ` Jonathan Cameron
2026-01-22 22:11     ` dan.j.williams
2026-01-22  3:33 ` [PATCH 8/9] cxl/port: Move endpoint component register management to cxl_port Dan Williams
2026-01-22 15:27   ` Jonathan Cameron
2026-01-22 21:24   ` Dave Jiang
2026-01-22  3:33 ` [PATCH 9/9] cxl/port: Unify endpoint and switch port lookup Dan Williams
2026-01-22 15:32   ` Jonathan Cameron
2026-01-22 21:24   ` Dave Jiang
2026-01-22 21:42 ` [PATCH 0/9] cxl/port: Unify RAS setup across port types Bowman, Terry

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