From: <dan.j.williams@intel.com>
To: Jonathan Cameron <jonathan.cameron@huawei.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dave@stgolabs.net>,
<dave.jiang@intel.com>, <alison.schofield@intel.com>,
<ira.weiny@intel.com>, <terry.bowman@amd.com>
Subject: Re: [PATCH 5/9] cxl/port: Move dport probe operations to a driver event
Date: Thu, 22 Jan 2026 13:53:51 -0800 [thread overview]
Message-ID: <69729c6fc25e7_3095100ea@dwillia2-mobl4.notmuch> (raw)
In-Reply-To: <20260122144425.000014ca@huawei.com>
Jonathan Cameron wrote:
> On Wed, 21 Jan 2026 19:33:26 -0800
> Dan Williams <dan.j.williams@intel.com> wrote:
>
> > In preparation for adding more register setup to the cxl_port_add_dport()
> > path (for RAS register mapping), move the dport creation event to a driver
> > callback. This achieves two goals, it puts driver operations logically
> > where they belong, in a driver, and it obviates the gymnastics of
> > DECLARE_TESTABLE() which just makes a mess of grepping for CXL symbols.
> >
> > In other words, a driver callback is less of an ongoing maintenance burden
> > than this DECLARE_TESTABLE arrangement that does not scale and diminishes
> > the grep-ability of the codebase.
> >
> > cxl_port_add_dport() moves mostly unmodified from drivers/cxl/core/port.c.
> > The only deliberate change is that it now assumes that the device_lock is
> > held on entry and the driver is attached (just like cxl_port_probe()).
> >
> > Reviewed-by: Terry Bowman <terry.bowman@amd.com>
> > Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Just a small comment on maybe adding some scary sounding docs, or
> a struct wrapper to deal with the very specific callback inside
> struct cxl_driver.
>
> With at least a comment,
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
>
> > ---
> > drivers/cxl/cxl.h | 25 +++------
> > tools/testing/cxl/exports.h | 13 -----
> > drivers/cxl/core/hdm.c | 6 +--
> > drivers/cxl/core/pci.c | 8 +--
> > drivers/cxl/core/port.c | 78 +++++++---------------------
> > drivers/cxl/port.c | 60 +++++++++++++++++++++
> > tools/testing/cxl/cxl_core_exports.c | 22 --------
> > tools/testing/cxl/test/mock.c | 24 +++------
> > tools/testing/cxl/Kbuild | 2 +
> > 9 files changed, 102 insertions(+), 136 deletions(-)
> > delete mode 100644 tools/testing/cxl/exports.h
> >
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index 6f3741a57932..75ff5f055f7f 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -840,8 +840,11 @@ struct cxl_endpoint_dvsec_info {
> > };
> >
> > int devm_cxl_switch_port_decoders_setup(struct cxl_port *port);
> > -int __devm_cxl_switch_port_decoders_setup(struct cxl_port *port);
> > int devm_cxl_endpoint_decoders_setup(struct cxl_port *port);
> > +void cxl_port_update_decoder_targets(struct cxl_port *port,
> > + struct cxl_dport *dport);
> > +int cxl_port_setup_regs(struct cxl_port *port,
> > + resource_size_t component_reg_phys);
> >
> > struct cxl_dev_state;
> > int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds,
> > @@ -855,6 +858,8 @@ struct cxl_driver {
> > const char *name;
> > int (*probe)(struct device *dev);
> > void (*remove)(struct device *dev);
> > + struct cxl_dport *(*add_dport)(struct cxl_port *port,
> > + struct device *dport_dev);
>
> Having a single callback in a generic driver struct seems unusual.
> Maybe wrap the structure or add some documentation to set expectations.
>
> Probably not the time for it, but why do we have our own probe and remove rather
> than using the ones in device_driver? Maybe we talked about this long
> ago, but I can't remember the answer :(
I think there were thoughts on a common 'struct cxl_device' indirection,
but fell through and never came back to cleanup these definitions.
I think for now add a comment about this being needed for the most
prevalent CXL object 'struct cxl_port', but that longer term we may want
to consider separate 'struct cxl_port_driver' and 'struct
cxl_memdev_driver' wrappers.
That would save needing to up-cast the 'struct device *' argument as the
first step of these probe routines.
next prev parent reply other threads:[~2026-01-22 21:54 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-22 3:33 [PATCH 0/9] cxl/port: Unify RAS setup across port types Dan Williams
2026-01-22 3:33 ` [PATCH 1/9] cxl/port: Cleanup handling of the nr_dports 0 -> 1 transition Dan Williams
2026-01-22 11:32 ` Jonathan Cameron
2026-01-22 19:58 ` dan.j.williams
2026-01-22 16:45 ` Dave Jiang
2026-01-22 3:33 ` [PATCH 2/9] cxl/port: Reduce number of @dport variables in cxl_port_add_dport() Dan Williams
2026-01-22 11:39 ` Jonathan Cameron
2026-01-22 20:02 ` dan.j.williams
2026-01-22 16:54 ` Dave Jiang
2026-01-22 3:33 ` [PATCH 3/9] cxl/port: Cleanup dport removal with a devres group Dan Williams
2026-01-22 11:59 ` Jonathan Cameron
2026-01-22 20:43 ` dan.j.williams
2026-01-23 12:14 ` Jonathan Cameron
2026-01-23 12:24 ` Jonathan Cameron
2026-01-30 23:58 ` dan.j.williams
2026-01-22 3:33 ` [PATCH 4/9] cxl/port: Move decoder setup before dport creation Dan Williams
2026-01-22 13:07 ` Jonathan Cameron
2026-01-22 21:42 ` dan.j.williams
2026-01-22 20:38 ` Dave Jiang
2026-01-22 3:33 ` [PATCH 5/9] cxl/port: Move dport probe operations to a driver event Dan Williams
2026-01-22 14:44 ` Jonathan Cameron
2026-01-22 21:53 ` dan.j.williams [this message]
2026-01-22 3:33 ` [PATCH 6/9] cxl/port: Move dport RAS setup to dport add time Dan Williams
2026-01-22 15:00 ` Jonathan Cameron
2026-01-22 21:56 ` dan.j.williams
2026-01-22 21:06 ` Dave Jiang
2026-01-22 3:33 ` [PATCH 7/9] cxl/port: Map CXL Endpoint Port and CXL Switch Port RAS registers Dan Williams
2026-01-22 15:25 ` Jonathan Cameron
2026-01-22 22:11 ` dan.j.williams
2026-01-22 3:33 ` [PATCH 8/9] cxl/port: Move endpoint component register management to cxl_port Dan Williams
2026-01-22 15:27 ` Jonathan Cameron
2026-01-22 21:24 ` Dave Jiang
2026-01-22 3:33 ` [PATCH 9/9] cxl/port: Unify endpoint and switch port lookup Dan Williams
2026-01-22 15:32 ` Jonathan Cameron
2026-01-22 21:24 ` Dave Jiang
2026-01-22 21:42 ` [PATCH 0/9] cxl/port: Unify RAS setup across port types Bowman, Terry
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=69729c6fc25e7_3095100ea@dwillia2-mobl4.notmuch \
--to=dan.j.williams@intel.com \
--cc=alison.schofield@intel.com \
--cc=dave.jiang@intel.com \
--cc=dave@stgolabs.net \
--cc=ira.weiny@intel.com \
--cc=jonathan.cameron@huawei.com \
--cc=linux-cxl@vger.kernel.org \
--cc=terry.bowman@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox