From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v6 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink
Date: Thu, 25 Oct 2018 17:03:06 +0300 [thread overview]
Message-ID: <20181025140306.GK9144@intel.com> (raw)
In-Reply-To: <20181024222840.25683-19-manasi.d.navare@intel.com>
On Wed, Oct 24, 2018 at 03:28:30PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh <gaurav.k.singh@intel.com>
>
> This patch enables decompression support in sink device
> before link training and disables the same during the
> DDI disabling.
>
> v2:(From Manasi)
> * Change the enable/disable function to take crtc_state
> instead of intel_dp as an argument (Manasi)
> * Use the compression_enable flag as part of crtc_state (Manasi)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 5 +++++
> drivers/gpu/drm/i915/intel_dp.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> 3 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index e40a8c97d34b..1de0a3917d7f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2930,6 +2930,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> intel_ddi_init_dp_buf_reg(encoder);
> if (!is_mst)
> intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> + intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> + DP_DECOMPRESSION_EN);
> intel_dp_start_link_train(intel_dp);
> if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> intel_dp_stop_link_train(intel_dp);
> @@ -3272,6 +3274,9 @@ static void intel_disable_ddi_dp(struct intel_encoder *encoder,
> intel_edp_drrs_disable(intel_dp, old_crtc_state);
> intel_psr_disable(intel_dp, old_crtc_state);
> intel_edp_backlight_off(old_conn_state);
> + /* Disable the decompression in DP Sink */
> + intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
> + ~DP_DECOMPRESSION_EN);
That looks suspicious.
I can't figure out what value you're actually passing here since I
can't find the definiiton of DP_DECOMPRESSION_EN anywhere.
> }
>
> static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 35162c3bc811..72e6605f0ed7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3005,6 +3005,21 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
> intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
> }
>
> +void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + int state)
> +{
> + int ret;
> +
> + if (!crtc_state->dsc_params.compression_enable)
> + return;
> +
> + ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, state);
> + if (ret < 0)
> + DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
> + state == DP_DECOMPRESSION_EN ? "enable" : "disable");
> +}
> +
> /* If the sink supports it, try to set the power state appropriately */
> void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c4be4ba7adac..4f5d17bcd54e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1786,6 +1786,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
> int intel_dp_retrain_link(struct intel_encoder *encoder,
> struct drm_modeset_acquire_ctx *ctx);
> void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
> +void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + int state);
> void intel_dp_encoder_reset(struct drm_encoder *encoder);
> void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
> void intel_dp_encoder_destroy(struct drm_encoder *encoder);
> --
> 2.18.0
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2018-10-25 14:03 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-24 22:28 [PATCH v6 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-10-24 22:28 ` [PATCH v6 01/28] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Manasi Navare
2018-10-24 22:28 ` [PATCH v6 02/28] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-10-24 22:28 ` [PATCH v6 03/28] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-10-24 22:28 ` [PATCH v6 04/28] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-12-19 18:54 ` [Intel-gfx] " Daniel Vetter
2019-01-30 11:06 ` Daniel Vetter
2019-01-30 18:06 ` Sean Paul
2019-01-30 18:27 ` Manasi Navare
2019-01-30 18:26 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 05/28] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-10-24 22:28 ` [PATCH v6 06/28] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-10-24 22:28 ` [PATCH v6 07/28] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-10-24 22:28 ` [PATCH v6 08/28] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-01 16:42 ` Ville Syrjälä
2018-11-01 16:53 ` Ville Syrjälä
2018-11-01 21:48 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 09/28] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-10-24 22:28 ` [PATCH v6 10/28] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-10-24 22:28 ` [PATCH v6 11/28] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-01 16:46 ` Ville Syrjälä
2018-11-01 23:54 ` Manasi Navare
2018-11-02 0:23 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 12/28] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-10-30 23:53 ` Manasi Navare
2018-10-31 13:10 ` Ville Syrjälä
2018-10-31 16:05 ` Manasi Navare
2018-10-31 16:13 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-10-29 20:30 ` Ville Syrjälä
2018-10-29 20:34 ` Ville Syrjälä
2018-10-29 23:08 ` Manasi Navare
2018-10-30 11:46 ` Ville Syrjälä
2018-10-29 21:42 ` Manasi Navare
2018-10-29 22:12 ` Manasi Navare
2018-10-30 11:41 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 14/28] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-10-24 22:28 ` [PATCH v6 15/28] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-10-24 22:28 ` [PATCH v6 16/28] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-10-24 22:28 ` [PATCH v6 17/28] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-10-24 22:28 ` [PATCH v6 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-10-25 14:03 ` Ville Syrjälä [this message]
2018-10-25 20:11 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 19/28] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-10-24 22:28 ` [PATCH v6 20/28] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-10-24 22:28 ` [PATCH v6 21/28] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-10-25 14:08 ` Ville Syrjälä
2018-10-29 19:24 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 22/28] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-10-25 14:09 ` Ville Syrjälä
2018-10-25 20:07 ` Manasi Navare
2018-10-30 23:45 ` Manasi Navare
2018-10-31 13:09 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 23/28] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-10-24 22:28 ` [PATCH v6 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-10-25 14:15 ` Ville Syrjälä
2018-10-25 20:05 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 25/28] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-10-25 14:16 ` Ville Syrjälä
2018-10-25 19:55 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 26/28] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-10-25 14:22 ` Ville Syrjälä
2018-10-25 19:41 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-10-24 22:28 ` Lyude Paul
2018-10-25 20:12 ` Manasi Navare
2018-10-29 20:39 ` Ville Syrjälä
2018-10-29 21:35 ` Manasi Navare
2018-10-30 11:26 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 28/28] drm/i915/dsc: Force DSC enable if requested by IGT/userspace Manasi Navare
2018-10-24 22:39 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev6) Patchwork
2018-10-24 22:50 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-24 23:02 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-10-31 23:36 ` [PATCH v6 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare
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