From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v6 12/28] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Date: Wed, 31 Oct 2018 15:10:15 +0200 [thread overview]
Message-ID: <20181031131015.GP9144@intel.com> (raw)
In-Reply-To: <20181030235349.GC3481@intel.com>
On Tue, Oct 30, 2018 at 04:53:49PM -0700, Manasi Navare wrote:
> On Wed, Oct 24, 2018 at 03:28:24PM -0700, Manasi Navare wrote:
> > Basic DSC parameters and DSC configuration data needs to be computed
> > for each of the requested mode during atomic check. This is
> > required since for certain modes, valid DSC parameters and config
> > data might not be computed in which case compression cannot be
> > enabled for that mode.
> > For that reason we need to add these params and config structure
> > to the intel_crtc_state so that if valid this state information
> > can directly be used while enabling DSC in atomic commit.
> >
> > v2:
> > * Rebase on drm-tip (Manasi)
> >
> > Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_drv.h | 9 +++++++++
> > 2 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 2d7761b8ac07..45fd7894722b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -53,6 +53,7 @@
> > #include <drm/drm_auth.h>
> > #include <drm/drm_cache.h>
> > #include <drm/drm_util.h>
> > +#include <drm/drm_dsc.h>
> >
> > #include "i915_params.h"
> > #include "i915_reg.h"
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 62c051098859..27d47950f438 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -931,6 +931,15 @@ struct intel_crtc_state {
> >
> > /* Output down scaling is done in LSPCON device */
> > bool lspcon_downsampling;
> > +
> > + /* Display Stream compression state */
> > + struct {
> > + bool compression_enable;
> > + bool dsc_split;
> > + u16 compressed_bpp;
> > + u8 slice_count;
> > + } dsc_params;
> > + struct drm_dsc_config dp_dsc_cfg;
>
> Ville, Jani should this be defined as a pointer to struct drm_dsc_config?
> struct drm_dsc_config *dp_dsc_cfg
> since we populate this in intel_dp_compute_config and then on only read during
> commit.
Pointer to where exactly? You need the memory for it somewhere.
>
> Manasi
>
> > };
> >
> > struct intel_crtc {
> > --
> > 2.18.0
> >
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2018-10-31 13:10 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-24 22:28 [PATCH v6 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-10-24 22:28 ` [PATCH v6 01/28] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Manasi Navare
2018-10-24 22:28 ` [PATCH v6 02/28] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-10-24 22:28 ` [PATCH v6 03/28] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-10-24 22:28 ` [PATCH v6 04/28] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-12-19 18:54 ` [Intel-gfx] " Daniel Vetter
2019-01-30 11:06 ` Daniel Vetter
2019-01-30 18:06 ` Sean Paul
2019-01-30 18:27 ` Manasi Navare
2019-01-30 18:26 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 05/28] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-10-24 22:28 ` [PATCH v6 06/28] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-10-24 22:28 ` [PATCH v6 07/28] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-10-24 22:28 ` [PATCH v6 08/28] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-01 16:42 ` Ville Syrjälä
2018-11-01 16:53 ` Ville Syrjälä
2018-11-01 21:48 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 09/28] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-10-24 22:28 ` [PATCH v6 10/28] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-10-24 22:28 ` [PATCH v6 11/28] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-01 16:46 ` Ville Syrjälä
2018-11-01 23:54 ` Manasi Navare
2018-11-02 0:23 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 12/28] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-10-30 23:53 ` Manasi Navare
2018-10-31 13:10 ` Ville Syrjälä [this message]
2018-10-31 16:05 ` Manasi Navare
2018-10-31 16:13 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-10-29 20:30 ` Ville Syrjälä
2018-10-29 20:34 ` Ville Syrjälä
2018-10-29 23:08 ` Manasi Navare
2018-10-30 11:46 ` Ville Syrjälä
2018-10-29 21:42 ` Manasi Navare
2018-10-29 22:12 ` Manasi Navare
2018-10-30 11:41 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 14/28] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-10-24 22:28 ` [PATCH v6 15/28] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-10-24 22:28 ` [PATCH v6 16/28] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-10-24 22:28 ` [PATCH v6 17/28] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-10-24 22:28 ` [PATCH v6 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-10-25 14:03 ` Ville Syrjälä
2018-10-25 20:11 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 19/28] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-10-24 22:28 ` [PATCH v6 20/28] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-10-24 22:28 ` [PATCH v6 21/28] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-10-25 14:08 ` Ville Syrjälä
2018-10-29 19:24 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 22/28] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-10-25 14:09 ` Ville Syrjälä
2018-10-25 20:07 ` Manasi Navare
2018-10-30 23:45 ` Manasi Navare
2018-10-31 13:09 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 23/28] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-10-24 22:28 ` [PATCH v6 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-10-25 14:15 ` Ville Syrjälä
2018-10-25 20:05 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 25/28] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-10-25 14:16 ` Ville Syrjälä
2018-10-25 19:55 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 26/28] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-10-25 14:22 ` Ville Syrjälä
2018-10-25 19:41 ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-10-24 22:28 ` Lyude Paul
2018-10-25 20:12 ` Manasi Navare
2018-10-29 20:39 ` Ville Syrjälä
2018-10-29 21:35 ` Manasi Navare
2018-10-30 11:26 ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 28/28] drm/i915/dsc: Force DSC enable if requested by IGT/userspace Manasi Navare
2018-10-24 22:39 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev6) Patchwork
2018-10-24 22:50 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-24 23:02 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-10-31 23:36 ` [PATCH v6 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare
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