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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH v6 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
Date: Tue, 30 Oct 2018 13:26:42 +0200	[thread overview]
Message-ID: <20181030112642.GR9144@intel.com> (raw)
In-Reply-To: <20181029213536.GB27040@intel.com>

On Mon, Oct 29, 2018 at 02:35:36PM -0700, Manasi Navare wrote:
> On Mon, Oct 29, 2018 at 10:39:21PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:39PM -0700, Manasi Navare wrote:
> > > DSC can be supported per DP connector. This patch adds a per connector
> > > debugfs node to expose DSC support capability by the kernel.
> > > The same node can be used from userspace to force DSC enable.
> > 
> > Why is the force_dsc thing split between two patches so strangely?
> 
> This patch just defines the force_dsc and sets it through the debugfs
> node. But how it configures DSC during atomic check is moved to a
> separate patch. 
> Would you prefer having that integrated with this patch itself?

Either that or split it in into "read only debugfs status" +
"add dsc_force" patches.

> 
> Manasi
> 
> > 
> > > 
> > > v2:
> > > * Use kstrtobool_from_user to avoid explicit error checking (Lyude)
> > > * Rebase on drm-tip (Manasi)
> > > 
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Lyude Paul <lyude@redhat.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > Reviewed-by: Lyude Paul <lyude@redhat.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_debugfs.c | 71 ++++++++++++++++++++++++++++-
> > >  drivers/gpu/drm/i915/intel_dp.c     |  1 +
> > >  drivers/gpu/drm/i915/intel_drv.h    |  3 ++
> > >  3 files changed, 74 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 5cadfcd03ea9..6e631f08dd4b 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -4999,6 +4999,72 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> > >  }
> > >  DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
> > >  
> > > +static int i915_dsc_support_show(struct seq_file *m, void *data)
> > > +{
> > > +	struct drm_connector *connector = m->private;
> > > +	struct intel_encoder *encoder = intel_attached_encoder(connector);
> > > +	struct intel_dp *intel_dp =
> > > +		enc_to_intel_dp(&encoder->base);
> > > +	struct intel_crtc *crtc;
> > > +	struct intel_crtc_state *crtc_state;
> > > +
> > > +	crtc = to_intel_crtc(encoder->base.crtc);
> > > +	crtc_state = to_intel_crtc_state(crtc->base.state);
> > > +	drm_modeset_lock(&crtc->base.mutex, NULL);
> > > +	seq_printf(m, "Enabled: %s\n",
> > > +		   yesno(crtc_state->dsc_params.compression_enable));
> > > +	seq_printf(m, "Supported: %s\n",
> > > +		   yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
> > > +	drm_modeset_unlock(&crtc->base.mutex);
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static ssize_t i915_dsc_support_write(struct file *file,
> > > +				      const char __user *ubuf,
> > > +				      size_t len, loff_t *offp)
> > > +{
> > > +	bool dsc_enable = false;
> > > +	int ret;
> > > +	struct drm_connector *connector =
> > > +		((struct seq_file *)file->private_data)->private;
> > > +	struct intel_encoder *encoder = intel_attached_encoder(connector);
> > > +	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > > +
> > > +	if (len == 0)
> > > +		return 0;
> > > +
> > > +	DRM_DEBUG_DRIVER("Copied %d bytes from user to force DSC\n",
> > > +			 (unsigned int)len);
> > > +
> > > +	ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
> > > +	if (ret < 0)
> > > +		return ret;
> > > +
> > > +	DRM_DEBUG_DRIVER("Got %s for DSC Enable\n",
> > > +			 (dsc_enable) ? "true" : "false");
> > > +	intel_dp->force_dsc_en = dsc_enable;
> > > +
> > > +	*offp += len;
> > > +	return len;
> > > +}
> > > +
> > > +static int i915_dsc_support_open(struct inode *inode,
> > > +				 struct file *file)
> > > +{
> > > +	return single_open(file, i915_dsc_support_show,
> > > +			   inode->i_private);
> > > +}
> > > +
> > > +static const struct file_operations i915_dsc_support_fops = {
> > > +	.owner = THIS_MODULE,
> > > +	.open = i915_dsc_support_open,
> > > +	.read = seq_read,
> > > +	.llseek = seq_lseek,
> > > +	.release = single_release,
> > > +	.write = i915_dsc_support_write
> > > +};
> > > +
> > >  /**
> > >   * i915_debugfs_connector_add - add i915 specific connector debugfs files
> > >   * @connector: pointer to a registered drm_connector
> > > @@ -5017,9 +5083,12 @@ int i915_debugfs_connector_add(struct drm_connector *connector)
> > >  		return -ENODEV;
> > >  
> > >  	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > > -	    connector->connector_type == DRM_MODE_CONNECTOR_eDP)
> > > +	    connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> > >  		debugfs_create_file("i915_dpcd", S_IRUGO, root,
> > >  				    connector, &i915_dpcd_fops);
> > > +		debugfs_create_file("i915_dsc_support", S_IRUGO, root,
> > > +				    connector, &i915_dsc_support_fops);
> > > +	}
> > >  
> > >  	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> > >  		debugfs_create_file("i915_panel_timings", S_IRUGO, root,
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 72e6605f0ed7..0b5939992c2b 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -2287,6 +2287,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> > >  	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> > >  		return false;
> > >  
> > > +	DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
> > >  	if (!intel_dp_compute_link_config(encoder, pipe_config))
> > >  		return false;
> > >  
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > > index 4f5d17bcd54e..16bbc3768e02 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1196,6 +1196,9 @@ struct intel_dp {
> > >  
> > >  	/* Displayport compliance testing */
> > >  	struct intel_dp_compliance compliance;
> > > +
> > > +	/* Display stream compression testing */
> > > +	bool force_dsc_en;
> > >  };
> > >  
> > >  enum lspcon_vendor {
> > > -- 
> > > 2.18.0
> > 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2018-10-30 11:26 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-24 22:28 [PATCH v6 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-10-24 22:28 ` [PATCH v6 01/28] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Manasi Navare
2018-10-24 22:28 ` [PATCH v6 02/28] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-10-24 22:28 ` [PATCH v6 03/28] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-10-24 22:28 ` [PATCH v6 04/28] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-12-19 18:54   ` [Intel-gfx] " Daniel Vetter
2019-01-30 11:06     ` Daniel Vetter
2019-01-30 18:06       ` Sean Paul
2019-01-30 18:27         ` Manasi Navare
2019-01-30 18:26       ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 05/28] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-10-24 22:28 ` [PATCH v6 06/28] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-10-24 22:28 ` [PATCH v6 07/28] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-10-24 22:28 ` [PATCH v6 08/28] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-01 16:42   ` Ville Syrjälä
2018-11-01 16:53     ` Ville Syrjälä
2018-11-01 21:48     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 09/28] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-10-24 22:28 ` [PATCH v6 10/28] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-10-24 22:28 ` [PATCH v6 11/28] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-01 16:46   ` Ville Syrjälä
2018-11-01 23:54     ` Manasi Navare
2018-11-02  0:23       ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 12/28] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-10-30 23:53   ` Manasi Navare
2018-10-31 13:10     ` Ville Syrjälä
2018-10-31 16:05       ` Manasi Navare
2018-10-31 16:13         ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-10-29 20:30   ` Ville Syrjälä
2018-10-29 20:34     ` Ville Syrjälä
2018-10-29 23:08       ` Manasi Navare
2018-10-30 11:46         ` Ville Syrjälä
2018-10-29 21:42     ` Manasi Navare
2018-10-29 22:12     ` Manasi Navare
2018-10-30 11:41       ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 14/28] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-10-24 22:28 ` [PATCH v6 15/28] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-10-24 22:28 ` [PATCH v6 16/28] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-10-24 22:28 ` [PATCH v6 17/28] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-10-24 22:28 ` [PATCH v6 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-10-25 14:03   ` Ville Syrjälä
2018-10-25 20:11     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 19/28] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-10-24 22:28 ` [PATCH v6 20/28] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-10-24 22:28 ` [PATCH v6 21/28] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-10-25 14:08   ` Ville Syrjälä
2018-10-29 19:24     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 22/28] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-10-25 14:09   ` Ville Syrjälä
2018-10-25 20:07     ` Manasi Navare
2018-10-30 23:45     ` Manasi Navare
2018-10-31 13:09       ` Ville Syrjälä
2018-10-24 22:28 ` [PATCH v6 23/28] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-10-24 22:28 ` [PATCH v6 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-10-25 14:15   ` Ville Syrjälä
2018-10-25 20:05     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 25/28] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-10-25 14:16   ` Ville Syrjälä
2018-10-25 19:55     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 26/28] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-10-25 14:22   ` Ville Syrjälä
2018-10-25 19:41     ` Manasi Navare
2018-10-24 22:28 ` [PATCH v6 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-10-24 22:28   ` Lyude Paul
2018-10-25 20:12     ` Manasi Navare
2018-10-29 20:39   ` Ville Syrjälä
2018-10-29 21:35     ` Manasi Navare
2018-10-30 11:26       ` Ville Syrjälä [this message]
2018-10-24 22:28 ` [PATCH v6 28/28] drm/i915/dsc: Force DSC enable if requested by IGT/userspace Manasi Navare
2018-10-24 22:39 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev6) Patchwork
2018-10-24 22:50 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-24 23:02 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-10-31 23:36 ` [PATCH v6 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare

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