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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 02/14] drm/i915: Clean up skl_program_scaler()
Date: Fri, 9 Nov 2018 19:24:01 +0200	[thread overview]
Message-ID: <20181109172401.GO9144@intel.com> (raw)
In-Reply-To: <20181107182953.GM9144@intel.com>

On Wed, Nov 07, 2018 at 08:29:53PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 01, 2018 at 11:13:50AM -0700, Rodrigo Vivi wrote:
> > On Thu, Nov 01, 2018 at 05:17:36PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Remove the "sizes are 0 based" stuff that is not even true for the
> > > scaler.
> > > 
> > > v2: Rebase
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> Thanks. First two patches pushed.

And now also 3-5 and 8. The rest had some amount of discussion still
happening, so I'll refrain from pushing more until I address Matt's
comments and repost the remaining patches.

Thanks for the reviews so far.

> 
> > 
> > > ---
> > >  drivers/gpu/drm/i915/intel_sprite.c | 18 +++++-------------
> > >  1 file changed, 5 insertions(+), 13 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > index 30b7485f1992..a77a17fda692 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -310,12 +310,11 @@ skl_plane_max_stride(struct intel_plane *plane,
> > >  }
> > >  
> > >  static void
> > > -skl_program_scaler(struct drm_i915_private *dev_priv,
> > > -		   struct intel_plane *plane,
> > > +skl_program_scaler(struct intel_plane *plane,
> > >  		   const struct intel_crtc_state *crtc_state,
> > >  		   const struct intel_plane_state *plane_state)
> > >  {
> > > -	enum plane_id plane_id = plane->id;
> > > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > >  	enum pipe pipe = plane->pipe;
> > >  	int scaler_id = plane_state->scaler_id;
> > >  	const struct intel_scaler *scaler =
> > > @@ -327,10 +326,6 @@ skl_program_scaler(struct drm_i915_private *dev_priv,
> > >  	u16 y_hphase, uv_rgb_hphase;
> > >  	u16 y_vphase, uv_rgb_vphase;
> > >  
> > > -	/* Sizes are 0 based */
> > > -	crtc_w--;
> > > -	crtc_h--;
> > > -
> > >  	/* TODO: handle sub-pixel coordinates */
> > >  	if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 &&
> > >  	    !icl_is_hdr_plane(plane)) {
> > > @@ -350,15 +345,14 @@ skl_program_scaler(struct drm_i915_private *dev_priv,
> > >  	}
> > >  
> > >  	I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
> > > -		      PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
> > > +		      PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
> > >  	I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
> > >  	I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
> > >  		      PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
> > >  	I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
> > >  		      PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
> > >  	I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
> > > -	I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
> > > -		      ((crtc_w + 1) << 16)|(crtc_h + 1));
> > > +	I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
> > >  }
> > >  
> > >  static void
> > > @@ -441,11 +435,9 @@ skl_program_plane(struct intel_plane *plane,
> > >  		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
> > >  	}
> > >  
> > > -	/* program plane scaler */
> > >  	if (plane_state->scaler_id >= 0) {
> > >  		if (!slave)
> > > -			skl_program_scaler(dev_priv, plane,
> > > -					   crtc_state, plane_state);
> > > +			skl_program_scaler(plane, crtc_state, plane_state);
> > >  
> > >  		I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
> > >  	} else {
> > > -- 
> > > 2.18.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-11-09 17:24 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-01 15:05 [PATCH 00/14] drm/i915: Program SKL+ watermarks/ddb more carefully Ville Syrjala
2018-11-01 15:05 ` [PATCH 01/14] drm/i915: Nuke posting reads from plane update/disable funcs Ville Syrjala
2018-11-01 18:08   ` Rodrigo Vivi
2018-11-01 15:05 ` [PATCH 02/14] drm/i915: Clean up skl_program_scaler() Ville Syrjala
2018-11-01 15:17   ` [PATCH v2 " Ville Syrjala
2018-11-01 18:13     ` Rodrigo Vivi
2018-11-07 18:29       ` Ville Syrjälä
2018-11-09 17:24         ` Ville Syrjälä [this message]
2018-11-01 15:05 ` [PATCH 03/14] drm/i915: Remove the PS_PWR_GATE write from skl_program_scaler() Ville Syrjala
2018-11-07 18:53   ` Rodrigo Vivi
2018-11-01 15:05 ` [PATCH 04/14] drm/i915: Polish the skl+ plane keyval/msk/max register setup Ville Syrjala
2018-11-07 18:41   ` [PATCH v2 " Ville Syrjala
2018-11-07 19:55   ` [PATCH " Rodrigo Vivi
2018-11-07 20:56     ` Ville Syrjälä
2018-11-01 15:05 ` [PATCH 05/14] drm/i915: Clean up skl+ PLANE_POS vs. scaler handling Ville Syrjala
2018-11-07 19:56   ` Rodrigo Vivi
2018-11-01 15:05 ` [PATCH 06/14] drm/i915: Reorganize plane register writes to make them more atomic Ville Syrjala
2018-11-07 18:42   ` [PATCH v2 " Ville Syrjala
2018-11-08 19:30     ` Matt Roper
2018-11-08 19:48       ` Ville Syrjälä
2018-11-07 21:26   ` [PATCH " Rodrigo Vivi
2018-11-07 21:38     ` Ville Syrjälä
2018-11-01 15:05 ` [PATCH 07/14] drm/i915: Move single buffered plane register writes to the end Ville Syrjala
2018-11-07 21:26   ` Rodrigo Vivi
2018-11-08 22:06   ` Matt Roper
2018-11-09 13:55     ` Ville Syrjälä
2018-11-01 15:05 ` [PATCH 08/14] drm/i915: Generalize skl_ddb_allocation_overlaps() Ville Syrjala
2018-11-07 21:28   ` Rodrigo Vivi
2018-11-01 15:06 ` [PATCH 09/14] drm/i915: Introduce crtc_state->update_planes bitmask Ville Syrjala
2018-11-07 21:49   ` Rodrigo Vivi
2018-11-08 11:32     ` Ville Syrjälä
2018-11-08 23:22   ` Matt Roper
2018-11-09 13:57     ` Ville Syrjälä
2018-11-01 15:06 ` [PATCH 10/14] drm/i915: Pass the new crtc_state to ->disable_plane() Ville Syrjala
2018-11-07 22:08   ` Rodrigo Vivi
2018-11-08 11:43     ` Ville Syrjälä
2018-11-08 23:52   ` Matt Roper
2018-11-09 14:32     ` Ville Syrjälä
2018-11-01 15:06 ` [PATCH 11/14] drm/i915: Fix latency==0 handling for level 0 watermark on skl+ Ville Syrjala
2018-11-07 22:09   ` Rodrigo Vivi
2018-11-09  0:01   ` Matt Roper
2018-11-09 14:34     ` Ville Syrjälä
2018-11-01 15:06 ` [PATCH 12/14] drm/i915: Remove some useless zeroing on skl+ wm calculations Ville Syrjala
2018-11-07 18:43   ` [PATCH v2 " Ville Syrjala
2018-11-07 22:11   ` [PATCH " Rodrigo Vivi
2018-11-08 11:46     ` Ville Syrjälä
2018-11-01 15:06 ` [PATCH 13/14] drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+ Ville Syrjala
2018-11-07 18:44   ` [PATCH v2 " Ville Syrjala
2018-11-09  1:38     ` Matt Roper
2018-11-09 14:53       ` Ville Syrjälä
2018-11-01 15:06 ` [PATCH 14/14] drm/i915: Commit skl+ planes in an order that avoids ddb overlaps Ville Syrjala
2018-11-01 15:08 ` ✗ Fi.CI.BAT: failure for drm/i915: Program SKL+ watermarks/ddb more carefully Patchwork
2018-11-01 16:04 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Program SKL+ watermarks/ddb more carefully (rev2) Patchwork
2018-11-01 16:09 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-01 16:26 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-01 18:13 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-07 19:01 ` ✗ Fi.CI.BAT: failure for drm/i915: Program SKL+ watermarks/ddb more carefully (rev6) Patchwork

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